RV_TIMER Simulation Results

Saturday July 13 2024 23:02:33 UTC

GitHub Revision: `d51405297e`

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 101086804359139103922259090811397817605469534164678958852189348539757618502888

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	random	rv_timer_random	40.878m	507.117ms	200	200	100.00
V1	csr_hw_reset	rv_timer_csr_hw_reset	0.620s	15.248us	5	5	100.00
V1	csr_rw	rv_timer_csr_rw	0.650s	40.374us	20	20	100.00
V1	csr_bit_bash	rv_timer_csr_bit_bash	3.630s	1.133ms	5	5	100.00
V1	csr_aliasing	rv_timer_csr_aliasing	0.840s	121.324us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	rv_timer_csr_mem_rw_with_rand_reset	1.670s	36.162us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	rv_timer_csr_rw	0.650s	40.374us	20	20	100.00
		rv_timer_csr_aliasing	0.840s	121.324us	5	5	100.00
V1		TOTAL			255	255	100.00
V2	random_reset	rv_timer_random_reset	56.878m	1.000s	46	50	92.00
V2	disabled	rv_timer_disabled	5.099m	197.136ms	49	50	98.00
V2	cfg_update_on_fly	rv_timer_cfg_update_on_fly	27.925m	1.003s	50	50	100.00
V2	no_interrupt_test	rv_timer_cfg_update_on_fly	27.925m	1.003s	50	50	100.00
V2	stress	rv_timer_stress_all	59.450m	626.645ms	49	50	98.00
V2	intr_test	rv_timer_intr_test	0.630s	50.504us	50	50	100.00
V2	tl_d_oob_addr_access	rv_timer_tl_errors	3.120s	325.080us	20	20	100.00
V2	tl_d_illegal_access	rv_timer_tl_errors	3.120s	325.080us	20	20	100.00
V2	tl_d_outstanding_access	rv_timer_csr_hw_reset	0.620s	15.248us	5	5	100.00
		rv_timer_csr_rw	0.650s	40.374us	20	20	100.00
		rv_timer_csr_aliasing	0.840s	121.324us	5	5	100.00
		rv_timer_same_csr_outstanding	0.800s	78.406us	20	20	100.00
V2	tl_d_partial_access	rv_timer_csr_hw_reset	0.620s	15.248us	5	5	100.00
		rv_timer_csr_rw	0.650s	40.374us	20	20	100.00
		rv_timer_csr_aliasing	0.840s	121.324us	5	5	100.00
		rv_timer_same_csr_outstanding	0.800s	78.406us	20	20	100.00
V2		TOTAL			284	290	97.93
V2S	tl_intg_err	rv_timer_sec_cm	0.920s	647.111us	5	5	100.00
		rv_timer_tl_intg_err	1.400s	1.648ms	20	20	100.00
V2S	sec_cm_bus_integrity	rv_timer_tl_intg_err	1.400s	1.648ms	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	rv_timer_stress_all_with_rand_reset	17.693m	172.727ms	6	50	12.00
V3		TOTAL			6	50	12.00
		TOTAL			570	620	91.94

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	7	7	4	57.14
V2S	2	2	2	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
99.66	99.36	98.73	100.00	--	100.00	100.00	99.89

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:825) [rv_timer_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 43 failures:
- Test rv_timer_stress_all_with_rand_reset has 43 failures.
  - 0.rv_timer_stress_all_with_rand_reset.61866084004556657053479034376495011452271900284862210558644335685666739230284
    Line 271, in log /container/opentitan-public/scratch/os_regression/rv_timer-sim-vcs/0.rv_timer_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 6906076709 ps: (cip_base_vseq.sv:825) [uvm_test_top.env.virtual_sequencer.rv_timer_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 6906076709 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 2.rv_timer_stress_all_with_rand_reset.41079642771188969306097795717994805289563066759101581755497849086205966071109
    Line 312, in log /container/opentitan-public/scratch/os_regression/rv_timer-sim-vcs/2.rv_timer_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 5789089023 ps: (cip_base_vseq.sv:825) [uvm_test_top.env.virtual_sequencer.rv_timer_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 5789089023 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 41 more failures.
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 6 failures:
- Test rv_timer_random_reset has 4 failures.
  - 25.rv_timer_random_reset.3930307156433952386367665804176454433467757862923111375579255131862390907499
    Line 251, in log /container/opentitan-public/scratch/os_regression/rv_timer-sim-vcs/25.rv_timer_random_reset/latest/run.log
```
  UVM_FATAL @ 1000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 1000000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 1000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 27.rv_timer_random_reset.90430655088616776529808968436133319821356788292505465164077873538286943450064
    Line 252, in log /container/opentitan-public/scratch/os_regression/rv_timer-sim-vcs/27.rv_timer_random_reset/latest/run.log
```
  UVM_FATAL @ 1000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 1000000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 1000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 2 more failures.
- Test rv_timer_disabled has 1 failures.
  - 44.rv_timer_disabled.90134534547819180107263478682210946837357227509008579638053860024896200284304
    Line 250, in log /container/opentitan-public/scratch/os_regression/rv_timer-sim-vcs/44.rv_timer_disabled/latest/run.log
```
  UVM_FATAL @ 1000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 1000000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 1000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rv_timer_stress_all has 1 failures.
  - 44.rv_timer_stress_all.89553517244875086590132390700234454250370334611766956506356230108724527646451
    Line 273, in log /container/opentitan-public/scratch/os_regression/rv_timer-sim-vcs/44.rv_timer_stress_all/latest/run.log
```
  UVM_FATAL @ 10000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 10000000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 10000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (cip_base_vseq.sv:749) [rv_timer_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. has 1 failures:
- Test rv_timer_stress_all_with_rand_reset has 1 failures.
  - 16.rv_timer_stress_all_with_rand_reset.111244946023886836090390498739601347380892445748148035919428658985703281483880
    Line 725, in log /container/opentitan-public/scratch/os_regression/rv_timer-sim-vcs/16.rv_timer_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 175522957274 ps: (cip_base_vseq.sv:749) [uvm_test_top.env.virtual_sequencer.rv_timer_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
  UVM_INFO @ 175522957274 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

RV_TIMER Simulation Results

Saturday July 13 2024 23:02:33 UTC

GitHub Revision: d51405297e

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 101086804359139103922259090811397817605469534164678958852189348539757618502888

Test Results

Testplan Progress

Coverage Results

Coverage Dashboard

Failure Buckets

Past Results

GitHub Revision: `d51405297e`