39211701b5| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | random | rv_timer_random | 43.950m | 1.581s | 200 | 200 | 100.00 |
| V1 | csr_hw_reset | rv_timer_csr_hw_reset | 0.590s | 14.213us | 5 | 5 | 100.00 |
| V1 | csr_rw | rv_timer_csr_rw | 0.660s | 38.992us | 20 | 20 | 100.00 |
| V1 | csr_bit_bash | rv_timer_csr_bit_bash | 3.570s | 3.863ms | 5 | 5 | 100.00 |
| V1 | csr_aliasing | rv_timer_csr_aliasing | 0.840s | 39.960us | 5 | 5 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | rv_timer_csr_mem_rw_with_rand_reset | 1.510s | 637.064us | 20 | 20 | 100.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | rv_timer_csr_rw | 0.660s | 38.992us | 20 | 20 | 100.00 |
| rv_timer_csr_aliasing | 0.840s | 39.960us | 5 | 5 | 100.00 | ||
| V1 | TOTAL | 255 | 255 | 100.00 | |||
| V2 | random_reset | rv_timer_random_reset | 16.294m | 611.815ms | 49 | 50 | 98.00 |
| V2 | disabled | rv_timer_disabled | 5.600m | 727.385ms | 47 | 50 | 94.00 |
| V2 | cfg_update_on_fly | rv_timer_cfg_update_on_fly | 15.076m | 1.666s | 50 | 50 | 100.00 |
| V2 | no_interrupt_test | rv_timer_cfg_update_on_fly | 15.076m | 1.666s | 50 | 50 | 100.00 |
| V2 | stress | rv_timer_stress_all | 1.685h | 6.344s | 50 | 50 | 100.00 |
| V2 | intr_test | rv_timer_intr_test | 0.600s | 13.256us | 50 | 50 | 100.00 |
| V2 | tl_d_oob_addr_access | rv_timer_tl_errors | 3.010s | 729.137us | 20 | 20 | 100.00 |
| V2 | tl_d_illegal_access | rv_timer_tl_errors | 3.010s | 729.137us | 20 | 20 | 100.00 |
| V2 | tl_d_outstanding_access | rv_timer_csr_hw_reset | 0.590s | 14.213us | 5 | 5 | 100.00 |
| rv_timer_csr_rw | 0.660s | 38.992us | 20 | 20 | 100.00 | ||
| rv_timer_csr_aliasing | 0.840s | 39.960us | 5 | 5 | 100.00 | ||
| rv_timer_same_csr_outstanding | 0.850s | 63.324us | 20 | 20 | 100.00 | ||
| V2 | tl_d_partial_access | rv_timer_csr_hw_reset | 0.590s | 14.213us | 5 | 5 | 100.00 |
| rv_timer_csr_rw | 0.660s | 38.992us | 20 | 20 | 100.00 | ||
| rv_timer_csr_aliasing | 0.840s | 39.960us | 5 | 5 | 100.00 | ||
| rv_timer_same_csr_outstanding | 0.850s | 63.324us | 20 | 20 | 100.00 | ||
| V2 | TOTAL | 286 | 290 | 98.62 | |||
| V2S | tl_intg_err | rv_timer_sec_cm | 0.950s | 174.004us | 5 | 5 | 100.00 |
| rv_timer_tl_intg_err | 1.450s | 445.700us | 20 | 20 | 100.00 | ||
| V2S | sec_cm_bus_integrity | rv_timer_tl_intg_err | 1.450s | 445.700us | 20 | 20 | 100.00 |
| V2S | TOTAL | 25 | 25 | 100.00 | |||
| V3 | stress_all_with_rand_reset | rv_timer_stress_all_with_rand_reset | 20.955m | 39.410ms | 10 | 50 | 20.00 |
| V3 | TOTAL | 10 | 50 | 20.00 | |||
| TOTAL | 576 | 620 | 92.90 |
| Items | Total | Written | Passing | Progress |
|---|---|---|---|---|
| V1 | 6 | 6 | 6 | 100.00 |
| V2 | 7 | 7 | 5 | 71.43 |
| V2S | 2 | 2 | 2 | 100.00 |
| V3 | 1 | 1 | 0 | 0.00 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
|---|---|---|---|---|---|---|---|
| 99.62 | 99.36 | 98.73 | 100.00 | -- | 100.00 | 100.00 | 99.66 |
UVM_ERROR (cip_base_vseq.sv:825) [rv_timer_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 40 failures:
0.rv_timer_stress_all_with_rand_reset.112848268310409166763262288893974187964026126604166037262025529460155284594756
Line 1699, in log /container/opentitan-public/scratch/os_regression/rv_timer-sim-vcs/0.rv_timer_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 245288416585 ps: (cip_base_vseq.sv:825) [uvm_test_top.env.virtual_sequencer.rv_timer_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 245288416585 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.rv_timer_stress_all_with_rand_reset.56027615250949231749362246212211966434786927567894300157268366328100170645153
Line 1436, in log /container/opentitan-public/scratch/os_regression/rv_timer-sim-vcs/1.rv_timer_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 123861215454 ps: (cip_base_vseq.sv:825) [uvm_test_top.env.virtual_sequencer.rv_timer_common_vseq] Check failed (!has_outstanding_access()) Waited 10020 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 123861215454 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 38 more failures.
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 4 failures:
6.rv_timer_disabled.74780399760900666094728501433713740170143723669827988952086062079704725755929
Line 252, in log /container/opentitan-public/scratch/os_regression/rv_timer-sim-vcs/6.rv_timer_disabled/latest/run.log
UVM_FATAL @ 1000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 1000000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 1000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
24.rv_timer_disabled.6090546379708564918370909361263330054354240075705970305696393130595599208430
Line 251, in log /container/opentitan-public/scratch/os_regression/rv_timer-sim-vcs/24.rv_timer_disabled/latest/run.log
UVM_FATAL @ 1000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 1000000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 1000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
20.rv_timer_random_reset.94139760503899179535322450720888345208228786635602326775175008852776369995905
Line 251, in log /container/opentitan-public/scratch/os_regression/rv_timer-sim-vcs/20.rv_timer_random_reset/latest/run.log
UVM_FATAL @ 1000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 1000000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 1000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---