2e5d86c9b5| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | random | rv_timer_random | 50.016m | 211.466ms | 200 | 200 | 100.00 |
| V1 | csr_hw_reset | rv_timer_csr_hw_reset | 0.630s | 49.887us | 5 | 5 | 100.00 |
| V1 | csr_rw | rv_timer_csr_rw | 0.630s | 15.132us | 20 | 20 | 100.00 |
| V1 | csr_bit_bash | rv_timer_csr_bit_bash | 3.660s | 1.604ms | 5 | 5 | 100.00 |
| V1 | csr_aliasing | rv_timer_csr_aliasing | 0.840s | 111.689us | 5 | 5 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | rv_timer_csr_mem_rw_with_rand_reset | 1.930s | 38.972us | 20 | 20 | 100.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | rv_timer_csr_rw | 0.630s | 15.132us | 20 | 20 | 100.00 |
| rv_timer_csr_aliasing | 0.840s | 111.689us | 5 | 5 | 100.00 | ||
| V1 | TOTAL | 255 | 255 | 100.00 | |||
| V2 | random_reset | rv_timer_random_reset | 22.237m | 408.801ms | 50 | 50 | 100.00 |
| V2 | disabled | rv_timer_disabled | 4.640m | 208.215ms | 46 | 50 | 92.00 |
| V2 | cfg_update_on_fly | rv_timer_cfg_update_on_fly | 22.939m | 2.693s | 50 | 50 | 100.00 |
| V2 | no_interrupt_test | rv_timer_cfg_update_on_fly | 22.939m | 2.693s | 50 | 50 | 100.00 |
| V2 | stress | rv_timer_stress_all | 54.822m | 1.050s | 50 | 50 | 100.00 |
| V2 | intr_test | rv_timer_intr_test | 0.620s | 40.888us | 50 | 50 | 100.00 |
| V2 | tl_d_oob_addr_access | rv_timer_tl_errors | 3.260s | 206.314us | 20 | 20 | 100.00 |
| V2 | tl_d_illegal_access | rv_timer_tl_errors | 3.260s | 206.314us | 20 | 20 | 100.00 |
| V2 | tl_d_outstanding_access | rv_timer_csr_hw_reset | 0.630s | 49.887us | 5 | 5 | 100.00 |
| rv_timer_csr_rw | 0.630s | 15.132us | 20 | 20 | 100.00 | ||
| rv_timer_csr_aliasing | 0.840s | 111.689us | 5 | 5 | 100.00 | ||
| rv_timer_same_csr_outstanding | 0.910s | 47.313us | 20 | 20 | 100.00 | ||
| V2 | tl_d_partial_access | rv_timer_csr_hw_reset | 0.630s | 49.887us | 5 | 5 | 100.00 |
| rv_timer_csr_rw | 0.630s | 15.132us | 20 | 20 | 100.00 | ||
| rv_timer_csr_aliasing | 0.840s | 111.689us | 5 | 5 | 100.00 | ||
| rv_timer_same_csr_outstanding | 0.910s | 47.313us | 20 | 20 | 100.00 | ||
| V2 | TOTAL | 286 | 290 | 98.62 | |||
| V2S | tl_intg_err | rv_timer_sec_cm | 0.870s | 101.141us | 5 | 5 | 100.00 |
| rv_timer_tl_intg_err | 1.430s | 775.938us | 20 | 20 | 100.00 | ||
| V2S | sec_cm_bus_integrity | rv_timer_tl_intg_err | 1.430s | 775.938us | 20 | 20 | 100.00 |
| V2S | TOTAL | 25 | 25 | 100.00 | |||
| V3 | stress_all_with_rand_reset | rv_timer_stress_all_with_rand_reset | 17.180m | 158.076ms | 15 | 50 | 30.00 |
| V3 | TOTAL | 15 | 50 | 30.00 | |||
| TOTAL | 581 | 620 | 93.71 |
| Items | Total | Written | Passing | Progress |
|---|---|---|---|---|
| V1 | 6 | 6 | 6 | 100.00 |
| V2 | 7 | 7 | 6 | 85.71 |
| V2S | 2 | 2 | 2 | 100.00 |
| V3 | 1 | 1 | 0 | 0.00 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
|---|---|---|---|---|---|---|---|
| 99.53 | 99.36 | 98.73 | 100.00 | -- | 100.00 | 100.00 | 99.09 |
UVM_ERROR (cip_base_vseq.sv:825) [rv_timer_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 34 failures:
0.rv_timer_stress_all_with_rand_reset.89259126762125271608055071283935836324966194348783422464251304121047575170044
Line 744, in log /container/opentitan-public/scratch/os_regression/rv_timer-sim-vcs/0.rv_timer_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 90582009756 ps: (cip_base_vseq.sv:825) [uvm_test_top.env.virtual_sequencer.rv_timer_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 90582009756 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.rv_timer_stress_all_with_rand_reset.39400748550991667164301358043430014451738364059351822515463234297019251682606
Line 279, in log /container/opentitan-public/scratch/os_regression/rv_timer-sim-vcs/1.rv_timer_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 17302505826 ps: (cip_base_vseq.sv:825) [uvm_test_top.env.virtual_sequencer.rv_timer_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 17302505826 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 32 more failures.
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 4 failures:
9.rv_timer_disabled.27402480396580642794374959481306908559995866204142283591312267717737419090773
Line 252, in log /container/opentitan-public/scratch/os_regression/rv_timer-sim-vcs/9.rv_timer_disabled/latest/run.log
UVM_FATAL @ 1000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 1000000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 1000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
18.rv_timer_disabled.22732857849281104693281138420393380130219452235277497311457331662766989878544
Line 252, in log /container/opentitan-public/scratch/os_regression/rv_timer-sim-vcs/18.rv_timer_disabled/latest/run.log
UVM_FATAL @ 1000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 1000000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 1000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 2 more failures.
UVM_ERROR (cip_base_vseq.sv:749) [rv_timer_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. has 1 failures:
7.rv_timer_stress_all_with_rand_reset.104637351979393494605258321637091273884218630792242815738819409317642735031154
Line 268, in log /container/opentitan-public/scratch/os_regression/rv_timer-sim-vcs/7.rv_timer_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 10405033027 ps: (cip_base_vseq.sv:749) [uvm_test_top.env.virtual_sequencer.rv_timer_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
UVM_INFO @ 10405033027 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---