6a84251492| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | random | rv_timer_random | 52.590m | 376.324ms | 199 | 200 | 99.50 |
| V1 | csr_hw_reset | rv_timer_csr_hw_reset | 0.660s | 67.152us | 5 | 5 | 100.00 |
| V1 | csr_rw | rv_timer_csr_rw | 0.630s | 17.110us | 20 | 20 | 100.00 |
| V1 | csr_bit_bash | rv_timer_csr_bit_bash | 3.170s | 176.087us | 5 | 5 | 100.00 |
| V1 | csr_aliasing | rv_timer_csr_aliasing | 0.830s | 35.889us | 5 | 5 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | rv_timer_csr_mem_rw_with_rand_reset | 1.480s | 57.466us | 20 | 20 | 100.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | rv_timer_csr_rw | 0.630s | 17.110us | 20 | 20 | 100.00 |
| rv_timer_csr_aliasing | 0.830s | 35.889us | 5 | 5 | 100.00 | ||
| V1 | TOTAL | 254 | 255 | 99.61 | |||
| V2 | random_reset | rv_timer_random_reset | 23.727m | 47.029ms | 50 | 50 | 100.00 |
| V2 | disabled | rv_timer_disabled | 6.653m | 882.686ms | 46 | 50 | 92.00 |
| V2 | cfg_update_on_fly | rv_timer_cfg_update_on_fly | 17.943m | 3.915s | 50 | 50 | 100.00 |
| V2 | no_interrupt_test | rv_timer_cfg_update_on_fly | 17.943m | 3.915s | 50 | 50 | 100.00 |
| V2 | stress | rv_timer_stress_all | 1.123h | 1.430s | 50 | 50 | 100.00 |
| V2 | intr_test | rv_timer_intr_test | 0.590s | 14.152us | 50 | 50 | 100.00 |
| V2 | tl_d_oob_addr_access | rv_timer_tl_errors | 3.380s | 180.544us | 20 | 20 | 100.00 |
| V2 | tl_d_illegal_access | rv_timer_tl_errors | 3.380s | 180.544us | 20 | 20 | 100.00 |
| V2 | tl_d_outstanding_access | rv_timer_csr_hw_reset | 0.660s | 67.152us | 5 | 5 | 100.00 |
| rv_timer_csr_rw | 0.630s | 17.110us | 20 | 20 | 100.00 | ||
| rv_timer_csr_aliasing | 0.830s | 35.889us | 5 | 5 | 100.00 | ||
| rv_timer_same_csr_outstanding | 0.840s | 38.482us | 20 | 20 | 100.00 | ||
| V2 | tl_d_partial_access | rv_timer_csr_hw_reset | 0.660s | 67.152us | 5 | 5 | 100.00 |
| rv_timer_csr_rw | 0.630s | 17.110us | 20 | 20 | 100.00 | ||
| rv_timer_csr_aliasing | 0.830s | 35.889us | 5 | 5 | 100.00 | ||
| rv_timer_same_csr_outstanding | 0.840s | 38.482us | 20 | 20 | 100.00 | ||
| V2 | TOTAL | 286 | 290 | 98.62 | |||
| V2S | tl_intg_err | rv_timer_sec_cm | 0.960s | 238.334us | 5 | 5 | 100.00 |
| rv_timer_tl_intg_err | 1.340s | 452.113us | 20 | 20 | 100.00 | ||
| V2S | sec_cm_bus_integrity | rv_timer_tl_intg_err | 1.340s | 452.113us | 20 | 20 | 100.00 |
| V2S | TOTAL | 25 | 25 | 100.00 | |||
| V3 | stress_all_with_rand_reset | rv_timer_stress_all_with_rand_reset | 37.653m | 165.574ms | 8 | 50 | 16.00 |
| V3 | TOTAL | 8 | 50 | 16.00 | |||
| TOTAL | 573 | 620 | 92.42 |
| Items | Total | Written | Passing | Progress |
|---|---|---|---|---|
| V1 | 6 | 6 | 5 | 83.33 |
| V2 | 7 | 7 | 6 | 85.71 |
| V2S | 2 | 2 | 2 | 100.00 |
| V3 | 1 | 1 | 0 | 0.00 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
|---|---|---|---|---|---|---|---|
| 99.62 | 99.36 | 98.73 | 100.00 | -- | 100.00 | 100.00 | 99.66 |
UVM_ERROR (cip_base_vseq.sv:825) [rv_timer_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 42 failures:
0.rv_timer_stress_all_with_rand_reset.115125988718305661743400963950283338712752635723617140816547062232386140507091
Line 323, in log /container/opentitan-public/scratch/os_regression/rv_timer-sim-vcs/0.rv_timer_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 121973075977 ps: (cip_base_vseq.sv:825) [uvm_test_top.env.virtual_sequencer.rv_timer_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 121973075977 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.rv_timer_stress_all_with_rand_reset.74698200414861279637066480022108809801667329332060981615789817341154065029242
Line 981, in log /container/opentitan-public/scratch/os_regression/rv_timer-sim-vcs/1.rv_timer_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 71822085910 ps: (cip_base_vseq.sv:825) [uvm_test_top.env.virtual_sequencer.rv_timer_common_vseq] Check failed (!has_outstanding_access()) Waited 10023 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 71822085910 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 40 more failures.
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 4 failures:
11.rv_timer_disabled.114723488955978197428105530937371293566668098887511266582637914591898812328884
Line 250, in log /container/opentitan-public/scratch/os_regression/rv_timer-sim-vcs/11.rv_timer_disabled/latest/run.log
UVM_FATAL @ 1000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 1000000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 1000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
24.rv_timer_disabled.104307457054141784504883343076449463723952860830476849536225396048720017293674
Line 251, in log /container/opentitan-public/scratch/os_regression/rv_timer-sim-vcs/24.rv_timer_disabled/latest/run.log
UVM_FATAL @ 1000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 1000000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 1000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 2 more failures.
Job rv_timer-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 1 failures:
63.rv_timer_random.61684637449851027808810750098665922079823893682544518103368040507841246105859
Log /container/opentitan-public/scratch/os_regression/rv_timer-sim-vcs/63.rv_timer_random/latest/run.log
Job ID: smart:7b894855-1c23-4eb8-986d-26ab9eb17b78