aad711e1bc| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | random | rv_timer_random | 49.351m | 565.752ms | 200 | 200 | 100.00 |
| V1 | csr_hw_reset | rv_timer_csr_hw_reset | 0.640s | 22.716us | 5 | 5 | 100.00 |
| V1 | csr_rw | rv_timer_csr_rw | 0.640s | 13.723us | 20 | 20 | 100.00 |
| V1 | csr_bit_bash | rv_timer_csr_bit_bash | 3.500s | 291.227us | 5 | 5 | 100.00 |
| V1 | csr_aliasing | rv_timer_csr_aliasing | 0.740s | 182.019us | 5 | 5 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | rv_timer_csr_mem_rw_with_rand_reset | 1.460s | 189.895us | 20 | 20 | 100.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | rv_timer_csr_rw | 0.640s | 13.723us | 20 | 20 | 100.00 |
| rv_timer_csr_aliasing | 0.740s | 182.019us | 5 | 5 | 100.00 | ||
| V1 | TOTAL | 255 | 255 | 100.00 | |||
| V2 | random_reset | rv_timer_random_reset | 8.666m | 218.008ms | 50 | 50 | 100.00 |
| V2 | disabled | rv_timer_disabled | 4.951m | 461.298ms | 47 | 50 | 94.00 |
| V2 | cfg_update_on_fly | rv_timer_cfg_update_on_fly | 30.610m | 1.060s | 50 | 50 | 100.00 |
| V2 | no_interrupt_test | rv_timer_cfg_update_on_fly | 30.610m | 1.060s | 50 | 50 | 100.00 |
| V2 | stress | rv_timer_stress_all | 1.404h | 525.637ms | 50 | 50 | 100.00 |
| V2 | intr_test | rv_timer_intr_test | 0.670s | 29.789us | 50 | 50 | 100.00 |
| V2 | tl_d_oob_addr_access | rv_timer_tl_errors | 2.950s | 238.216us | 20 | 20 | 100.00 |
| V2 | tl_d_illegal_access | rv_timer_tl_errors | 2.950s | 238.216us | 20 | 20 | 100.00 |
| V2 | tl_d_outstanding_access | rv_timer_csr_hw_reset | 0.640s | 22.716us | 5 | 5 | 100.00 |
| rv_timer_csr_rw | 0.640s | 13.723us | 20 | 20 | 100.00 | ||
| rv_timer_csr_aliasing | 0.740s | 182.019us | 5 | 5 | 100.00 | ||
| rv_timer_same_csr_outstanding | 0.850s | 43.025us | 20 | 20 | 100.00 | ||
| V2 | tl_d_partial_access | rv_timer_csr_hw_reset | 0.640s | 22.716us | 5 | 5 | 100.00 |
| rv_timer_csr_rw | 0.640s | 13.723us | 20 | 20 | 100.00 | ||
| rv_timer_csr_aliasing | 0.740s | 182.019us | 5 | 5 | 100.00 | ||
| rv_timer_same_csr_outstanding | 0.850s | 43.025us | 20 | 20 | 100.00 | ||
| V2 | TOTAL | 287 | 290 | 98.97 | |||
| V2S | tl_intg_err | rv_timer_sec_cm | 1.010s | 1.006ms | 5 | 5 | 100.00 |
| rv_timer_tl_intg_err | 1.360s | 134.856us | 20 | 20 | 100.00 | ||
| V2S | sec_cm_bus_integrity | rv_timer_tl_intg_err | 1.360s | 134.856us | 20 | 20 | 100.00 |
| V2S | TOTAL | 25 | 25 | 100.00 | |||
| V3 | stress_all_with_rand_reset | rv_timer_stress_all_with_rand_reset | 17.785m | 147.140ms | 18 | 50 | 36.00 |
| V3 | TOTAL | 18 | 50 | 36.00 | |||
| TOTAL | 585 | 620 | 94.35 |
| Items | Total | Written | Passing | Progress |
|---|---|---|---|---|
| V1 | 6 | 6 | 6 | 100.00 |
| V2 | 7 | 7 | 6 | 85.71 |
| V2S | 2 | 2 | 2 | 100.00 |
| V3 | 1 | 1 | 0 | 0.00 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
|---|---|---|---|---|---|---|---|
| 99.62 | 99.36 | 98.73 | 100.00 | -- | 100.00 | 100.00 | 99.66 |
UVM_ERROR (cip_base_vseq.sv:825) [rv_timer_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 32 failures:
1.rv_timer_stress_all_with_rand_reset.42058376061235592327790316137068496933458160450953614678860760477213118269608
Line 370, in log /container/opentitan-public/scratch/os_regression/rv_timer-sim-vcs/1.rv_timer_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 11063800513 ps: (cip_base_vseq.sv:825) [uvm_test_top.env.virtual_sequencer.rv_timer_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 11063800513 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
2.rv_timer_stress_all_with_rand_reset.88766383007196952397940440118780479173894776241128757418247237048478350406281
Line 604, in log /container/opentitan-public/scratch/os_regression/rv_timer-sim-vcs/2.rv_timer_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 65078803960 ps: (cip_base_vseq.sv:825) [uvm_test_top.env.virtual_sequencer.rv_timer_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 65078803960 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 30 more failures.
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 3 failures:
21.rv_timer_disabled.15700076549051675026146909947284035995212971084249640842256142182370673663469
Line 252, in log /container/opentitan-public/scratch/os_regression/rv_timer-sim-vcs/21.rv_timer_disabled/latest/run.log
UVM_FATAL @ 1000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 1000000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 1000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
26.rv_timer_disabled.272987926090346073462437441725969592245525995282468346055964163568001723091
Line 253, in log /container/opentitan-public/scratch/os_regression/rv_timer-sim-vcs/26.rv_timer_disabled/latest/run.log
UVM_FATAL @ 1000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 1000000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 1000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.