RV_TIMER Simulation Results

Sunday July 14 2024 23:02:31 UTC

GitHub Revision: `c04cc5d074`

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 63544391231451201456762274895161998707503467555380647510071702152169450996489

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	random	rv_timer_random	58.855m	1.173s	200	200	100.00
V1	csr_hw_reset	rv_timer_csr_hw_reset	0.630s	44.774us	5	5	100.00
V1	csr_rw	rv_timer_csr_rw	0.690s	31.029us	20	20	100.00
V1	csr_bit_bash	rv_timer_csr_bit_bash	2.680s	277.438us	5	5	100.00
V1	csr_aliasing	rv_timer_csr_aliasing	0.820s	83.943us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	rv_timer_csr_mem_rw_with_rand_reset	1.420s	85.354us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	rv_timer_csr_rw	0.690s	31.029us	20	20	100.00
		rv_timer_csr_aliasing	0.820s	83.943us	5	5	100.00
V1		TOTAL			255	255	100.00
V2	random_reset	rv_timer_random_reset	20.189m	206.171ms	50	50	100.00
V2	disabled	rv_timer_disabled	5.113m	386.239ms	47	50	94.00
V2	cfg_update_on_fly	rv_timer_cfg_update_on_fly	24.807m	6.117s	50	50	100.00
V2	no_interrupt_test	rv_timer_cfg_update_on_fly	24.807m	6.117s	50	50	100.00
V2	stress	rv_timer_stress_all	1.731h	4.033s	50	50	100.00
V2	intr_test	rv_timer_intr_test	0.660s	14.766us	50	50	100.00
V2	tl_d_oob_addr_access	rv_timer_tl_errors	2.960s	205.799us	20	20	100.00
V2	tl_d_illegal_access	rv_timer_tl_errors	2.960s	205.799us	20	20	100.00
V2	tl_d_outstanding_access	rv_timer_csr_hw_reset	0.630s	44.774us	5	5	100.00
		rv_timer_csr_rw	0.690s	31.029us	20	20	100.00
		rv_timer_csr_aliasing	0.820s	83.943us	5	5	100.00
		rv_timer_same_csr_outstanding	0.850s	113.451us	20	20	100.00
V2	tl_d_partial_access	rv_timer_csr_hw_reset	0.630s	44.774us	5	5	100.00
		rv_timer_csr_rw	0.690s	31.029us	20	20	100.00
		rv_timer_csr_aliasing	0.820s	83.943us	5	5	100.00
		rv_timer_same_csr_outstanding	0.850s	113.451us	20	20	100.00
V2		TOTAL			287	290	98.97
V2S	tl_intg_err	rv_timer_sec_cm	0.940s	58.946us	5	5	100.00
		rv_timer_tl_intg_err	1.420s	418.951us	20	20	100.00
V2S	sec_cm_bus_integrity	rv_timer_tl_intg_err	1.420s	418.951us	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	rv_timer_stress_all_with_rand_reset	31.817m	170.116ms	12	50	24.00
V3		TOTAL			12	50	24.00
		TOTAL			579	620	93.39

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	7	7	6	85.71
V2S	2	2	2	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
99.57	99.36	98.73	100.00	--	100.00	100.00	99.32

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:825) [rv_timer_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 37 failures:
- Test rv_timer_stress_all_with_rand_reset has 37 failures.
  - 1.rv_timer_stress_all_with_rand_reset.26230509001356789648679047583140520586598140626888647551204668606220875183205
    Line 361, in log /container/opentitan-public/scratch/os_regression/rv_timer-sim-vcs/1.rv_timer_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 56529531923 ps: (cip_base_vseq.sv:825) [uvm_test_top.env.virtual_sequencer.rv_timer_common_vseq] Check failed (!has_outstanding_access()) Waited 10001 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 56529531923 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 2.rv_timer_stress_all_with_rand_reset.44271708998968402307135904818616674692672459016254833486666652699035963888446
    Line 582, in log /container/opentitan-public/scratch/os_regression/rv_timer-sim-vcs/2.rv_timer_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 113800751631 ps: (cip_base_vseq.sv:825) [uvm_test_top.env.virtual_sequencer.rv_timer_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 113800751631 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 35 more failures.
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 3 failures:
- Test rv_timer_disabled has 3 failures.
  - 1.rv_timer_disabled.86806160651997564668520797409076751852925177537906997319119436446560881153003
    Line 252, in log /container/opentitan-public/scratch/os_regression/rv_timer-sim-vcs/1.rv_timer_disabled/latest/run.log
```
  UVM_FATAL @ 1000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 1000000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 1000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 2.rv_timer_disabled.47338119578288055541029683029445907115120883205242047197465826134354796282159
    Line 252, in log /container/opentitan-public/scratch/os_regression/rv_timer-sim-vcs/2.rv_timer_disabled/latest/run.log
```
  UVM_FATAL @ 1000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 1000000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 1000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 1 more failures.
UVM_ERROR (cip_base_vseq.sv:749) [rv_timer_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. has 1 failures:
- Test rv_timer_stress_all_with_rand_reset has 1 failures.
  - 20.rv_timer_stress_all_with_rand_reset.55753238154083415490496535690075103889072700426096122729600427202625009017230
    Line 368, in log /container/opentitan-public/scratch/os_regression/rv_timer-sim-vcs/20.rv_timer_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 24715588459 ps: (cip_base_vseq.sv:749) [uvm_test_top.env.virtual_sequencer.rv_timer_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
  UVM_INFO @ 24715588459 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

RV_TIMER Simulation Results

Sunday July 14 2024 23:02:31 UTC

GitHub Revision: c04cc5d074

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 63544391231451201456762274895161998707503467555380647510071702152169450996489

Test Results

Testplan Progress

Coverage Results

Coverage Dashboard

Failure Buckets

Past Results

GitHub Revision: `c04cc5d074`