RV_TIMER Simulation Results

Wednesday July 17 2024 23:02:16 UTC

GitHub Revision: 8b2da8db5e

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 31877364624131593519988921539075110140045739991215723614576185349550879231344

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 random rv_timer_random 45.653m 1.903s 200 200 100.00
V1 csr_hw_reset rv_timer_csr_hw_reset 0.610s 32.505us 5 5 100.00
V1 csr_rw rv_timer_csr_rw 0.650s 19.867us 20 20 100.00
V1 csr_bit_bash rv_timer_csr_bit_bash 3.700s 1.181ms 5 5 100.00
V1 csr_aliasing rv_timer_csr_aliasing 0.880s 476.083us 5 5 100.00
V1 csr_mem_rw_with_rand_reset rv_timer_csr_mem_rw_with_rand_reset 1.410s 105.249us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr rv_timer_csr_rw 0.650s 19.867us 20 20 100.00
rv_timer_csr_aliasing 0.880s 476.083us 5 5 100.00
V1 TOTAL 255 255 100.00
V2 random_reset rv_timer_random_reset 19.601m 33.798ms 49 50 98.00
V2 disabled rv_timer_disabled 4.695m 910.844ms 46 50 92.00
V2 cfg_update_on_fly rv_timer_cfg_update_on_fly 17.203m 2.332s 50 50 100.00
V2 no_interrupt_test rv_timer_cfg_update_on_fly 17.203m 2.332s 50 50 100.00
V2 stress rv_timer_stress_all 1.460h 591.752ms 50 50 100.00
V2 intr_test rv_timer_intr_test 0.600s 72.194us 50 50 100.00
V2 tl_d_oob_addr_access rv_timer_tl_errors 3.400s 719.773us 20 20 100.00
V2 tl_d_illegal_access rv_timer_tl_errors 3.400s 719.773us 20 20 100.00
V2 tl_d_outstanding_access rv_timer_csr_hw_reset 0.610s 32.505us 5 5 100.00
rv_timer_csr_rw 0.650s 19.867us 20 20 100.00
rv_timer_csr_aliasing 0.880s 476.083us 5 5 100.00
rv_timer_same_csr_outstanding 0.830s 164.766us 20 20 100.00
V2 tl_d_partial_access rv_timer_csr_hw_reset 0.610s 32.505us 5 5 100.00
rv_timer_csr_rw 0.650s 19.867us 20 20 100.00
rv_timer_csr_aliasing 0.880s 476.083us 5 5 100.00
rv_timer_same_csr_outstanding 0.830s 164.766us 20 20 100.00
V2 TOTAL 285 290 98.28
V2S tl_intg_err rv_timer_sec_cm 0.950s 759.021us 5 5 100.00
rv_timer_tl_intg_err 1.510s 206.318us 20 20 100.00
V2S sec_cm_bus_integrity rv_timer_tl_intg_err 1.510s 206.318us 20 20 100.00
V2S TOTAL 25 25 100.00
V3 stress_all_with_rand_reset rv_timer_stress_all_with_rand_reset 17.612m 220.046ms 15 50 30.00
V3 TOTAL 15 50 30.00
TOTAL 580 620 93.55

Testplan Progress

Items Total Written Passing Progress
V1 6 6 6 100.00
V2 7 7 5 71.43
V2S 2 2 2 100.00
V3 1 1 0 0.00

Coverage Results

Coverage Dashboard

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
99.57 99.36 98.73 100.00 -- 100.00 100.00 99.32

Failure Buckets

Past Results