RV_TIMER Simulation Results

Thursday August 01 2024 23:02:20 UTC

GitHub Revision: `625f353e9c`

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 85273092133191575795496895645039765542965103003083525273509664765586668778052

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	random	rv_timer_random	54.726m	227.765ms	200	200	100.00
V1	csr_hw_reset	rv_timer_csr_hw_reset	0.600s	16.478us	5	5	100.00
V1	csr_rw	rv_timer_csr_rw	0.610s	47.989us	20	20	100.00
V1	csr_bit_bash	rv_timer_csr_bit_bash	3.450s	1.248ms	5	5	100.00
V1	csr_aliasing	rv_timer_csr_aliasing	0.820s	33.403us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	rv_timer_csr_mem_rw_with_rand_reset	1.090s	112.076us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	rv_timer_csr_rw	0.610s	47.989us	20	20	100.00
		rv_timer_csr_aliasing	0.820s	33.403us	5	5	100.00
V1		TOTAL			255	255	100.00
V2	random_reset	rv_timer_random_reset	30.988m	238.770ms	50	50	100.00
V2	disabled	rv_timer_disabled	4.950m	737.090ms	46	50	92.00
V2	cfg_update_on_fly	rv_timer_cfg_update_on_fly	38.093m	3.933s	50	50	100.00
V2	no_interrupt_test	rv_timer_cfg_update_on_fly	38.093m	3.933s	50	50	100.00
V2	stress	rv_timer_stress_all	48.856m	1.194s	50	50	100.00
V2	intr_test	rv_timer_intr_test	0.630s	19.179us	50	50	100.00
V2	tl_d_oob_addr_access	rv_timer_tl_errors	2.830s	112.810us	20	20	100.00
V2	tl_d_illegal_access	rv_timer_tl_errors	2.830s	112.810us	20	20	100.00
V2	tl_d_outstanding_access	rv_timer_csr_hw_reset	0.600s	16.478us	5	5	100.00
		rv_timer_csr_rw	0.610s	47.989us	20	20	100.00
		rv_timer_csr_aliasing	0.820s	33.403us	5	5	100.00
		rv_timer_same_csr_outstanding	0.830s	97.057us	20	20	100.00
V2	tl_d_partial_access	rv_timer_csr_hw_reset	0.600s	16.478us	5	5	100.00
		rv_timer_csr_rw	0.610s	47.989us	20	20	100.00
		rv_timer_csr_aliasing	0.820s	33.403us	5	5	100.00
		rv_timer_same_csr_outstanding	0.830s	97.057us	20	20	100.00
V2		TOTAL			286	290	98.62
V2S	tl_intg_err	rv_timer_sec_cm	0.910s	173.387us	5	5	100.00
		rv_timer_tl_intg_err	1.430s	605.121us	20	20	100.00
V2S	sec_cm_bus_integrity	rv_timer_tl_intg_err	1.430s	605.121us	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	rv_timer_stress_all_with_rand_reset	23.131m	136.779ms	13	50	26.00
V3		TOTAL			13	50	26.00
		TOTAL			579	620	93.39

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	7	7	6	85.71
V2S	2	2	2	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
99.57	99.36	98.73	100.00	--	100.00	100.00	99.32

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:836) [rv_timer_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 35 failures:
- Test rv_timer_stress_all_with_rand_reset has 35 failures.
  - 0.rv_timer_stress_all_with_rand_reset.57744919547337500652034770329903422132185101998824175770757244301639610420359
    Line 546, in log /container/opentitan-public/scratch/os_regression/rv_timer-sim-vcs/0.rv_timer_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 56834324097 ps: (cip_base_vseq.sv:836) [uvm_test_top.env.virtual_sequencer.rv_timer_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 56834324097 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 1.rv_timer_stress_all_with_rand_reset.72133873992145888501703054396889064535844863202505959980110958412353542970870
    Line 328, in log /container/opentitan-public/scratch/os_regression/rv_timer-sim-vcs/1.rv_timer_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 111629193353 ps: (cip_base_vseq.sv:836) [uvm_test_top.env.virtual_sequencer.rv_timer_common_vseq] Check failed (!has_outstanding_access()) Waited 10021 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 111629193353 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 33 more failures.
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 4 failures:
- Test rv_timer_disabled has 4 failures.
  - 1.rv_timer_disabled.9879505978739046560695972860187292703236643103006323200280824240241867467295
    Line 253, in log /container/opentitan-public/scratch/os_regression/rv_timer-sim-vcs/1.rv_timer_disabled/latest/run.log
```
  UVM_FATAL @ 1000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 1000000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 1000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 7.rv_timer_disabled.55281593930329714578758319684919604028680683750105962543019511261167406533998
    Line 252, in log /container/opentitan-public/scratch/os_regression/rv_timer-sim-vcs/7.rv_timer_disabled/latest/run.log
```
  UVM_FATAL @ 1000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 1000000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 1000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 2 more failures.
UVM_ERROR (cip_base_vseq.sv:755) [rv_timer_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. has 2 failures:
- Test rv_timer_stress_all_with_rand_reset has 2 failures.
  - 24.rv_timer_stress_all_with_rand_reset.66015543448885611841047856927624299327325269113170225242106273021262502919979
    Line 1023, in log /container/opentitan-public/scratch/os_regression/rv_timer-sim-vcs/24.rv_timer_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 89884327209 ps: (cip_base_vseq.sv:755) [uvm_test_top.env.virtual_sequencer.rv_timer_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
  UVM_INFO @ 89884327209 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 42.rv_timer_stress_all_with_rand_reset.346335695931457632922633877056069215800138978761725854985066379565842283424
    Line 362, in log /container/opentitan-public/scratch/os_regression/rv_timer-sim-vcs/42.rv_timer_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 9488744657 ps: (cip_base_vseq.sv:755) [uvm_test_top.env.virtual_sequencer.rv_timer_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
  UVM_INFO @ 9488744657 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

RV_TIMER Simulation Results

Thursday August 01 2024 23:02:20 UTC

GitHub Revision: 625f353e9c

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 85273092133191575795496895645039765542965103003083525273509664765586668778052

Test Results

Testplan Progress

Coverage Results

Coverage Dashboard

Failure Buckets

Past Results

GitHub Revision: `625f353e9c`