f1535c5540| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | random | rv_timer_random | 46.525m | 483.036ms | 200 | 200 | 100.00 |
| V1 | csr_hw_reset | rv_timer_csr_hw_reset | 0.650s | 57.776us | 5 | 5 | 100.00 |
| V1 | csr_rw | rv_timer_csr_rw | 0.610s | 40.711us | 20 | 20 | 100.00 |
| V1 | csr_bit_bash | rv_timer_csr_bit_bash | 3.570s | 294.443us | 5 | 5 | 100.00 |
| V1 | csr_aliasing | rv_timer_csr_aliasing | 0.850s | 33.829us | 5 | 5 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | rv_timer_csr_mem_rw_with_rand_reset | 1.780s | 145.969us | 20 | 20 | 100.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | rv_timer_csr_rw | 0.610s | 40.711us | 20 | 20 | 100.00 |
| rv_timer_csr_aliasing | 0.850s | 33.829us | 5 | 5 | 100.00 | ||
| V1 | TOTAL | 255 | 255 | 100.00 | |||
| V2 | random_reset | rv_timer_random_reset | 18.533m | 177.243ms | 49 | 50 | 98.00 |
| V2 | disabled | rv_timer_disabled | 4.911m | 388.570ms | 48 | 50 | 96.00 |
| V2 | cfg_update_on_fly | rv_timer_cfg_update_on_fly | 18.527m | 5.102s | 50 | 50 | 100.00 |
| V2 | no_interrupt_test | rv_timer_cfg_update_on_fly | 18.527m | 5.102s | 50 | 50 | 100.00 |
| V2 | stress | rv_timer_stress_all | 57.168m | 872.262ms | 50 | 50 | 100.00 |
| V2 | intr_test | rv_timer_intr_test | 0.630s | 15.771us | 50 | 50 | 100.00 |
| V2 | tl_d_oob_addr_access | rv_timer_tl_errors | 3.560s | 669.161us | 20 | 20 | 100.00 |
| V2 | tl_d_illegal_access | rv_timer_tl_errors | 3.560s | 669.161us | 20 | 20 | 100.00 |
| V2 | tl_d_outstanding_access | rv_timer_csr_hw_reset | 0.650s | 57.776us | 5 | 5 | 100.00 |
| rv_timer_csr_rw | 0.610s | 40.711us | 20 | 20 | 100.00 | ||
| rv_timer_csr_aliasing | 0.850s | 33.829us | 5 | 5 | 100.00 | ||
| rv_timer_same_csr_outstanding | 0.890s | 46.276us | 20 | 20 | 100.00 | ||
| V2 | tl_d_partial_access | rv_timer_csr_hw_reset | 0.650s | 57.776us | 5 | 5 | 100.00 |
| rv_timer_csr_rw | 0.610s | 40.711us | 20 | 20 | 100.00 | ||
| rv_timer_csr_aliasing | 0.850s | 33.829us | 5 | 5 | 100.00 | ||
| rv_timer_same_csr_outstanding | 0.890s | 46.276us | 20 | 20 | 100.00 | ||
| V2 | TOTAL | 287 | 290 | 98.97 | |||
| V2S | tl_intg_err | rv_timer_sec_cm | 0.960s | 322.546us | 5 | 5 | 100.00 |
| rv_timer_tl_intg_err | 1.870s | 500.476us | 20 | 20 | 100.00 | ||
| V2S | sec_cm_bus_integrity | rv_timer_tl_intg_err | 1.870s | 500.476us | 20 | 20 | 100.00 |
| V2S | TOTAL | 25 | 25 | 100.00 | |||
| V3 | stress_all_with_rand_reset | rv_timer_stress_all_with_rand_reset | 1.308m | 6.740ms | 15 | 50 | 30.00 |
| V3 | TOTAL | 15 | 50 | 30.00 | |||
| TOTAL | 582 | 620 | 93.87 |
| Items | Total | Written | Passing | Progress |
|---|---|---|---|---|
| V1 | 6 | 6 | 6 | 100.00 |
| V2 | 7 | 7 | 5 | 71.43 |
| V2S | 2 | 2 | 2 | 100.00 |
| V3 | 1 | 1 | 0 | 0.00 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
|---|---|---|---|---|---|---|---|
| 99.66 | 99.36 | 99.04 | 100.00 | -- | 100.00 | 100.00 | 99.55 |
UVM_ERROR (cip_base_vseq.sv:867) [rv_timer_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 34 failures:
2.rv_timer_stress_all_with_rand_reset.86314287829848023193712551563391541304234535762838941356685431619158175389858
Line 260, in log /container/opentitan-public/scratch/os_regression/rv_timer-sim-vcs/2.rv_timer_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 3709863777 ps: (cip_base_vseq.sv:867) [uvm_test_top.env.virtual_sequencer.rv_timer_common_vseq] Check failed (!has_outstanding_access()) Waited 10011 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 3709863777 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
3.rv_timer_stress_all_with_rand_reset.99417405719760686265331005540041071225579794660946410962242594664622483650893
Line 255, in log /container/opentitan-public/scratch/os_regression/rv_timer-sim-vcs/3.rv_timer_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 11234884447 ps: (cip_base_vseq.sv:867) [uvm_test_top.env.virtual_sequencer.rv_timer_common_vseq] Check failed (!has_outstanding_access()) Waited 10010 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 11234884447 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 32 more failures.
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 3 failures:
Test rv_timer_disabled has 2 failures.
6.rv_timer_disabled.32223589391064799459059007704153563552719641839487650594715872514809004574767
Line 252, in log /container/opentitan-public/scratch/os_regression/rv_timer-sim-vcs/6.rv_timer_disabled/latest/run.log
UVM_FATAL @ 1000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 1000000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 1000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
9.rv_timer_disabled.13060497915810020951882670111543238121708136321109716213985959106680507109662
Line 252, in log /container/opentitan-public/scratch/os_regression/rv_timer-sim-vcs/9.rv_timer_disabled/latest/run.log
UVM_FATAL @ 1000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 1000000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 1000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test rv_timer_random_reset has 1 failures.
27.rv_timer_random_reset.87346367032177988638634282465765971864137491272099537679851998199536103058801
Line 253, in log /container/opentitan-public/scratch/os_regression/rv_timer-sim-vcs/27.rv_timer_random_reset/latest/run.log
UVM_FATAL @ 1000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 1000000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 1000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:771) [rv_timer_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. has 1 failures:
39.rv_timer_stress_all_with_rand_reset.100559582980129447029860129057213905550959068150140923114505812906593136416954
Line 288, in log /container/opentitan-public/scratch/os_regression/rv_timer-sim-vcs/39.rv_timer_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 4613111286 ps: (cip_base_vseq.sv:771) [uvm_test_top.env.virtual_sequencer.rv_timer_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
UVM_INFO @ 4613111286 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---