RV_TIMER Simulation Results

Friday August 16 2024 23:02:10 UTC

GitHub Revision: `76588857da`

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 107397868712693014844033025164446565408841343499325418676943424680076749785789

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	random	rv_timer_random	51.167m	150.350ms	200	200	100.00
V1	csr_hw_reset	rv_timer_csr_hw_reset	0.620s	19.055us	5	5	100.00
V1	csr_rw	rv_timer_csr_rw	0.620s	34.908us	20	20	100.00
V1	csr_bit_bash	rv_timer_csr_bit_bash	3.640s	530.326us	5	5	100.00
V1	csr_aliasing	rv_timer_csr_aliasing	0.820s	17.202us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	rv_timer_csr_mem_rw_with_rand_reset	1.420s	31.868us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	rv_timer_csr_rw	0.620s	34.908us	20	20	100.00
		rv_timer_csr_aliasing	0.820s	17.202us	5	5	100.00
V1		TOTAL			255	255	100.00
V2	random_reset	rv_timer_random_reset	12.406m	44.657ms	49	50	98.00
V2	disabled	rv_timer_disabled	5.093m	691.503ms	48	50	96.00
V2	cfg_update_on_fly	rv_timer_cfg_update_on_fly	39.863m	4.008s	50	50	100.00
V2	no_interrupt_test	rv_timer_cfg_update_on_fly	39.863m	4.008s	50	50	100.00
V2	stress	rv_timer_stress_all	1.117h	1.555s	50	50	100.00
V2	intr_test	rv_timer_intr_test	0.650s	12.053us	50	50	100.00
V2	tl_d_oob_addr_access	rv_timer_tl_errors	3.480s	589.374us	20	20	100.00
V2	tl_d_illegal_access	rv_timer_tl_errors	3.480s	589.374us	20	20	100.00
V2	tl_d_outstanding_access	rv_timer_csr_hw_reset	0.620s	19.055us	5	5	100.00
		rv_timer_csr_rw	0.620s	34.908us	20	20	100.00
		rv_timer_csr_aliasing	0.820s	17.202us	5	5	100.00
		rv_timer_same_csr_outstanding	0.890s	49.617us	20	20	100.00
V2	tl_d_partial_access	rv_timer_csr_hw_reset	0.620s	19.055us	5	5	100.00
		rv_timer_csr_rw	0.620s	34.908us	20	20	100.00
		rv_timer_csr_aliasing	0.820s	17.202us	5	5	100.00
		rv_timer_same_csr_outstanding	0.890s	49.617us	20	20	100.00
V2		TOTAL			287	290	98.97
V2S	tl_intg_err	rv_timer_sec_cm	0.910s	85.956us	5	5	100.00
		rv_timer_tl_intg_err	1.440s	378.720us	20	20	100.00
V2S	sec_cm_bus_integrity	rv_timer_tl_intg_err	1.440s	378.720us	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	rv_timer_stress_all_with_rand_reset	1.012m	21.569ms	14	50	28.00
V3		TOTAL			14	50	28.00
		TOTAL			581	620	93.71

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	7	7	5	71.43
V2S	2	2	2	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
99.58	99.36	99.04	100.00	--	100.00	100.00	99.09

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:867) [rv_timer_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 35 failures:
- Test rv_timer_stress_all_with_rand_reset has 35 failures.
  - 0.rv_timer_stress_all_with_rand_reset.15799142402539485148157931862061176888367522272744028728171417686259297068248
    Line 272, in log /container/opentitan-public/scratch/os_regression/rv_timer-sim-vcs/0.rv_timer_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 1945610242 ps: (cip_base_vseq.sv:867) [uvm_test_top.env.virtual_sequencer.rv_timer_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 1945610242 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 2.rv_timer_stress_all_with_rand_reset.112916748740681232440675632100315179098508424502510676889351971982949404638445
    Line 426, in log /container/opentitan-public/scratch/os_regression/rv_timer-sim-vcs/2.rv_timer_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 7919161706 ps: (cip_base_vseq.sv:867) [uvm_test_top.env.virtual_sequencer.rv_timer_common_vseq] Check failed (!has_outstanding_access()) Waited 10005 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 7919161706 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 33 more failures.
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 3 failures:
- Test rv_timer_random_reset has 1 failures.
  - 7.rv_timer_random_reset.41215078041838175104330635141300960024206317528603579352968919979309197765817
    Line 254, in log /container/opentitan-public/scratch/os_regression/rv_timer-sim-vcs/7.rv_timer_random_reset/latest/run.log
```
  UVM_FATAL @ 1000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 1000000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 1000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rv_timer_disabled has 2 failures.
  - 21.rv_timer_disabled.40496536326805959587082611151417478217890750980739497175686935064742911481472
    Line 253, in log /container/opentitan-public/scratch/os_regression/rv_timer-sim-vcs/21.rv_timer_disabled/latest/run.log
```
  UVM_FATAL @ 1000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 1000000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 1000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 47.rv_timer_disabled.1236933567300580500947293234249541304047740717549460034863574688481903066940
    Line 252, in log /container/opentitan-public/scratch/os_regression/rv_timer-sim-vcs/47.rv_timer_disabled/latest/run.log
```
  UVM_FATAL @ 1000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 1000000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 1000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (cip_base_vseq.sv:771) [rv_timer_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. has 1 failures:
- Test rv_timer_stress_all_with_rand_reset has 1 failures.
  - 46.rv_timer_stress_all_with_rand_reset.2516623372110992789821691598605866013606181715157117207402381538417280646457
    Line 304, in log /container/opentitan-public/scratch/os_regression/rv_timer-sim-vcs/46.rv_timer_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 2150777216 ps: (cip_base_vseq.sv:771) [uvm_test_top.env.virtual_sequencer.rv_timer_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
  UVM_INFO @ 2150777216 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

RV_TIMER Simulation Results

Friday August 16 2024 23:02:10 UTC

GitHub Revision: 76588857da

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 107397868712693014844033025164446565408841343499325418676943424680076749785789

Test Results

Testplan Progress

Coverage Results

Coverage Dashboard

Failure Buckets

Past Results

GitHub Revision: `76588857da`