584c3d46af| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | random | rv_timer_random | 58.659m | 143.762ms | 200 | 200 | 100.00 |
| V1 | csr_hw_reset | rv_timer_csr_hw_reset | 0.580s | 18.199us | 5 | 5 | 100.00 |
| V1 | csr_rw | rv_timer_csr_rw | 0.640s | 51.230us | 20 | 20 | 100.00 |
| V1 | csr_bit_bash | rv_timer_csr_bit_bash | 3.770s | 421.056us | 5 | 5 | 100.00 |
| V1 | csr_aliasing | rv_timer_csr_aliasing | 0.790s | 38.520us | 5 | 5 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | rv_timer_csr_mem_rw_with_rand_reset | 1.090s | 36.284us | 20 | 20 | 100.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | rv_timer_csr_rw | 0.640s | 51.230us | 20 | 20 | 100.00 |
| rv_timer_csr_aliasing | 0.790s | 38.520us | 5 | 5 | 100.00 | ||
| V1 | TOTAL | 255 | 255 | 100.00 | |||
| V2 | random_reset | rv_timer_random_reset | 7.926m | 260.462ms | 50 | 50 | 100.00 |
| V2 | disabled | rv_timer_disabled | 4.694m | 196.681ms | 47 | 50 | 94.00 |
| V2 | cfg_update_on_fly | rv_timer_cfg_update_on_fly | 31.331m | 5.859s | 50 | 50 | 100.00 |
| V2 | no_interrupt_test | rv_timer_cfg_update_on_fly | 31.331m | 5.859s | 50 | 50 | 100.00 |
| V2 | stress | rv_timer_stress_all | 1.179h | 615.851ms | 50 | 50 | 100.00 |
| V2 | intr_test | rv_timer_intr_test | 0.610s | 14.016us | 50 | 50 | 100.00 |
| V2 | tl_d_oob_addr_access | rv_timer_tl_errors | 2.920s | 634.767us | 20 | 20 | 100.00 |
| V2 | tl_d_illegal_access | rv_timer_tl_errors | 2.920s | 634.767us | 20 | 20 | 100.00 |
| V2 | tl_d_outstanding_access | rv_timer_csr_hw_reset | 0.580s | 18.199us | 5 | 5 | 100.00 |
| rv_timer_csr_rw | 0.640s | 51.230us | 20 | 20 | 100.00 | ||
| rv_timer_csr_aliasing | 0.790s | 38.520us | 5 | 5 | 100.00 | ||
| rv_timer_same_csr_outstanding | 0.820s | 33.970us | 20 | 20 | 100.00 | ||
| V2 | tl_d_partial_access | rv_timer_csr_hw_reset | 0.580s | 18.199us | 5 | 5 | 100.00 |
| rv_timer_csr_rw | 0.640s | 51.230us | 20 | 20 | 100.00 | ||
| rv_timer_csr_aliasing | 0.790s | 38.520us | 5 | 5 | 100.00 | ||
| rv_timer_same_csr_outstanding | 0.820s | 33.970us | 20 | 20 | 100.00 | ||
| V2 | TOTAL | 287 | 290 | 98.97 | |||
| V2S | tl_intg_err | rv_timer_sec_cm | 0.970s | 272.312us | 5 | 5 | 100.00 |
| rv_timer_tl_intg_err | 1.390s | 177.376us | 20 | 20 | 100.00 | ||
| V2S | sec_cm_bus_integrity | rv_timer_tl_intg_err | 1.390s | 177.376us | 20 | 20 | 100.00 |
| V2S | TOTAL | 25 | 25 | 100.00 | |||
| V3 | stress_all_with_rand_reset | rv_timer_stress_all_with_rand_reset | 1.084m | 10.234ms | 17 | 50 | 34.00 |
| V3 | TOTAL | 17 | 50 | 34.00 | |||
| TOTAL | 584 | 620 | 94.19 |
| Items | Total | Written | Passing | Progress |
|---|---|---|---|---|
| V1 | 6 | 6 | 6 | 100.00 |
| V2 | 7 | 7 | 6 | 85.71 |
| V2S | 2 | 2 | 2 | 100.00 |
| V3 | 1 | 1 | 0 | 0.00 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
|---|---|---|---|---|---|---|---|
| 99.62 | 99.36 | 98.73 | 100.00 | -- | 100.00 | 100.00 | 99.66 |
UVM_ERROR (cip_base_vseq.sv:867) [rv_timer_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 33 failures:
1.rv_timer_stress_all_with_rand_reset.54335762469737631027111684454612258717130946641707724807477139683053371336228
Line 281, in log /container/opentitan-public/scratch/os_regression/rv_timer-sim-vcs/1.rv_timer_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 5522525434 ps: (cip_base_vseq.sv:867) [uvm_test_top.env.virtual_sequencer.rv_timer_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 5522525434 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
4.rv_timer_stress_all_with_rand_reset.34793765506583066854430497977916677339915011628896731039948020177997934945087
Line 289, in log /container/opentitan-public/scratch/os_regression/rv_timer-sim-vcs/4.rv_timer_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 1025551647 ps: (cip_base_vseq.sv:867) [uvm_test_top.env.virtual_sequencer.rv_timer_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 1025551647 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 31 more failures.
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 3 failures:
31.rv_timer_disabled.78531075885494234089027104594576945273422748913656631440825574450874648959733
Line 251, in log /container/opentitan-public/scratch/os_regression/rv_timer-sim-vcs/31.rv_timer_disabled/latest/run.log
UVM_FATAL @ 1000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 1000000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 1000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
39.rv_timer_disabled.37880708437612060647566034563636600859190488528133534338156700187918691693521
Line 251, in log /container/opentitan-public/scratch/os_regression/rv_timer-sim-vcs/39.rv_timer_disabled/latest/run.log
UVM_FATAL @ 1000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 1000000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 1000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.