RV_TIMER Simulation Results

Thursday August 15 2024 23:02:21 UTC

GitHub Revision: `d09e282b26`

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 47908880312501934977153450267828796412449789719488445881682136509150457490963

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	random	rv_timer_random	51.391m	160.325ms	199	200	99.50
V1	csr_hw_reset	rv_timer_csr_hw_reset	0.640s	57.017us	5	5	100.00
V1	csr_rw	rv_timer_csr_rw	0.640s	26.965us	20	20	100.00
V1	csr_bit_bash	rv_timer_csr_bit_bash	2.730s	1.043ms	5	5	100.00
V1	csr_aliasing	rv_timer_csr_aliasing	0.860s	34.935us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	rv_timer_csr_mem_rw_with_rand_reset	1.520s	111.192us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	rv_timer_csr_rw	0.640s	26.965us	20	20	100.00
		rv_timer_csr_aliasing	0.860s	34.935us	5	5	100.00
V1		TOTAL			254	255	99.61
V2	random_reset	rv_timer_random_reset	22.084m	136.861ms	50	50	100.00
V2	disabled	rv_timer_disabled	5.501m	211.902ms	48	50	96.00
V2	cfg_update_on_fly	rv_timer_cfg_update_on_fly	27.532m	1.770s	50	50	100.00
V2	no_interrupt_test	rv_timer_cfg_update_on_fly	27.532m	1.770s	50	50	100.00
V2	stress	rv_timer_stress_all	1.942h	5.840s	50	50	100.00
V2	intr_test	rv_timer_intr_test	0.610s	13.091us	50	50	100.00
V2	tl_d_oob_addr_access	rv_timer_tl_errors	2.310s	1.021ms	20	20	100.00
V2	tl_d_illegal_access	rv_timer_tl_errors	2.310s	1.021ms	20	20	100.00
V2	tl_d_outstanding_access	rv_timer_csr_hw_reset	0.640s	57.017us	5	5	100.00
		rv_timer_csr_rw	0.640s	26.965us	20	20	100.00
		rv_timer_csr_aliasing	0.860s	34.935us	5	5	100.00
		rv_timer_same_csr_outstanding	0.840s	34.309us	20	20	100.00
V2	tl_d_partial_access	rv_timer_csr_hw_reset	0.640s	57.017us	5	5	100.00
		rv_timer_csr_rw	0.640s	26.965us	20	20	100.00
		rv_timer_csr_aliasing	0.860s	34.935us	5	5	100.00
		rv_timer_same_csr_outstanding	0.840s	34.309us	20	20	100.00
V2		TOTAL			288	290	99.31
V2S	tl_intg_err	rv_timer_sec_cm	0.910s	64.468us	5	5	100.00
		rv_timer_tl_intg_err	1.430s	382.818us	20	20	100.00
V2S	sec_cm_bus_integrity	rv_timer_tl_intg_err	1.430s	382.818us	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	rv_timer_stress_all_with_rand_reset	1.037m	3.709ms	14	50	28.00
V3		TOTAL			14	50	28.00
		TOTAL			581	620	93.71

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	5	83.33
V2	7	7	6	85.71
V2S	2	2	2	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
99.64	99.36	98.73	100.00	--	100.00	100.00	99.77

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:867) [rv_timer_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 35 failures:
- Test rv_timer_stress_all_with_rand_reset has 35 failures.
  - 0.rv_timer_stress_all_with_rand_reset.106675215459229480153874315593409316179409939360797468346757309047183029184219
    Line 293, in log /container/opentitan-public/scratch/os_regression/rv_timer-sim-vcs/0.rv_timer_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 12944144152 ps: (cip_base_vseq.sv:867) [uvm_test_top.env.virtual_sequencer.rv_timer_common_vseq] Check failed (!has_outstanding_access()) Waited 10002 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 12944144152 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 1.rv_timer_stress_all_with_rand_reset.61165787395708334728220312772139997881186009427438709572502006799371769342517
    Line 285, in log /container/opentitan-public/scratch/os_regression/rv_timer-sim-vcs/1.rv_timer_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 7881907305 ps: (cip_base_vseq.sv:867) [uvm_test_top.env.virtual_sequencer.rv_timer_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 7881907305 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 33 more failures.
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 2 failures:
- Test rv_timer_disabled has 2 failures.
  - 34.rv_timer_disabled.83513662127696018446084027373165559041199611722185323810718488938269417754422
    Line 250, in log /container/opentitan-public/scratch/os_regression/rv_timer-sim-vcs/34.rv_timer_disabled/latest/run.log
```
  UVM_FATAL @ 1000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 1000000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 1000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 37.rv_timer_disabled.113114013675923621416919581935605784648935091434586394204833188493814582260850
    Line 251, in log /container/opentitan-public/scratch/os_regression/rv_timer-sim-vcs/37.rv_timer_disabled/latest/run.log
```
  UVM_FATAL @ 1000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 1000000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 1000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (cip_base_vseq.sv:771) [rv_timer_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. has 1 failures:
- Test rv_timer_stress_all_with_rand_reset has 1 failures.
  - 7.rv_timer_stress_all_with_rand_reset.30674208538579026548568170314175265363051607063949430537353207594033610335333
    Line 274, in log /container/opentitan-public/scratch/os_regression/rv_timer-sim-vcs/7.rv_timer_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 4189554109 ps: (cip_base_vseq.sv:771) [uvm_test_top.env.virtual_sequencer.rv_timer_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
  UVM_INFO @ 4189554109 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Job rv_timer-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 1 failures:
- Test rv_timer_random has 1 failures.
  - 55.rv_timer_random.41789805304536431052609096629627177145293179223491167117859849998032418097080
    Log /container/opentitan-public/scratch/os_regression/rv_timer-sim-vcs/55.rv_timer_random/latest/run.log
```
  Job ID: smart:176c0f4a-0b63-4888-8405-1e7f4fcb4395
```

RV_TIMER Simulation Results

Thursday August 15 2024 23:02:21 UTC

GitHub Revision: d09e282b26

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 47908880312501934977153450267828796412449789719488445881682136509150457490963

Test Results

Testplan Progress

Coverage Results

Coverage Dashboard

Failure Buckets

Past Results

GitHub Revision: `d09e282b26`