SPI_DEVICE Simulation Results

Thursday May 18 2023 07:04:58 UTC

GitHub Revision: `ac0bef2ce`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 2907120974

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	spi_device_smoke	1.460s	111.418us	50	50	100.00
V1	csr_hw_reset	spi_device_csr_hw_reset	1.370s	77.191us	5	5	100.00
V1	csr_rw	spi_device_csr_rw	2.400s	179.075us	20	20	100.00
V1	csr_bit_bash	spi_device_csr_bit_bash	39.520s	13.590ms	5	5	100.00
V1	csr_aliasing	spi_device_csr_aliasing	24.330s	1.513ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	spi_device_csr_mem_rw_with_rand_reset	2.930s	90.549us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	spi_device_csr_rw	2.400s	179.075us	20	20	100.00
		spi_device_csr_aliasing	24.330s	1.513ms	5	5	100.00
V1	mem_walk	spi_device_mem_walk	9.620s	447.010us	5	5	100.00
V1	mem_partial_access	spi_device_mem_partial_access	6.500s	256.728us	5	5	100.00
V1		TOTAL			115	115	100.00
V2	base_random_seq	spi_device_txrx	31.447m	1.070s	50	50	100.00
V2	fifo_full	spi_device_fifo_full	49.944m	53.562ms	49	50	98.00
V2	fifo_underflow_overflow	spi_device_fifo_underflow_overflow	49.093m	355.883ms	46	50	92.00
V2	dummy_sck_and_dummy_csb	spi_device_dummy_item_extra_dly	31.532m	339.606ms	50	50	100.00
V2	extra_delay_on_spi	spi_device_dummy_item_extra_dly	31.532m	339.606ms	50	50	100.00
V2	tx_async_fifo_reset	spi_device_tx_async_fifo_reset	0.900s	17.157us	50	50	100.00
V2	rx_async_fifo_reset	spi_device_rx_async_fifo_reset	0.960s	112.247us	50	50	100.00
V2	interrupts	spi_device_intr	2.484m	732.900ms	50	50	100.00
V2	abort	spi_device_abort	0.820s	53.496us	50	50	100.00
V2	byte_transfer_on_spi	spi_device_byte_transfer	3.860s	372.180us	50	50	100.00
V2	rx_timeout	spi_device_rx_timeout	6.820s	850.100us	50	50	100.00
V2	bit_transfer_on_spi	spi_device_bit_transfer	3.190s	1.344ms	50	50	100.00
V2	extreme_fifo_setting	spi_device_extreme_fifo_size	1.304h	320.623ms	50	50	100.00
V2	perf	spi_device_perf	32.025m	116.234ms	50	50	100.00
V2	csb_read	spi_device_csb_read	0.980s	22.756us	50	50	100.00
V2	mem_parity	spi_device_mem_parity	1.110s	25.956us	18	20	90.00
V2	mem_cfg	spi_device_ram_cfg	0.810s	22.512us	20	20	100.00
V2	tpm_read	spi_device_tpm_rw	12.540s	879.110us	50	50	100.00
V2	tpm_write	spi_device_tpm_rw	12.540s	879.110us	50	50	100.00
V2	tpm_hw_reg	spi_device_tpm_read_hw_reg	42.490s	14.828ms	50	50	100.00
		spi_device_tpm_sts_read	1.290s	219.468us	50	50	100.00
V2	tpm_fully_random_case	spi_device_tpm_all	2.892m	67.195ms	50	50	100.00
V2	pass_cmd_filtering	spi_device_pass_cmd_filtering	43.670s	60.004ms	50	50	100.00
		spi_device_flash_all	10.298m	303.591ms	50	50	100.00
V2	pass_addr_translation	spi_device_pass_addr_payload_swap	51.160s	17.861ms	50	50	100.00
		spi_device_flash_all	10.298m	303.591ms	50	50	100.00
V2	pass_payload_translation	spi_device_pass_addr_payload_swap	51.160s	17.861ms	50	50	100.00
		spi_device_flash_all	10.298m	303.591ms	50	50	100.00
V2	cmd_info_slots	spi_device_flash_all	10.298m	303.591ms	50	50	100.00
V2	cmd_read_status	spi_device_intercept	15.810s	16.823ms	50	50	100.00
		spi_device_flash_all	10.298m	303.591ms	50	50	100.00
V2	cmd_read_jedec	spi_device_intercept	15.810s	16.823ms	50	50	100.00
		spi_device_flash_all	10.298m	303.591ms	50	50	100.00
V2	cmd_read_sfdp	spi_device_intercept	15.810s	16.823ms	50	50	100.00
		spi_device_flash_all	10.298m	303.591ms	50	50	100.00
V2	cmd_fast_read	spi_device_intercept	15.810s	16.823ms	50	50	100.00
		spi_device_flash_all	10.298m	303.591ms	50	50	100.00
V2	flash_cmd_upload	spi_device_upload	38.930s	13.857ms	50	50	100.00
V2	mailbox_command	spi_device_mailbox	1.143m	102.739ms	50	50	100.00
V2	mailbox_cross_outside_command	spi_device_mailbox	1.143m	102.739ms	50	50	100.00
V2	mailbox_cross_inside_command	spi_device_mailbox	1.143m	102.739ms	50	50	100.00
V2	cmd_read_buffer	spi_device_flash_mode	1.504m	18.734ms	50	50	100.00
		spi_device_read_buffer_direct	8.260s	2.292ms	50	50	100.00
V2	cmd_dummy_cycle	spi_device_mailbox	1.143m	102.739ms	50	50	100.00
		spi_device_flash_all	10.298m	303.591ms	50	50	100.00
V2	quad_spi	spi_device_flash_all	10.298m	303.591ms	50	50	100.00
V2	dual_spi	spi_device_flash_all	10.298m	303.591ms	50	50	100.00
V2	4b_3b_feature	spi_device_cfg_cmd	10.830s	6.437ms	50	50	100.00
V2	write_enable_disable	spi_device_cfg_cmd	10.830s	6.437ms	50	50	100.00
V2	TPM_with_flash_or_passthrough_mode	spi_device_flash_and_tpm	11.724m	424.839ms	49	50	98.00
V2	tpm_and_flash_trans_with_min_inactive_time	spi_device_flash_and_tpm_min_idle	10.349m	64.769ms	49	50	98.00
V2	stress_all	spi_device_stress_all	44.402m	83.287ms	14	50	28.00
V2	alert_test	spi_device_alert_test	0.780s	25.778us	50	50	100.00
V2	intr_test	spi_device_intr_test	0.810s	18.361us	50	50	100.00
V2	tl_d_oob_addr_access	spi_device_tl_errors	5.310s	353.542us	20	20	100.00
V2	tl_d_illegal_access	spi_device_tl_errors	5.310s	353.542us	20	20	100.00
V2	tl_d_outstanding_access	spi_device_csr_hw_reset	1.370s	77.191us	5	5	100.00
		spi_device_csr_rw	2.400s	179.075us	20	20	100.00
		spi_device_csr_aliasing	24.330s	1.513ms	5	5	100.00
		spi_device_same_csr_outstanding	4.670s	229.816us	20	20	100.00
V2	tl_d_partial_access	spi_device_csr_hw_reset	1.370s	77.191us	5	5	100.00
		spi_device_csr_rw	2.400s	179.075us	20	20	100.00
		spi_device_csr_aliasing	24.330s	1.513ms	5	5	100.00
		spi_device_same_csr_outstanding	4.670s	229.816us	20	20	100.00
V2		TOTAL			1635	1680	97.32
V2S	tl_intg_err	spi_device_sec_cm	1.100s	55.727us	5	5	100.00
		spi_device_tl_intg_err	24.160s	1.099ms	20	20	100.00
V2S	sec_cm_bus_integrity	spi_device_tl_intg_err	24.160s	1.099ms	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	spi_device_stress_all_with_rand_reset			0	0	--
V3		TOTAL			0	0	--
		TOTAL			1775	1820	97.53

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	8	100.00
V2	36	36	30	83.33
V2S	2	2	2	100.00
V3	1	0	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
96.95	99.01	96.24	98.63	92.06	97.95	96.16	98.59

Failure Buckets

UVM_ERROR (mem_model.sv:48) [exp_mem_spi_device_reg_block] Check failed act_data === system_memory[addr] (* [*] vs * [*]) addr * read out mismatch has 33 failures:

Test spi_device_stress_all has 33 failures.

1.spi_device_stress_all.1888864261
Line 230, in log /container/opentitan-public/scratch/os_regression/spi_device-sim-vcs/1.spi_device_stress_all/latest/run.log

  UVM_ERROR @ 345050628141 ps: (mem_model.sv:48) [exp_mem_spi_device_reg_block] Check failed act_data === system_memory[addr] (0x3b [111011] vs 0xa9 [10101001]) addr 0x41e69834 read out mismatch
  UVM_ERROR @ 345050628141 ps: (mem_model.sv:48) [exp_mem_spi_device_reg_block] Check failed act_data === system_memory[addr] (0x5a [1011010] vs 0xe0 [11100000]) addr 0x41e69835 read out mismatch
  UVM_ERROR @ 345050628141 ps: (mem_model.sv:48) [exp_mem_spi_device_reg_block] Check failed act_data === system_memory[addr] (0xa [1010] vs 0x1e [11110]) addr 0x41e69836 read out mismatch
  UVM_ERROR @ 345050628141 ps: (mem_model.sv:48) [exp_mem_spi_device_reg_block] Check failed act_data === system_memory[addr] (0xe7 [11100111] vs 0xf6 [11110110]) addr 0x41e69837 read out mismatch
  UVM_ERROR @ 345065961505 ps: (mem_model.sv:48) [exp_mem_spi_device_reg_block] Check failed act_data === system_memory[addr] (0x3d [111101] vs 0x95 [10010101]) addr 0x41e69838 read out mismatch

3.spi_device_stress_all.1586429980
Line 223, in log /container/opentitan-public/scratch/os_regression/spi_device-sim-vcs/3.spi_device_stress_all/latest/run.log

  UVM_ERROR @ 3287546458 ps: (mem_model.sv:48) [exp_mem_spi_device_reg_block] Check failed act_data === system_memory[addr] (0xdd [11011101] vs 0xae [10101110]) addr 0xa8747ac4 read out mismatch
  UVM_ERROR @ 3287546458 ps: (mem_model.sv:48) [exp_mem_spi_device_reg_block] Check failed act_data === system_memory[addr] (0xcc [11001100] vs 0x53 [1010011]) addr 0xa8747ac5 read out mismatch
  UVM_ERROR @ 3287546458 ps: (mem_model.sv:48) [exp_mem_spi_device_reg_block] Check failed act_data === system_memory[addr] (0xd3 [11010011] vs 0x74 [1110100]) addr 0xa8747ac6 read out mismatch
  UVM_ERROR @ 3287546458 ps: (mem_model.sv:48) [exp_mem_spi_device_reg_block] Check failed act_data === system_memory[addr] (0xf7 [11110111] vs 0xce [11001110]) addr 0xa8747ac7 read out mismatch
  UVM_ERROR @ 3289358929 ps: (mem_model.sv:48) [exp_mem_spi_device_reg_block] Check failed act_data === system_memory[addr] (0x32 [110010] vs 0xec [11101100]) addr 0xa8747ac8 read out mismatch

... and 31 more failures.

UVM_WARNING (uvm_reg_field.svh:1264) [UVM/FLD/SET/BSY] Setting the value of field "generic_rx_full" while containing register "spi_device_reg_block.intr_state" is being accessed may result in loss of desired field value. A race condition between threads concurrently accessing the register model is the likely cause of the problem. has 4 failures:

Test spi_device_stress_all has 2 failures.

13.spi_device_stress_all.2819600684
Line 250, in log /container/opentitan-public/scratch/os_regression/spi_device-sim-vcs/13.spi_device_stress_all/latest/run.log

  UVM_WARNING @ 8304820302 ps: (uvm_reg_field.svh:1264) [UVM/FLD/SET/BSY] Setting the value of field "generic_rx_full" while containing register "spi_device_reg_block.intr_state" is being accessed may result in loss of desired field value. A race condition between threads concurrently accessing the register model is the likely cause of the problem.
  UVM_WARNING @ 8304820302 ps: (uvm_reg_field.svh:1264) [UVM/FLD/SET/BSY] Setting the value of field "generic_rx_watermark" while containing register "spi_device_reg_block.intr_state" is being accessed may result in loss of desired field value. A race condition between threads concurrently accessing the register model is the likely cause of the problem.
  UVM_WARNING @ 8304820302 ps: (uvm_reg_field.svh:1264) [UVM/FLD/SET/BSY] Setting the value of field "generic_tx_watermark" while containing register "spi_device_reg_block.intr_state" is being accessed may result in loss of desired field value. A race condition between threads concurrently accessing the register model is the likely cause of the problem.
  UVM_WARNING @ 8304820302 ps: (uvm_reg_field.svh:1264) [UVM/FLD/SET/BSY] Setting the value of field "generic_rx_error" while containing register "spi_device_reg_block.intr_state" is being accessed may result in loss of desired field value. A race condition between threads concurrently accessing the register model is the likely cause of the problem.
  UVM_WARNING @ 8304820302 ps: (uvm_reg_field.svh:1264) [UVM/FLD/SET/BSY] Setting the value of field "generic_rx_overflow" while containing register "spi_device_reg_block.intr_state" is being accessed may result in loss of desired field value. A race condition between threads concurrently accessing the register model is the likely cause of the problem.

23.spi_device_stress_all.1015781672
Line 236, in log /container/opentitan-public/scratch/os_regression/spi_device-sim-vcs/23.spi_device_stress_all/latest/run.log

  UVM_WARNING @ 3175777526 ps: (uvm_reg_field.svh:1264) [UVM/FLD/SET/BSY] Setting the value of field "generic_rx_full" while containing register "spi_device_reg_block.intr_state" is being accessed may result in loss of desired field value. A race condition between threads concurrently accessing the register model is the likely cause of the problem.
  UVM_WARNING @ 3175777526 ps: (uvm_reg_field.svh:1264) [UVM/FLD/SET/BSY] Setting the value of field "generic_rx_watermark" while containing register "spi_device_reg_block.intr_state" is being accessed may result in loss of desired field value. A race condition between threads concurrently accessing the register model is the likely cause of the problem.
  UVM_WARNING @ 3175777526 ps: (uvm_reg_field.svh:1264) [UVM/FLD/SET/BSY] Setting the value of field "generic_tx_watermark" while containing register "spi_device_reg_block.intr_state" is being accessed may result in loss of desired field value. A race condition between threads concurrently accessing the register model is the likely cause of the problem.
  UVM_WARNING @ 3175777526 ps: (uvm_reg_field.svh:1264) [UVM/FLD/SET/BSY] Setting the value of field "generic_rx_error" while containing register "spi_device_reg_block.intr_state" is being accessed may result in loss of desired field value. A race condition between threads concurrently accessing the register model is the likely cause of the problem.
  UVM_WARNING @ 3175777526 ps: (uvm_reg_field.svh:1264) [UVM/FLD/SET/BSY] Setting the value of field "generic_rx_overflow" while containing register "spi_device_reg_block.intr_state" is being accessed may result in loss of desired field value. A race condition between threads concurrently accessing the register model is the likely cause of the problem.

Test spi_device_flash_and_tpm has 1 failures.

16.spi_device_flash_and_tpm.44583037
Line 218, in log /container/opentitan-public/scratch/os_regression/spi_device-sim-vcs/16.spi_device_flash_and_tpm/latest/run.log

  UVM_WARNING @ 1459836482 ps: (uvm_reg_field.svh:1264) [UVM/FLD/SET/BSY] Setting the value of field "generic_rx_full" while containing register "spi_device_reg_block.intr_state" is being accessed may result in loss of desired field value. A race condition between threads concurrently accessing the register model is the likely cause of the problem.
  UVM_WARNING @ 1459836482 ps: (uvm_reg_field.svh:1264) [UVM/FLD/SET/BSY] Setting the value of field "generic_rx_watermark" while containing register "spi_device_reg_block.intr_state" is being accessed may result in loss of desired field value. A race condition between threads concurrently accessing the register model is the likely cause of the problem.
  UVM_WARNING @ 1459836482 ps: (uvm_reg_field.svh:1264) [UVM/FLD/SET/BSY] Setting the value of field "generic_tx_watermark" while containing register "spi_device_reg_block.intr_state" is being accessed may result in loss of desired field value. A race condition between threads concurrently accessing the register model is the likely cause of the problem.
  UVM_WARNING @ 1459836482 ps: (uvm_reg_field.svh:1264) [UVM/FLD/SET/BSY] Setting the value of field "generic_rx_error" while containing register "spi_device_reg_block.intr_state" is being accessed may result in loss of desired field value. A race condition between threads concurrently accessing the register model is the likely cause of the problem.
  UVM_WARNING @ 1459836482 ps: (uvm_reg_field.svh:1264) [UVM/FLD/SET/BSY] Setting the value of field "generic_rx_overflow" while containing register "spi_device_reg_block.intr_state" is being accessed may result in loss of desired field value. A race condition between threads concurrently accessing the register model is the likely cause of the problem.

Test spi_device_flash_and_tpm_min_idle has 1 failures.

43.spi_device_flash_and_tpm_min_idle.1533243323
Line 221, in log /container/opentitan-public/scratch/os_regression/spi_device-sim-vcs/43.spi_device_flash_and_tpm_min_idle/latest/run.log

  UVM_WARNING @ 11676788025 ps: (uvm_reg_field.svh:1264) [UVM/FLD/SET/BSY] Setting the value of field "generic_rx_full" while containing register "spi_device_reg_block.intr_state" is being accessed may result in loss of desired field value. A race condition between threads concurrently accessing the register model is the likely cause of the problem.
  UVM_WARNING @ 11676788025 ps: (uvm_reg_field.svh:1264) [UVM/FLD/SET/BSY] Setting the value of field "generic_rx_watermark" while containing register "spi_device_reg_block.intr_state" is being accessed may result in loss of desired field value. A race condition between threads concurrently accessing the register model is the likely cause of the problem.
  UVM_WARNING @ 11676788025 ps: (uvm_reg_field.svh:1264) [UVM/FLD/SET/BSY] Setting the value of field "generic_tx_watermark" while containing register "spi_device_reg_block.intr_state" is being accessed may result in loss of desired field value. A race condition between threads concurrently accessing the register model is the likely cause of the problem.
  UVM_WARNING @ 11676788025 ps: (uvm_reg_field.svh:1264) [UVM/FLD/SET/BSY] Setting the value of field "generic_rx_error" while containing register "spi_device_reg_block.intr_state" is being accessed may result in loss of desired field value. A race condition between threads concurrently accessing the register model is the likely cause of the problem.
  UVM_WARNING @ 11676788025 ps: (uvm_reg_field.svh:1264) [UVM/FLD/SET/BSY] Setting the value of field "generic_rx_overflow" while containing register "spi_device_reg_block.intr_state" is being accessed may result in loss of desired field value. A race condition between threads concurrently accessing the register model is the likely cause of the problem.

UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 2 failures:
- Test spi_device_fifo_underflow_overflow has 2 failures.
  - 0.spi_device_fifo_underflow_overflow.952705513
    Line 221, in log /container/opentitan-public/scratch/os_regression/spi_device-sim-vcs/0.spi_device_fifo_underflow_overflow/latest/run.log
```
  UVM_FATAL @ 1500000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 1500000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 1500000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 14.spi_device_fifo_underflow_overflow.4208363902
    Line 221, in log /container/opentitan-public/scratch/os_regression/spi_device-sim-vcs/14.spi_device_fifo_underflow_overflow/latest/run.log
```
  UVM_FATAL @ 1500000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 1500000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 1500000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR (cip_base_vseq.sv:245) [spi_device_mem_parity_vseq] Check failed masked_data == exp_data (* [*] vs * [*]) addr * read out mismatch has 2 failures:

Test spi_device_mem_parity has 2 failures.

5.spi_device_mem_parity.131766254
Line 215, in log /container/opentitan-public/scratch/os_regression/spi_device-sim-vcs/5.spi_device_mem_parity/latest/run.log

  UVM_ERROR @   1052416 ps: (cip_base_vseq.sv:245) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed masked_data == exp_data (66847232 [0x3fc0200] vs 4294967295 [0xffffffff]) addr 0x30 read out mismatch
  UVM_ERROR @   1052416 ps: (cip_base_vseq.sv:245) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed rsp.d_error == exp_err_rsp (0 [0x0] vs 1 [0x1]) unexpected error response for addr: 0x00000030
  UVM_ERROR @   1102416 ps: (cip_base_vseq.sv:245) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed masked_data == exp_data (66847232 [0x3fc0200] vs 4294967295 [0xffffffff]) addr 0x30 read out mismatch
  UVM_ERROR @   1102416 ps: (cip_base_vseq.sv:245) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed rsp.d_error == exp_err_rsp (0 [0x0] vs 1 [0x1]) unexpected error response for addr: 0x00000030
  UVM_ERROR @   1302416 ps: (cip_base_vseq.sv:245) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed masked_data == exp_data (66847232 [0x3fc0200] vs 4294967295 [0xffffffff]) addr 0x30 read out mismatch

16.spi_device_mem_parity.2454206606
Line 215, in log /container/opentitan-public/scratch/os_regression/spi_device-sim-vcs/16.spi_device_mem_parity/latest/run.log

  UVM_ERROR @   5623568 ps: (cip_base_vseq.sv:245) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed masked_data == exp_data (128 [0x80] vs 4294967295 [0xffffffff]) addr 0x18 read out mismatch
  UVM_ERROR @   5623568 ps: (cip_base_vseq.sv:245) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed rsp.d_error == exp_err_rsp (0 [0x0] vs 1 [0x1]) unexpected error response for addr: 0x00000018
  UVM_ERROR @   5797480 ps: (cip_base_vseq.sv:245) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed masked_data == exp_data (128 [0x80] vs 4294967295 [0xffffffff]) addr 0x18 read out mismatch
  UVM_ERROR @   5797480 ps: (cip_base_vseq.sv:245) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed rsp.d_error == exp_err_rsp (0 [0x0] vs 1 [0x1]) unexpected error response for addr: 0x00000018
  UVM_ERROR @   5971392 ps: (cip_base_vseq.sv:245) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed masked_data == exp_data (128 [0x80] vs 4294967295 [0xffffffff]) addr 0x18 read out mismatch

Offending '(!dst_pulse_o)' has 1 failures:

Test spi_device_fifo_underflow_overflow has 1 failures.

8.spi_device_fifo_underflow_overflow.184493519
Line 220, in log /container/opentitan-public/scratch/os_regression/spi_device-sim-vcs/8.spi_device_fifo_underflow_overflow/latest/run.log

      Offending '(!dst_pulse_o)'
  UVM_ERROR @ 5140985823 ps: (prim_pulse_sync.sv:96) [ASSERT FAILED] DstPulseCheck_A
  "../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv", 96: tb.dut.u_rxf_overflow.DstPulseCheck_A: started at 20419303878ps failed at 20419414989ps
      Offending '(!dst_pulse_o)'
  UVM_ERROR @ 20419414989 ps: (prim_pulse_sync.sv:96) [ASSERT FAILED] DstPulseCheck_A

UVM_ERROR (cip_base_vseq.sv:365) [spi_device_intr_vseq] Check failed act_pins == exp_pins (* [*] vs * [*]) has 1 failures:

Test spi_device_stress_all has 1 failures.

35.spi_device_stress_all.1386752630
Line 225, in log /container/opentitan-public/scratch/os_regression/spi_device-sim-vcs/35.spi_device_stress_all/latest/run.log

  UVM_ERROR @ 34105630259 ps: (cip_base_vseq.sv:365) [uvm_test_top.env.virtual_sequencer.spi_device_intr_vseq] Check failed act_pins == exp_pins (0 [0x0] vs 1 [0x1])
  UVM_ERROR @ 34105810259 ps: (csr_utils_pkg.sv:457) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: spi_device_reg_block.intr_state reset value: 0x0
  UVM_ERROR @ 34107410259 ps: (csr_utils_pkg.sv:457) [csr_utils::csr_rd_check] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: spi_device_reg_block.status.rxf_empty reset value: 0x1
  UVM_ERROR @ 34107930259 ps: (csr_utils_pkg.sv:457) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 16 [0x10]) Regname: spi_device_reg_block.intr_state reset value: 0x0
  UVM_ERROR @ 34108870259 ps: (csr_utils_pkg.sv:457) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: spi_device_reg_block.status.rxf_full reset value: 0x0

Job spi_device-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 1 failures:
- Test spi_device_fifo_full has 1 failures.
  - 37.spi_device_fifo_full.982345065
    Log /container/opentitan-public/scratch/os_regression/spi_device-sim-vcs/37.spi_device_fifo_full/latest/run.log
```
  Job ID: smart:ac0fa93b-db9b-432f-ad61-30d7294b4901
```
UVM_FATAL (spi_device_base_vseq.sv:410) [spi_device_fifo_underflow_overflow_vseq] wait_for_rx_avail_bytes::SramDataAvail has 1 failures:
- Test spi_device_fifo_underflow_overflow has 1 failures.
  - 45.spi_device_fifo_underflow_overflow.562708634
    Line 221, in log /container/opentitan-public/scratch/os_regression/spi_device-sim-vcs/45.spi_device_fifo_underflow_overflow/latest/run.log
```
  UVM_FATAL @ 866374768666 ps: (spi_device_base_vseq.sv:410) [uvm_test_top.env.virtual_sequencer.spi_device_fifo_underflow_overflow_vseq] wait_for_rx_avail_bytes::SramDataAvail
  UVM_INFO @ 866374768666 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```