SPI_DEVICE Simulation Results

Wednesday December 27 2023 20:02:24 UTC

GitHub Revision: `0c759b93ab`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 85416116840666724748485424200434981761468351851988553961117902923833034512693

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	spi_device_smoke	1.310s	247.424us	50	50	100.00
V1	csr_hw_reset	spi_device_csr_hw_reset	1.410s	191.875us	5	5	100.00
V1	csr_rw	spi_device_csr_rw	2.800s	118.913us	20	20	100.00
V1	csr_bit_bash	spi_device_csr_bit_bash	34.180s	580.139us	5	5	100.00
V1	csr_aliasing	spi_device_csr_aliasing	28.160s	2.210ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	spi_device_csr_mem_rw_with_rand_reset	3.220s	37.426us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	spi_device_csr_rw	2.800s	118.913us	20	20	100.00
		spi_device_csr_aliasing	28.160s	2.210ms	5	5	100.00
V1	mem_walk	spi_device_mem_walk	15.780s	2.727ms	5	5	100.00
V1	mem_partial_access	spi_device_mem_partial_access	6.410s	224.498us	5	5	100.00
V1		TOTAL			115	115	100.00
V2	base_random_seq	spi_device_txrx	45.580m	205.255ms	50	50	100.00
V2	fifo_full	spi_device_fifo_full	45.799m	188.899ms	50	50	100.00
V2	fifo_underflow_overflow	spi_device_fifo_underflow_overflow	30.887m	84.913ms	50	50	100.00
V2	dummy_sck_and_dummy_csb	spi_device_dummy_item_extra_dly	38.641m	81.596ms	50	50	100.00
V2	extra_delay_on_spi	spi_device_dummy_item_extra_dly	38.641m	81.596ms	50	50	100.00
V2	tx_async_fifo_reset	spi_device_tx_async_fifo_reset	0.840s	17.755us	50	50	100.00
V2	rx_async_fifo_reset	spi_device_rx_async_fifo_reset	1.020s	160.313us	48	50	96.00
V2	interrupts	spi_device_intr	2.307m	118.397ms	50	50	100.00
V2	abort	spi_device_abort	0.810s	17.478us	50	50	100.00
V2	byte_transfer_on_spi	spi_device_byte_transfer	3.690s	623.573us	50	50	100.00
V2	rx_timeout	spi_device_rx_timeout	7.000s	985.227us	50	50	100.00
V2	bit_transfer_on_spi	spi_device_bit_transfer	3.400s	1.708ms	50	50	100.00
V2	extreme_fifo_setting	spi_device_extreme_fifo_size	1.121h	86.767ms	49	50	98.00
V2	perf	spi_device_perf	43.461m	86.742ms	50	50	100.00
V2	csb_read	spi_device_csb_read	0.820s	64.454us	50	50	100.00
V2	mem_parity	spi_device_mem_parity	1.120s	33.946us	20	20	100.00
V2	mem_cfg	spi_device_ram_cfg	0.810s	58.624us	20	20	100.00
V2	tpm_read	spi_device_tpm_rw	13.850s	1.175ms	50	50	100.00
V2	tpm_write	spi_device_tpm_rw	13.850s	1.175ms	50	50	100.00
V2	tpm_hw_reg	spi_device_tpm_read_hw_reg	30.450s	36.715ms	50	50	100.00
		spi_device_tpm_sts_read	1.140s	1.306ms	50	50	100.00
V2	tpm_fully_random_case	spi_device_tpm_all	3.123m	22.994ms	48	50	96.00
V2	pass_cmd_filtering	spi_device_pass_cmd_filtering	1.142m	49.273ms	50	50	100.00
		spi_device_flash_all	7.334m	126.911ms	49	50	98.00
V2	pass_addr_translation	spi_device_pass_addr_payload_swap	44.860s	174.162ms	50	50	100.00
		spi_device_flash_all	7.334m	126.911ms	49	50	98.00
V2	pass_payload_translation	spi_device_pass_addr_payload_swap	44.860s	174.162ms	50	50	100.00
		spi_device_flash_all	7.334m	126.911ms	49	50	98.00
V2	cmd_info_slots	spi_device_flash_all	7.334m	126.911ms	49	50	98.00
V2	cmd_read_status	spi_device_intercept	16.400s	19.819ms	50	50	100.00
		spi_device_flash_all	7.334m	126.911ms	49	50	98.00
V2	cmd_read_jedec	spi_device_intercept	16.400s	19.819ms	50	50	100.00
		spi_device_flash_all	7.334m	126.911ms	49	50	98.00
V2	cmd_read_sfdp	spi_device_intercept	16.400s	19.819ms	50	50	100.00
		spi_device_flash_all	7.334m	126.911ms	49	50	98.00
V2	cmd_fast_read	spi_device_intercept	16.400s	19.819ms	50	50	100.00
		spi_device_flash_all	7.334m	126.911ms	49	50	98.00
V2	flash_cmd_upload	spi_device_upload	48.190s	63.747ms	50	50	100.00
V2	mailbox_command	spi_device_mailbox	1.016m	222.601ms	50	50	100.00
V2	mailbox_cross_outside_command	spi_device_mailbox	1.016m	222.601ms	50	50	100.00
V2	mailbox_cross_inside_command	spi_device_mailbox	1.016m	222.601ms	50	50	100.00
V2	cmd_read_buffer	spi_device_flash_mode	1.137m	30.833ms	48	50	96.00
		spi_device_read_buffer_direct	8.190s	1.701ms	50	50	100.00
V2	cmd_dummy_cycle	spi_device_mailbox	1.016m	222.601ms	50	50	100.00
		spi_device_flash_all	7.334m	126.911ms	49	50	98.00
V2	quad_spi	spi_device_flash_all	7.334m	126.911ms	49	50	98.00
V2	dual_spi	spi_device_flash_all	7.334m	126.911ms	49	50	98.00
V2	4b_3b_feature	spi_device_cfg_cmd	13.250s	3.626ms	48	50	96.00
V2	write_enable_disable	spi_device_cfg_cmd	13.250s	3.626ms	48	50	96.00
V2	TPM_with_flash_or_passthrough_mode	spi_device_flash_and_tpm	8.501m	384.009ms	49	50	98.00
V2	tpm_and_flash_trans_with_min_inactive_time	spi_device_flash_and_tpm_min_idle	11.840m	1.500s	43	50	86.00
V2	stress_all	spi_device_stress_all	2.021h	2.732s	35	50	70.00
V2	alert_test	spi_device_alert_test	0.820s	16.557us	50	50	100.00
V2	intr_test	spi_device_intr_test	0.830s	36.158us	50	50	100.00
V2	tl_d_oob_addr_access	spi_device_tl_errors	6.330s	204.960us	20	20	100.00
V2	tl_d_illegal_access	spi_device_tl_errors	6.330s	204.960us	20	20	100.00
V2	tl_d_outstanding_access	spi_device_csr_hw_reset	1.410s	191.875us	5	5	100.00
		spi_device_csr_rw	2.800s	118.913us	20	20	100.00
		spi_device_csr_aliasing	28.160s	2.210ms	5	5	100.00
		spi_device_same_csr_outstanding	4.520s	212.099us	20	20	100.00
V2	tl_d_partial_access	spi_device_csr_hw_reset	1.410s	191.875us	5	5	100.00
		spi_device_csr_rw	2.800s	118.913us	20	20	100.00
		spi_device_csr_aliasing	28.160s	2.210ms	5	5	100.00
		spi_device_same_csr_outstanding	4.520s	212.099us	20	20	100.00
V2		TOTAL			1647	1680	98.04
V2S	tl_intg_err	spi_device_sec_cm	1.300s	222.502us	5	5	100.00
		spi_device_tl_intg_err	24.030s	10.682ms	20	20	100.00
V2S	sec_cm_bus_integrity	spi_device_tl_intg_err	24.030s	10.682ms	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	spi_device_stress_all_with_rand_reset			0	0	--
V3		TOTAL			0	0	--
		TOTAL			1787	1820	98.19

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	8	100.00
V2	36	36	27	75.00
V2S	2	2	2	100.00
V3	1	0	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.10	99.01	96.33	98.63	92.06	98.05	95.86	99.76

Failure Buckets

UVM_ERROR (csr_utils_pkg.sv:457) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: spi_device_reg_block.cfg.addr_4b_en reset value: * has 12 failures:

Test spi_device_stress_all has 5 failures.

1.spi_device_stress_all.10199252398567882245535618914484491166291994918693415158501758295190512554390
Line 264, in log /container/opentitan-public/scratch/os_regression/spi_device-sim-vcs/1.spi_device_stress_all/latest/run.log

  UVM_ERROR @ 7850099634 ps: (csr_utils_pkg.sv:457) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: spi_device_reg_block.cfg.addr_4b_en reset value: 0x0
  UVM_INFO @ 8623286634 ps: (spi_device_flash_all_vseq.sv:46) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_and_tpm_vseq.flash_vseq] running iteration 10/14
  UVM_INFO @ 9224776634 ps: (spi_device_flash_all_vseq.sv:46) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_and_tpm_vseq.flash_vseq] running iteration 11/14
  UVM_INFO @ 9722745634 ps: (spi_device_flash_all_vseq.sv:46) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_and_tpm_vseq.flash_vseq] running iteration 12/14
  UVM_INFO @ 10126910634 ps: (spi_device_flash_all_vseq.sv:46) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_and_tpm_vseq.flash_vseq] running iteration 13/14

28.spi_device_stress_all.49965031397302320694219893571503730295860829747583275723398623041724837401079
Line 290, in log /container/opentitan-public/scratch/os_regression/spi_device-sim-vcs/28.spi_device_stress_all/latest/run.log

  UVM_ERROR @ 97131096458 ps: (csr_utils_pkg.sv:457) [csr_utils::csr_rd_check] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: spi_device_reg_block.cfg.addr_4b_en reset value: 0x0
  UVM_INFO @ 97319447611 ps: (spi_device_tpm_read_hw_reg_vseq.sv:48) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_and_tpm_vseq.tpm_vseq] starting sequence 8/19
  UVM_INFO @ 97609755466 ps: (spi_device_tpm_read_hw_reg_vseq.sv:48) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_and_tpm_vseq.tpm_vseq] starting sequence 9/19
  UVM_INFO @ 97804273187 ps: (spi_device_tpm_read_hw_reg_vseq.sv:48) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_and_tpm_vseq.tpm_vseq] starting sequence 10/19
  UVM_INFO @ 97946854239 ps: (spi_device_tpm_read_hw_reg_vseq.sv:48) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_and_tpm_vseq.tpm_vseq] starting sequence 11/19

... and 3 more failures.

Test spi_device_flash_and_tpm_min_idle has 4 failures.

7.spi_device_flash_and_tpm_min_idle.84841874285293297569013597275911251451473267892897422405092156238572300437288
Line 251, in log /container/opentitan-public/scratch/os_regression/spi_device-sim-vcs/7.spi_device_flash_and_tpm_min_idle/latest/run.log

  UVM_ERROR @ 286043943 ps: (csr_utils_pkg.sv:457) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: spi_device_reg_block.cfg.addr_4b_en reset value: 0x0
  UVM_INFO @ 443976080 ps: (spi_device_tpm_read_hw_reg_vseq.sv:48) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_and_tpm_min_idle_vseq.tpm_vseq] starting sequence 2/5
  UVM_INFO @ 476989236 ps: (spi_device_flash_all_vseq.sv:46) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_and_tpm_min_idle_vseq.flash_vseq] running iteration 2/7
  UVM_ERROR @ 738475087 ps: (spi_device_scoreboard.sv:1085) [uvm_test_top.env.scoreboard] Check failed item.d_data[i] == intr_exp[i] (0 [0x0] vs 1 [0x1]) Compare PayloadOverflow mismatch, act (0x0) != exp 1
  UVM_INFO @ 747079529 ps: (spi_device_tpm_read_hw_reg_vseq.sv:48) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_and_tpm_min_idle_vseq.tpm_vseq] starting sequence 3/5

14.spi_device_flash_and_tpm_min_idle.93808579494369763493199733630180758221023556889501405812300778017968308126099
Line 254, in log /container/opentitan-public/scratch/os_regression/spi_device-sim-vcs/14.spi_device_flash_and_tpm_min_idle/latest/run.log

  UVM_ERROR @ 1063785591 ps: (csr_utils_pkg.sv:457) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: spi_device_reg_block.cfg.addr_4b_en reset value: 0x0
  UVM_INFO @ 1243840946 ps: (spi_device_flash_all_vseq.sv:46) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_and_tpm_min_idle_vseq.flash_vseq] running iteration 3/16
  UVM_INFO @ 1730312460 ps: (spi_device_flash_all_vseq.sv:46) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_and_tpm_min_idle_vseq.flash_vseq] running iteration 4/16
  UVM_INFO @ 2043604707 ps: (spi_device_flash_all_vseq.sv:46) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_and_tpm_min_idle_vseq.flash_vseq] running iteration 5/16
  UVM_INFO @ 2396364343 ps: (spi_device_flash_all_vseq.sv:46) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_and_tpm_min_idle_vseq.flash_vseq] running iteration 6/16

... and 2 more failures.

Test spi_device_flash_all has 1 failures.

35.spi_device_flash_all.99945434822200165815495287918598883756783865152587132891147878890964534243339
Line 252, in log /container/opentitan-public/scratch/os_regression/spi_device-sim-vcs/35.spi_device_flash_all/latest/run.log

  UVM_ERROR @ 4326188107 ps: (csr_utils_pkg.sv:457) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: spi_device_reg_block.cfg.addr_4b_en reset value: 0x0
  UVM_INFO @ 5187301027 ps: (spi_device_flash_all_vseq.sv:46) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_all_vseq] running iteration 4/14
  UVM_INFO @ 7562534033 ps: (spi_device_flash_all_vseq.sv:46) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_all_vseq] running iteration 5/14
  UVM_INFO @ 9790652401 ps: (spi_device_flash_all_vseq.sv:46) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_all_vseq] running iteration 6/14
  UVM_INFO @ 11530989116 ps: (spi_device_flash_all_vseq.sv:46) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_all_vseq] running iteration 7/14

Test spi_device_flash_and_tpm has 1 failures.

41.spi_device_flash_and_tpm.84107909509030289146191054293493167275601975992834600246226242346341037333420
Line 264, in log /container/opentitan-public/scratch/os_regression/spi_device-sim-vcs/41.spi_device_flash_and_tpm/latest/run.log

  UVM_ERROR @ 7646086348 ps: (csr_utils_pkg.sv:457) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: spi_device_reg_block.cfg.addr_4b_en reset value: 0x0
  UVM_INFO @ 7877725028 ps: (spi_device_tpm_read_hw_reg_vseq.sv:48) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_and_tpm_vseq.tpm_vseq] starting sequence 10/20
  UVM_INFO @ 8689339953 ps: (spi_device_flash_all_vseq.sv:46) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_and_tpm_vseq.flash_vseq] running iteration 7/16
  UVM_INFO @ 8868007658 ps: (spi_device_tpm_read_hw_reg_vseq.sv:48) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_and_tpm_vseq.tpm_vseq] starting sequence 11/20
  UVM_INFO @ 9871881333 ps: (spi_device_tpm_read_hw_reg_vseq.sv:48) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_and_tpm_vseq.tpm_vseq] starting sequence 12/20

Test spi_device_cfg_cmd has 1 failures.

49.spi_device_cfg_cmd.47769042264117339426595231388553647231219628912222504816143941365561918309807
Line 262, in log /container/opentitan-public/scratch/os_regression/spi_device-sim-vcs/49.spi_device_cfg_cmd/latest/run.log

  UVM_ERROR @ 944500729 ps: (csr_utils_pkg.sv:457) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: spi_device_reg_block.cfg.addr_4b_en reset value: 0x0
  UVM_INFO @ 946660729 ps: (spi_device_pass_cmd_filtering_vseq.sv:18) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_cfg_cmd_vseq] running iteration 14, test op = 0xb7
  UVM_INFO @ 949940729 ps: (spi_device_pass_cmd_filtering_vseq.sv:18) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_cfg_cmd_vseq] running iteration 15, test op = 0x4
  UVM_INFO @ 1008100729 ps: (spi_device_pass_cmd_filtering_vseq.sv:18) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_cfg_cmd_vseq] running iteration 16, test op = 0xe9
  UVM_INFO @ 1068220729 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]

UVM_ERROR (spi_device_scoreboard.sv:1395) [scoreboard] Check failed rx_word_q.size == * (* [*] vs * [*]) has 2 failures:
- Test spi_device_rx_async_fifo_reset has 2 failures.
  - 2.spi_device_rx_async_fifo_reset.95163611358642917688021254149816106572173717556339312268463248292976101057128
    Line 256, in log /container/opentitan-public/scratch/os_regression/spi_device-sim-vcs/2.spi_device_rx_async_fifo_reset/latest/run.log
```
  UVM_ERROR @  90915224 ps: (spi_device_scoreboard.sv:1395) [uvm_test_top.env.scoreboard] Check failed rx_word_q.size == 0 (2 [0x2] vs 0 [0x0])
  UVM_INFO @  90915224 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 35.spi_device_rx_async_fifo_reset.102381394348037014668017411843134560267409977151403876826009583248101550942310
    Line 256, in log /container/opentitan-public/scratch/os_regression/spi_device-sim-vcs/35.spi_device_rx_async_fifo_reset/latest/run.log
```
  UVM_ERROR @  79324151 ps: (spi_device_scoreboard.sv:1395) [uvm_test_top.env.scoreboard] Check failed rx_word_q.size == 0 (2 [0x2] vs 0 [0x0])
  UVM_INFO @  79324151 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 2 failures:
- Test spi_device_flash_and_tpm_min_idle has 1 failures.
  - 3.spi_device_flash_and_tpm_min_idle.67808989487189091908802895901386949298042337963984208713569847942048411121554
    Line 278, in log /container/opentitan-public/scratch/os_regression/spi_device-sim-vcs/3.spi_device_flash_and_tpm_min_idle/latest/run.log
```
  UVM_FATAL @ 1500000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 1500000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 1500000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test spi_device_extreme_fifo_size has 1 failures.
  - 49.spi_device_extreme_fifo_size.87996947354598263193001435334571831784740600836591346881180776557176031808995
    Line 254, in log /container/opentitan-public/scratch/os_regression/spi_device-sim-vcs/49.spi_device_extreme_fifo_size/latest/run.log
```
  UVM_FATAL @ 1500000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 1500000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 1500000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

Exit reason: Error: User command failed UVM_ERROR (spi_device_scoreboard.sv:263) [scoreboard] Check failed tpm_read_sw_q.size == * (* [*] vs * [*]) has 2 failures:

Test spi_device_tpm_all has 2 failures.

9.spi_device_tpm_all.89999109709349825963241194165358033987233329721931922248218416279291529779434
Line 259, in log /container/opentitan-public/scratch/os_regression/spi_device-sim-vcs/9.spi_device_tpm_all/latest/run.log

  UVM_ERROR @ 1479889674 ps: (spi_device_scoreboard.sv:263) [uvm_test_top.env.scoreboard] Check failed tpm_read_sw_q.size == 1 (0 [0x0] vs 1 [0x1])
  UVM_INFO @ 1479889674 ps: (uvm_comparer.svh:401) [MISCMP] Miscompare for host_item: lhs = @185835 : rhs = @0
  
  Error-[NOA] Null object access
  ../src/lowrisc_dv_spi_device_env_0.1/spi_device_scoreboard.sv, 309

12.spi_device_tpm_all.83384233062338888437611284207029781489148405881263036713204186492639965848451
Line 254, in log /container/opentitan-public/scratch/os_regression/spi_device-sim-vcs/12.spi_device_tpm_all/latest/run.log

  UVM_ERROR @ 1596860412 ps: (spi_device_scoreboard.sv:263) [uvm_test_top.env.scoreboard] Check failed tpm_read_sw_q.size == 1 (0 [0x0] vs 1 [0x1])
  UVM_INFO @ 1596860412 ps: (uvm_comparer.svh:401) [MISCMP] Miscompare for host_item: lhs = @65973 : rhs = @0
  
  Error-[NOA] Null object access
  ../src/lowrisc_dv_spi_device_env_0.1/spi_device_scoreboard.sv, 309

UVM_FATAL (spi_device_scoreboard.sv:890) [scoreboard] timeout occurred! has 2 failures:
- Test spi_device_flash_mode has 2 failures.
  - 18.spi_device_flash_mode.11516214299767655775674983367699366202700203135735819975405641297151780470367
    Line 248, in log /container/opentitan-public/scratch/os_regression/spi_device-sim-vcs/18.spi_device_flash_mode/latest/run.log
```
  UVM_FATAL @ 33145306660 ps: (spi_device_scoreboard.sv:890) [uvm_test_top.env.scoreboard] timeout occurred!
  UVM_INFO @ 33145306660 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 20.spi_device_flash_mode.36797072981677680379951597110940950636603756217435232162192273178546057607044
    Line 248, in log /container/opentitan-public/scratch/os_regression/spi_device-sim-vcs/20.spi_device_flash_mode/latest/run.log
```
  UVM_FATAL @ 14184428643 ps: (spi_device_scoreboard.sv:890) [uvm_test_top.env.scoreboard] timeout occurred!
  UVM_INFO @ 14184428643 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR (spi_device_scoreboard.sv:1054) [scoreboard] Check failed (item.d_data inside {exp_data_q}) act (*) != exp '{'{other_status:*, wel:*, busy:*}} has 2 failures:

Test spi_device_flash_and_tpm_min_idle has 1 failures.

22.spi_device_flash_and_tpm_min_idle.108218232419752182888656387242384129098245842811118427018111482548609450581455
Line 250, in log /container/opentitan-public/scratch/os_regression/spi_device-sim-vcs/22.spi_device_flash_and_tpm_min_idle/latest/run.log

  UVM_ERROR @ 567762574 ps: (spi_device_scoreboard.sv:1054) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0x6e2bba) != exp '{'{other_status:'h19f76b, wel:'h0, busy:'h0}}
  UVM_INFO @ 788030039 ps: (spi_device_tpm_read_hw_reg_vseq.sv:48) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_and_tpm_min_idle_vseq.tpm_vseq] starting sequence 2/19
  UVM_INFO @ 861860930 ps: (spi_device_flash_all_vseq.sv:46) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_and_tpm_min_idle_vseq.flash_vseq] running iteration 1/20
  UVM_INFO @ 1496167282 ps: (spi_device_flash_all_vseq.sv:46) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_and_tpm_min_idle_vseq.flash_vseq] running iteration 2/20
  UVM_INFO @ 1528043302 ps: (spi_device_tpm_read_hw_reg_vseq.sv:48) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_and_tpm_min_idle_vseq.tpm_vseq] starting sequence 3/19

Test spi_device_stress_all has 1 failures.

38.spi_device_stress_all.43422138342590600406048628242817856326858130871577699326954795985695095371711
Line 260, in log /container/opentitan-public/scratch/os_regression/spi_device-sim-vcs/38.spi_device_stress_all/latest/run.log

  UVM_ERROR @ 1304944435 ps: (spi_device_scoreboard.sv:1054) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0x1e0eda) != exp '{'{other_status:'h0, wel:'h0, busy:'h0}}
  UVM_INFO @ 1633464435 ps: (spi_device_flash_all_vseq.sv:46) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_and_tpm_vseq.flash_vseq] running iteration 1/16
  UVM_INFO @ 1643524435 ps: (spi_device_tpm_read_hw_reg_vseq.sv:48) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_and_tpm_vseq.tpm_vseq] starting sequence 2/4
  UVM_INFO @ 2128368413 ps: (spi_device_flash_all_vseq.sv:46) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_and_tpm_vseq.flash_vseq] running iteration 2/16
  UVM_INFO @ 2149734435 ps: (spi_device_tpm_read_hw_reg_vseq.sv:48) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_and_tpm_vseq.tpm_vseq] starting sequence 3/4

UVM_WARNING (uvm_reg_field.svh:1191) [RegModel] Trying to predict value of field 'addr_4b_en' while register 'spi_device_reg_block.cfg' is being accessed has 1 failures:

Test spi_device_stress_all has 1 failures.

4.spi_device_stress_all.45869147816862704911348157588956619059552836279040877871767828622917104371111
Line 440, in log /container/opentitan-public/scratch/os_regression/spi_device-sim-vcs/4.spi_device_stress_all/latest/run.log

  UVM_WARNING @ 58112996958 ps: (uvm_reg_field.svh:1191) [RegModel] Trying to predict value of field 'addr_4b_en' while register 'spi_device_reg_block.cfg' is being accessed
  UVM_INFO @ 58227102642 ps: (spi_device_flash_all_vseq.sv:46) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_and_tpm_vseq.flash_vseq] running iteration 8/17
  UVM_INFO @ 58303812123 ps: (spi_device_tpm_read_hw_reg_vseq.sv:48) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_and_tpm_vseq.tpm_vseq] starting sequence 9/9
  UVM_INFO @ 58642573457 ps: (spi_device_flash_all_vseq.sv:46) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_and_tpm_vseq.flash_vseq] running iteration 9/17
  UVM_INFO @ 58850743265 ps: (spi_device_flash_all_vseq.sv:46) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_and_tpm_vseq.flash_vseq] running iteration 10/17

UVM_ERROR (spi_device_scoreboard.sv:436) scoreboard [scoreboard] Compare TPM reg failed, offset: *, act: *, exp: '{*} has 1 failures:

Test spi_device_flash_and_tpm_min_idle has 1 failures.

9.spi_device_flash_and_tpm_min_idle.104607899703716139063201678317606478585346523617069481885388185542303844325846
Line 250, in log /container/opentitan-public/scratch/os_regression/spi_device-sim-vcs/9.spi_device_flash_and_tpm_min_idle/latest/run.log

  UVM_ERROR @  18990733 ps: (spi_device_scoreboard.sv:436) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] Compare TPM reg failed, offset: 0, act: 0x28b568b3, exp: '{'hffffff44}
  UVM_FATAL @  54829963 ps: (spi_device_scoreboard.sv:1165) [uvm_test_top.env.scoreboard] Check failed tpm_read_sw_q.size == 0 (1 [0x1] vs 0 [0x0])
  UVM_INFO @  54829963 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR (spi_device_env_pkg.sv:177) [read_tx_avail_bytes] Check failed rptr >= wptr (* [*] vs * [*]) get_sram_space_bytes:: has 1 failures:

Test spi_device_stress_all has 1 failures.

9.spi_device_stress_all.105031860704989296688684801237700335003384780128407005911915682067907897291405
Line 292, in log /container/opentitan-public/scratch/os_regression/spi_device-sim-vcs/9.spi_device_stress_all/latest/run.log

  UVM_ERROR @ 33626472216 ps: (spi_device_env_pkg.sv:177) [read_tx_avail_bytes] Check failed rptr >= wptr (4 [0x4] vs 1416 [0x588]) get_sram_space_bytes::
  UVM_ERROR @ 33640072216 ps: (spi_device_env_pkg.sv:177) [read_tx_avail_bytes] Check failed rptr >= wptr (4 [0x4] vs 1780 [0x6f4]) get_sram_space_bytes::
  UVM_ERROR @ 33649072216 ps: (mem_model.sv:35) [rx_mem] read from uninitialized addr 0x2fb
  UVM_ERROR @ 33649072216 ps: (mem_model.sv:35) [rx_mem] read from uninitialized addr 0x2fa
  UVM_ERROR @ 33649072216 ps: (mem_model.sv:35) [rx_mem] read from uninitialized addr 0x2f9

UVM_ERROR (spi_device_scoreboard.sv:838) scoreboard [scoreboard] Compare failed, downstream item: has 1 failures:

Test spi_device_stress_all has 1 failures.

10.spi_device_stress_all.104427765249151884393403460640577830222303022939711214322472504433497196897473
Line 286, in log /container/opentitan-public/scratch/os_regression/spi_device-sim-vcs/10.spi_device_stress_all/latest/run.log

  UVM_ERROR @ 113054257063 ps: (spi_device_scoreboard.sv:838) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] Compare failed, downstream item:
  -------------------------------------------------------------
  Name                   Type              Size  Value
  -------------------------------------------------------------
  host_item              spi_item          -     @34867862

Exit reason: Error: User command failed Job returned non-zero exit code has 1 failures:

Test spi_device_cfg_cmd has 1 failures.

15.spi_device_cfg_cmd.17679396073804821877890802698927255146631889112017458370239775352357065910287
Log /container/opentitan-public/scratch/os_regression/spi_device-sim-vcs/15.spi_device_cfg_cmd/latest/run.log

  [make]: simulate
  cd /workspace/15.spi_device_cfg_cmd/latest && /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3595102223 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_cfg_cmd.3595102223
  Chronologic VCS simulator copyright 1991-2022
  Contains Synopsys proprietary information.
  Compiler version T-2022.06-SP2_Full64; Runtime version T-2022.06-SP2_Full64;  Dec 27 13:31 2023
  Cannot find license file.
  Make sure that you have a license file and that your
  LM_LICENSE_FILE is pointing to the right location.
  
  make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:175: simulate] Error 255

UVM_ERROR (spi_monitor.sv:323) [monitor] Check failed data[i] !== *'bz (z [0xz] vs z [0xz]) has 1 failures:

Test spi_device_stress_all has 1 failures.

18.spi_device_stress_all.25041656755092729789865553037646701554397277417558789596887892122767091919039
Line 252, in log /container/opentitan-public/scratch/os_regression/spi_device-sim-vcs/18.spi_device_stress_all/latest/run.log

  UVM_ERROR @ 3485237302 ps: (spi_monitor.sv:323) [uvm_test_top.env.spi_device_agent.monitor] Check failed data[i] !== 1'bz (z [0xz] vs z [0xz])
  UVM_ERROR @ 3485237302 ps: (spi_monitor.sv:323) [uvm_test_top.env.spi_device_agent.monitor] Check failed data[i] !== 1'bz (z [0xz] vs z [0xz])
  UVM_ERROR @ 3485237302 ps: (spi_monitor.sv:323) [uvm_test_top.env.spi_device_agent.monitor] Check failed data[i] !== 1'bz (z [0xz] vs z [0xz])
  UVM_ERROR @ 3485237302 ps: (spi_monitor.sv:323) [uvm_test_top.env.spi_device_agent.monitor] Check failed data[i] !== 1'bz (z [0xz] vs z [0xz])
  UVM_ERROR @ 3485237302 ps: (spi_monitor.sv:323) [uvm_test_top.env.spi_device_agent.monitor] Check failed data[i] !== 1'bz (z [0xz] vs z [0xz])

UVM_ERROR (mem_model.sv:35) [rx_mem] read from uninitialized addr * has 1 failures:

Test spi_device_stress_all has 1 failures.

25.spi_device_stress_all.80789290315341113484431104667222034078757823481831267688148180496314503975854
Line 285, in log /container/opentitan-public/scratch/os_regression/spi_device-sim-vcs/25.spi_device_stress_all/latest/run.log

  UVM_ERROR @ 105487121182 ps: (mem_model.sv:35) [rx_mem] read from uninitialized addr 0x637
  UVM_ERROR @ 105487121182 ps: (mem_model.sv:35) [rx_mem] read from uninitialized addr 0x636
  UVM_ERROR @ 105487121182 ps: (mem_model.sv:35) [rx_mem] read from uninitialized addr 0x635
  UVM_ERROR @ 105487121182 ps: (mem_model.sv:35) [rx_mem] read from uninitialized addr 0x634
  UVM_ERROR @ 105487121182 ps: (spi_device_scoreboard.sv:985) [uvm_test_top.env.scoreboard] Check failed item.d_data == data_exp (3988930392 [0xedc23f58] vs 1811937374 [0x6bfff85e]) Compare SPI RX data, addr: 0x634

UVM_FATAL (spi_device_base_vseq.sv:413) [spi_device_intr_vseq] wait_for_rx_avail_bytes::SramDataAvail has 1 failures:
- Test spi_device_stress_all has 1 failures.
  - 26.spi_device_stress_all.99481015284581744370330341737609270945785766669683708234626675225599082342979
    Line 358, in log /container/opentitan-public/scratch/os_regression/spi_device-sim-vcs/26.spi_device_stress_all/latest/run.log
```
  UVM_FATAL @ 112947327503 ps: (spi_device_base_vseq.sv:413) [uvm_test_top.env.virtual_sequencer.spi_device_intr_vseq] wait_for_rx_avail_bytes::SramDataAvail
  UVM_INFO @ 112947327503 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR (spi_device_scoreboard.sv:1085) [scoreboard] Check failed item.d_data[i] == intr_exp[i] (* [*] vs * [*]) Compare PayloadOverflow mismatch, act (*) != exp * has 1 failures:

Test spi_device_stress_all has 1 failures.

29.spi_device_stress_all.9233442510323056972161466876376797723937440169519535778982101037301284556736
Line 347, in log /container/opentitan-public/scratch/os_regression/spi_device-sim-vcs/29.spi_device_stress_all/latest/run.log

  UVM_ERROR @ 77010586876 ps: (spi_device_scoreboard.sv:1085) [uvm_test_top.env.scoreboard] Check failed item.d_data[i] == intr_exp[i] (0 [0x0] vs 1 [0x1]) Compare PayloadOverflow mismatch, act (0x0) != exp 1
  UVM_INFO @ 78047661644 ps: (spi_device_flash_all_vseq.sv:46) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_and_tpm_vseq.flash_vseq] running iteration 9/13
  UVM_INFO @ 82748989948 ps: (spi_device_tpm_read_hw_reg_vseq.sv:48) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_and_tpm_vseq.tpm_vseq] starting sequence 8/9
  UVM_INFO @ 83798083100 ps: (spi_device_flash_all_vseq.sv:46) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_and_tpm_vseq.flash_vseq] running iteration 10/13
  UVM_INFO @ 88794370156 ps: (spi_device_flash_all_vseq.sv:46) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_and_tpm_vseq.flash_vseq] running iteration 11/13

UVM_FATAL (csr_utils_pkg.sv:566) [csr_utils::csr_spinwait] timeout spi_device_reg_block.async_fifo_level.rxlvl (addr=*) == * has 1 failures:
- Test spi_device_stress_all has 1 failures.
  - 34.spi_device_stress_all.12565060306593916824496255412840727629510947046250827717210787551862596567073
    Line 387, in log /container/opentitan-public/scratch/os_regression/spi_device-sim-vcs/34.spi_device_stress_all/latest/run.log
```
  UVM_FATAL @ 2731527262708 ps: (csr_utils_pkg.sv:566) [csr_utils::csr_spinwait] timeout spi_device_reg_block.async_fifo_level.rxlvl (addr=0x7245801c) == 0x0
  UVM_INFO @ 2731527262708 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR (spi_device_scoreboard.sv:497) scoreboard [scoreboard] flash_status mismatch, backdoor value: *, exp: * has 1 failures:

Test spi_device_stress_all has 1 failures.

44.spi_device_stress_all.4425542449789855835885450793717900962153536259847062977421402679740083143062
Line 282, in log /container/opentitan-public/scratch/os_regression/spi_device-sim-vcs/44.spi_device_stress_all/latest/run.log

  UVM_ERROR @ 197016364681 ps: (spi_device_scoreboard.sv:497) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] flash_status mismatch, backdoor value: 0x966e06, exp: 0x1ec502
  UVM_ERROR @ 197016364681 ps: (spi_device_scoreboard.sv:497) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] flash_status mismatch, backdoor value: 0x966e06, exp: 0x1ec502
  UVM_INFO @ 208695153610 ps: (spi_device_flash_all_vseq.sv:46) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_and_tpm_vseq.flash_vseq] running iteration 10/16
  UVM_INFO @ 217359754588 ps: (spi_device_flash_all_vseq.sv:46) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_and_tpm_vseq.flash_vseq] running iteration 11/16
  UVM_INFO @ 240822639294 ps: (spi_device_flash_all_vseq.sv:46) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_and_tpm_vseq.flash_vseq] running iteration 12/16