Unified Coverage Report :: Module :: spid_upload

Module : spid_upload

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.70	100.00	87.18		100.00	96.30	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_spi_device_0.1/rtl/spid_upload.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_upload	96.70	100.00	87.18		100.00	96.30	100.00

---

Module Instance : tb.dut.u_upload

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.70	100.00	87.18		100.00	96.30	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.13	98.58	73.82		100.00	93.98	89.29

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.39	96.31	94.03	97.00		93.33	96.30	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_addrfifo	93.75	100.00	75.00			100.00	100.00
u_arbiter	71.57	92.21	51.22			71.43	71.43
u_cmdfifo	93.75	100.00	75.00			100.00	100.00
u_payload_buffer	94.44	100.00	77.78			100.00	100.00
u_payloadptr_clr_psync	100.00	100.00	100.00			100.00	100.00

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : spid_upload

	Line No.	Total	Covered	Percent
TOTAL		120	120	100.00
CONT_ASSIGN	134	1	1	100.00
CONT_ASSIGN	137	1	1	100.00
CONT_ASSIGN	143	1	1	100.00
CONT_ASSIGN	194	1	1	100.00
CONT_ASSIGN	206	1	1	100.00
CONT_ASSIGN	213	1	1	100.00
CONT_ASSIGN	234	1	1	100.00
CONT_ASSIGN	241	1	1	100.00
CONT_ASSIGN	242	1	1	100.00
CONT_ASSIGN	244	1	1	100.00
CONT_ASSIGN	246	1	1	100.00
CONT_ASSIGN	247	1	1	100.00
CONT_ASSIGN	248	1	1	100.00
ALWAYS	252	6	6	100.00
ALWAYS	258	3	3	100.00
ALWAYS	264	4	4	100.00
ALWAYS	301	6	6	100.00
ALWAYS	313	3	3	100.00
ALWAYS	319	5	5	100.00
CONT_ASSIGN	327	1	1	100.00
ALWAYS	346	10	10	100.00
ALWAYS	367	8	8	100.00
ALWAYS	390	8	8	100.00
ALWAYS	408	6	6	100.00
ALWAYS	418	6	6	100.00
CONT_ASSIGN	425	1	1	100.00
ALWAYS	428	3	3	100.00
ALWAYS	438	26	26	100.00
CONT_ASSIGN	575	1	1	100.00
CONT_ASSIGN	582	1	1	100.00
CONT_ASSIGN	583	1	1	100.00
CONT_ASSIGN	584	1	1	100.00
CONT_ASSIGN	585	1	1	100.00
CONT_ASSIGN	635	1	1	100.00
CONT_ASSIGN	642	1	1	100.00
CONT_ASSIGN	643	1	1	100.00
CONT_ASSIGN	644	1	1	100.00
CONT_ASSIGN	645	1	1	100.00
CONT_ASSIGN	711	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_spi_device_0.1/rtl/spid_upload.sv' or '../src/lowrisc_ip_spi_device_0.1/rtl/spid_upload.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
134	1	1
137	1	1
143	1	1
194	1	1
206	1	1
213	1	1
234	1	1
241	1	1
242	1	1
244	1	1
246	1	1
247	1	1
248	1	1
252	2	2
253	2	2
254	2	2
			MISSING_ELSE
258	1	1
259	1	1
260	1	1
			MISSING_ELSE
264	1	1
265	1	1
266	1	1
267	1	1
			MISSING_ELSE
301	2	2
304	2	2
305	2	2
			MISSING_ELSE
313	2	2
314	1	1
319	2	2
320	1	1
321	1	1
323	1	1
327	1	1
346	1	1
347	1	1
348	1	1
349	1	1
350	1	1
351	1	1
352	1	1
353	1	1
355	1	1
			MISSING_ELSE
357	1	1
			MISSING_ELSE
367	2	2
368	2	2
369	1	1
370	1	1
371	1	1
372	1	1
			MISSING_ELSE
390	2	2
391	2	2
392	1	1
395	1	1
396	1	1
399	1	1
			MISSING_ELSE
408	2	2
409	2	2
410	1	1
411	1	1
			MISSING_ELSE
418	2	2
419	2	2
420	1	1
421	1	1
			MISSING_ELSE
425	1	1
428	1	1
429	1	1
431	1	1
438	1	1
440	1	1
441	1	1
442	1	1
444	1	1
445	1	1
447	1	1
449	1	1
450	1	1
452	1	1
454	1	1
455	1	1
456	1	1
459	1	1
461	1	1
465	1	1
469	1	1
471	1	1
			==> MISSING_ELSE
475	1	1
			MISSING_ELSE
481	1	1
483	1	1
484	1	1
486	1	1
			MISSING_ELSE
492	1	1
493	1	1
494	1	1
			MISSING_ELSE
575	1	1
582	1	1
583	1	1
584	1	1
585	1	1
635	1	1
642	1	1
643	1	1
644	1	1
645	1	1
711	1	1

---

Cond Coverage for Module : spid_upload

	Total	Covered	Percent
Conditions	39	34	87.18
Logical	39	34	87.18
Non-Logical	0	0
Event	0	0

 LINE       242
 EXPRESSION (cmdinfo_addr_mode != AddrDisabled)
            -----------------1-----------------

-1-	Status	Tests
0	Covered	T4,T1,T2
1	Covered	T9,T10,T17

 LINE       244
 EXPRESSION (cmdinfo_addr_mode == Addr4B)
            --------------1--------------

-1-	Status	Tests
0	Covered	T4,T1,T2
1	Covered	T9,T10,T5

 LINE       253
 EXPRESSION (cmdinfo_addr_4b_en ? 5'd31 : 5'd23)
             ---------1--------

-1-	Status	Tests
0	Covered	T6,T7,T44
1	Covered	T5,T7,T44

 LINE       266
 EXPRESSION (s2p_valid_i && addr_shift)
             -----1-----    -----2----

-1-	-2-	Status	Tests
0	1	Covered	T5,T6,T7
1	0	Covered	T1,T9,T3
1	1	Covered	T5,T6,T7

 LINE       304
 EXPRESSION (cmdfifo_wvalid && cmdfifo_wready)
             -------1------    -------2------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Covered	T5,T6,T7

 LINE       320
 EXPRESSION (sys_csb_deasserted_pulse_i && csb_cmdfifo_set)
             -------------1------------    -------2-------

-1-	-2-	Status	Tests
0	1	Covered	T5,T6,T7
1	0	Covered	T1,T9,T3
1	1	Covered	T5,T6,T7

 LINE       353
 EXPRESSION (payloadptr == 8'((PayloadByte - 1)))
            ------------------1------------------

-1-	Status	Tests
0	Covered	T5,T6,T7
1	Covered	T5,T6,T7

 LINE       369
 EXPRESSION (sys_csb_deasserted_pulse_i && payload_max)
             -------------1------------    -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T5,T6,T7
1	0	Covered	T1,T9,T3
1	1	Covered	T5,T6,T7

 LINE       371
 EXPRESSION (sys_csb_deasserted_pulse_i && ((!payload_max)))
             -------------1------------    --------2-------

-1-	-2-	Status	Tests
0	1	Covered	T4,T1,T2
1	0	Not Covered
1	1	Covered	T1,T9,T3

 LINE       392
 EXPRESSION (sys_csb_deasserted_pulse_i && payload_max)
             -------------1------------    -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T5,T6,T7
1	0	Covered	T1,T9,T3
1	1	Covered	T5,T6,T7

 LINE       396
 EXPRESSION (sys_csb_deasserted_pulse_i && ((!payload_max)))
             -------------1------------    --------2-------

-1-	-2-	Status	Tests
0	1	Covered	T4,T1,T2
1	0	Not Covered
1	1	Covered	T1,T9,T3

 LINE       410
 EXPRESSION (payloadptr_inc && payload_max)
             -------1------    -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T5,T6,T7
1	0	Covered	T5,T6,T7
1	1	Covered	T5,T6,T7

 LINE       454
 EXPRESSION (s2p_valid_i && (cmd_only_sel_dp_i == DpUpload))
             -----1-----    ---------------2---------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T9,T3
1	1	Covered	T5,T6,T7

 LINE       454
 SUB-EXPRESSION (cmd_only_sel_dp_i == DpUpload)
                ---------------1---------------

-1-	Status	Tests
0	Covered	T4,T1,T2
1	Covered	T5,T6,T7

 LINE       483
 EXPRESSION (addrcnt == '0)
            -------1-------

-1-	Status	Tests
0	Covered	T5,T6,T7
1	Covered	T5,T6,T7

---

FSM Coverage for Module : spid_upload

Summary for FSM :: st_q

	Total	Covered	Percent
States	3	3	100.00	(Not included in score)
Transitions	3	3	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: st_q

---

states	Line No.	Covered	Tests
StAddress	456	Covered	T5,T6,T7
StIdle	453	Covered	T4,T1,T2
StPayload	461	Covered	T5,T6,T7

transitions	Line No.	Covered	Tests
StAddress->StPayload	484	Covered	T5,T6,T7
StIdle->StAddress	456	Covered	T5,T6,T7
StIdle->StPayload	461	Covered	T5,T6,T44

---

Branch Coverage for Module : spid_upload

	Line No.	Total	Covered	Percent
Branches		54	52	96.30
IF	252	5	5	100.00
IF	259	2	2	100.00
IF	264	3	3	100.00
IF	301	4	4	100.00
IF	313	2	2	100.00
IF	319	3	3	100.00
IF	346	5	5	100.00
IF	367	5	5	100.00
IF	390	5	5	100.00
IF	408	4	4	100.00
IF	418	4	4	100.00
IF	428	2	2	100.00
CASE	452	10	8	80.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_spi_device_0.1/rtl/spid_upload.sv' or '../src/lowrisc_ip_spi_device_0.1/rtl/spid_upload.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	252	if ((!rst_ni))
-2-:	253	if (addr_update)
-3-:	253	(cmdinfo_addr_4b_en) ? 
-4-:	254	if (addr_shift)

Branches:

-1-	-2-	-3-	-4-	Status	Tests
1	-	-	-	Covered	T4,T1,T2
0	1	1	-	Covered	T5,T7,T44
0	1	0	-	Covered	T6,T7,T44
0	0	-	1	Covered	T5,T6,T7
0	0	-	0	Covered	T1,T9,T3

	LineNo.	Expression
-1-:	259	if (addr_shift)

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T7
0	Covered	T4,T1,T2

	LineNo.	Expression
-1-:	264	if ((!rst_ni))
-2-:	266	if ((s2p_valid_i && addr_shift))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T4,T1,T2
0	1	Covered	T5,T6,T7
0	0	Covered	T1,T9,T3

	LineNo.	Expression
-1-:	301	if ((!sys_rst_ni))
-2-:	304	if ((cmdfifo_wvalid && cmdfifo_wready))
-3-:	305	if (sck_csb_asserted_pulse_i)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T1,T2
0	1	-	Covered	T5,T6,T7
0	0	1	Covered	T1,T9,T3
0	0	0	Covered	T1,T9,T3

	LineNo.	Expression
-1-:	313	if ((!sys_rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T2
0	Covered	T1,T9,T3

	LineNo.	Expression
-1-:	319	if ((!sys_rst_ni))
-2-:	320	if ((sys_csb_deasserted_pulse_i && csb_cmdfifo_set))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T4,T1,T2
0	1	Covered	T5,T6,T7
0	0	Covered	T4,T1,T2

	LineNo.	Expression
-1-:	346	if ((!sys_rst_ni))
-2-:	349	if (payloadptr_clr)
-3-:	352	if (payloadptr_inc)
-4-:	353	if ((payloadptr == 8'((PayloadByte - 1))))

Branches:

-1-	-2-	-3-	-4-	Status	Tests
1	-	-	-	Covered	T4,T1,T2
0	1	-	-	Covered	T5,T6,T7
0	0	1	1	Covered	T5,T6,T7
0	0	1	0	Covered	T5,T6,T7
0	0	0	-	Covered	T1,T9,T3

	LineNo.	Expression
-1-:	367	if ((!sys_rst_ni))
-2-:	368	if (sys_payloadptr_clr_posedge)
-3-:	369	if ((sys_csb_deasserted_pulse_i && payload_max))
-4-:	371	if ((sys_csb_deasserted_pulse_i && (!payload_max)))

Branches:

-1-	-2-	-3-	-4-	Status	Tests
1	-	-	-	Covered	T4,T1,T2
0	1	-	-	Covered	T5,T6,T7
0	0	1	-	Covered	T5,T6,T7
0	0	0	1	Covered	T1,T9,T3
0	0	0	0	Covered	T4,T1,T2

	LineNo.	Expression
-1-:	390	if ((!sys_rst_ni))
-2-:	391	if (sys_payloadptr_clr_posedge)
-3-:	392	if ((sys_csb_deasserted_pulse_i && payload_max))
-4-:	396	if ((sys_csb_deasserted_pulse_i && (!payload_max)))

Branches:

-1-	-2-	-3-	-4-	Status	Tests
1	-	-	-	Covered	T4,T1,T2
0	1	-	-	Covered	T5,T6,T7
0	0	1	-	Covered	T5,T6,T7
0	0	0	1	Covered	T1,T9,T3
0	0	0	0	Covered	T4,T1,T2

	LineNo.	Expression
-1-:	408	if ((!sys_rst_ni))
-2-:	409	if (payloadptr_clr)
-3-:	410	if ((payloadptr_inc && payload_max))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T1,T2
0	1	-	Covered	T5,T6,T7
0	0	1	Covered	T5,T6,T7
0	0	0	Covered	T1,T9,T3

	LineNo.	Expression
-1-:	418	if ((!sys_rst_ni))
-2-:	419	if (sys_payloadptr_clr_posedge)
-3-:	420	if (sys_csb_deasserted_pulse_i)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T1,T2
0	1	-	Covered	T5,T6,T7
0	0	1	Covered	T1,T9,T3
0	0	0	Covered	T4,T1,T2

	LineNo.	Expression
-1-:	428	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T2
0	Covered	T1,T9,T3

	LineNo.	Expression
-1-:	452	case (st_q)
-2-:	454	if ((s2p_valid_i && (cmd_only_sel_dp_i == DpUpload)))
-3-:	455	if (cmdinfo_addr_en)
-4-:	469	if (cmd_only_info_i.busy)
-5-:	483	if ((addrcnt == '0))
-6-:	492	if (s2p_valid_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	Status	Tests
StIdle	1	1	-	-	-	Covered	T5,T6,T7
StIdle	1	0	-	-	-	Covered	T5,T6,T44
StIdle	1	-	1	-	-	Covered	T5,T6,T7
StIdle	1	-	0	-	-	Not Covered
StIdle	0	-	-	-	-	Covered	T4,T1,T2
StAddress	-	-	-	1	-	Covered	T5,T6,T7
StAddress	-	-	-	0	-	Covered	T5,T6,T7
StPayload	-	-	-	-	1	Covered	T5,T6,T7
StPayload	-	-	-	-	0	Covered	T5,T6,T7
default	-	-	-	-	-	Not Covered

---

Assert Coverage for Module : spid_upload

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AddrFifoNeverFull_M	386536807	1856	0	0
CmdFifoNeverFull_M	386536807	2494	0	0
CmdFifoPush_A	386536807	2494	0	0
FifosOnlyOneValid_A	386536807	335033634	0	0
PayloadNeverFull_M	386536807	708357	0	0

AddrFifoNeverFull_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	386536807	1856	0	0
T5	144411	2	0	0
T6	624216	11	0	0
T7	0	14	0	0
T11	101926	0	0	0
T18	0	4	0	0
T19	78353	0	0	0
T20	0	17	0	0
T22	0	2	0	0
T27	0	7	0	0
T28	0	15	0	0
T33	20673	0	0	0
T44	0	20	0	0
T45	0	14	0	0
T49	75745	0	0	0
T50	66388	0	0	0
T51	562019	0	0	0
T52	130934	0	0	0
T53	384833	0	0	0

CmdFifoNeverFull_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	386536807	2494	0	0
T5	144411	3	0	0
T6	624216	12	0	0
T7	0	14	0	0
T11	101926	0	0	0
T18	0	4	0	0
T19	78353	0	0	0
T20	0	26	0	0
T22	0	4	0	0
T27	0	8	0	0
T28	0	19	0	0
T33	20673	0	0	0
T44	0	26	0	0
T45	0	23	0	0
T49	75745	0	0	0
T50	66388	0	0	0
T51	562019	0	0	0
T52	130934	0	0	0
T53	384833	0	0	0

CmdFifoPush_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	386536807	2494	0	0
T5	144411	3	0	0
T6	624216	12	0	0
T7	0	14	0	0
T11	101926	0	0	0
T18	0	4	0	0
T19	78353	0	0	0
T20	0	26	0	0
T22	0	4	0	0
T27	0	8	0	0
T28	0	19	0	0
T33	20673	0	0	0
T44	0	26	0	0
T45	0	23	0	0
T49	75745	0	0	0
T50	66388	0	0	0
T51	562019	0	0	0
T52	130934	0	0	0
T53	384833	0	0	0

FifosOnlyOneValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	386536807	335033634	0	0
T1	3059	3051	0	0
T3	3272	3263	0	0
T8	385	384	0	0
T9	171344	171072	0	0
T10	22753	22308	0	0
T12	82497	82496	0	0
T13	367079	325824	0	0
T14	473954	473952	0	0
T15	10327	9632	0	0
T16	417	416	0	0

PayloadNeverFull_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	386536807	708357	0	0
T5	144411	769	0	0
T6	624216	7124	0	0
T7	0	1701	0	0
T11	101926	0	0	0
T18	0	256	0	0
T19	78353	0	0	0
T20	0	3286	0	0
T22	0	5	0	0
T27	0	6482	0	0
T28	0	2029	0	0
T33	20673	0	0	0
T44	0	7327	0	0
T45	0	1710	0	0
T49	75745	0	0	0
T50	66388	0	0	0
T51	562019	0	0	0
T52	130934	0	0	0
T53	384833	0	0	0