Unified Coverage Report :: Module :: spi_device

Module : spi_device

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.39	96.31	94.03	97.00		93.33	96.30

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_spi_device_0.1/rtl/spi_device.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut	95.39	96.31	94.03	97.00		93.33	96.30

---

Module Instance : tb.dut

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.39	96.31	94.03	97.00		93.33	96.30

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.66	99.01	96.33	98.63	92.06	98.05	95.86

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							tb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_alert_tx[0].u_prim_alert_sender	100.00			100.00
spi_device_csr_assert	100.00						100.00
tlul_assert_device	100.00	100.00				100.00	100.00
u_clk_csb_buf	100.00	100.00
u_clk_csb_edge_0	100.00	100.00	100.00			100.00
u_clk_csb_mux	64.81	100.00	44.44				50.00
u_clk_spi	85.19	100.00	55.56				100.00
u_clk_spi_in_buf	100.00	100.00
u_clk_spi_in_mux	64.81	100.00	44.44				50.00
u_clk_spi_out_buf	100.00	100.00
u_clk_spi_out_mux	64.81	100.00	44.44				50.00
u_cmdparse	99.06	100.00	97.33		100.00	97.96	100.00
u_csb_buf	100.00	100.00
u_csb_edge_spiclk	94.44	100.00	83.33			100.00
u_csb_edge_sysclk	100.00	100.00	100.00			100.00
u_csb_rst_scan_mux	64.81	100.00	44.44				50.00
u_flash_readbuf_flip_pulse_sync	100.00	100.00	100.00			100.00	100.00
u_flash_readbuf_watermark_pulse_sync	100.00	100.00	100.00			100.00	100.00
u_fwmode	94.94	99.27	89.44		100.00	97.11	88.89
u_intr_cmdfifo_not_empty	100.00	100.00	100.00			100.00	100.00
u_intr_payload_not_empty	100.00	100.00	100.00			100.00	100.00
u_intr_payload_overflow	100.00	100.00	100.00			100.00	100.00
u_intr_readbuf_flip	100.00	100.00	100.00			100.00	100.00
u_intr_readbuf_watermark	100.00	100.00	100.00			100.00	100.00
u_intr_rxerr	100.00	100.00	100.00			100.00	100.00
u_intr_rxf	100.00	100.00	100.00			100.00	100.00
u_intr_rxlvl	100.00	100.00	100.00			100.00	100.00
u_intr_rxoverflow	100.00	100.00	100.00			100.00	100.00
u_intr_tpm_cmdaddr_notempty	100.00	100.00	100.00			100.00	100.00
u_intr_txlvl	100.00	100.00	100.00			100.00	100.00
u_intr_txunderflow	100.00	100.00	100.00			100.00	100.00
u_intr_upload_edge	100.00	100.00				100.00
u_jedec	99.38	100.00	100.00		100.00	96.88	100.00
u_memory_2p	100.00	100.00	100.00			100.00	100.00
u_p2s	90.20	100.00	84.62			76.19	100.00
u_passthrough	90.46	94.33	90.09		75.00	92.86	100.00
u_readcmd	93.14	97.16	93.19		87.50	87.82	100.00
u_reg	99.68	99.49	99.57	100.00		99.32	100.00
u_rx_rst_scan_mux	64.81	100.00	44.44				50.00
u_rxf_overflow	75.00	100.00	100.00			100.00	0.00
u_s2p	89.85	100.00	85.71			73.68	100.00
u_scanmode_sync	100.00						100.00
u_sck_csb_edge	94.44	100.00	83.33			100.00
u_sck_tog_edge	100.00	100.00	100.00			100.00
u_spi_tpm	96.43	99.76	93.53		91.67	97.18	100.00
u_spid_addr_4b	100.00	100.00	100.00			100.00
u_spid_status	96.19	100.00	86.84		100.00	94.12	100.00
u_sram_clk_cg	83.33	100.00	50.00			100.00
u_sram_clk_scan	64.81	100.00	44.44				50.00
u_sram_clk_sel	100.00	100.00	100.00				100.00
u_sram_rst_scanmux	64.81	100.00	44.44				50.00
u_sram_rst_sel	100.00	100.00	100.00				100.00
u_sync_rxf	100.00	100.00				100.00
u_sync_txe	100.00	100.00				100.00
u_sys_sram_arbiter	87.03	100.00	70.73			96.43	80.95
u_sys_tpm_csb_sync	100.00	100.00				100.00
u_tlul2sram	88.21	88.70	77.78			86.36	100.00
u_tpm_csb_buf	100.00	100.00
u_tpm_csb_rst_scan_mux	64.81	100.00	44.44				50.00
u_tpm_csb_rst_sync	70.83	88.89	44.44			100.00	50.00
u_tx_rst_scan_mux	64.81	100.00	44.44				50.00
u_txf_underflow	75.00	100.00	100.00			100.00	0.00
u_upload	91.13	98.58	73.82		100.00	93.98	89.29

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : spi_device

	Line No.	Total	Covered	Percent
TOTAL		244	235	96.31
CONT_ASSIGN	191	1	1	100.00
CONT_ASSIGN	341	1	1	100.00
CONT_ASSIGN	400	1	1	100.00
CONT_ASSIGN	401	1	1	100.00
CONT_ASSIGN	402	1	1	100.00
CONT_ASSIGN	403	1	1	100.00
CONT_ASSIGN	405	1	1	100.00
CONT_ASSIGN	406	1	1	100.00
CONT_ASSIGN	408	1	1	100.00
CONT_ASSIGN	410	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	415	1	1	100.00
CONT_ASSIGN	416	1	1	100.00
CONT_ASSIGN	417	1	1	100.00
CONT_ASSIGN	419	1	1	100.00
CONT_ASSIGN	420	1	1	100.00
CONT_ASSIGN	423	1	1	100.00
CONT_ASSIGN	424	1	1	100.00
CONT_ASSIGN	427	1	1	100.00
CONT_ASSIGN	430	1	1	100.00
CONT_ASSIGN	431	1	1	100.00
CONT_ASSIGN	434	1	1	100.00
CONT_ASSIGN	435	1	1	100.00
CONT_ASSIGN	438	1	1	100.00
CONT_ASSIGN	439	1	1	100.00
ALWAYS	443	3	3	100.00
ALWAYS	447	3	3	100.00
CONT_ASSIGN	463	1	1	100.00
CONT_ASSIGN	467	1	1	100.00
CONT_ASSIGN	468	1	1	100.00
ALWAYS	480	5	5	100.00
CONT_ASSIGN	490	1	1	100.00
CONT_ASSIGN	491	0	0
CONT_ASSIGN	493	1	1	100.00
CONT_ASSIGN	494	1	1	100.00
ALWAYS	497	5	5	100.00
CONT_ASSIGN	505	1	1	100.00
CONT_ASSIGN	506	1	1	100.00
CONT_ASSIGN	623	1	1	100.00
CONT_ASSIGN	725	1	1	100.00
CONT_ASSIGN	732	1	1	100.00
CONT_ASSIGN	734	1	1	100.00
ALWAYS	737	4	4	100.00
CONT_ASSIGN	745	1	1	100.00
CONT_ASSIGN	751	1	1	100.00
CONT_ASSIGN	754	1	1	100.00
CONT_ASSIGN	755	1	1	100.00
CONT_ASSIGN	759	1	1	100.00
ALWAYS	764	0	0
ALWAYS	764	2	2	100.00
CONT_ASSIGN	769	1	1	100.00
CONT_ASSIGN	770	1	1	100.00
ALWAYS	778	0	0
ALWAYS	778	12	12	100.00
CONT_ASSIGN	844	1	1	100.00
CONT_ASSIGN	845	1	1	100.00
CONT_ASSIGN	846	1	1	100.00
ALWAYS	1095	6	6	100.00
ALWAYS	1121	4	4	100.00
CONT_ASSIGN	1140	1	1	100.00
ALWAYS	1164	3	3	100.00
ALWAYS	1170	8	8	100.00
ALWAYS	1208	35	35	100.00
ALWAYS	1301	13	13	100.00
ALWAYS	1338	3	3	100.00
CONT_ASSIGN	1540	1	1	100.00
CONT_ASSIGN	1542	1	1	100.00
CONT_ASSIGN	1545	1	1	100.00
CONT_ASSIGN	1546	1	1	100.00
CONT_ASSIGN	1548	1	1	100.00
CONT_ASSIGN	1549	1	1	100.00
CONT_ASSIGN	1588	1	0	0.00
CONT_ASSIGN	1618	1	0	0.00
CONT_ASSIGN	1702	1	1	100.00
CONT_ASSIGN	1703	1	1	100.00
CONT_ASSIGN	1705	1	1	100.00
CONT_ASSIGN	1707	1	1	100.00
CONT_ASSIGN	1708	1	1	100.00
CONT_ASSIGN	1710	1	1	100.00
CONT_ASSIGN	1714	1	1	100.00
CONT_ASSIGN	1717	1	1	100.00
CONT_ASSIGN	1720	1	1	100.00
CONT_ASSIGN	1723	1	1	100.00
CONT_ASSIGN	1726	1	1	100.00
CONT_ASSIGN	1729	1	1	100.00
CONT_ASSIGN	1736	1	1	100.00
CONT_ASSIGN	1737	1	1	100.00
CONT_ASSIGN	1779	1	1	100.00
CONT_ASSIGN	1881	1	0	0.00
CONT_ASSIGN	1889	1	1	100.00
CONT_ASSIGN	1890	1	1	100.00
CONT_ASSIGN	1891	1	1	100.00
CONT_ASSIGN	1892	1	1	100.00
CONT_ASSIGN	1893	1	1	100.00
CONT_ASSIGN	1896	1	1	100.00
CONT_ASSIGN	1905	1	1	100.00
CONT_ASSIGN	1905	1	1	100.00
CONT_ASSIGN	1905	1	1	100.00
CONT_ASSIGN	1905	1	1	100.00
CONT_ASSIGN	1905	1	1	100.00
CONT_ASSIGN	1908	1	1	100.00
CONT_ASSIGN	1909	1	1	100.00
CONT_ASSIGN	1910	1	1	100.00
CONT_ASSIGN	1911	1	1	100.00
CONT_ASSIGN	1912	1	1	100.00
CONT_ASSIGN	1913	1	1	100.00
CONT_ASSIGN	1915	1	1	100.00
CONT_ASSIGN	1919	1	1	100.00
CONT_ASSIGN	1921	1	1	100.00
CONT_ASSIGN	1922	1	1	100.00
CONT_ASSIGN	1929	1	1	100.00
CONT_ASSIGN	1931	1	1	100.00
CONT_ASSIGN	1933	1	1	100.00
CONT_ASSIGN	1937	1	1	100.00
CONT_ASSIGN	1939	1	1	100.00
CONT_ASSIGN	1940	1	1	100.00
CONT_ASSIGN	1976	1	1	100.00
ALWAYS	1983	6	6	100.00
CONT_ASSIGN	1994	1	1	100.00
CONT_ASSIGN	1994	1	1	100.00
CONT_ASSIGN	1996	1	1	100.00
CONT_ASSIGN	1996	1	1	100.00
CONT_ASSIGN	1996	1	1	100.00
CONT_ASSIGN	1997	1	1	100.00
CONT_ASSIGN	1997	1	0	0.00
CONT_ASSIGN	1997	1	0	0.00
CONT_ASSIGN	1998	1	1	100.00
CONT_ASSIGN	1998	1	0	0.00
CONT_ASSIGN	1998	1	0	0.00
CONT_ASSIGN	1999	1	1	100.00
CONT_ASSIGN	1999	1	0	0.00
CONT_ASSIGN	1999	1	0	0.00
CONT_ASSIGN	2001	1	1	100.00
CONT_ASSIGN	2001	1	1	100.00
CONT_ASSIGN	2001	1	1	100.00
CONT_ASSIGN	2002	1	1	100.00
CONT_ASSIGN	2002	1	1	100.00
CONT_ASSIGN	2002	1	1	100.00
CONT_ASSIGN	2003	1	1	100.00
CONT_ASSIGN	2003	1	1	100.00
CONT_ASSIGN	2003	1	1	100.00
CONT_ASSIGN	2046	1	1	100.00
CONT_ASSIGN	2047	1	1	100.00
CONT_ASSIGN	2048	1	1	100.00
CONT_ASSIGN	2049	1	1	100.00
CONT_ASSIGN	2050	1	1	100.00
CONT_ASSIGN	2052	1	1	100.00
CONT_ASSIGN	2053	1	1	100.00
CONT_ASSIGN	2054	1	1	100.00
CONT_ASSIGN	2113	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_spi_device_0.1/rtl/spi_device.sv' or '../src/lowrisc_ip_spi_device_0.1/rtl/spi_device.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
191	1	1
341	1	1
400	1	1
401	1	1
402	1	1
403	1	1
405	1	1
406	1	1
408	1	1
410	1	1
414	1	1
415	1	1
416	1	1
417	1	1
419	1	1
420	1	1
423	1	1
424	1	1
427	1	1
430	1	1
431	1	1
434	1	1
435	1	1
438	1	1
439	1	1
443	2	2
444	1	1
447	2	2
448	1	1
463	1	1
467	1	1
468	1	1
480	1	1
481	1	1
482	1	1
484	1	1
485	1	1
490	1	1
491		unreachable
493	1	1
494	1	1
497	1	1
498	1	1
499	1	1
501	1	1
502	1	1
505	1	1
506	1	1
623	1	1
725	1	1
732	1	1
734	1	1
737	1	1
738	1	1
739	1	1
740	1	1
			MISSING_ELSE
745	1	1
751	1	1
754	1	1
755	1	1
759	1	1
764	1	1
765	1	1
769	1	1
770	1	1
778	1	1
779	1	1
797	1	1
798	1	1
802	1	1
803	1	1
805	1	1
806	1	1
808	1	1
809	1	1
811	1	1
812	1	1
844	1	1
845	1	1
846	1	1
1095	2	2
1096	1	1
1097	1	1
1098	1	1
1099	1	1
			MISSING_ELSE
1121	2	2
1122	1	1
1123	1	1
			MISSING_ELSE
1140	1	1
1164	2	2
1165	1	1
1170	1	1
1172	1	1
1173	1	1
1180	1	1
1184	1	1
1185	1	1
1189	1	1
1190	1	1
1208	1	1
1209	1	1
1210	1	1
1211	1	1
1213	1	1
1215	1	1
1221	1	1
1227	1	1
1229	1	1
1231	1	1
1232	1	1
1233	1	1
1237	1	1
1238	1	1
1243	1	1
1244	1	1
1246	1	1
1248	1	1
1250	1	1
1254	1	1
1256	1	1
1257	1	1
1258	1	1
1261	1	1
1263	1	1
1264	1	1
1265	1	1
1270	1	1
1272	1	1
1273	1	1
1274	1	1
1278	1	1
1280	1	1
1281	1	1
1282	1	1
1301	1	1
1302	1	1
1304	1	1
1306	1	1
1307	1	1
1311	1	1
1313	1	1
1314	1	1
1318	1	1
1319	1	1
1320	1	1
1322	1	1
1323	1	1
1338	2	2
1339	1	1
1540	1	1
1542	1	1
1545	1	1
1546	1	1
1548	1	1
1549	1	1
1588	0	1
1618	0	1
1702	1	1
1703	1	1
1705	1	1
1707	1	1
1708	1	1
1710	1	1
1714	1	1
1717	1	1
1720	1	1
1723	1	1
1726	1	1
1729	1	1
1736	1	1
1737	1	1
1779	1	1
1881	0	1
1889	1	1
1890	1	1
1891	1	1
1892	1	1
1893	1	1
1896	1	1
1905	5	5
1908	1	1
1909	1	1
1910	1	1
1911	1	1
1912	1	1
1913	1	1
1915	1	1
1919	1	1
1921	1	1
1922	1	1
1929	1	1
1931	1	1
1933	1	1
1937	1	1
1939	1	1
1940	1	1
1976	1	1
1983	1	1
1984	1	1
1985	1	1
1986	1	1
1987	1	1
1989	1	1
			MISSING_ELSE
1994	2	2
1996	3	3
1997	1	3
1998	1	3
1999	1	3
2001	3	3
2002	3	3
2003	3	3
2046	1	1
2047	1	1
2048	1	1
2049	1	1
2050	1	1
2052	1	1
2053	1	1
2054	1	1
2113	1	1

---

Cond Coverage for Module : spi_device

	Total	Covered	Percent
Conditions	67	63	94.03
Logical	67	63	94.03
Non-Logical	0	0
Event	0	0

 LINE       191
 EXPRESSION (payload_depth != '0)
            ----------1----------

-1-	Status	Tests
0	Covered	T4,T1,T2
1	Covered	T5,T6,T7

 LINE       490
 EXPRESSION (((~sram_rxf_full_q)) & sram_rxf_full)
             ----------1---------   ------2------

-1-	-2-	Status	Tests
0	1	Covered	T41,T51,T33
1	0	Covered	T4,T1,T2
1	1	Covered	T41,T51,T33

 LINE       491
 EXPRESSION (((~fwm_rxerr_q)) & fwm_rxerr)
             --------1-------   ----2----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Covered	T4,T1,T2
1	1	Unreachable

 LINE       505
 EXPRESSION (((~rxlvl)) && rxlvl_d)
             -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T3,T40,T41
1	0	Covered	T4,T1,T2
1	1	Covered	T3,T40,T41

 LINE       506
 EXPRESSION (((~txlvl)) && txlvl_d)
             -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T8
1	0	Covered	T4,T1,T2
1	1	Covered	T1,T3,T8

 LINE       845
 EXPRESSION ((cpha ^ cpol) ? sck_n : cio_sck_i)
             ------1------

-1-	Status	Tests
0	Covered	T4,T1,T2
1	Covered	T1,T3,T12

 LINE       845
 SUB-EXPRESSION (cpha ^ cpol)
                 --1-   --2-

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T2
0	1	Covered	T1,T3,T12
1	0	Covered	T1,T3,T13
1	1	Covered	T1,T3,T8

 LINE       846
 EXPRESSION ((cpha ^ cpol) ? cio_sck_i : sck_n)
             ------1------

-1-	Status	Tests
0	Covered	T4,T1,T2
1	Covered	T1,T3,T12

 LINE       846
 SUB-EXPRESSION (cpha ^ cpol)
                 --1-   --2-

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T2
0	1	Covered	T1,T3,T12
1	0	Covered	T1,T3,T13
1	1	Covered	T1,T3,T8

 LINE       899
 EXPRESSION (rst_ni & ((~rst_csb_buf)))
             ---1--   --------2-------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T4,T1,T2
1	1	Covered	T1,T9,T3

 LINE       908
 EXPRESSION (rst_ni & ((~rst_txfifo_reg)))
             ---1--   ---------2---------

-1-	-2-	Status	Tests
0	1	Covered	T4,T1,T2
1	0	Covered	T94,T95,T96
1	1	Covered	T4,T1,T2

 LINE       917
 EXPRESSION (rst_ni & ((~rst_rxfifo_reg)))
             ---1--   ---------2---------

-1-	-2-	Status	Tests
0	1	Covered	T4,T1,T2
1	0	Covered	T41,T97,T98
1	1	Covered	T4,T1,T2

 LINE       928
 EXPRESSION (rst_ni & ((~rst_tpm_csb_buf)))
             ---1--   ----------2---------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T4,T1,T2
1	1	Covered	T13,T5,T50

 LINE       976
 EXPRESSION (spi_mode == FwMode)
            ----------1---------

-1-	Status	Tests
0	Covered	T4,T1,T2
1	Covered	T1,T3,T8

 LINE       1003
 EXPRESSION (spi_mode == FwMode)
            ----------1---------

-1-	Status	Tests
0	Covered	T4,T1,T2
1	Covered	T1,T3,T8

 LINE       1140
 EXPRESSION (spi_clk_pos_edge | spi_clk_neg_edge)
             --------1-------   --------2-------

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T2
0	1	Covered	T5,T50,T52
1	0	Covered	T5,T50,T52

 LINE       1194
 EXPRESSION (cmd_only_dp_sel == DpUpload)
            --------------1--------------

-1-	Status	Tests
0	Covered	T4,T1,T2
1	Covered	T5,T6,T7

 LINE       1304
 EXPRESSION (cfg_tpm_en && ((!sck_tpm_csb_buf)))
             -----1----    ----------2---------

-1-	-2-	Status	Tests
0	1	Covered	T13,T99,T100
1	0	Covered	T5,T50,T52
1	1	Covered	T5,T50,T52

 LINE       1540
 EXPRESSION (reg2hw.flash_status.busy.qe && reg2hw.flash_status.status.qe)
             -------------1-------------    --------------2--------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Covered	T9,T15,T10

 LINE       1548
 EXPRESSION (cmd_only_dp_sel == DpWrEn)
            -------------1-------------

-1-	Status	Tests
0	Covered	T4,T1,T2
1	Covered	T15,T5,T6

 LINE       1549
 EXPRESSION (cmd_only_dp_sel == DpWrDi)
            -------------1-------------

-1-	Status	Tests
0	Covered	T4,T1,T2
1	Covered	T15,T5,T6

 LINE       1736
 EXPRESSION (cmd_only_dp_sel == DpEn4B)
            -------------1-------------

-1-	Status	Tests
0	Covered	T4,T1,T2
1	Covered	T15,T6,T7

 LINE       1737
 EXPRESSION (cmd_only_dp_sel == DpEx4B)
            -------------1-------------

-1-	Status	Tests
0	Covered	T4,T1,T2
1	Covered	T19,T6,T7

 LINE       1986
 EXPRESSION ((0 != j) && sys_sram_l2m[j].req)
             ----1---    ---------2---------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T9
1	0	Covered	T4,T1,T2
1	1	Covered	T5,T6,T7

 LINE       1986
 SUB-EXPRESSION (0 != j)
                ----1---

-1-	Status	Tests
0	Covered	T4,T1,T2
1	Covered	T4,T1,T2

 LINE       2113
 SUB-EXPRESSION (reg2hw.alert_test.q & reg2hw.alert_test.qe)
                 ---------1---------   ----------2---------

-1-	-2-	Status	Tests
0	1	Covered	T101,T102,T103
1	0	Covered	T4,T1,T2
1	1	Covered	T101,T102,T103

---

Toggle Coverage for Module : spi_device

	Total	Covered	Percent
Totals	63	58	92.06
Total Bits	466	452	97.00
Total Bits 0->1	233	226	97.00
Total Bits 1->0	233	226	97.00

Ports	63	58	92.06
Port Bits	466	452	97.00
Port Bits 0->1	233	226	97.00
Port Bits 1->0	233	226	97.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T4,T1,T2	Yes	T4,T1,T2	INPUT
rst_ni	Yes	Yes	T78,T81,T82	Yes	T4,T1,T2	INPUT
tl_i.d_ready	Yes	Yes	T1,T2,T9	Yes	T4,T1,T2	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T9	Yes	T1,T2,T9	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T9	Yes	T1,T2,T9	INPUT
tl_i.a_user.instr_type[3:0]	Yes	Yes	T3,T12,T79	Yes	T3,T12,T79	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T1,T2,T9	Yes	T1,T2,T9	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T1,T2,T9	Yes	T1,T2,T9	INPUT
tl_i.a_address[31:0]	Yes	Yes	T1,T2,T9	Yes	T1,T2,T9	INPUT
tl_i.a_source[7:0]	Yes	Yes	T2,T3,T8	Yes	T2,T3,T8	INPUT
tl_i.a_size[1:0]	Yes	Yes	T1,T2,T9	Yes	T1,T2,T9	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[2:0]	Yes	Yes	T1,T2,T9	Yes	T1,T2,T9	INPUT
tl_i.a_valid	Yes	Yes	T4,T1,T2	Yes	T4,T1,T2	INPUT
tl_o.a_ready	Yes	Yes	T4,T1,T2	Yes	T4,T1,T2	OUTPUT
tl_o.d_error	Yes	Yes	T2,T81,T82	Yes	T2,T81,T82	OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T1,T9,T3	Yes	T1,T9,T3	OUTPUT
tl_o.d_user.rsp_intg[5:0]	Yes	Yes	*T4,*T1,T2	Yes	T1,T2,T9	OUTPUT
tl_o.d_user.rsp_intg[6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T4,T1,T2	Yes	T1,T2,T9	OUTPUT
tl_o.d_sink	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_source[7:0]	Yes	Yes	T1,T2,T9	Yes	T4,T1,T2	OUTPUT
tl_o.d_size[1:0]	Yes	Yes	T1,T2,T9	Yes	T1,T2,T9	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T1,*T2,*T9	Yes	T1,T2,T9	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T4,T1,T2	Yes	T4,T1,T2	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T4,T1,T2	Yes	T4,T1,T2	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T78,T104,T105	Yes	T78,T104,T105	INPUT
alert_rx_i[0].ping_n	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[0].ping_p	Unreachable	Unreachable		Unreachable		INPUT
alert_tx_o[0].alert_n	Yes	Yes	T4,T1,T2	Yes	T4,T1,T2	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T78,T104,T105	Yes	T78,T104,T105	OUTPUT
cio_sck_i	Yes	Yes	T1,T9,T3	Yes	T1,T9,T3	INPUT
cio_csb_i	Yes	Yes	T1,T9,T3	Yes	T1,T9,T3	INPUT
cio_sd_o[3:0]	Yes	Yes	T9,T15,T10	Yes	T9,T15,T10	OUTPUT
cio_sd_en_o[3:0]	Yes	Yes	T9,T10,T5	Yes	T9,T10,T5	OUTPUT
cio_sd_i[3:0]	Yes	Yes	T1,T9,T3	Yes	T1,T9,T3	INPUT
cio_tpm_csb_i	Yes	Yes	T13,T5,T50	Yes	T13,T5,T50	INPUT
passthrough_o.s_en[0]	Yes	Yes	*T9,*T15,*T17	Yes	T9,T15,T17	OUTPUT
passthrough_o.s_en[3:1]	No	No		No		OUTPUT
passthrough_o.s[3:0]	Yes	Yes	T1,T9,T3	Yes	T1,T9,T3	OUTPUT
passthrough_o.csb_en	No	No		No		OUTPUT
passthrough_o.csb	Yes	Yes	T1,T9,T3	Yes	T1,T9,T3	OUTPUT
passthrough_o.sck_en	No	No		No		OUTPUT
passthrough_o.sck	Yes	Yes	T1,T9,T3	Yes	T1,T9,T3	OUTPUT
passthrough_o.passthrough_en	Yes	Yes	T78,T104,T106	Yes	T9,T78,T85	OUTPUT
passthrough_i.s[3:0]	Yes	Yes	T1,T9,T3	Yes	T1,T9,T3	INPUT
intr_generic_rx_full_o	Yes	Yes	T78,T79,T80	Yes	T78,T79,T80	OUTPUT
intr_generic_rx_watermark_o	Yes	Yes	T3,T78,T79	Yes	T3,T78,T79	OUTPUT
intr_generic_tx_watermark_o	Yes	Yes	T1,T3,T12	Yes	T1,T3,T12	OUTPUT
intr_generic_rx_error_o	Yes	Yes	T78,T79,T80	Yes	T78,T79,T80	OUTPUT
intr_generic_rx_overflow_o	Yes	Yes	T79,T80,T86	Yes	T79,T80,T86	OUTPUT
intr_generic_tx_underflow_o	Yes	Yes	T78,T79,T80	Yes	T78,T79,T80	OUTPUT
intr_upload_cmdfifo_not_empty_o	Yes	Yes	T78,T79,T80	Yes	T78,T79,T80	OUTPUT
intr_upload_payload_not_empty_o	Yes	Yes	T80,T86,T87	Yes	T80,T86,T87	OUTPUT
intr_upload_payload_overflow_o	Yes	Yes	T78,T80,T86	Yes	T78,T80,T86	OUTPUT
intr_readbuf_watermark_o	Yes	Yes	T78,T79,T80	Yes	T78,T79,T80	OUTPUT
intr_readbuf_flip_o	Yes	Yes	T78,T80,T86	Yes	T78,T80,T86	OUTPUT
intr_tpm_header_not_empty_o	Yes	Yes	T78,T79,T80	Yes	T78,T79,T80	OUTPUT
ram_cfg_i.b_ram_lcfg.cfg[3:0]	Yes	Yes	T4,T42,T107	Yes	T4,T42,T107	INPUT
ram_cfg_i.b_ram_lcfg.cfg_en	Yes	Yes	T4,T42,T107	Yes	T4,T42,T107	INPUT
ram_cfg_i.a_ram_lcfg.cfg[3:0]	Yes	Yes	T4,T42,T107	Yes	T4,T42,T107	INPUT
ram_cfg_i.a_ram_lcfg.cfg_en	Yes	Yes	T4,T42,T107	Yes	T4,T42,T107	INPUT
ram_cfg_i.b_ram_fcfg.cfg[3:0]	Yes	Yes	T4,T42,T107	Yes	T4,T42,T107	INPUT
ram_cfg_i.b_ram_fcfg.cfg_en	Yes	Yes	T4,T42,T107	Yes	T4,T42,T107	INPUT
ram_cfg_i.a_ram_fcfg.cfg[3:0]	Yes	Yes	T4,T42,T107	Yes	T4,T42,T107	INPUT
ram_cfg_i.a_ram_fcfg.cfg_en	Yes	Yes	T4,T42,T107	Yes	T4,T42,T107	INPUT
sck_monitor_o	Yes	Yes	T1,T9,T3	Yes	T1,T9,T3	OUTPUT
mbist_en_i	Unreachable	Unreachable		Unreachable		INPUT
scan_clk_i	No	No		No		INPUT
scan_rst_ni	No	No		No		INPUT
scanmode_i[3:0]	Unreachable	Unreachable		Unreachable		INPUT

*Tests covering at least one bit in the range

---

Branch Coverage for Module : spi_device

	Line No.	Total	Covered	Percent
Branches		45	42	93.33
TERNARY	845	2	2	100.00
TERNARY	846	2	2	100.00
IF	443	2	2	100.00
IF	447	2	2	100.00
IF	480	2	2	100.00
IF	497	2	2	100.00
IF	737	3	3	100.00
IF	1095	4	4	100.00
IF	1121	3	3	100.00
IF	1164	2	2	100.00
CASE	1180	4	4	100.00
CASE	1227	8	6	75.00
IF	1304	5	4	80.00
IF	1338	2	2	100.00
IF	1986	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_spi_device_0.1/rtl/spi_device.sv' or '../src/lowrisc_ip_spi_device_0.1/rtl/spi_device.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	845	((cpha ^ cpol)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T12
0	Covered	T4,T1,T2

	LineNo.	Expression
-1-:	846	((cpha ^ cpol)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T12
0	Covered	T4,T1,T2

	LineNo.	Expression
-1-:	443	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T2
0	Covered	T1,T9,T3

	LineNo.	Expression
-1-:	447	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T2
0	Covered	T1,T9,T3

	LineNo.	Expression
-1-:	480	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T2
0	Covered	T4,T1,T2

	LineNo.	Expression
-1-:	497	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T2
0	Covered	T4,T1,T2

	LineNo.	Expression
-1-:	737	if ((!rst_ni))
-2-:	739	if (sys_csb_deasserted_pulse)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T4,T1,T2
0	1	Covered	T1,T9,T3
0	0	Covered	T4,T1,T2

	LineNo.	Expression
-1-:	1095	if ((!tpm_rst_n))
-2-:	1096	if (spi_clk_csb_rst_pulse)
-3-:	1098	if (spi_clk_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T1,T2
0	1	-	Covered	T5,T50,T52
0	0	1	Covered	T5,T50,T52
0	0	0	Covered	T5,T50,T52

	LineNo.	Expression
-1-:	1121	if ((!rst_ni))
-2-:	1122	if (sys_csb_pos_pulse_stretch)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T4,T1,T2
0	1	Covered	T5,T50,T52
0	0	Covered	T4,T1,T2

	LineNo.	Expression
-1-:	1164	if ((!rst_spi_n))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T2
0	Covered	T1,T9,T3

	LineNo.	Expression
-1-:	1180	case (cmd_dp_sel)
-2-:	1194	if ((cmd_only_dp_sel == DpUpload))

Branches:

-1-	-2-	Status	Tests
DpReadCmd DpReadSFDP	-	Covered	T9,T10,T5
DpUpload	-	Covered	T5,T6,T7
default	1	Covered	T5,T6,T7
default	0	Covered	T4,T1,T2

	LineNo.	Expression
-1-:	1227	case (spi_mode)
-2-:	1246	case (cmd_dp_sel)

Branches:

-1-	-2-	Status	Tests
FwMode	-	Covered	T1,T3,T8
FlashMode PassThrough	DpNone	Covered	T4,T1,T2
FlashMode PassThrough	DpReadCmd DpReadSFDP	Covered	T9,T10,T5
FlashMode PassThrough	DpReadStatus	Covered	T5,T6,T7
FlashMode PassThrough	DpReadJEDEC	Covered	T5,T6,T7
FlashMode PassThrough	DpUpload	Covered	T5,T6,T7
FlashMode PassThrough	default	Not Covered
default	-	Not Covered

	LineNo.	Expression
-1-:	1304	if ((cfg_tpm_en && (!sck_tpm_csb_buf)))
-2-:	1311	case (spi_mode)
-3-:	1318	if (intercept_en)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T5,T50,T52
0	FwMode FlashMode	-	Covered	T4,T1,T2
0	PassThrough	1	Covered	T9,T6,T7
0	PassThrough	0	Covered	T9,T15,T17
0	default	-	Not Covered

	LineNo.	Expression
-1-:	1338	if ((!rst_spi_n))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T2
0	Covered	T1,T9,T3

	LineNo.	Expression
-1-:	1986	if (((0 != j) && sys_sram_l2m[j].req))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T7
0	Covered	T4,T1,T2

---

Assert Coverage for Module : spi_device

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	27	27	100.00	26	96.30
Cover properties	0	0		0
Cover sequences	0	0		0
Total	27	27	100.00	26	96.30

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AlertKnownO_A	1929928785	1929792554	0	0
CioSdoEnOKnown	1929928785	1929792554	0	0
CioSdoEnOffWhenInactive	1929928785	1929792554	0	0
CsPulseWidth_A	1929928785	1832360329	0	0
FpvSecCmRegWeOnehotCheck_A	1929928785	110	0	0
InterceptLevel_M	386538025	0	0	0
IntrReadbufFlipOKnown	1929928785	1929792554	0	0
IntrReadbufWatermarkOKnown	1929928785	1929792554	0	0
IntrRxerrOKnown	1929928785	1929792554	0	0
IntrRxfOKnown	1929928785	1929792554	0	0
IntrRxlvlOKnown	1929928785	1929792554	0	0
IntrRxoverflowOKnown	1929928785	1929792554	0	0
IntrTpmHeaderNotEmptyOKnown	1929928785	1929792554	0	0
IntrTxlvlOKnown	1929928785	1929792554	0	0
IntrTxunderflowOKnown	1929928785	1929792554	0	0
IntrUploadCmdfifoNotEmptyOKnown	1929928785	1929792554	0	0
IntrUploadPayloadNotEmptyOKnown	1929928785	1929792554	0	0
IntrUploadPayloadOverflowOKnown	1929928785	1929792554	0	0
PayloadStartIdxWidthMatch_A	1607	1607	0	0
SpiModeKnown_A	1929928785	1929792554	0	0
TpmEnableWhenTpmCsbIdle_M	1929928785	339	0	0
TpmRdfifoNotFull_A	1929928785	283317	0	0
TpmWrPtrMatch_A	1607	1607	0	0
g_sram_connect[0].ReqAlwaysAccepted_A	1929928785	11636332	0	0
g_sram_connect[1].ReqAlwaysAccepted_A	1929928785	2494	0	0
g_sram_connect[2].ReqAlwaysAccepted_A	1929928785	1856	0	0
scanmodeKnown	1929928785	1929928785	0	0

AlertKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1929928785	1929792554	0	0
T1	27981	27924	0	0
T2	2039	1967	0	0
T3	7816	7743	0	0
T4	1093	1024	0	0
T8	2698	2641	0	0
T9	120201	120196	0	0
T12	590596	590587	0	0
T13	123576	123568	0	0
T14	239078	239069	0	0
T15	12123	12057	0	0

CioSdoEnOKnown

Name	Attempts	Real Successes	Failures	Incomplete
Total	1929928785	1929792554	0	0
T1	27981	27924	0	0
T2	2039	1967	0	0
T3	7816	7743	0	0
T4	1093	1024	0	0
T8	2698	2641	0	0
T9	120201	120196	0	0
T12	590596	590587	0	0
T13	123576	123568	0	0
T14	239078	239069	0	0
T15	12123	12057	0	0

CioSdoEnOffWhenInactive

Name	Attempts	Real Successes	Failures	Incomplete
Total	1929928785	1929792554	0	0
T1	27981	27924	0	0
T2	2039	1967	0	0
T3	7816	7743	0	0
T4	1093	1024	0	0
T8	2698	2641	0	0
T9	120201	120196	0	0
T12	590596	590587	0	0
T13	123576	123568	0	0
T14	239078	239069	0	0
T15	12123	12057	0	0

CsPulseWidth_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1929928785	1832360329	0	0
T1	27981	27924	0	0
T2	2039	1967	0	0
T3	7816	7743	0	0
T4	1093	1024	0	0
T8	2698	2641	0	0
T9	120201	120196	0	0
T12	590596	590587	0	0
T13	123576	123132	0	0
T14	239078	239069	0	0
T15	12123	12057	0	0

FpvSecCmRegWeOnehotCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1929928785	110	0	0
T108	3014	10	0	0
T109	3385	10	0	0
T110	9067	30	0	0
T111	0	30	0	0
T112	0	30	0	0
T113	447617	0	0	0
T114	314041	0	0	0
T115	27472	0	0	0
T116	378784	0	0	0
T117	1275	0	0	0
T118	620857	0	0	0
T119	663558	0	0	0

InterceptLevel_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	386538025	0	0	0

IntrReadbufFlipOKnown

Name	Attempts	Real Successes	Failures	Incomplete
Total	1929928785	1929792554	0	0
T1	27981	27924	0	0
T2	2039	1967	0	0
T3	7816	7743	0	0
T4	1093	1024	0	0
T8	2698	2641	0	0
T9	120201	120196	0	0
T12	590596	590587	0	0
T13	123576	123568	0	0
T14	239078	239069	0	0
T15	12123	12057	0	0

IntrReadbufWatermarkOKnown

Name	Attempts	Real Successes	Failures	Incomplete
Total	1929928785	1929792554	0	0
T1	27981	27924	0	0
T2	2039	1967	0	0
T3	7816	7743	0	0
T4	1093	1024	0	0
T8	2698	2641	0	0
T9	120201	120196	0	0
T12	590596	590587	0	0
T13	123576	123568	0	0
T14	239078	239069	0	0
T15	12123	12057	0	0

IntrRxerrOKnown

Name	Attempts	Real Successes	Failures	Incomplete
Total	1929928785	1929792554	0	0
T1	27981	27924	0	0
T2	2039	1967	0	0
T3	7816	7743	0	0
T4	1093	1024	0	0
T8	2698	2641	0	0
T9	120201	120196	0	0
T12	590596	590587	0	0
T13	123576	123568	0	0
T14	239078	239069	0	0
T15	12123	12057	0	0

IntrRxfOKnown

Name	Attempts	Real Successes	Failures	Incomplete
Total	1929928785	1929792554	0	0
T1	27981	27924	0	0
T2	2039	1967	0	0
T3	7816	7743	0	0
T4	1093	1024	0	0
T8	2698	2641	0	0
T9	120201	120196	0	0
T12	590596	590587	0	0
T13	123576	123568	0	0
T14	239078	239069	0	0
T15	12123	12057	0	0

IntrRxlvlOKnown

Name	Attempts	Real Successes	Failures	Incomplete
Total	1929928785	1929792554	0	0
T1	27981	27924	0	0
T2	2039	1967	0	0
T3	7816	7743	0	0
T4	1093	1024	0	0
T8	2698	2641	0	0
T9	120201	120196	0	0
T12	590596	590587	0	0
T13	123576	123568	0	0
T14	239078	239069	0	0
T15	12123	12057	0	0

IntrRxoverflowOKnown

Name	Attempts	Real Successes	Failures	Incomplete
Total	1929928785	1929792554	0	0
T1	27981	27924	0	0
T2	2039	1967	0	0
T3	7816	7743	0	0
T4	1093	1024	0	0
T8	2698	2641	0	0
T9	120201	120196	0	0
T12	590596	590587	0	0
T13	123576	123568	0	0
T14	239078	239069	0	0
T15	12123	12057	0	0

IntrTpmHeaderNotEmptyOKnown

Name	Attempts	Real Successes	Failures	Incomplete
Total	1929928785	1929792554	0	0
T1	27981	27924	0	0
T2	2039	1967	0	0
T3	7816	7743	0	0
T4	1093	1024	0	0
T8	2698	2641	0	0
T9	120201	120196	0	0
T12	590596	590587	0	0
T13	123576	123568	0	0
T14	239078	239069	0	0
T15	12123	12057	0	0

IntrTxlvlOKnown

Name	Attempts	Real Successes	Failures	Incomplete
Total	1929928785	1929792554	0	0
T1	27981	27924	0	0
T2	2039	1967	0	0
T3	7816	7743	0	0
T4	1093	1024	0	0
T8	2698	2641	0	0
T9	120201	120196	0	0
T12	590596	590587	0	0
T13	123576	123568	0	0
T14	239078	239069	0	0
T15	12123	12057	0	0

IntrTxunderflowOKnown

Name	Attempts	Real Successes	Failures	Incomplete
Total	1929928785	1929792554	0	0
T1	27981	27924	0	0
T2	2039	1967	0	0
T3	7816	7743	0	0
T4	1093	1024	0	0
T8	2698	2641	0	0
T9	120201	120196	0	0
T12	590596	590587	0	0
T13	123576	123568	0	0
T14	239078	239069	0	0
T15	12123	12057	0	0

IntrUploadCmdfifoNotEmptyOKnown

Name	Attempts	Real Successes	Failures	Incomplete
Total	1929928785	1929792554	0	0
T1	27981	27924	0	0
T2	2039	1967	0	0
T3	7816	7743	0	0
T4	1093	1024	0	0
T8	2698	2641	0	0
T9	120201	120196	0	0
T12	590596	590587	0	0
T13	123576	123568	0	0
T14	239078	239069	0	0
T15	12123	12057	0	0

IntrUploadPayloadNotEmptyOKnown

Name	Attempts	Real Successes	Failures	Incomplete
Total	1929928785	1929792554	0	0
T1	27981	27924	0	0
T2	2039	1967	0	0
T3	7816	7743	0	0
T4	1093	1024	0	0
T8	2698	2641	0	0
T9	120201	120196	0	0
T12	590596	590587	0	0
T13	123576	123568	0	0
T14	239078	239069	0	0
T15	12123	12057	0	0

IntrUploadPayloadOverflowOKnown

Name	Attempts	Real Successes	Failures	Incomplete
Total	1929928785	1929792554	0	0
T1	27981	27924	0	0
T2	2039	1967	0	0
T3	7816	7743	0	0
T4	1093	1024	0	0
T8	2698	2641	0	0
T9	120201	120196	0	0
T12	590596	590587	0	0
T13	123576	123568	0	0
T14	239078	239069	0	0
T15	12123	12057	0	0

PayloadStartIdxWidthMatch_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1607	1607	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0

SpiModeKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1929928785	1929792554	0	0
T1	27981	27924	0	0
T2	2039	1967	0	0
T3	7816	7743	0	0
T4	1093	1024	0	0
T8	2698	2641	0	0
T9	120201	120196	0	0
T12	590596	590587	0	0
T13	123576	123568	0	0
T14	239078	239069	0	0
T15	12123	12057	0	0

TpmEnableWhenTpmCsbIdle_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	1929928785	339	0	0
T5	731216	1	0	0
T6	254164	1	0	0
T11	56621	0	0	0
T19	86821	0	0	0
T33	225006	0	0	0
T39	0	1	0	0
T44	0	1	0	0
T49	527265	0	0	0
T50	44901	1	0	0
T51	225987	0	0	0
T52	644525	1	0	0
T53	288721	0	0	0
T120	0	1	0	0
T121	0	1	0	0
T122	0	1	0	0
T123	0	1	0	0

TpmRdfifoNotFull_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1929928785	283317	0	0
T5	731216	1598	0	0
T6	254164	1533	0	0
T11	56621	0	0	0
T19	86821	0	0	0
T22	0	2697	0	0
T33	225006	0	0	0
T39	0	979	0	0
T44	0	965	0	0
T49	527265	0	0	0
T50	44901	0	0	0
T51	225987	0	0	0
T52	644525	1569	0	0
T53	288721	0	0	0
T120	0	2947	0	0
T121	0	1979	0	0
T122	0	46	0	0
T124	0	813	0	0

TpmWrPtrMatch_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1607	1607	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0

g_sram_connect[0].ReqAlwaysAccepted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1929928785	11636332	0	0
T1	27981	170	0	0
T2	2039	200	0	0
T3	7816	184	0	0
T8	2698	24	0	0
T9	120201	1024	0	0
T10	0	1024	0	0
T12	590596	5156	0	0
T13	123576	20364	0	0
T14	239078	29622	0	0
T15	12123	1024	0	0
T42	1644	0	0	0

g_sram_connect[1].ReqAlwaysAccepted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1929928785	2494	0	0
T5	731216	3	0	0
T6	254164	12	0	0
T7	0	14	0	0
T11	56621	0	0	0
T18	0	4	0	0
T19	86821	0	0	0
T20	0	26	0	0
T22	0	4	0	0
T27	0	8	0	0
T28	0	19	0	0
T33	225006	0	0	0
T44	0	26	0	0
T45	0	23	0	0
T49	527265	0	0	0
T50	44901	0	0	0
T51	225987	0	0	0
T52	644525	0	0	0
T53	288721	0	0	0

g_sram_connect[2].ReqAlwaysAccepted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1929928785	1856	0	0
T5	731216	2	0	0
T6	254164	11	0	0
T7	0	14	0	0
T11	56621	0	0	0
T18	0	4	0	0
T19	86821	0	0	0
T20	0	17	0	0
T22	0	2	0	0
T27	0	7	0	0
T28	0	15	0	0
T33	225006	0	0	0
T44	0	20	0	0
T45	0	14	0	0
T49	527265	0	0	0
T50	44901	0	0	0
T51	225987	0	0	0
T52	644525	0	0	0
T53	288721	0	0	0

scanmodeKnown

Name	Attempts	Real Successes	Failures	Incomplete
Total	1929928785	1929928785	0	0
T1	27981	27981	0	0
T2	2039	2039	0	0
T3	7816	7816	0	0
T4	1093	1093	0	0
T8	2698	2698	0	0
T9	120201	120201	0	0
T12	590596	590596	0	0
T13	123576	123576	0	0
T14	239078	239078	0	0
T15	12123	12123	0	0