Unified Coverage Report :: Module :: spi_passthrough

Module : spi_passthrough

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
89.75	94.15	88.12		75.00	91.49	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_spi_device_0.1/rtl/spi_passthrough.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_passthrough	89.75	94.15	88.12		75.00	91.49	100.00

---

Module Instance : tb.dut.u_passthrough

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
89.75	94.15	88.12		75.00	91.49	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.07	94.33	89.19		75.00	91.84	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.71	95.79	89.19	96.92		91.18	95.45	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_pt_isck_cg	100.00	100.00	100.00			100.00
u_pt_sck_cg	100.00	100.00	100.00			100.00

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : spi_passthrough

	Line No.	Total	Covered	Percent
TOTAL		188	177	94.15
CONT_ASSIGN	281	1	1	100.00
CONT_ASSIGN	286	1	1	100.00
CONT_ASSIGN	336	1	1	100.00
CONT_ASSIGN	343	1	1	100.00
ALWAYS	346	4	4	100.00
ALWAYS	355	4	4	100.00
ALWAYS	359	3	3	100.00
CONT_ASSIGN	365	1	1	100.00
ALWAYS	370	4	4	100.00
CONT_ASSIGN	382	1	1	100.00
CONT_ASSIGN	383	1	1	100.00
ALWAYS	386	4	4	100.00
ALWAYS	410	8	8	100.00
ALWAYS	424	4	4	100.00
ALWAYS	435	4	4	100.00
CONT_ASSIGN	449	0	0
CONT_ASSIGN	460	1	1	100.00
ALWAYS	464	6	6	100.00
CONT_ASSIGN	484	1	1	100.00
ALWAYS	487	6	6	100.00
ALWAYS	499	3	3	100.00
CONT_ASSIGN	505	1	1	100.00
ALWAYS	514	3	3	100.00
ALWAYS	528	4	4	100.00
ALWAYS	536	3	3	100.00
ALWAYS	541	6	6	100.00
ALWAYS	547	3	3	100.00
CONT_ASSIGN	551	1	1	100.00
CONT_ASSIGN	554	1	1	100.00
ALWAYS	569	5	5	100.00
CONT_ASSIGN	578	1	1	100.00
CONT_ASSIGN	580	1	1	100.00
CONT_ASSIGN	583	1	1	100.00
CONT_ASSIGN	584	1	1	100.00
ALWAYS	590	6	6	100.00
CONT_ASSIGN	597	1	1	100.00
ALWAYS	604	6	4	66.67
CONT_ASSIGN	612	1	1	100.00
CONT_ASSIGN	617	1	1	100.00
ALWAYS	621	3	3	100.00
CONT_ASSIGN	624	1	1	100.00
CONT_ASSIGN	626	1	1	100.00
ALWAYS	628	3	3	100.00
CONT_ASSIGN	651	1	1	100.00
CONT_ASSIGN	653	1	1	100.00
CONT_ASSIGN	659	1	1	100.00
CONT_ASSIGN	662	1	1	100.00
ALWAYS	670	3	3	100.00
ALWAYS	678	68	59	86.76

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_spi_device_0.1/rtl/spi_passthrough.sv' or '../src/lowrisc_ip_spi_device_0.1/rtl/spi_passthrough.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
281	1	1
286	1	1
336	1	1
343	1	1
346	1	1
347	1	1
348	1	1
349	1	1
			MISSING_ELSE
355	2	2
356	2	2
			MISSING_ELSE
359	2	2
360	1	1
365	1	1
370	1	1
371	1	1
372	1	1
373	1	1
			MISSING_ELSE
382	1	1
383	1	1
386	1	1
387	1	1
388	1	1
396	1	1
			MISSING_ELSE
410	1	1
411	1	1
412	1	1
413	1	1
414	1	1
415	1	1
416	1	1
417	1	1
			MISSING_ELSE
			MISSING_ELSE
			MISSING_ELSE
424	1	1
425	1	1
426	1	1
429	1	1
			MISSING_ELSE
435	1	1
436	1	1
437	1	1
440	1	1
			MISSING_ELSE
449		unreachable
460	1	1
464	1	1
465	1	1
467	1	1
470	1	1
472	1	1
475	1	1
			MISSING_ELSE
484	1	1
487	1	1
488	1	1
489	1	1
492	1	1
493	1	1
494	1	1
			MISSING_ELSE
499	2	2
500	1	1
505	1	1
514	2	2
515	1	1
528	1	1
529	1	1
530	1	1
531	1	1
			MISSING_ELSE
536	2	2
537	1	1
541	2	2
542	2	2
543	2	2
			MISSING_ELSE
547	2	2
548	1	1
551	1	1
554	1	1
569	1	1
570	1	1
571	1	1
573	1	1
574	1	1
578	1	1
580	1	1
583	1	1
584	1	1
590	2	2
591	1	1
592	1	1
593	1	1
594	1	1
			MISSING_ELSE
597	1	1
604	1	1
605	1	1
606	1	1
607	0	1
608	1	1
609	0	1
			MISSING_ELSE
612	1	1
617	1	1
621	2	2
622	1	1
624	1	1
626	1	1
628	2	2
629	1	1
651	1	1
653	1	1
659	1	1
662	1	1
670	1	1
671	1	1
673	1	1
678	1	1
681	1	1
684	1	1
687	1	1
690	1	1
693	1	1
696	1	1
697	1	1
700	1	1
701	1	1
703	1	1
705	1	1
706	1	1
707	1	1
708	1	1
709	1	1
712	1	1
713	1	1
723	1	1
724	1	1
726	1	1
727	1	1
728	1	1
730	1	1
731	1	1
732	1	1
734	1	1
735	1	1
737	1	1
739	1	1
			MISSING_ELSE
743	1	1
745	1	1
746	1	1
			MISSING_ELSE
751	0	1
752	0	1
754	0	1
755	0	1
757	0	1
763	1	1
764	1	1
765	1	1
770	1	1
773	1	1
774	1	1
779	1	1
782	1	1
783	1	1
787	1	1
788	1	1
789	1	1
791	1	1
792	1	1
793	0	1
795	0	1
			MISSING_ELSE
801	1	1
802	1	1
803	0	1
805	0	1
806	1	1
807	1	1
809	1	1
810	1	1
811	1	1
813	1	1
814	1	1
816	1	1
818	1	1
821	1	1
			MISSING_ELSE

---

Cond Coverage for Module : spi_passthrough

	Total	Covered	Percent
Conditions	101	89	88.12
Logical	101	89	88.12
Non-Logical	0	0
Event	0	0

 LINE       281
 EXPRESSION (spi_mode_i == PassThrough)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T7,T8,T9

 LINE       365
 SUB-EXPRESSION (filter | csb_deassert)
                 ---1--   ------2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T7,T8,T9
1	0	Covered	T7,T8,T9

 LINE       372
 EXPRESSION (bitcnt != '1)
            -------1------

-1-	Status	Tests
0	Covered	T7,T8,T9
1	Covered	T7,T8,T9

 LINE       382
 EXPRESSION (bitcnt == 6'(6))
            --------1--------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T7,T8,T9

 LINE       383
 EXPRESSION (bitcnt == 6'(7))
            --------1--------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T7,T8,T9

 LINE       414
 EXPRESSION (cmd_info_i[i].opcode == {opcode_d[6:0], 1'b1})
            -----------------------1-----------------------

-1-	Status	Tests
0	Covered	T7,T8,T9
1	Covered	T7,T8,T9

 LINE       416
 EXPRESSION (cmd_info_i[i].opcode == {opcode_d[6:0], 1'b0})
            -----------------------1-----------------------

-1-	Status	Tests
0	Covered	T7,T8,T9
1	Covered	T7,T8,T12

 LINE       472
 EXPRESSION ((cmdinfo7th_addr_mode == Addr4B) ? (5'(31)) : (5'(23)))
             ----------------1---------------

-1-	Status	Tests
0	Covered	T7,T8,T9
1	Covered	T7,T8,T9

 LINE       472
 SUB-EXPRESSION (cmdinfo7th_addr_mode == Addr4B)
                ----------------1---------------

-1-	Status	Tests
0	Covered	T7,T8,T9
1	Covered	T7,T8,T9

 LINE       484
 EXPRESSION (st == StAddress)
            --------1--------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T7,T8,T9

 LINE       493
 EXPRESSION (addrcnt != '0)
            -------1-------

-1-	Status	Tests
0	Covered	T7,T8,T9
1	Covered	T7,T8,T9

 LINE       505
 EXPRESSION (cfg_addr_mask_i[addrcnt_outclk] ? cfg_addr_value_i[addrcnt_outclk] : host_s_i[0])
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T7,T8,T9

 LINE       530
 EXPRESSION ((payloadcnt != '0) && payload_replace)
             ---------1--------    -------2-------

-1-	-2-	Status	Tests
0	1	Covered	T4,T14,T23
1	0	Covered	T7,T8,T9
1	1	Covered	T4,T14,T23

 LINE       530
 SUB-EXPRESSION (payloadcnt != '0)
                ---------1--------

-1-	Status	Tests
0	Covered	T4,T14,T23
1	Covered	T7,T8,T9

 LINE       551
 EXPRESSION (payloadcnt == '0)
            ---------1--------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T14,T23

 LINE       554
 EXPRESSION (cfg_payload_mask_i[payloadcnt_outclk] ? cfg_payload_data_i[payloadcnt_outclk] : host_s_i[0])
             ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T7,T8,T11

 LINE       578
 EXPRESSION (addr_phase_outclk & cmd_info_addr_swap_en_outclk)
             --------1--------   --------------2-------------

-1-	-2-	Status	Tests
0	1	Covered	T7,T4,T14
1	0	Covered	T8,T9,T12
1	1	Covered	T7,T4,T14

 LINE       580
 EXPRESSION (payload_replace_outclk & cmd_info_payload_swap_en_outclk)
             -----------1----------   ---------------2---------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T14,T23
1	0	Covered	T4,T5,T23
1	1	Covered	T4,T14,T23

 LINE       583
 EXPRESSION (addr_swap_en | payload_swap_en)
             ------1-----   -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T14,T23
1	0	Covered	T7,T4,T14

 LINE       584
 EXPRESSION (addr_swap_en ? addr_swap : payload_swap)
             ------1-----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T7,T4,T14

 LINE       593
 EXPRESSION (st == StHighZ)
            -------1-------

-1-	Status	Tests
0	Covered	T7,T8,T9
1	Covered	T7,T8,T9

 LINE       597
 EXPRESSION (dummycnt == '0)
            --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       608
 EXPRESSION (st == StMByte)
            -------1-------

-1-	Status	Tests
0	Covered	T7,T8,T9
1	Not Covered

 LINE       612
 EXPRESSION (mbyte_cnt == '0)
            --------1--------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       617
 EXPRESSION (swap_en ? ({host_s_i[3:1], swap_data}) : host_s_i)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T7,T4,T14

 LINE       653
 EXPRESSION (cfg_cpol_i ? pt_gated_isck_inv : pt_gated_sck)
             -----1----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       659
 EXPRESSION (host_csb_i | csb_deassert_outclk)
             -----1----   ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T1,T10,T7
0	1	Covered	T7,T8,T9
1	0	Covered	T1,T2,T3

 LINE       662
 EXPRESSION (is_active && ((!passthrough_block_i)))
             ----1----    ------------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T5,T23
1	1	Covered	T7,T8,T9

 LINE       707
 EXPRESSION (cmd_8th && cmd_filter[host_s_i[0]])
             ---1---    -----------2-----------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T7,T8,T9
1	1	Covered	T7,T8,T9

 LINE       712
 EXPRESSION (cmd_8th && cmd_info_d.valid)
             ---1---    --------2-------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T7,T8,T9
1	1	Covered	T7,T8,T9

 LINE       723
 EXPRESSION (cmd_info_d.addr_mode != AddrDisabled)
            -------------------1------------------

-1-	Status	Tests
0	Covered	T7,T12,T4
1	Covered	T7,T8,T9

 LINE       732
 EXPRESSION (cmd_info_d.payload_en != 4'b0)
            ---------------1---------------

-1-	Status	Tests
0	Covered	T4,T5,T23
1	Covered	T7,T12,T4

 LINE       734
 EXPRESSION (cmd_info_d.payload_dir == PayloadOut)
            -------------------1------------------

-1-	Status	Tests
0	Covered	T4,T5,T23
1	Covered	T7,T12,T4

 LINE       789
 EXPRESSION (dummycnt_zero && (cmd_info.payload_dir == PayloadOut))
             ------1------    ------------------2-----------------

-1-	-2-	Status	Tests
0	1	Covered	T7,T8,T9
1	0	Not Covered
1	1	Covered	T7,T8,T9

 LINE       789
 SUB-EXPRESSION (cmd_info.payload_dir == PayloadOut)
                ------------------1-----------------

-1-	Status	Tests
0	Not Covered
1	Covered	T7,T8,T9

 LINE       792
 EXPRESSION (dummycnt_zero && (cmd_info.payload_dir == PayloadIn))
             ------1------    -----------------2-----------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       792
 SUB-EXPRESSION (cmd_info.payload_dir == PayloadIn)
                -----------------1-----------------

-1-	Status	Tests
0	Covered	T7,T8,T9
1	Not Covered

 LINE       801
 EXPRESSION (addrcnt == '0)
            -------1-------

-1-	Status	Tests
0	Covered	T7,T8,T9
1	Covered	T7,T8,T9

 LINE       811
 EXPRESSION ((cmd_info.payload_en != 4'b0) && (cmd_info.payload_dir == PayloadOut))
             --------------1--------------    ------------------2-----------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T23,T27
1	0	Covered	T4,T14,T23
1	1	Covered	T7,T4,T14

 LINE       811
 SUB-EXPRESSION (cmd_info.payload_en != 4'b0)
                --------------1--------------

-1-	Status	Tests
0	Covered	T4,T23,T27
1	Covered	T7,T4,T14

 LINE       811
 SUB-EXPRESSION (cmd_info.payload_dir == PayloadOut)
                ------------------1-----------------

-1-	Status	Tests
0	Covered	T4,T14,T23
1	Covered	T7,T4,T14

 LINE       814
 EXPRESSION ((cmd_info.payload_en != 4'b0) && (cmd_info.payload_dir == PayloadIn))
             --------------1--------------    -----------------2-----------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Covered	T4,T14,T23

 LINE       814
 SUB-EXPRESSION (cmd_info.payload_en != 4'b0)
                --------------1--------------

-1-	Status	Tests
0	Covered	T4,T23,T27
1	Covered	T4,T14,T23

 LINE       814
 SUB-EXPRESSION (cmd_info.payload_dir == PayloadIn)
                -----------------1-----------------

-1-	Status	Tests
0	Covered	T4,T23,T27
1	Covered	T4,T14,T23

---

FSM Coverage for Module : spi_passthrough

Summary for FSM :: st

	Total	Covered	Percent
States	7	6	85.71	(Not included in score)
Transitions	12	9	75.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: st

---

states	Line No.	Covered	Tests
StAddress	724	Covered	T7,T8,T9
StDriving	737	Covered	T4,T14,T5
StFilter	708	Covered	T7,T8,T9
StHighZ	728	Covered	T7,T8,T9
StIdle	706	Covered	T1,T2,T3
StMByte	757	Not Covered
StWait	735	Covered	T7,T8,T9

transitions	Line No.	Covered	Tests
StAddress->StDriving	816	Covered	T4,T14,T23
StAddress->StHighZ	807	Covered	T7,T8,T9
StAddress->StMByte	803	Not Covered
StAddress->StWait	813	Covered	T7,T4,T14
StHighZ->StDriving	793	Not Covered
StHighZ->StWait	791	Covered	T7,T8,T9
StIdle->StAddress	724	Covered	T7,T8,T9
StIdle->StDriving	737	Covered	T4,T5,T23
StIdle->StFilter	708	Covered	T7,T8,T9
StIdle->StHighZ	728	Covered	T7,T12,T4
StIdle->StWait	735	Covered	T7,T12,T4
StMByte->StHighZ	752	Not Covered

---

Branch Coverage for Module : spi_passthrough

	Line No.	Total	Covered	Percent
Branches		94	86	91.49
TERNARY	505	2	2	100.00
TERNARY	554	2	2	100.00
TERNARY	584	2	2	100.00
TERNARY	617	2	2	100.00
TERNARY	653	2	1	50.00
IF	346	3	3	100.00
IF	355	3	3	100.00
IF	359	2	2	100.00
IF	370	3	3	100.00
IF	386	3	3	100.00
IF	411	2	2	100.00
IF	424	3	3	100.00
IF	435	3	3	100.00
IF	467	3	3	100.00
IF	487	4	4	100.00
IF	499	2	2	100.00
IF	514	2	2	100.00
IF	528	3	3	100.00
IF	536	2	2	100.00
IF	541	4	4	100.00
IF	547	2	2	100.00
IF	569	2	2	100.00
IF	590	4	4	100.00
IF	604	4	2	50.00
IF	621	2	2	100.00
IF	628	2	2	100.00
IF	670	2	2	100.00
CASE	703	24	19	79.17

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_spi_device_0.1/rtl/spi_passthrough.sv' or '../src/lowrisc_ip_spi_device_0.1/rtl/spi_passthrough.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	505	(cfg_addr_mask_i[addrcnt_outclk]) ? 

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T9
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	554	(cfg_payload_mask_i[payloadcnt_outclk]) ? 

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T11
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	584	(addr_swap_en) ? 

Branches:

-1-	Status	Tests
1	Covered	T7,T4,T14
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	617	(swap_en) ? 

Branches:

-1-	Status	Tests
1	Covered	T7,T4,T14
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	653	(cfg_cpol_i) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	346	if ((!rst_ni))
-2-:	348	if ((bitcnt < 6'(8)))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T7,T8,T9
0	0	Covered	T7,T8,T9

	LineNo.	Expression
-1-:	355	if ((!rst_ni))
-2-:	356	if (filter)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T7,T8,T9
0	0	Covered	T7,T8,T9

	LineNo.	Expression
-1-:	359	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T7,T8,T9

	LineNo.	Expression
-1-:	370	if ((!rst_ni))
-2-:	372	if ((bitcnt != '1))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T7,T8,T9
0	0	Covered	T7,T8,T9

	LineNo.	Expression
-1-:	386	if ((!rst_ni))
-2-:	388	if (cmd_7th)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T7,T8,T9
0	0	Covered	T7,T8,T9

	LineNo.	Expression
-1-:	411	if (cmd_7th)

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T9
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	424	if ((!rst_ni))
-2-:	426	if (cmd_7th)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T7,T8,T9
0	0	Covered	T7,T8,T9

	LineNo.	Expression
-1-:	435	if ((!rst_ni))
-2-:	437	if (cmd_info_latch)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T7,T8,T9
0	0	Covered	T7,T8,T9

	LineNo.	Expression
-1-:	467	if (cmd_8th)
-2-:	472	((cmdinfo7th_addr_mode == Addr4B)) ? 

Branches:

-1-	-2-	Status	Tests
1	1	Covered	T7,T8,T9
1	0	Covered	T7,T8,T9
0	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	487	if ((!rst_ni))
-2-:	489	if (addr_set)
-3-:	493	if ((addrcnt != '0))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T7,T8,T9
0	0	1	Covered	T7,T8,T9
0	0	0	Covered	T7,T8,T9

	LineNo.	Expression
-1-:	499	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T7,T8,T9

	LineNo.	Expression
-1-:	514	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T7,T8,T9

	LineNo.	Expression
-1-:	528	if ((!rst_ni))
-2-:	530	if (((payloadcnt != '0) && payload_replace))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T4,T14,T23
0	0	Covered	T7,T8,T9

	LineNo.	Expression
-1-:	536	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T7,T8,T9

	LineNo.	Expression
-1-:	541	if ((!rst_ni))
-2-:	542	if (payload_replace_set)
-3-:	543	if (payload_replace_clr)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T4,T14,T5
0	0	1	Covered	T4,T14,T23
0	0	0	Covered	T7,T8,T9

	LineNo.	Expression
-1-:	547	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T7,T8,T9

	LineNo.	Expression
-1-:	569	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T7,T8,T9

	LineNo.	Expression
-1-:	590	if ((!rst_ni))
-2-:	591	if (dummy_set)
-3-:	593	if ((st == StHighZ))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T7,T8,T9
0	0	1	Covered	T7,T8,T9
0	0	0	Covered	T7,T8,T9

	LineNo.	Expression
-1-:	604	if ((!rst_ni))
-2-:	606	if (mbyte_set)
-3-:	608	if ((st == StMByte))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Not Covered
0	0	1	Not Covered
0	0	0	Covered	T7,T8,T9

	LineNo.	Expression
-1-:	621	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T7,T8,T9

	LineNo.	Expression
-1-:	628	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T7,T8,T9

	LineNo.	Expression
-1-:	670	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T7,T8,T9

	LineNo.	Expression
-1-:	703	case (st)
-2-:	705	if ((!is_active))
-3-:	707	if ((cmd_8th && cmd_filter[host_s_i[0]]))
-4-:	712	if ((cmd_8th && cmd_info_d.valid))
-5-:	723	if ((cmd_info_d.addr_mode != AddrDisabled))
-6-:	727	if (cmd_info_d.dummy_en)
-7-:	732	if ((cmd_info_d.payload_en != 4'b0))
-8-:	734	if ((cmd_info_d.payload_dir == PayloadOut))
-9-:	743	if (cmd_8th)
-10-:	751	if (mbytecnt_zero)
-11-:	789	if ((dummycnt_zero && (cmd_info.payload_dir == PayloadOut)))
-12-:	792	if ((dummycnt_zero && (cmd_info.payload_dir == PayloadIn)))
-13-:	801	if ((addrcnt == '0))
-14-:	802	if (cmd_info.mbyte_en)
-15-:	806	if (cmd_info.dummy_en)
-16-:	811	if (((cmd_info.payload_en != 4'b0) && (cmd_info.payload_dir == PayloadOut)))
-17-:	814	if (((cmd_info.payload_en != 4'b0) && (cmd_info.payload_dir == PayloadIn)))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	-15-	-16-	-17-	Status	Tests
StIdle	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
StIdle	0	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T7,T8,T9
StIdle	0	0	1	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T7,T8,T9
StIdle	0	0	1	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T7,T12,T4
StIdle	0	0	1	0	0	1	1	-	-	-	-	-	-	-	-	-	Covered	T7,T12,T4
StIdle	0	0	1	0	0	1	0	-	-	-	-	-	-	-	-	-	Covered	T4,T5,T23
StIdle	0	0	1	0	0	0	-	-	-	-	-	-	-	-	-	-	Covered	T4,T5,T23
StIdle	0	0	0	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T7,T8,T9
StIdle	0	0	0	-	-	-	-	0	-	-	-	-	-	-	-	-	Covered	T7,T8,T9
StMByte	-	-	-	-	-	-	-	-	1	-	-	-	-	-	-	-	Not Covered
StMByte	-	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	Not Covered
StFilter	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T7,T8,T9
StWait	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T7,T8,T9
StDriving	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T4,T14,T5
StHighZ	-	-	-	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T7,T8,T9
StHighZ	-	-	-	-	-	-	-	-	-	0	1	-	-	-	-	-	Not Covered
StHighZ	-	-	-	-	-	-	-	-	-	0	0	-	-	-	-	-	Covered	T7,T8,T9
StAddress	-	-	-	-	-	-	-	-	-	-	-	1	1	-	-	-	Not Covered
StAddress	-	-	-	-	-	-	-	-	-	-	-	1	0	1	-	-	Covered	T7,T8,T9
StAddress	-	-	-	-	-	-	-	-	-	-	-	1	0	0	1	-	Covered	T7,T4,T14
StAddress	-	-	-	-	-	-	-	-	-	-	-	1	0	0	0	1	Covered	T4,T14,T23
StAddress	-	-	-	-	-	-	-	-	-	-	-	1	0	0	0	0	Covered	T4,T23,T27
StAddress	-	-	-	-	-	-	-	-	-	-	-	0	-	-	-	-	Covered	T7,T8,T9
default	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered

---

Assert Coverage for Module : spi_passthrough

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AddrSetInStIdle_A	8432	8432	0	0
PassThroughStKnown_A	186997894	145864202	0	0
PayloadSwapConstraint_M	186997894	2100936	0	0

AddrSetInStIdle_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8432	8432	0	0
T4	116	116	0	0
T5	21	21	0	0
T7	10	10	0	0
T8	6	6	0	0
T9	2	2	0	0
T12	6	6	0	0
T13	6	6	0	0
T14	6	6	0	0
T23	50	50	0	0
T34	7	7	0	0

PassThroughStKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	186997894	145864202	0	0
T4	100733	100260	0	0
T5	0	265428	0	0
T7	175857	175032	0	0
T8	74526	74526	0	0
T9	20428	20428	0	0
T11	11749	11749	0	0
T12	140178	140178	0	0
T13	15516	15516	0	0
T14	221150	220364	0	0
T15	0	13543	0	0
T17	4250	0	0	0
T18	101454	0	0	0

PayloadSwapConstraint_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	186997894	2100936	0	0
T4	100733	43504	0	0
T14	221150	64	0	0
T15	13543	0	0	0
T18	101454	0	0	0
T19	3221	0	0	0
T22	72	0	0	0
T23	622872	17392	0	0
T27	100709	25248	0	0
T34	62877	0	0	0
T35	0	30184	0	0
T36	0	1048	0	0
T37	0	45968	0	0
T38	0	22408	0	0
T39	0	24280	0	0
T40	0	10312	0	0
T41	92556	0	0	0