Unified Coverage Report :: Module :: spi_device

Module : spi_device

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.71	95.79	89.19	96.92		91.18	95.45

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_spi_device_0.1/rtl/spi_device.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut	93.71	95.79	89.19	96.92		91.18	95.45

---

Module Instance : tb.dut

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.71	95.79	89.19	96.92		91.18	95.45

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.01	98.54	94.89	98.60	90.20	97.31	96.54

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							tb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_alert_tx[0].u_prim_alert_sender	100.00			100.00
spi_device_csr_assert	100.00						100.00
tlul_assert_device	100.00	100.00				100.00	100.00
u_clk_csb_buf	100.00	100.00
u_clk_csb_edge_0	100.00	100.00	100.00			100.00
u_clk_csb_mux	64.81	100.00	44.44				50.00
u_clk_spi	85.19	100.00	55.56				100.00
u_clk_spi_in_buf	100.00	100.00
u_clk_spi_in_mux	64.81	100.00	44.44				50.00
u_clk_spi_out_buf	100.00	100.00
u_clk_spi_out_mux	64.81	100.00	44.44				50.00
u_cmdparse	97.58	100.00	92.00		100.00	95.92	100.00
u_csb_buf	100.00	100.00
u_csb_edge_spiclk	94.44	100.00	83.33			100.00
u_csb_edge_sysclk	100.00	100.00	100.00			100.00
u_csb_rst_scan_mux	64.81	100.00	44.44				50.00
u_flash_readbuf_flip_pulse_sync	100.00	100.00	100.00			100.00	100.00
u_flash_readbuf_watermark_pulse_sync	100.00	100.00	100.00			100.00	100.00
u_intr_cmdfifo_not_empty	100.00	100.00	100.00			100.00	100.00
u_intr_payload_not_empty	100.00	100.00	100.00			100.00	100.00
u_intr_payload_overflow	100.00	100.00	100.00			100.00	100.00
u_intr_readbuf_flip	100.00	100.00	100.00			100.00	100.00
u_intr_readbuf_watermark	100.00	100.00	100.00			100.00	100.00
u_intr_tpm_cmdaddr_notempty	100.00	100.00	100.00			100.00	100.00
u_intr_upload_edge	100.00	100.00				100.00
u_jedec	99.38	100.00	100.00		100.00	96.88	100.00
u_p2s	84.57	100.00	69.23			69.05	100.00
u_passthrough	90.07	94.33	89.19		75.00	91.84	100.00
u_readcmd	93.14	97.16	93.19		87.50	87.82	100.00
u_reg	99.62	99.48	99.33	100.00		99.30	100.00
u_s2p	86.75	100.00	78.57			68.42	100.00
u_scanmode_sync	100.00						100.00
u_sck_csb_edge	94.44	100.00	83.33			100.00
u_sck_tog_edge	100.00	100.00	100.00			100.00
u_spi_tpm	96.43	99.76	93.53		91.67	97.18	100.00
u_spid_addr_4b	100.00	100.00	100.00			100.00
u_spid_dpram	95.45	100.00	81.82			100.00	100.00
u_spid_status	96.19	100.00	86.84		100.00	94.12	100.00
u_sys_sram_arbiter	87.03	100.00	70.73			96.43	80.95
u_sys_tpm_csb_sync	100.00	100.00				100.00
u_tlul2sram_egress	71.12	81.67	59.07			62.50	81.25
u_tlul2sram_ingress	86.46	87.92	73.84			84.09	100.00
u_tpm_csb_buf	100.00	100.00
u_tpm_csb_rst_scan_mux	64.81	100.00	44.44				50.00
u_tpm_csb_rst_sync	70.83	88.89	44.44			100.00	50.00
u_upload	91.13	98.58	73.82		100.00	93.98	89.29

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : spi_device

	Line No.	Total	Covered	Percent
TOTAL		214	205	95.79
CONT_ASSIGN	175	1	1	100.00
CONT_ASSIGN	297	1	1	100.00
CONT_ASSIGN	356	1	1	100.00
CONT_ASSIGN	357	1	1	100.00
CONT_ASSIGN	358	1	1	100.00
CONT_ASSIGN	359	1	1	100.00
CONT_ASSIGN	364	1	1	100.00
CONT_ASSIGN	365	1	1	100.00
CONT_ASSIGN	367	1	1	100.00
CONT_ASSIGN	382	1	1	100.00
CONT_ASSIGN	484	1	1	100.00
CONT_ASSIGN	491	1	1	100.00
CONT_ASSIGN	493	1	1	100.00
ALWAYS	496	4	4	100.00
CONT_ASSIGN	504	1	1	100.00
CONT_ASSIGN	510	1	1	100.00
CONT_ASSIGN	513	1	1	100.00
CONT_ASSIGN	514	1	1	100.00
CONT_ASSIGN	518	1	1	100.00
ALWAYS	523	0	0
ALWAYS	523	2	2	100.00
CONT_ASSIGN	528	1	1	100.00
CONT_ASSIGN	529	1	1	100.00
ALWAYS	537	0	0
ALWAYS	537	12	12	100.00
CONT_ASSIGN	600	1	1	100.00
CONT_ASSIGN	601	1	1	100.00
CONT_ASSIGN	602	1	1	100.00
ALWAYS	769	6	6	100.00
ALWAYS	795	4	4	100.00
CONT_ASSIGN	814	1	1	100.00
ALWAYS	836	3	3	100.00
ALWAYS	842	8	8	100.00
ALWAYS	880	28	28	100.00
ALWAYS	954	13	13	100.00
ALWAYS	991	3	3	100.00
CONT_ASSIGN	1123	1	1	100.00
CONT_ASSIGN	1125	1	1	100.00
CONT_ASSIGN	1128	1	1	100.00
CONT_ASSIGN	1129	1	1	100.00
CONT_ASSIGN	1131	1	1	100.00
CONT_ASSIGN	1132	1	1	100.00
CONT_ASSIGN	1171	1	0	0.00
CONT_ASSIGN	1201	1	0	0.00
CONT_ASSIGN	1285	1	1	100.00
CONT_ASSIGN	1286	1	1	100.00
CONT_ASSIGN	1288	1	1	100.00
CONT_ASSIGN	1290	1	1	100.00
CONT_ASSIGN	1291	1	1	100.00
CONT_ASSIGN	1293	1	1	100.00
CONT_ASSIGN	1297	1	1	100.00
CONT_ASSIGN	1300	1	1	100.00
CONT_ASSIGN	1303	1	1	100.00
CONT_ASSIGN	1306	1	1	100.00
CONT_ASSIGN	1309	1	1	100.00
CONT_ASSIGN	1312	1	1	100.00
CONT_ASSIGN	1319	1	1	100.00
CONT_ASSIGN	1320	1	1	100.00
CONT_ASSIGN	1362	1	1	100.00
CONT_ASSIGN	1464	1	0	0.00
CONT_ASSIGN	1472	1	1	100.00
CONT_ASSIGN	1473	1	1	100.00
CONT_ASSIGN	1474	1	1	100.00
CONT_ASSIGN	1475	1	1	100.00
CONT_ASSIGN	1476	1	1	100.00
CONT_ASSIGN	1479	1	1	100.00
CONT_ASSIGN	1488	1	1	100.00
CONT_ASSIGN	1488	1	1	100.00
CONT_ASSIGN	1488	1	1	100.00
CONT_ASSIGN	1488	1	1	100.00
CONT_ASSIGN	1488	1	1	100.00
CONT_ASSIGN	1491	1	1	100.00
CONT_ASSIGN	1492	1	1	100.00
CONT_ASSIGN	1493	1	1	100.00
CONT_ASSIGN	1494	1	1	100.00
CONT_ASSIGN	1495	1	1	100.00
CONT_ASSIGN	1496	1	1	100.00
CONT_ASSIGN	1498	1	1	100.00
CONT_ASSIGN	1502	1	1	100.00
CONT_ASSIGN	1504	1	1	100.00
CONT_ASSIGN	1505	1	1	100.00
CONT_ASSIGN	1512	1	1	100.00
CONT_ASSIGN	1514	1	1	100.00
CONT_ASSIGN	1516	1	1	100.00
CONT_ASSIGN	1520	1	1	100.00
CONT_ASSIGN	1522	1	1	100.00
CONT_ASSIGN	1523	1	1	100.00
CONT_ASSIGN	1534	1	1	100.00
CONT_ASSIGN	1535	1	1	100.00
CONT_ASSIGN	1536	1	1	100.00
CONT_ASSIGN	1537	1	1	100.00
CONT_ASSIGN	1590	1	1	100.00
CONT_ASSIGN	1592	1	1	100.00
ALWAYS	1597	4	4	100.00
ALWAYS	1606	0	0
ALWAYS	1606	9	9	100.00
CONT_ASSIGN	1623	1	1	100.00
CONT_ASSIGN	1623	1	1	100.00
CONT_ASSIGN	1623	1	1	100.00
CONT_ASSIGN	1623	1	1	100.00
CONT_ASSIGN	1624	1	1	100.00
CONT_ASSIGN	1624	1	1	100.00
CONT_ASSIGN	1624	1	0	0.00
CONT_ASSIGN	1624	1	0	0.00
CONT_ASSIGN	1625	1	1	100.00
CONT_ASSIGN	1625	1	1	100.00
CONT_ASSIGN	1625	1	0	0.00
CONT_ASSIGN	1625	1	0	0.00
CONT_ASSIGN	1626	1	1	100.00
CONT_ASSIGN	1626	1	1	100.00
CONT_ASSIGN	1626	1	0	0.00
CONT_ASSIGN	1626	1	0	0.00
CONT_ASSIGN	1628	1	1	100.00
CONT_ASSIGN	1628	1	1	100.00
CONT_ASSIGN	1628	1	1	100.00
CONT_ASSIGN	1628	1	1	100.00
CONT_ASSIGN	1629	1	1	100.00
CONT_ASSIGN	1629	1	1	100.00
CONT_ASSIGN	1629	1	1	100.00
CONT_ASSIGN	1629	1	1	100.00
CONT_ASSIGN	1630	1	1	100.00
CONT_ASSIGN	1630	1	1	100.00
CONT_ASSIGN	1630	1	1	100.00
CONT_ASSIGN	1630	1	1	100.00
CONT_ASSIGN	1673	1	1	100.00
CONT_ASSIGN	1674	1	1	100.00
CONT_ASSIGN	1675	1	1	100.00
CONT_ASSIGN	1676	1	1	100.00
CONT_ASSIGN	1677	1	1	100.00
CONT_ASSIGN	1679	1	1	100.00
CONT_ASSIGN	1680	1	1	100.00
CONT_ASSIGN	1681	1	1	100.00
CONT_ASSIGN	1737	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_spi_device_0.1/rtl/spi_device.sv' or '../src/lowrisc_ip_spi_device_0.1/rtl/spi_device.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
175	1	1
297	1	1
356	1	1
357	1	1
358	1	1
359	1	1
364	1	1
365	1	1
367	1	1
382	1	1
484	1	1
491	1	1
493	1	1
496	1	1
497	1	1
498	1	1
499	1	1
			MISSING_ELSE
504	1	1
510	1	1
513	1	1
514	1	1
518	1	1
523	1	1
524	1	1
528	1	1
529	1	1
537	1	1
538	1	1
556	1	1
557	1	1
561	1	1
562	1	1
564	1	1
565	1	1
567	1	1
568	1	1
570	1	1
571	1	1
600	1	1
601	1	1
602	1	1
769	2	2
770	1	1
771	1	1
772	1	1
773	1	1
			MISSING_ELSE
795	2	2
796	1	1
797	1	1
			MISSING_ELSE
814	1	1
836	2	2
837	1	1
842	1	1
844	1	1
845	1	1
852	1	1
856	1	1
857	1	1
861	1	1
862	1	1
880	1	1
881	1	1
882	1	1
883	1	1
885	1	1
887	1	1
893	1	1
896	1	1
897	1	1
899	1	1
901	1	1
903	1	1
907	1	1
909	1	1
910	1	1
911	1	1
914	1	1
916	1	1
917	1	1
918	1	1
923	1	1
925	1	1
926	1	1
927	1	1
931	1	1
933	1	1
934	1	1
935	1	1
954	1	1
955	1	1
957	1	1
959	1	1
960	1	1
964	1	1
966	1	1
967	1	1
971	1	1
972	1	1
973	1	1
975	1	1
976	1	1
991	2	2
992	1	1
1123	1	1
1125	1	1
1128	1	1
1129	1	1
1131	1	1
1132	1	1
1171	0	1
1201	0	1
1285	1	1
1286	1	1
1288	1	1
1290	1	1
1291	1	1
1293	1	1
1297	1	1
1300	1	1
1303	1	1
1306	1	1
1309	1	1
1312	1	1
1319	1	1
1320	1	1
1362	1	1
1464	0	1
1472	1	1
1473	1	1
1474	1	1
1475	1	1
1476	1	1
1479	1	1
1488	5	5
1491	1	1
1492	1	1
1493	1	1
1494	1	1
1495	1	1
1496	1	1
1498	1	1
1502	1	1
1504	1	1
1505	1	1
1512	1	1
1514	1	1
1516	1	1
1520	1	1
1522	1	1
1523	1	1
1534	1	1
1535	1	1
1536	1	1
1537	1	1
1590	1	1
1592	1	1
1597	1	1
1598	1	1
1599	1	1
1600	1	1
			MISSING_ELSE
1606	1	1
1607	1	1
1609	1	1
1612	1	1
1613	1	1
1614	1	1
1615	1	1
1617	1	1
1618	1	1
1623	4	4
1624	2	4
1625	2	4
1626	2	4
1628	4	4
1629	4	4
1630	4	4
1673	1	1
1674	1	1
1675	1	1
1676	1	1
1677	1	1
1679	1	1
1680	1	1
1681	1	1
1737	1	1

---

Cond Coverage for Module : spi_device

	Total	Covered	Percent
Conditions	37	33	89.19
Logical	37	33	89.19
Non-Logical	0	0
Event	0	0

 LINE       175
 EXPRESSION (payload_depth != '0)
            ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T5,T23

 LINE       655
 EXPRESSION (rst_ni & ((~rst_csb_buf)))
             ---1--   --------2-------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T10,T7

 LINE       666
 EXPRESSION (rst_ni & ((~rst_tpm_csb_buf)))
             ---1--   ----------2---------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       814
 EXPRESSION (spi_clk_pos_edge | spi_clk_neg_edge)
             --------1-------   --------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T3,T17
1	0	Covered	T2,T3,T17

 LINE       866
 EXPRESSION (cmd_only_dp_sel == DpUpload)
            --------------1--------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T5,T6

 LINE       957
 EXPRESSION (cfg_tpm_en && ((!sck_tpm_csb_buf)))
             -----1----    ----------2---------

-1-	-2-	Status	Tests
0	1	Covered	T1,T10,T20
1	0	Covered	T2,T3,T17
1	1	Covered	T2,T3,T17

 LINE       1123
 EXPRESSION (reg2hw.flash_status.busy.qe && reg2hw.flash_status.status.qe)
             -------------1-------------    --------------2--------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Covered	T11,T13,T4

 LINE       1131
 EXPRESSION (cmd_only_dp_sel == DpWrEn)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T6,T23

 LINE       1132
 EXPRESSION (cmd_only_dp_sel == DpWrDi)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T5,T6

 LINE       1319
 EXPRESSION (cmd_only_dp_sel == DpEn4B)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T5,T6

 LINE       1320
 EXPRESSION (cmd_only_dp_sel == DpEx4B)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T5,T6

 LINE       1599
 EXPRESSION ((i != SysSramFwEgress) && (i != SysSramFwIngress))
             -----------1----------    -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       1599
 SUB-EXPRESSION (i != SysSramFwEgress)
                -----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       1599
 SUB-EXPRESSION (i != SysSramFwIngress)
                -----------1-----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       1737
 SUB-EXPRESSION (reg2hw.alert_test.q & reg2hw.alert_test.qe)
                 ---------1---------   ----------2---------

-1-	-2-	Status	Tests
0	1	Covered	T16,T32,T33
1	0	Covered	T1,T2,T3
1	1	Covered	T16,T32,T33

---

Toggle Coverage for Module : spi_device

	Total	Covered	Percent
Totals	57	52	91.23
Total Bits	454	440	96.92
Total Bits 0->1	227	220	96.92
Total Bits 1->0	227	220	96.92

Ports	57	52	91.23
Port Bits	454	440	96.92
Port Bits 0->1	227	220	96.92
Port Bits 1->0	227	220	96.92

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T20,T23,T29	Yes	T1,T2,T3	INPUT
tl_i.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T8	Yes	T1,T2,T8	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_source[7:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_size[1:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[2:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_o.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_error	Yes	Yes	T24,T25,T44	Yes	T24,T25,T44	OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_user.rsp_intg[5:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_user.rsp_intg[6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T2,T3,T7	OUTPUT
tl_o.d_sink	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_source[7:0]	Yes	Yes	T3,T7,T8	Yes	T2,T3,T7	OUTPUT
tl_o.d_size[1:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T2,*T3,*T7	Yes	T2,T3,T7	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T16,T32,T33	Yes	T16,T32,T33	INPUT
alert_rx_i[0].ping_n	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[0].ping_p	Unreachable	Unreachable		Unreachable		INPUT
alert_tx_o[0].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T16,T32,T33	Yes	T16,T32,T33	OUTPUT
cio_sck_i	Yes	Yes	T2,T3,T7	Yes	T2,T3,T7	INPUT
cio_csb_i	Yes	Yes	T1,T10,T7	Yes	T1,T10,T7	INPUT
cio_sd_o[3:0]	Yes	Yes	T7,T8,T9	Yes	T7,T8,T9	OUTPUT
cio_sd_en_o[3:0]	Yes	Yes	T7,T8,T9	Yes	T7,T8,T9	OUTPUT
cio_sd_i[3:0]	Yes	Yes	T2,T3,T7	Yes	T2,T3,T7	INPUT
cio_tpm_csb_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
passthrough_o.s_en[0]	Yes	Yes	*T7,*T8,*T9	Yes	T7,T8,T9	OUTPUT
passthrough_o.s_en[3:1]	No	No		No		OUTPUT
passthrough_o.s[3:0]	Yes	Yes	T2,T3,T7	Yes	T2,T3,T7	OUTPUT
passthrough_o.csb_en	No	No		No		OUTPUT
passthrough_o.csb	Yes	Yes	T1,T10,T7	Yes	T1,T10,T7	OUTPUT
passthrough_o.sck_en	No	No		No		OUTPUT
passthrough_o.sck	Yes	Yes	T2,T3,T7	Yes	T2,T3,T7	OUTPUT
passthrough_o.passthrough_en	Yes	Yes	T4,T5,T23	Yes	T7,T8,T9	OUTPUT
passthrough_i.s[3:0]	Yes	Yes	T2,T3,T7	Yes	T2,T3,T7	INPUT
intr_upload_cmdfifo_not_empty_o	Yes	Yes	T20,T29,T31	Yes	T20,T29,T31	OUTPUT
intr_upload_payload_not_empty_o	Yes	Yes	T20,T23,T29	Yes	T20,T23,T29	OUTPUT
intr_upload_payload_overflow_o	Yes	Yes	T20,T29,T31	Yes	T20,T29,T31	OUTPUT
intr_readbuf_watermark_o	Yes	Yes	T20,T23,T29	Yes	T20,T23,T29	OUTPUT
intr_readbuf_flip_o	Yes	Yes	T20,T29,T31	Yes	T20,T29,T31	OUTPUT
intr_tpm_header_not_empty_o	Yes	Yes	T20,T23,T29	Yes	T20,T23,T29	OUTPUT
ram_cfg_i.b_ram_lcfg.cfg[3:0]	Yes	Yes	T45,T46,T47	Yes	T45,T46,T47	INPUT
ram_cfg_i.b_ram_lcfg.cfg_en	Yes	Yes	T45,T46,T47	Yes	T45,T46,T47	INPUT
ram_cfg_i.a_ram_lcfg.cfg[3:0]	Yes	Yes	T45,T46,T47	Yes	T45,T46,T47	INPUT
ram_cfg_i.a_ram_lcfg.cfg_en	Yes	Yes	T45,T46,T47	Yes	T45,T46,T47	INPUT
ram_cfg_i.b_ram_fcfg.cfg[3:0]	Yes	Yes	T45,T46,T47	Yes	T45,T46,T47	INPUT
ram_cfg_i.b_ram_fcfg.cfg_en	Yes	Yes	T45,T46,T47	Yes	T45,T46,T47	INPUT
ram_cfg_i.a_ram_fcfg.cfg[3:0]	Yes	Yes	T45,T46,T47	Yes	T45,T46,T47	INPUT
ram_cfg_i.a_ram_fcfg.cfg_en	Yes	Yes	T45,T46,T47	Yes	T45,T46,T47	INPUT
sck_monitor_o	Yes	Yes	T2,T3,T7	Yes	T2,T3,T7	OUTPUT
mbist_en_i	Unreachable	Unreachable		Unreachable		INPUT
scan_clk_i	No	No		No		INPUT
scan_rst_ni	No	No		No		INPUT
scanmode_i[3:0]	Unreachable	Unreachable		Unreachable		INPUT

*Tests covering at least one bit in the range

---

Branch Coverage for Module : spi_device

	Line No.	Total	Covered	Percent
Branches		34	31	91.18
IF	496	3	3	100.00
IF	769	4	4	100.00
IF	795	3	3	100.00
IF	836	2	2	100.00
CASE	852	4	4	100.00
CASE	893	7	5	71.43
IF	957	5	4	80.00
IF	991	2	2	100.00
IF	1599	2	2	100.00
IF	1609	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_spi_device_0.1/rtl/spi_device.sv' or '../src/lowrisc_ip_spi_device_0.1/rtl/spi_device.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	496	if ((!rst_ni))
-2-:	498	if (sys_csb_deasserted_pulse)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T10,T7
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	769	if ((!tpm_rst_n))
-2-:	770	if (spi_clk_csb_rst_pulse)
-3-:	772	if (spi_clk_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T2,T3,T17
0	0	1	Covered	T2,T3,T17
0	0	0	Covered	T2,T3,T17

	LineNo.	Expression
-1-:	795	if ((!rst_ni))
-2-:	796	if (sys_csb_pos_pulse_stretch)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T2,T3,T17
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	836	if ((!rst_spi_n))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T7,T8,T9

	LineNo.	Expression
-1-:	852	case (cmd_dp_sel)
-2-:	866	if ((cmd_only_dp_sel == DpUpload))

Branches:

-1-	-2-	Status	Tests
DpReadCmd DpReadSFDP	-	Covered	T7,T8,T9
DpUpload	-	Covered	T4,T5,T6
default	1	Covered	T4,T5,T6
default	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	893	case (spi_mode)
-2-:	899	case (cmd_dp_sel)

Branches:

-1-	-2-	Status	Tests
FlashMode PassThrough	DpNone	Covered	T1,T2,T3
FlashMode PassThrough	DpReadCmd DpReadSFDP	Covered	T7,T8,T9
FlashMode PassThrough	DpReadStatus	Covered	T4,T5,T6
FlashMode PassThrough	DpReadJEDEC	Covered	T4,T6,T23
FlashMode PassThrough	DpUpload	Covered	T4,T5,T6
FlashMode PassThrough	default	Not Covered
default	-	Not Covered

	LineNo.	Expression
-1-:	957	if ((cfg_tpm_en && (!sck_tpm_csb_buf)))
-2-:	964	case (spi_mode)
-3-:	971	if (intercept_en)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T2,T3,T17
0	FlashMode	-	Covered	T1,T2,T3
0	PassThrough	1	Covered	T13,T4,T5
0	PassThrough	0	Covered	T7,T8,T9
0	default	-	Not Covered

	LineNo.	Expression
-1-:	991	if ((!rst_spi_n))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T7,T8,T9

	LineNo.	Expression
-1-:	1599	if (((i != SysSramFwEgress) && (i != SysSramFwIngress)))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	1609	if (sys_sram_hw_req)

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T1,T2,T3

---

Assert Coverage for Module : spi_device

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	22	22	100.00	21	95.45
Cover properties	0	0		0
Cover sequences	0	0		0
Total	22	22	100.00	21	95.45

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AlertKnownO_A	576134620	576051877	0	0
CioSdoEnOKnown	576134620	576051877	0	0
CioSdoEnOffWhenInactive	576134620	576051877	0	0
CsPulseWidth_A	576134620	494510450	0	0
FpvSecCmRegWeOnehotCheck_A	576134620	90	0	0
InterceptLevel_M	186998803	0	0	0
IntrReadbufFlipOKnown	576134620	576051877	0	0
IntrReadbufWatermarkOKnown	576134620	576051877	0	0
IntrTpmHeaderNotEmptyOKnown	576134620	576051877	0	0
IntrUploadCmdfifoNotEmptyOKnown	576134620	576051877	0	0
IntrUploadPayloadNotEmptyOKnown	576134620	576051877	0	0
IntrUploadPayloadOverflowOKnown	576134620	576051877	0	0
PayloadStartIdxWidthMatch_A	922	922	0	0
SpiModeKnown_A	576134620	576051877	0	0
TpmEnableWhenTpmCsbIdle_M	576134620	340	0	0
TpmRdfifoNotFull_A	576134620	260962	0	0
TpmWrPtrMatch_A	922	922	0	0
g_sram_connect[0].ReqAlwaysAccepted_A	576134620	2210896	0	0
g_sram_connect[1].ReqAlwaysAccepted_A	576134620	56689	0	0
g_sram_connect[2].ReqAlwaysAccepted_A	576134620	2439	0	0
g_sram_connect[3].ReqAlwaysAccepted_A	576134620	1886	0	0
scanmodeKnown	576134620	576134620	0	0

AlertKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	576134620	576051877	0	0
T1	2048	1980	0	0
T2	11842	11786	0	0
T3	380270	380176	0	0
T7	55033	54955	0	0
T8	152980	152899	0	0
T9	68355	68305	0	0
T10	1520	1449	0	0
T11	19483	19404	0	0
T12	566282	566207	0	0
T16	950	860	0	0

CioSdoEnOKnown

Name	Attempts	Real Successes	Failures	Incomplete
Total	576134620	576051877	0	0
T1	2048	1980	0	0
T2	11842	11786	0	0
T3	380270	380176	0	0
T7	55033	54955	0	0
T8	152980	152899	0	0
T9	68355	68305	0	0
T10	1520	1449	0	0
T11	19483	19404	0	0
T12	566282	566207	0	0
T16	950	860	0	0

CioSdoEnOffWhenInactive

Name	Attempts	Real Successes	Failures	Incomplete
Total	576134620	576051877	0	0
T1	2048	1980	0	0
T2	11842	11786	0	0
T3	380270	380176	0	0
T7	55033	54955	0	0
T8	152980	152899	0	0
T9	68355	68305	0	0
T10	1520	1449	0	0
T11	19483	19404	0	0
T12	566282	566207	0	0
T16	950	860	0	0

CsPulseWidth_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	576134620	494510450	0	0
T1	2048	1595	0	0
T2	11842	1257	0	0
T3	380270	44397	0	0
T7	55033	54955	0	0
T8	152980	152899	0	0
T9	68355	68305	0	0
T10	1520	1190	0	0
T11	19483	19404	0	0
T12	566282	566207	0	0
T16	950	860	0	0

FpvSecCmRegWeOnehotCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	576134620	90	0	0
T48	4355	10	0	0
T49	7885	30	0	0
T50	0	10	0	0
T51	0	10	0	0
T52	0	30	0	0
T53	26346	0	0	0
T54	16110	0	0	0
T55	128809	0	0	0
T56	763017	0	0	0
T57	1719	0	0	0
T58	2047	0	0	0
T59	13281	0	0	0
T60	8985	0	0	0

InterceptLevel_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	186998803	0	0	0

IntrReadbufFlipOKnown

Name	Attempts	Real Successes	Failures	Incomplete
Total	576134620	576051877	0	0
T1	2048	1980	0	0
T2	11842	11786	0	0
T3	380270	380176	0	0
T7	55033	54955	0	0
T8	152980	152899	0	0
T9	68355	68305	0	0
T10	1520	1449	0	0
T11	19483	19404	0	0
T12	566282	566207	0	0
T16	950	860	0	0

IntrReadbufWatermarkOKnown

Name	Attempts	Real Successes	Failures	Incomplete
Total	576134620	576051877	0	0
T1	2048	1980	0	0
T2	11842	11786	0	0
T3	380270	380176	0	0
T7	55033	54955	0	0
T8	152980	152899	0	0
T9	68355	68305	0	0
T10	1520	1449	0	0
T11	19483	19404	0	0
T12	566282	566207	0	0
T16	950	860	0	0

IntrTpmHeaderNotEmptyOKnown

Name	Attempts	Real Successes	Failures	Incomplete
Total	576134620	576051877	0	0
T1	2048	1980	0	0
T2	11842	11786	0	0
T3	380270	380176	0	0
T7	55033	54955	0	0
T8	152980	152899	0	0
T9	68355	68305	0	0
T10	1520	1449	0	0
T11	19483	19404	0	0
T12	566282	566207	0	0
T16	950	860	0	0

IntrUploadCmdfifoNotEmptyOKnown

Name	Attempts	Real Successes	Failures	Incomplete
Total	576134620	576051877	0	0
T1	2048	1980	0	0
T2	11842	11786	0	0
T3	380270	380176	0	0
T7	55033	54955	0	0
T8	152980	152899	0	0
T9	68355	68305	0	0
T10	1520	1449	0	0
T11	19483	19404	0	0
T12	566282	566207	0	0
T16	950	860	0	0

IntrUploadPayloadNotEmptyOKnown

Name	Attempts	Real Successes	Failures	Incomplete
Total	576134620	576051877	0	0
T1	2048	1980	0	0
T2	11842	11786	0	0
T3	380270	380176	0	0
T7	55033	54955	0	0
T8	152980	152899	0	0
T9	68355	68305	0	0
T10	1520	1449	0	0
T11	19483	19404	0	0
T12	566282	566207	0	0
T16	950	860	0	0

IntrUploadPayloadOverflowOKnown

Name	Attempts	Real Successes	Failures	Incomplete
Total	576134620	576051877	0	0
T1	2048	1980	0	0
T2	11842	11786	0	0
T3	380270	380176	0	0
T7	55033	54955	0	0
T8	152980	152899	0	0
T9	68355	68305	0	0
T10	1520	1449	0	0
T11	19483	19404	0	0
T12	566282	566207	0	0
T16	950	860	0	0

PayloadStartIdxWidthMatch_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	922	922	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T16	1	1	0	0

SpiModeKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	576134620	576051877	0	0
T1	2048	1980	0	0
T2	11842	11786	0	0
T3	380270	380176	0	0
T7	55033	54955	0	0
T8	152980	152899	0	0
T9	68355	68305	0	0
T10	1520	1449	0	0
T11	19483	19404	0	0
T12	566282	566207	0	0
T16	950	860	0	0

TpmEnableWhenTpmCsbIdle_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	576134620	340	0	0
T2	11842	1	0	0
T3	380270	1	0	0
T5	0	1	0	0
T7	55033	0	0	0
T8	152980	0	0	0
T9	68355	0	0	0
T10	1520	0	0	0
T11	19483	0	0	0
T12	566282	0	0	0
T16	950	0	0	0
T17	26571	1	0	0
T18	0	1	0	0
T19	0	1	0	0
T22	0	1	0	0
T23	0	1	0	0
T27	0	1	0	0
T41	0	1	0	0

TpmRdfifoNotFull_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	576134620	260962	0	0
T2	11842	76	0	0
T3	380270	702	0	0
T5	0	2108	0	0
T7	55033	0	0	0
T8	152980	0	0	0
T9	68355	0	0	0
T10	1520	0	0	0
T11	19483	0	0	0
T12	566282	0	0	0
T16	950	0	0	0
T17	26571	65	0	0
T19	0	39	0	0
T23	0	325	0	0
T27	0	2445	0	0
T28	0	1732	0	0
T29	0	4556	0	0
T31	0	1543	0	0

TpmWrPtrMatch_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	922	922	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T16	1	1	0	0

g_sram_connect[0].ReqAlwaysAccepted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	576134620	2210896	0	0
T4	314426	11648	0	0
T5	0	2496	0	0
T7	55033	832	0	0
T8	152980	832	0	0
T9	68355	832	0	0
T11	19483	832	0	0
T12	566282	832	0	0
T13	11131	832	0	0
T14	0	832	0	0
T15	0	832	0	0
T16	950	0	0	0
T17	26571	0	0	0
T18	66879	0	0	0

g_sram_connect[1].ReqAlwaysAccepted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	576134620	56689	0	0
T4	314426	641	0	0
T5	591984	64	0	0
T6	63231	0	0	0
T14	177435	0	0	0
T15	7937	0	0	0
T18	66879	0	0	0
T19	5782	0	0	0
T22	1292	0	0	0
T23	0	326	0	0
T24	0	100	0	0
T25	0	100	0	0
T27	0	129	0	0
T28	0	321	0	0
T29	0	544	0	0
T30	0	424	0	0
T31	0	175	0	0
T32	1270	0	0	0
T33	990	0	0	0

g_sram_connect[2].ReqAlwaysAccepted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	576134620	2439	0	0
T4	314426	29	0	0
T5	591984	1	0	0
T6	63231	2	0	0
T14	177435	0	0	0
T15	7937	0	0	0
T18	66879	0	0	0
T19	5782	0	0	0
T22	1292	0	0	0
T23	0	12	0	0
T27	0	5	0	0
T28	0	26	0	0
T29	0	24	0	0
T30	0	16	0	0
T31	0	5	0	0
T32	1270	0	0	0
T33	990	0	0	0
T42	0	2	0	0

g_sram_connect[3].ReqAlwaysAccepted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	576134620	1886	0	0
T4	314426	28	0	0
T5	591984	1	0	0
T6	63231	2	0	0
T14	177435	0	0	0
T15	7937	0	0	0
T18	66879	0	0	0
T19	5782	0	0	0
T22	1292	0	0	0
T23	0	5	0	0
T27	0	4	0	0
T28	0	20	0	0
T29	0	17	0	0
T30	0	11	0	0
T31	0	3	0	0
T32	1270	0	0	0
T33	990	0	0	0
T42	0	2	0	0

scanmodeKnown

Name	Attempts	Real Successes	Failures	Incomplete
Total	576134620	576134620	0	0
T1	2048	2048	0	0
T2	11842	11842	0	0
T3	380270	380270	0	0
T7	55033	55033	0	0
T8	152980	152980	0	0
T9	68355	68355	0	0
T10	1520	1520	0	0
T11	19483	19483	0	0
T12	566282	566282	0	0
T16	950	950	0	0