Assert Coverage for Module :
spi_device_csr_assert_fpv
Assertion Details
TlulOOBAddrErr_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
577947680 |
3148 |
0 |
0 |
T44 |
1606 |
2 |
0 |
0 |
T72 |
19625 |
4 |
0 |
0 |
T73 |
4928 |
5 |
0 |
0 |
T74 |
53512 |
1 |
0 |
0 |
T75 |
4755 |
152 |
0 |
0 |
T76 |
2120 |
4 |
0 |
0 |
T78 |
0 |
1 |
0 |
0 |
T92 |
0 |
2 |
0 |
0 |
T95 |
2971 |
0 |
0 |
0 |
T96 |
2702 |
0 |
0 |
0 |
T97 |
3512 |
0 |
0 |
0 |
T98 |
2047 |
0 |
0 |
0 |
T100 |
0 |
5 |
0 |
0 |
T129 |
0 |
1 |
0 |
0 |
addr_swap_data_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
577947680 |
1399 |
0 |
0 |
T73 |
4928 |
5 |
0 |
0 |
T78 |
26027 |
0 |
0 |
0 |
T95 |
2971 |
9 |
0 |
0 |
T96 |
2702 |
0 |
0 |
0 |
T97 |
3512 |
0 |
0 |
0 |
T98 |
2047 |
0 |
0 |
0 |
T99 |
7712 |
21 |
0 |
0 |
T103 |
1313 |
0 |
0 |
0 |
T129 |
0 |
11 |
0 |
0 |
T130 |
127473 |
784 |
0 |
0 |
T131 |
0 |
41 |
0 |
0 |
T132 |
0 |
51 |
0 |
0 |
T133 |
0 |
14 |
0 |
0 |
T134 |
0 |
2 |
0 |
0 |
T135 |
0 |
6 |
0 |
0 |
T136 |
1400 |
0 |
0 |
0 |
addr_swap_mask_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
577947680 |
1369 |
0 |
0 |
T73 |
4928 |
10 |
0 |
0 |
T78 |
26027 |
0 |
0 |
0 |
T95 |
2971 |
6 |
0 |
0 |
T96 |
2702 |
0 |
0 |
0 |
T97 |
3512 |
7 |
0 |
0 |
T98 |
2047 |
0 |
0 |
0 |
T99 |
7712 |
24 |
0 |
0 |
T103 |
1313 |
0 |
0 |
0 |
T129 |
0 |
7 |
0 |
0 |
T130 |
127473 |
804 |
0 |
0 |
T131 |
0 |
64 |
0 |
0 |
T132 |
0 |
48 |
0 |
0 |
T133 |
0 |
12 |
0 |
0 |
T134 |
0 |
1 |
0 |
0 |
T136 |
1400 |
0 |
0 |
0 |
cmd_filter_0_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
577947680 |
5912 |
0 |
0 |
T73 |
4928 |
5 |
0 |
0 |
T78 |
26027 |
0 |
0 |
0 |
T95 |
2971 |
17 |
0 |
0 |
T96 |
2702 |
0 |
0 |
0 |
T97 |
3512 |
136 |
0 |
0 |
T98 |
2047 |
0 |
0 |
0 |
T99 |
7712 |
0 |
0 |
0 |
T103 |
1313 |
0 |
0 |
0 |
T129 |
0 |
4 |
0 |
0 |
T130 |
127473 |
838 |
0 |
0 |
T131 |
0 |
66 |
0 |
0 |
T132 |
0 |
14 |
0 |
0 |
T133 |
0 |
15 |
0 |
0 |
T134 |
0 |
2 |
0 |
0 |
T135 |
0 |
1 |
0 |
0 |
T136 |
1400 |
0 |
0 |
0 |
cmd_filter_1_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
577947680 |
4287 |
0 |
0 |
T73 |
4928 |
1 |
0 |
0 |
T78 |
26027 |
0 |
0 |
0 |
T95 |
2971 |
6 |
0 |
0 |
T96 |
2702 |
0 |
0 |
0 |
T97 |
3512 |
115 |
0 |
0 |
T98 |
2047 |
0 |
0 |
0 |
T99 |
7712 |
4 |
0 |
0 |
T103 |
1313 |
0 |
0 |
0 |
T129 |
0 |
6 |
0 |
0 |
T130 |
127473 |
781 |
0 |
0 |
T131 |
0 |
83 |
0 |
0 |
T132 |
0 |
90 |
0 |
0 |
T133 |
0 |
7 |
0 |
0 |
T134 |
0 |
5 |
0 |
0 |
T136 |
1400 |
0 |
0 |
0 |
cmd_filter_2_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
577947680 |
5488 |
0 |
0 |
T73 |
4928 |
4 |
0 |
0 |
T78 |
26027 |
0 |
0 |
0 |
T95 |
2971 |
10 |
0 |
0 |
T96 |
2702 |
0 |
0 |
0 |
T97 |
3512 |
3 |
0 |
0 |
T98 |
2047 |
0 |
0 |
0 |
T99 |
7712 |
28 |
0 |
0 |
T103 |
1313 |
0 |
0 |
0 |
T129 |
0 |
10 |
0 |
0 |
T130 |
127473 |
776 |
0 |
0 |
T131 |
0 |
75 |
0 |
0 |
T132 |
0 |
29 |
0 |
0 |
T133 |
0 |
12 |
0 |
0 |
T134 |
0 |
2 |
0 |
0 |
T136 |
1400 |
0 |
0 |
0 |
cmd_filter_3_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
577947680 |
5192 |
0 |
0 |
T73 |
4928 |
5 |
0 |
0 |
T78 |
26027 |
0 |
0 |
0 |
T95 |
2971 |
4 |
0 |
0 |
T96 |
2702 |
0 |
0 |
0 |
T97 |
3512 |
122 |
0 |
0 |
T98 |
2047 |
0 |
0 |
0 |
T99 |
7712 |
10 |
0 |
0 |
T103 |
1313 |
0 |
0 |
0 |
T129 |
0 |
13 |
0 |
0 |
T130 |
127473 |
777 |
0 |
0 |
T131 |
0 |
59 |
0 |
0 |
T132 |
0 |
30 |
0 |
0 |
T133 |
0 |
8 |
0 |
0 |
T134 |
0 |
2 |
0 |
0 |
T136 |
1400 |
0 |
0 |
0 |
cmd_filter_4_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
577947680 |
4873 |
0 |
0 |
T73 |
4928 |
11 |
0 |
0 |
T78 |
26027 |
0 |
0 |
0 |
T95 |
2971 |
6 |
0 |
0 |
T96 |
2702 |
0 |
0 |
0 |
T97 |
3512 |
0 |
0 |
0 |
T98 |
2047 |
0 |
0 |
0 |
T99 |
7712 |
26 |
0 |
0 |
T103 |
1313 |
0 |
0 |
0 |
T129 |
0 |
8 |
0 |
0 |
T130 |
127473 |
823 |
0 |
0 |
T131 |
0 |
34 |
0 |
0 |
T132 |
0 |
61 |
0 |
0 |
T133 |
0 |
5 |
0 |
0 |
T134 |
0 |
3 |
0 |
0 |
T135 |
0 |
13 |
0 |
0 |
T136 |
1400 |
0 |
0 |
0 |
cmd_filter_5_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
577947680 |
5226 |
0 |
0 |
T73 |
4928 |
5 |
0 |
0 |
T78 |
26027 |
0 |
0 |
0 |
T95 |
2971 |
3 |
0 |
0 |
T96 |
2702 |
0 |
0 |
0 |
T97 |
3512 |
127 |
0 |
0 |
T98 |
2047 |
0 |
0 |
0 |
T99 |
7712 |
22 |
0 |
0 |
T103 |
1313 |
0 |
0 |
0 |
T129 |
0 |
14 |
0 |
0 |
T130 |
127473 |
773 |
0 |
0 |
T131 |
0 |
89 |
0 |
0 |
T132 |
0 |
41 |
0 |
0 |
T133 |
0 |
8 |
0 |
0 |
T134 |
0 |
4 |
0 |
0 |
T136 |
1400 |
0 |
0 |
0 |
cmd_filter_6_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
577947680 |
5601 |
0 |
0 |
T73 |
4928 |
1 |
0 |
0 |
T78 |
26027 |
0 |
0 |
0 |
T95 |
2971 |
10 |
0 |
0 |
T96 |
2702 |
0 |
0 |
0 |
T97 |
3512 |
2 |
0 |
0 |
T98 |
2047 |
0 |
0 |
0 |
T99 |
7712 |
26 |
0 |
0 |
T103 |
1313 |
0 |
0 |
0 |
T129 |
0 |
9 |
0 |
0 |
T130 |
127473 |
787 |
0 |
0 |
T131 |
0 |
86 |
0 |
0 |
T132 |
0 |
41 |
0 |
0 |
T133 |
0 |
24 |
0 |
0 |
T135 |
0 |
2 |
0 |
0 |
T136 |
1400 |
0 |
0 |
0 |
cmd_filter_7_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
577947680 |
4535 |
0 |
0 |
T73 |
4928 |
2 |
0 |
0 |
T78 |
26027 |
0 |
0 |
0 |
T95 |
2971 |
4 |
0 |
0 |
T96 |
2702 |
0 |
0 |
0 |
T97 |
3512 |
2 |
0 |
0 |
T98 |
2047 |
0 |
0 |
0 |
T99 |
7712 |
1 |
0 |
0 |
T103 |
1313 |
0 |
0 |
0 |
T130 |
127473 |
825 |
0 |
0 |
T131 |
0 |
29 |
0 |
0 |
T132 |
0 |
35 |
0 |
0 |
T133 |
0 |
18 |
0 |
0 |
T134 |
0 |
5 |
0 |
0 |
T135 |
0 |
3 |
0 |
0 |
T136 |
1400 |
0 |
0 |
0 |
cmd_info_0_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
577947680 |
2658 |
0 |
0 |
T73 |
4928 |
7 |
0 |
0 |
T78 |
26027 |
0 |
0 |
0 |
T95 |
2971 |
10 |
0 |
0 |
T96 |
2702 |
0 |
0 |
0 |
T97 |
3512 |
2 |
0 |
0 |
T98 |
2047 |
0 |
0 |
0 |
T99 |
7712 |
20 |
0 |
0 |
T103 |
1313 |
0 |
0 |
0 |
T129 |
0 |
8 |
0 |
0 |
T130 |
127473 |
749 |
0 |
0 |
T131 |
0 |
58 |
0 |
0 |
T132 |
0 |
59 |
0 |
0 |
T133 |
0 |
11 |
0 |
0 |
T134 |
0 |
8 |
0 |
0 |
T136 |
1400 |
0 |
0 |
0 |
cmd_info_10_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
577947680 |
2668 |
0 |
0 |
T78 |
26027 |
0 |
0 |
0 |
T95 |
2971 |
8 |
0 |
0 |
T96 |
2702 |
0 |
0 |
0 |
T97 |
3512 |
5 |
0 |
0 |
T98 |
2047 |
0 |
0 |
0 |
T99 |
7712 |
17 |
0 |
0 |
T103 |
1313 |
0 |
0 |
0 |
T129 |
0 |
7 |
0 |
0 |
T130 |
127473 |
819 |
0 |
0 |
T131 |
0 |
70 |
0 |
0 |
T132 |
0 |
71 |
0 |
0 |
T133 |
0 |
10 |
0 |
0 |
T134 |
0 |
5 |
0 |
0 |
T136 |
1400 |
0 |
0 |
0 |
T137 |
0 |
51 |
0 |
0 |
T138 |
5690 |
0 |
0 |
0 |
cmd_info_11_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
577947680 |
2601 |
0 |
0 |
T73 |
4928 |
8 |
0 |
0 |
T78 |
26027 |
0 |
0 |
0 |
T95 |
2971 |
3 |
0 |
0 |
T96 |
2702 |
0 |
0 |
0 |
T97 |
3512 |
2 |
0 |
0 |
T98 |
2047 |
0 |
0 |
0 |
T99 |
7712 |
3 |
0 |
0 |
T103 |
1313 |
0 |
0 |
0 |
T129 |
0 |
4 |
0 |
0 |
T130 |
127473 |
820 |
0 |
0 |
T131 |
0 |
70 |
0 |
0 |
T132 |
0 |
37 |
0 |
0 |
T133 |
0 |
10 |
0 |
0 |
T134 |
0 |
5 |
0 |
0 |
T136 |
1400 |
0 |
0 |
0 |
cmd_info_12_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
577947680 |
2844 |
0 |
0 |
T78 |
26027 |
0 |
0 |
0 |
T95 |
2971 |
5 |
0 |
0 |
T96 |
2702 |
0 |
0 |
0 |
T97 |
3512 |
3 |
0 |
0 |
T98 |
2047 |
0 |
0 |
0 |
T99 |
7712 |
57 |
0 |
0 |
T103 |
1313 |
0 |
0 |
0 |
T129 |
0 |
13 |
0 |
0 |
T130 |
127473 |
809 |
0 |
0 |
T131 |
0 |
74 |
0 |
0 |
T132 |
0 |
58 |
0 |
0 |
T133 |
0 |
9 |
0 |
0 |
T134 |
0 |
4 |
0 |
0 |
T135 |
0 |
21 |
0 |
0 |
T136 |
1400 |
0 |
0 |
0 |
T138 |
5690 |
0 |
0 |
0 |
cmd_info_13_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
577947680 |
2788 |
0 |
0 |
T73 |
4928 |
1 |
0 |
0 |
T78 |
26027 |
0 |
0 |
0 |
T95 |
2971 |
2 |
0 |
0 |
T96 |
2702 |
0 |
0 |
0 |
T97 |
3512 |
4 |
0 |
0 |
T98 |
2047 |
0 |
0 |
0 |
T99 |
7712 |
15 |
0 |
0 |
T103 |
1313 |
0 |
0 |
0 |
T129 |
0 |
10 |
0 |
0 |
T130 |
127473 |
710 |
0 |
0 |
T131 |
0 |
44 |
0 |
0 |
T132 |
0 |
74 |
0 |
0 |
T133 |
0 |
14 |
0 |
0 |
T134 |
0 |
3 |
0 |
0 |
T136 |
1400 |
0 |
0 |
0 |
cmd_info_14_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
577947680 |
2601 |
0 |
0 |
T73 |
4928 |
5 |
0 |
0 |
T78 |
26027 |
0 |
0 |
0 |
T95 |
2971 |
7 |
0 |
0 |
T96 |
2702 |
0 |
0 |
0 |
T97 |
3512 |
21 |
0 |
0 |
T98 |
2047 |
0 |
0 |
0 |
T99 |
7712 |
60 |
0 |
0 |
T103 |
1313 |
0 |
0 |
0 |
T129 |
0 |
7 |
0 |
0 |
T130 |
127473 |
751 |
0 |
0 |
T131 |
0 |
86 |
0 |
0 |
T132 |
0 |
26 |
0 |
0 |
T133 |
0 |
9 |
0 |
0 |
T134 |
0 |
3 |
0 |
0 |
T136 |
1400 |
0 |
0 |
0 |
cmd_info_15_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
577947680 |
2850 |
0 |
0 |
T73 |
4928 |
1 |
0 |
0 |
T78 |
26027 |
0 |
0 |
0 |
T95 |
2971 |
10 |
0 |
0 |
T96 |
2702 |
0 |
0 |
0 |
T97 |
3512 |
47 |
0 |
0 |
T98 |
2047 |
0 |
0 |
0 |
T99 |
7712 |
12 |
0 |
0 |
T103 |
1313 |
0 |
0 |
0 |
T129 |
0 |
6 |
0 |
0 |
T130 |
127473 |
821 |
0 |
0 |
T131 |
0 |
108 |
0 |
0 |
T132 |
0 |
35 |
0 |
0 |
T133 |
0 |
13 |
0 |
0 |
T134 |
0 |
5 |
0 |
0 |
T136 |
1400 |
0 |
0 |
0 |
cmd_info_16_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
577947680 |
2473 |
0 |
0 |
T73 |
4928 |
3 |
0 |
0 |
T78 |
26027 |
0 |
0 |
0 |
T95 |
2971 |
4 |
0 |
0 |
T96 |
2702 |
0 |
0 |
0 |
T97 |
3512 |
1 |
0 |
0 |
T98 |
2047 |
0 |
0 |
0 |
T99 |
7712 |
35 |
0 |
0 |
T103 |
1313 |
0 |
0 |
0 |
T129 |
0 |
8 |
0 |
0 |
T130 |
127473 |
809 |
0 |
0 |
T131 |
0 |
58 |
0 |
0 |
T132 |
0 |
12 |
0 |
0 |
T133 |
0 |
11 |
0 |
0 |
T134 |
0 |
7 |
0 |
0 |
T136 |
1400 |
0 |
0 |
0 |
cmd_info_17_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
577947680 |
2942 |
0 |
0 |
T73 |
4928 |
9 |
0 |
0 |
T78 |
26027 |
0 |
0 |
0 |
T95 |
2971 |
6 |
0 |
0 |
T96 |
2702 |
0 |
0 |
0 |
T97 |
3512 |
5 |
0 |
0 |
T98 |
2047 |
0 |
0 |
0 |
T99 |
7712 |
21 |
0 |
0 |
T103 |
1313 |
0 |
0 |
0 |
T129 |
0 |
8 |
0 |
0 |
T130 |
127473 |
824 |
0 |
0 |
T131 |
0 |
44 |
0 |
0 |
T132 |
0 |
63 |
0 |
0 |
T133 |
0 |
19 |
0 |
0 |
T134 |
0 |
7 |
0 |
0 |
T136 |
1400 |
0 |
0 |
0 |
cmd_info_18_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
577947680 |
2847 |
0 |
0 |
T78 |
26027 |
0 |
0 |
0 |
T95 |
2971 |
11 |
0 |
0 |
T96 |
2702 |
0 |
0 |
0 |
T97 |
3512 |
31 |
0 |
0 |
T98 |
2047 |
0 |
0 |
0 |
T99 |
7712 |
17 |
0 |
0 |
T103 |
1313 |
0 |
0 |
0 |
T129 |
0 |
7 |
0 |
0 |
T130 |
127473 |
784 |
0 |
0 |
T131 |
0 |
40 |
0 |
0 |
T132 |
0 |
78 |
0 |
0 |
T133 |
0 |
9 |
0 |
0 |
T134 |
0 |
6 |
0 |
0 |
T135 |
0 |
5 |
0 |
0 |
T136 |
1400 |
0 |
0 |
0 |
T138 |
5690 |
0 |
0 |
0 |
cmd_info_19_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
577947680 |
2686 |
0 |
0 |
T78 |
26027 |
0 |
0 |
0 |
T95 |
2971 |
9 |
0 |
0 |
T96 |
2702 |
0 |
0 |
0 |
T97 |
3512 |
52 |
0 |
0 |
T98 |
2047 |
0 |
0 |
0 |
T99 |
7712 |
50 |
0 |
0 |
T103 |
1313 |
0 |
0 |
0 |
T129 |
0 |
7 |
0 |
0 |
T130 |
127473 |
751 |
0 |
0 |
T131 |
0 |
121 |
0 |
0 |
T132 |
0 |
34 |
0 |
0 |
T133 |
0 |
13 |
0 |
0 |
T135 |
0 |
14 |
0 |
0 |
T136 |
1400 |
0 |
0 |
0 |
T137 |
0 |
33 |
0 |
0 |
T138 |
5690 |
0 |
0 |
0 |
cmd_info_1_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
577947680 |
2725 |
0 |
0 |
T73 |
4928 |
6 |
0 |
0 |
T78 |
26027 |
0 |
0 |
0 |
T95 |
2971 |
8 |
0 |
0 |
T96 |
2702 |
0 |
0 |
0 |
T97 |
3512 |
43 |
0 |
0 |
T98 |
2047 |
0 |
0 |
0 |
T99 |
7712 |
28 |
0 |
0 |
T103 |
1313 |
0 |
0 |
0 |
T129 |
0 |
7 |
0 |
0 |
T130 |
127473 |
834 |
0 |
0 |
T131 |
0 |
39 |
0 |
0 |
T132 |
0 |
54 |
0 |
0 |
T133 |
0 |
10 |
0 |
0 |
T134 |
0 |
7 |
0 |
0 |
T136 |
1400 |
0 |
0 |
0 |
cmd_info_20_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
577947680 |
2405 |
0 |
0 |
T73 |
4928 |
9 |
0 |
0 |
T78 |
26027 |
0 |
0 |
0 |
T95 |
2971 |
4 |
0 |
0 |
T96 |
2702 |
0 |
0 |
0 |
T97 |
3512 |
32 |
0 |
0 |
T98 |
2047 |
0 |
0 |
0 |
T99 |
7712 |
30 |
0 |
0 |
T103 |
1313 |
0 |
0 |
0 |
T129 |
0 |
14 |
0 |
0 |
T130 |
127473 |
805 |
0 |
0 |
T131 |
0 |
29 |
0 |
0 |
T132 |
0 |
62 |
0 |
0 |
T133 |
0 |
17 |
0 |
0 |
T134 |
0 |
2 |
0 |
0 |
T136 |
1400 |
0 |
0 |
0 |
cmd_info_21_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
577947680 |
2736 |
0 |
0 |
T73 |
4928 |
9 |
0 |
0 |
T78 |
26027 |
0 |
0 |
0 |
T95 |
2971 |
11 |
0 |
0 |
T96 |
2702 |
0 |
0 |
0 |
T97 |
3512 |
1 |
0 |
0 |
T98 |
2047 |
0 |
0 |
0 |
T99 |
7712 |
6 |
0 |
0 |
T103 |
1313 |
0 |
0 |
0 |
T129 |
0 |
5 |
0 |
0 |
T130 |
127473 |
815 |
0 |
0 |
T131 |
0 |
58 |
0 |
0 |
T132 |
0 |
47 |
0 |
0 |
T133 |
0 |
20 |
0 |
0 |
T134 |
0 |
2 |
0 |
0 |
T136 |
1400 |
0 |
0 |
0 |
cmd_info_22_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
577947680 |
2610 |
0 |
0 |
T73 |
4928 |
6 |
0 |
0 |
T78 |
26027 |
0 |
0 |
0 |
T95 |
2971 |
9 |
0 |
0 |
T96 |
2702 |
0 |
0 |
0 |
T97 |
3512 |
55 |
0 |
0 |
T98 |
2047 |
0 |
0 |
0 |
T99 |
7712 |
13 |
0 |
0 |
T103 |
1313 |
0 |
0 |
0 |
T129 |
0 |
1 |
0 |
0 |
T130 |
127473 |
776 |
0 |
0 |
T131 |
0 |
90 |
0 |
0 |
T132 |
0 |
29 |
0 |
0 |
T133 |
0 |
13 |
0 |
0 |
T134 |
0 |
6 |
0 |
0 |
T136 |
1400 |
0 |
0 |
0 |
cmd_info_23_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
577947680 |
3111 |
0 |
0 |
T73 |
4928 |
30 |
0 |
0 |
T78 |
26027 |
0 |
0 |
0 |
T95 |
2971 |
10 |
0 |
0 |
T96 |
2702 |
0 |
0 |
0 |
T97 |
3512 |
49 |
0 |
0 |
T98 |
2047 |
0 |
0 |
0 |
T99 |
7712 |
28 |
0 |
0 |
T103 |
1313 |
0 |
0 |
0 |
T129 |
0 |
15 |
0 |
0 |
T130 |
127473 |
836 |
0 |
0 |
T131 |
0 |
69 |
0 |
0 |
T132 |
0 |
22 |
0 |
0 |
T133 |
0 |
8 |
0 |
0 |
T134 |
0 |
5 |
0 |
0 |
T136 |
1400 |
0 |
0 |
0 |
cmd_info_2_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
577947680 |
2730 |
0 |
0 |
T73 |
4928 |
9 |
0 |
0 |
T78 |
26027 |
0 |
0 |
0 |
T95 |
2971 |
3 |
0 |
0 |
T96 |
2702 |
0 |
0 |
0 |
T97 |
3512 |
3 |
0 |
0 |
T98 |
2047 |
0 |
0 |
0 |
T99 |
7712 |
16 |
0 |
0 |
T103 |
1313 |
0 |
0 |
0 |
T129 |
0 |
13 |
0 |
0 |
T130 |
127473 |
783 |
0 |
0 |
T131 |
0 |
84 |
0 |
0 |
T132 |
0 |
60 |
0 |
0 |
T133 |
0 |
13 |
0 |
0 |
T134 |
0 |
4 |
0 |
0 |
T136 |
1400 |
0 |
0 |
0 |
cmd_info_3_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
577947680 |
2724 |
0 |
0 |
T73 |
4928 |
18 |
0 |
0 |
T78 |
26027 |
0 |
0 |
0 |
T95 |
2971 |
2 |
0 |
0 |
T96 |
2702 |
0 |
0 |
0 |
T97 |
3512 |
4 |
0 |
0 |
T98 |
2047 |
0 |
0 |
0 |
T99 |
7712 |
61 |
0 |
0 |
T103 |
1313 |
0 |
0 |
0 |
T129 |
0 |
10 |
0 |
0 |
T130 |
127473 |
872 |
0 |
0 |
T131 |
0 |
36 |
0 |
0 |
T132 |
0 |
27 |
0 |
0 |
T133 |
0 |
18 |
0 |
0 |
T134 |
0 |
5 |
0 |
0 |
T136 |
1400 |
0 |
0 |
0 |
cmd_info_4_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
577947680 |
2580 |
0 |
0 |
T73 |
4928 |
10 |
0 |
0 |
T78 |
26027 |
0 |
0 |
0 |
T95 |
2971 |
13 |
0 |
0 |
T96 |
2702 |
0 |
0 |
0 |
T97 |
3512 |
42 |
0 |
0 |
T98 |
2047 |
0 |
0 |
0 |
T99 |
7712 |
14 |
0 |
0 |
T103 |
1313 |
0 |
0 |
0 |
T129 |
0 |
6 |
0 |
0 |
T130 |
127473 |
778 |
0 |
0 |
T131 |
0 |
59 |
0 |
0 |
T132 |
0 |
36 |
0 |
0 |
T133 |
0 |
12 |
0 |
0 |
T134 |
0 |
4 |
0 |
0 |
T136 |
1400 |
0 |
0 |
0 |
cmd_info_5_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
577947680 |
3073 |
0 |
0 |
T73 |
4928 |
18 |
0 |
0 |
T78 |
26027 |
0 |
0 |
0 |
T95 |
2971 |
8 |
0 |
0 |
T96 |
2702 |
0 |
0 |
0 |
T97 |
3512 |
39 |
0 |
0 |
T98 |
2047 |
0 |
0 |
0 |
T99 |
7712 |
31 |
0 |
0 |
T103 |
1313 |
0 |
0 |
0 |
T129 |
0 |
14 |
0 |
0 |
T130 |
127473 |
879 |
0 |
0 |
T131 |
0 |
20 |
0 |
0 |
T132 |
0 |
69 |
0 |
0 |
T133 |
0 |
15 |
0 |
0 |
T134 |
0 |
1 |
0 |
0 |
T136 |
1400 |
0 |
0 |
0 |
cmd_info_6_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
577947680 |
2591 |
0 |
0 |
T73 |
4928 |
1 |
0 |
0 |
T78 |
26027 |
0 |
0 |
0 |
T95 |
2971 |
12 |
0 |
0 |
T96 |
2702 |
0 |
0 |
0 |
T97 |
3512 |
5 |
0 |
0 |
T98 |
2047 |
0 |
0 |
0 |
T99 |
7712 |
18 |
0 |
0 |
T103 |
1313 |
0 |
0 |
0 |
T129 |
0 |
9 |
0 |
0 |
T130 |
127473 |
791 |
0 |
0 |
T131 |
0 |
75 |
0 |
0 |
T132 |
0 |
63 |
0 |
0 |
T133 |
0 |
4 |
0 |
0 |
T135 |
0 |
9 |
0 |
0 |
T136 |
1400 |
0 |
0 |
0 |
cmd_info_7_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
577947680 |
2683 |
0 |
0 |
T73 |
4928 |
11 |
0 |
0 |
T78 |
26027 |
0 |
0 |
0 |
T95 |
2971 |
10 |
0 |
0 |
T96 |
2702 |
0 |
0 |
0 |
T97 |
3512 |
7 |
0 |
0 |
T98 |
2047 |
0 |
0 |
0 |
T99 |
7712 |
33 |
0 |
0 |
T103 |
1313 |
0 |
0 |
0 |
T129 |
0 |
7 |
0 |
0 |
T130 |
127473 |
805 |
0 |
0 |
T131 |
0 |
26 |
0 |
0 |
T132 |
0 |
53 |
0 |
0 |
T133 |
0 |
1 |
0 |
0 |
T134 |
0 |
4 |
0 |
0 |
T136 |
1400 |
0 |
0 |
0 |
cmd_info_8_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
577947680 |
2781 |
0 |
0 |
T73 |
4928 |
6 |
0 |
0 |
T78 |
26027 |
0 |
0 |
0 |
T95 |
2971 |
1 |
0 |
0 |
T96 |
2702 |
0 |
0 |
0 |
T97 |
3512 |
4 |
0 |
0 |
T98 |
2047 |
0 |
0 |
0 |
T99 |
7712 |
13 |
0 |
0 |
T103 |
1313 |
0 |
0 |
0 |
T129 |
0 |
4 |
0 |
0 |
T130 |
127473 |
864 |
0 |
0 |
T131 |
0 |
62 |
0 |
0 |
T132 |
0 |
39 |
0 |
0 |
T133 |
0 |
7 |
0 |
0 |
T134 |
0 |
2 |
0 |
0 |
T136 |
1400 |
0 |
0 |
0 |
cmd_info_9_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
577947680 |
2616 |
0 |
0 |
T73 |
4928 |
2 |
0 |
0 |
T78 |
26027 |
0 |
0 |
0 |
T95 |
2971 |
11 |
0 |
0 |
T96 |
2702 |
0 |
0 |
0 |
T97 |
3512 |
2 |
0 |
0 |
T98 |
2047 |
0 |
0 |
0 |
T99 |
7712 |
11 |
0 |
0 |
T103 |
1313 |
0 |
0 |
0 |
T129 |
0 |
11 |
0 |
0 |
T130 |
127473 |
850 |
0 |
0 |
T131 |
0 |
46 |
0 |
0 |
T132 |
0 |
36 |
0 |
0 |
T133 |
0 |
6 |
0 |
0 |
T135 |
0 |
6 |
0 |
0 |
T136 |
1400 |
0 |
0 |
0 |
cmd_info_en4b_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
577947680 |
1508 |
0 |
0 |
T73 |
4928 |
4 |
0 |
0 |
T78 |
26027 |
0 |
0 |
0 |
T95 |
2971 |
9 |
0 |
0 |
T96 |
2702 |
0 |
0 |
0 |
T97 |
3512 |
3 |
0 |
0 |
T98 |
2047 |
0 |
0 |
0 |
T99 |
7712 |
27 |
0 |
0 |
T103 |
1313 |
0 |
0 |
0 |
T129 |
0 |
12 |
0 |
0 |
T130 |
127473 |
816 |
0 |
0 |
T131 |
0 |
61 |
0 |
0 |
T132 |
0 |
18 |
0 |
0 |
T133 |
0 |
3 |
0 |
0 |
T134 |
0 |
1 |
0 |
0 |
T136 |
1400 |
0 |
0 |
0 |
cmd_info_ex4b_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
577947680 |
1538 |
0 |
0 |
T73 |
4928 |
9 |
0 |
0 |
T78 |
26027 |
0 |
0 |
0 |
T95 |
2971 |
12 |
0 |
0 |
T96 |
2702 |
0 |
0 |
0 |
T97 |
3512 |
8 |
0 |
0 |
T98 |
2047 |
0 |
0 |
0 |
T99 |
7712 |
10 |
0 |
0 |
T103 |
1313 |
0 |
0 |
0 |
T129 |
0 |
8 |
0 |
0 |
T130 |
127473 |
773 |
0 |
0 |
T131 |
0 |
55 |
0 |
0 |
T132 |
0 |
22 |
0 |
0 |
T133 |
0 |
12 |
0 |
0 |
T134 |
0 |
4 |
0 |
0 |
T136 |
1400 |
0 |
0 |
0 |
cmd_info_wrdi_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
577947680 |
1441 |
0 |
0 |
T73 |
4928 |
7 |
0 |
0 |
T78 |
26027 |
0 |
0 |
0 |
T95 |
2971 |
6 |
0 |
0 |
T96 |
2702 |
0 |
0 |
0 |
T97 |
3512 |
3 |
0 |
0 |
T98 |
2047 |
0 |
0 |
0 |
T99 |
7712 |
17 |
0 |
0 |
T103 |
1313 |
0 |
0 |
0 |
T129 |
0 |
6 |
0 |
0 |
T130 |
127473 |
771 |
0 |
0 |
T131 |
0 |
23 |
0 |
0 |
T132 |
0 |
19 |
0 |
0 |
T133 |
0 |
10 |
0 |
0 |
T134 |
0 |
7 |
0 |
0 |
T136 |
1400 |
0 |
0 |
0 |
cmd_info_wren_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
577947680 |
1571 |
0 |
0 |
T73 |
4928 |
3 |
0 |
0 |
T78 |
26027 |
0 |
0 |
0 |
T95 |
2971 |
6 |
0 |
0 |
T96 |
2702 |
0 |
0 |
0 |
T97 |
3512 |
5 |
0 |
0 |
T98 |
2047 |
0 |
0 |
0 |
T99 |
7712 |
43 |
0 |
0 |
T103 |
1313 |
0 |
0 |
0 |
T129 |
0 |
13 |
0 |
0 |
T130 |
127473 |
818 |
0 |
0 |
T131 |
0 |
32 |
0 |
0 |
T132 |
0 |
62 |
0 |
0 |
T133 |
0 |
13 |
0 |
0 |
T134 |
0 |
3 |
0 |
0 |
T136 |
1400 |
0 |
0 |
0 |
control_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
577947680 |
1273 |
0 |
0 |
T73 |
4928 |
23 |
0 |
0 |
T78 |
26027 |
0 |
0 |
0 |
T95 |
2971 |
1 |
0 |
0 |
T96 |
2702 |
0 |
0 |
0 |
T97 |
3512 |
3 |
0 |
0 |
T98 |
2047 |
0 |
0 |
0 |
T99 |
7712 |
12 |
0 |
0 |
T103 |
1313 |
0 |
0 |
0 |
T129 |
0 |
4 |
0 |
0 |
T130 |
127473 |
760 |
0 |
0 |
T131 |
0 |
67 |
0 |
0 |
T132 |
0 |
26 |
0 |
0 |
T133 |
0 |
6 |
0 |
0 |
T134 |
0 |
3 |
0 |
0 |
T136 |
1400 |
0 |
0 |
0 |
intercept_en_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
577947680 |
1773 |
0 |
0 |
T73 |
4928 |
6 |
0 |
0 |
T78 |
26027 |
0 |
0 |
0 |
T95 |
2971 |
3 |
0 |
0 |
T96 |
2702 |
0 |
0 |
0 |
T97 |
3512 |
8 |
0 |
0 |
T98 |
2047 |
0 |
0 |
0 |
T99 |
7712 |
9 |
0 |
0 |
T103 |
1313 |
0 |
0 |
0 |
T129 |
0 |
14 |
0 |
0 |
T130 |
127473 |
833 |
0 |
0 |
T131 |
0 |
49 |
0 |
0 |
T132 |
0 |
27 |
0 |
0 |
T133 |
0 |
20 |
0 |
0 |
T134 |
0 |
6 |
0 |
0 |
T136 |
1400 |
0 |
0 |
0 |
intr_enable_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
577947680 |
2681 |
0 |
0 |
T5 |
591984 |
0 |
0 |
0 |
T6 |
63231 |
0 |
0 |
0 |
T20 |
5187 |
7 |
0 |
0 |
T21 |
1685 |
0 |
0 |
0 |
T23 |
191621 |
5 |
0 |
0 |
T27 |
430200 |
0 |
0 |
0 |
T28 |
845518 |
0 |
0 |
0 |
T34 |
19718 |
0 |
0 |
0 |
T36 |
0 |
10 |
0 |
0 |
T41 |
46814 |
0 |
0 |
0 |
T73 |
0 |
1 |
0 |
0 |
T95 |
0 |
6 |
0 |
0 |
T97 |
0 |
19 |
0 |
0 |
T119 |
1104 |
0 |
0 |
0 |
T130 |
0 |
758 |
0 |
0 |
T139 |
0 |
8 |
0 |
0 |
T140 |
0 |
27 |
0 |
0 |
T141 |
0 |
7 |
0 |
0 |
jedec_cc_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
577947680 |
1629 |
0 |
0 |
T73 |
4928 |
19 |
0 |
0 |
T78 |
26027 |
0 |
0 |
0 |
T95 |
2971 |
7 |
0 |
0 |
T96 |
2702 |
0 |
0 |
0 |
T97 |
3512 |
9 |
0 |
0 |
T98 |
2047 |
0 |
0 |
0 |
T99 |
7712 |
8 |
0 |
0 |
T103 |
1313 |
0 |
0 |
0 |
T129 |
0 |
7 |
0 |
0 |
T130 |
127473 |
771 |
0 |
0 |
T131 |
0 |
107 |
0 |
0 |
T132 |
0 |
38 |
0 |
0 |
T133 |
0 |
17 |
0 |
0 |
T134 |
0 |
9 |
0 |
0 |
T136 |
1400 |
0 |
0 |
0 |
jedec_id_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
577947680 |
1612 |
0 |
0 |
T73 |
4928 |
11 |
0 |
0 |
T78 |
26027 |
0 |
0 |
0 |
T95 |
2971 |
11 |
0 |
0 |
T96 |
2702 |
0 |
0 |
0 |
T97 |
3512 |
6 |
0 |
0 |
T98 |
2047 |
0 |
0 |
0 |
T99 |
7712 |
25 |
0 |
0 |
T103 |
1313 |
0 |
0 |
0 |
T129 |
0 |
6 |
0 |
0 |
T130 |
127473 |
830 |
0 |
0 |
T131 |
0 |
52 |
0 |
0 |
T132 |
0 |
67 |
0 |
0 |
T133 |
0 |
17 |
0 |
0 |
T136 |
1400 |
0 |
0 |
0 |
T137 |
0 |
10 |
0 |
0 |
mailbox_addr_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
577947680 |
1364 |
0 |
0 |
T73 |
4928 |
4 |
0 |
0 |
T78 |
26027 |
0 |
0 |
0 |
T95 |
2971 |
11 |
0 |
0 |
T96 |
2702 |
0 |
0 |
0 |
T97 |
3512 |
0 |
0 |
0 |
T98 |
2047 |
0 |
0 |
0 |
T99 |
7712 |
33 |
0 |
0 |
T103 |
1313 |
0 |
0 |
0 |
T129 |
0 |
14 |
0 |
0 |
T130 |
127473 |
770 |
0 |
0 |
T131 |
0 |
71 |
0 |
0 |
T132 |
0 |
21 |
0 |
0 |
T133 |
0 |
16 |
0 |
0 |
T134 |
0 |
6 |
0 |
0 |
T135 |
0 |
13 |
0 |
0 |
T136 |
1400 |
0 |
0 |
0 |
payload_swap_data_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
577947680 |
1391 |
0 |
0 |
T78 |
26027 |
0 |
0 |
0 |
T95 |
2971 |
11 |
0 |
0 |
T96 |
2702 |
0 |
0 |
0 |
T97 |
3512 |
3 |
0 |
0 |
T98 |
2047 |
0 |
0 |
0 |
T99 |
7712 |
5 |
0 |
0 |
T103 |
1313 |
0 |
0 |
0 |
T129 |
0 |
9 |
0 |
0 |
T130 |
127473 |
858 |
0 |
0 |
T131 |
0 |
33 |
0 |
0 |
T132 |
0 |
59 |
0 |
0 |
T133 |
0 |
3 |
0 |
0 |
T134 |
0 |
2 |
0 |
0 |
T135 |
0 |
4 |
0 |
0 |
T136 |
1400 |
0 |
0 |
0 |
T138 |
5690 |
0 |
0 |
0 |
payload_swap_mask_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
577947680 |
1498 |
0 |
0 |
T78 |
26027 |
0 |
0 |
0 |
T95 |
2971 |
1 |
0 |
0 |
T96 |
2702 |
0 |
0 |
0 |
T97 |
3512 |
1 |
0 |
0 |
T98 |
2047 |
0 |
0 |
0 |
T99 |
7712 |
26 |
0 |
0 |
T103 |
1313 |
0 |
0 |
0 |
T129 |
0 |
3 |
0 |
0 |
T130 |
127473 |
872 |
0 |
0 |
T131 |
0 |
67 |
0 |
0 |
T132 |
0 |
71 |
0 |
0 |
T133 |
0 |
10 |
0 |
0 |
T134 |
0 |
9 |
0 |
0 |
T135 |
0 |
7 |
0 |
0 |
T136 |
1400 |
0 |
0 |
0 |
T138 |
5690 |
0 |
0 |
0 |
read_threshold_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
577947680 |
1456 |
0 |
0 |
T73 |
4928 |
1 |
0 |
0 |
T78 |
26027 |
0 |
0 |
0 |
T95 |
2971 |
15 |
0 |
0 |
T96 |
2702 |
0 |
0 |
0 |
T97 |
3512 |
1 |
0 |
0 |
T98 |
2047 |
0 |
0 |
0 |
T99 |
7712 |
30 |
0 |
0 |
T103 |
1313 |
0 |
0 |
0 |
T129 |
0 |
14 |
0 |
0 |
T130 |
127473 |
766 |
0 |
0 |
T131 |
0 |
87 |
0 |
0 |
T132 |
0 |
25 |
0 |
0 |
T133 |
0 |
11 |
0 |
0 |
T134 |
0 |
8 |
0 |
0 |
T136 |
1400 |
0 |
0 |
0 |
tpm_access_0_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
577947680 |
1727 |
0 |
0 |
T73 |
4928 |
1 |
0 |
0 |
T78 |
26027 |
0 |
0 |
0 |
T95 |
2971 |
3 |
0 |
0 |
T96 |
2702 |
0 |
0 |
0 |
T97 |
3512 |
14 |
0 |
0 |
T98 |
2047 |
0 |
0 |
0 |
T99 |
7712 |
27 |
0 |
0 |
T103 |
1313 |
0 |
0 |
0 |
T129 |
0 |
15 |
0 |
0 |
T130 |
127473 |
796 |
0 |
0 |
T131 |
0 |
84 |
0 |
0 |
T132 |
0 |
35 |
0 |
0 |
T133 |
0 |
9 |
0 |
0 |
T134 |
0 |
5 |
0 |
0 |
T136 |
1400 |
0 |
0 |
0 |
tpm_access_1_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
577947680 |
1426 |
0 |
0 |
T73 |
4928 |
2 |
0 |
0 |
T78 |
26027 |
0 |
0 |
0 |
T95 |
2971 |
8 |
0 |
0 |
T96 |
2702 |
0 |
0 |
0 |
T97 |
3512 |
9 |
0 |
0 |
T98 |
2047 |
0 |
0 |
0 |
T99 |
7712 |
18 |
0 |
0 |
T103 |
1313 |
0 |
0 |
0 |
T129 |
0 |
6 |
0 |
0 |
T130 |
127473 |
838 |
0 |
0 |
T131 |
0 |
78 |
0 |
0 |
T132 |
0 |
12 |
0 |
0 |
T133 |
0 |
4 |
0 |
0 |
T134 |
0 |
4 |
0 |
0 |
T136 |
1400 |
0 |
0 |
0 |
tpm_cfg_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
577947680 |
1820 |
0 |
0 |
T73 |
4928 |
6 |
0 |
0 |
T78 |
26027 |
0 |
0 |
0 |
T95 |
2971 |
3 |
0 |
0 |
T96 |
2702 |
0 |
0 |
0 |
T97 |
3512 |
21 |
0 |
0 |
T98 |
2047 |
0 |
0 |
0 |
T99 |
7712 |
34 |
0 |
0 |
T103 |
1313 |
0 |
0 |
0 |
T129 |
0 |
3 |
0 |
0 |
T130 |
127473 |
743 |
0 |
0 |
T131 |
0 |
41 |
0 |
0 |
T132 |
0 |
40 |
0 |
0 |
T133 |
0 |
14 |
0 |
0 |
T134 |
0 |
4 |
0 |
0 |
T136 |
1400 |
0 |
0 |
0 |
tpm_did_vid_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
577947680 |
1511 |
0 |
0 |
T73 |
4928 |
8 |
0 |
0 |
T78 |
26027 |
0 |
0 |
0 |
T95 |
2971 |
1 |
0 |
0 |
T96 |
2702 |
0 |
0 |
0 |
T97 |
3512 |
2 |
0 |
0 |
T98 |
2047 |
0 |
0 |
0 |
T99 |
7712 |
25 |
0 |
0 |
T103 |
1313 |
0 |
0 |
0 |
T129 |
0 |
8 |
0 |
0 |
T130 |
127473 |
784 |
0 |
0 |
T131 |
0 |
89 |
0 |
0 |
T132 |
0 |
53 |
0 |
0 |
T133 |
0 |
4 |
0 |
0 |
T134 |
0 |
3 |
0 |
0 |
T136 |
1400 |
0 |
0 |
0 |
tpm_int_enable_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
577947680 |
1287 |
0 |
0 |
T73 |
4928 |
4 |
0 |
0 |
T78 |
26027 |
0 |
0 |
0 |
T95 |
2971 |
4 |
0 |
0 |
T96 |
2702 |
0 |
0 |
0 |
T97 |
3512 |
2 |
0 |
0 |
T98 |
2047 |
0 |
0 |
0 |
T99 |
7712 |
6 |
0 |
0 |
T103 |
1313 |
0 |
0 |
0 |
T129 |
0 |
9 |
0 |
0 |
T130 |
127473 |
798 |
0 |
0 |
T131 |
0 |
49 |
0 |
0 |
T132 |
0 |
47 |
0 |
0 |
T133 |
0 |
2 |
0 |
0 |
T134 |
0 |
6 |
0 |
0 |
T136 |
1400 |
0 |
0 |
0 |
tpm_int_status_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
577947680 |
1468 |
0 |
0 |
T73 |
4928 |
4 |
0 |
0 |
T78 |
26027 |
0 |
0 |
0 |
T95 |
2971 |
4 |
0 |
0 |
T96 |
2702 |
0 |
0 |
0 |
T97 |
3512 |
6 |
0 |
0 |
T98 |
2047 |
0 |
0 |
0 |
T99 |
7712 |
3 |
0 |
0 |
T103 |
1313 |
0 |
0 |
0 |
T129 |
0 |
4 |
0 |
0 |
T130 |
127473 |
803 |
0 |
0 |
T131 |
0 |
108 |
0 |
0 |
T132 |
0 |
43 |
0 |
0 |
T133 |
0 |
15 |
0 |
0 |
T134 |
0 |
10 |
0 |
0 |
T136 |
1400 |
0 |
0 |
0 |
tpm_int_vector_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
577947680 |
1339 |
0 |
0 |
T73 |
4928 |
5 |
0 |
0 |
T78 |
26027 |
0 |
0 |
0 |
T95 |
2971 |
9 |
0 |
0 |
T96 |
2702 |
0 |
0 |
0 |
T97 |
3512 |
0 |
0 |
0 |
T98 |
2047 |
0 |
0 |
0 |
T99 |
7712 |
19 |
0 |
0 |
T103 |
1313 |
0 |
0 |
0 |
T129 |
0 |
5 |
0 |
0 |
T130 |
127473 |
775 |
0 |
0 |
T131 |
0 |
45 |
0 |
0 |
T132 |
0 |
16 |
0 |
0 |
T133 |
0 |
1 |
0 |
0 |
T134 |
0 |
6 |
0 |
0 |
T135 |
0 |
1 |
0 |
0 |
T136 |
1400 |
0 |
0 |
0 |
tpm_intf_capability_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
577947680 |
1561 |
0 |
0 |
T73 |
4928 |
5 |
0 |
0 |
T78 |
26027 |
0 |
0 |
0 |
T95 |
2971 |
7 |
0 |
0 |
T96 |
2702 |
0 |
0 |
0 |
T97 |
3512 |
4 |
0 |
0 |
T98 |
2047 |
0 |
0 |
0 |
T99 |
7712 |
17 |
0 |
0 |
T103 |
1313 |
0 |
0 |
0 |
T129 |
0 |
18 |
0 |
0 |
T130 |
127473 |
955 |
0 |
0 |
T131 |
0 |
30 |
0 |
0 |
T132 |
0 |
70 |
0 |
0 |
T133 |
0 |
9 |
0 |
0 |
T134 |
0 |
4 |
0 |
0 |
T136 |
1400 |
0 |
0 |
0 |
tpm_rid_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
577947680 |
1331 |
0 |
0 |
T78 |
26027 |
0 |
0 |
0 |
T95 |
2971 |
5 |
0 |
0 |
T96 |
2702 |
0 |
0 |
0 |
T97 |
3512 |
5 |
0 |
0 |
T98 |
2047 |
0 |
0 |
0 |
T99 |
7712 |
33 |
0 |
0 |
T103 |
1313 |
0 |
0 |
0 |
T129 |
0 |
11 |
0 |
0 |
T130 |
127473 |
864 |
0 |
0 |
T131 |
0 |
9 |
0 |
0 |
T132 |
0 |
18 |
0 |
0 |
T133 |
0 |
1 |
0 |
0 |
T134 |
0 |
2 |
0 |
0 |
T136 |
1400 |
0 |
0 |
0 |
T137 |
0 |
33 |
0 |
0 |
T138 |
5690 |
0 |
0 |
0 |
tpm_sts_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
577947680 |
1532 |
0 |
0 |
T73 |
4928 |
13 |
0 |
0 |
T78 |
26027 |
0 |
0 |
0 |
T95 |
2971 |
10 |
0 |
0 |
T96 |
2702 |
0 |
0 |
0 |
T97 |
3512 |
0 |
0 |
0 |
T98 |
2047 |
0 |
0 |
0 |
T99 |
7712 |
42 |
0 |
0 |
T103 |
1313 |
0 |
0 |
0 |
T129 |
0 |
3 |
0 |
0 |
T130 |
127473 |
856 |
0 |
0 |
T131 |
0 |
47 |
0 |
0 |
T132 |
0 |
38 |
0 |
0 |
T133 |
0 |
7 |
0 |
0 |
T135 |
0 |
3 |
0 |
0 |
T136 |
1400 |
0 |
0 |
0 |
T137 |
0 |
65 |
0 |
0 |