Unified Coverage Report :: Module :: spid_addr_4b

Module : spid_addr_4b

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_spi_device_0.1/rtl/spid_addr_4b.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_spid_addr_4b	100.00	100.00	100.00			100.00

---

Module Instance : tb.dut.u_spid_addr_4b

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.71	95.79	89.19	96.92		91.18	95.45	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_spi2sys_sync	100.00	100.00				100.00
u_sys2spi_sync	100.00	100.00				100.00

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : spid_addr_4b

	Line No.	Total	Covered	Percent
TOTAL		28	28	100.00
ALWAYS	83	8	8	100.00
CONT_ASSIGN	108	1	1	100.00
CONT_ASSIGN	110	1	1	100.00
CONT_ASSIGN	111	1	1	100.00
ALWAYS	115	6	6	100.00
ALWAYS	128	3	3	100.00
ALWAYS	136	8	8	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_spi_device_0.1/rtl/spid_addr_4b.sv' or '../src/lowrisc_ip_spi_device_0.1/rtl/spid_addr_4b.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
83	1	1
84	1	1
85	1	1
86	1	1
89	1	1
90	1	1
93	1	1
94	1	1
108	1	1
110	1	1
111	1	1
115	1	1
116	1	1
117	1	1
118	1	1
119	1	1
120	1	1
			MISSING_ELSE
128	1	1
129	1	1
131	1	1
136	1	1
137	1	1
138	1	1
140	1	1
141	1	1
143	1	1
144	1	1
147	1	1
			MISSING_ELSE

---

Cond Coverage for Module : spid_addr_4b

	Total	Covered	Percent
Conditions	21	21	100.00
Logical	21	21	100.00
Non-Logical	0	0
Event	0	0

 LINE       86
 EXPRESSION (sys_csb_deasserted_pulse_i && (sys_cfg_addr_4b_en_sync != reg2hw_cfg_addr_4b_en_q_i))
             -------------1------------    ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T8,T9,T12
1	0	Covered	T1,T10,T7
1	1	Covered	T4,T5,T6

 LINE       86
 SUB-EXPRESSION (sys_cfg_addr_4b_en_sync != reg2hw_cfg_addr_4b_en_q_i)
                ---------------------------1--------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T8,T9,T12

 LINE       108
 EXPRESSION (spi_reg_cfg_addr_4b_en_sync ? spi_addr_4b_clr_i : spi_addr_4b_set_i)
             -------------1-------------

-1-	Status	Tests
0	Covered	T2,T3,T7
1	Covered	T1,T2,T3

 LINE       110
 EXPRESSION (spi_reg_cfg_addr_4b_en_sync == spi_cfg_addr_4b_en_o)
            --------------------------1--------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T7

 LINE       111
 EXPRESSION (spi_reg_cfg_addr_4b_en_sync != spi_cfg_addr_4b_en_o)
            --------------------------1--------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       117
 EXPRESSION (((!addr_4b_en_locked)) & addr_4b_en_lock_condition)
             -----------1----------   ------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T142,T143,T144
1	0	Covered	T2,T3,T7
1	1	Covered	T4,T5,T6

 LINE       119
 EXPRESSION (addr_4b_en_locked & addr_4b_en_unlock_condition)
             --------1--------   -------------2-------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T7
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

 LINE       144
 EXPRESSION (spi_csb_asserted_pulse_d1 & ((!addr_4b_en_locked)) & addr_4b_en_sw_update_condition)
             ------------1------------   -----------2----------   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T2,T3,T7
1	0	1	Covered	T69,T121,T122
1	1	0	Covered	T7,T8,T9
1	1	1	Covered	T8,T9,T12

---

Branch Coverage for Module : spid_addr_4b

	Line No.	Total	Covered	Percent
Branches		16	16	100.00
TERNARY	108	2	2	100.00
IF	83	3	3	100.00
IF	115	4	4	100.00
IF	128	2	2	100.00
IF	136	5	5	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_spi_device_0.1/rtl/spid_addr_4b.sv' or '../src/lowrisc_ip_spi_device_0.1/rtl/spid_addr_4b.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	108	(spi_reg_cfg_addr_4b_en_sync) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T3,T7

	LineNo.	Expression
-1-:	83	if ((!sys_rst_ni))
-2-:	86	if ((sys_csb_deasserted_pulse_i && (sys_cfg_addr_4b_en_sync != reg2hw_cfg_addr_4b_en_q_i)))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T4,T5,T6
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	115	if ((!sys_rst_ni))
-2-:	117	if (((!addr_4b_en_locked) & addr_4b_en_lock_condition))
-3-:	119	if ((addr_4b_en_locked & addr_4b_en_unlock_condition))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T4,T5,T6
0	0	1	Covered	T4,T5,T6
0	0	0	Covered	T2,T3,T7

	LineNo.	Expression
-1-:	128	if ((!sys_rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T3,T7

	LineNo.	Expression
-1-:	136	if ((!sys_rst_ni))
-2-:	138	if (spi_addr_4b_set_i)
-3-:	141	if (spi_addr_4b_clr_i)
-4-:	144	if (((spi_csb_asserted_pulse_d1 & (!addr_4b_en_locked)) & addr_4b_en_sw_update_condition))

Branches:

-1-	-2-	-3-	-4-	Status	Tests
1	-	-	-	Covered	T1,T2,T3
0	1	-	-	Covered	T4,T5,T6
0	0	1	-	Covered	T4,T5,T6
0	0	0	1	Covered	T8,T9,T12
0	0	0	0	Covered	T2,T3,T7