Line Coverage for Module :
spid_jedec
| Line No. | Total | Covered | Percent |
TOTAL | | 47 | 47 | 100.00 |
CONT_ASSIGN | 64 | 1 | 1 | 100.00 |
ALWAYS | 72 | 4 | 4 | 100.00 |
CONT_ASSIGN | 78 | 1 | 1 | 100.00 |
ALWAYS | 82 | 4 | 4 | 100.00 |
ALWAYS | 90 | 5 | 5 | 100.00 |
ALWAYS | 100 | 8 | 8 | 100.00 |
ALWAYS | 120 | 4 | 4 | 100.00 |
CONT_ASSIGN | 124 | 1 | 1 | 100.00 |
ALWAYS | 131 | 3 | 3 | 100.00 |
ALWAYS | 137 | 16 | 16 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_spi_device_0.1/rtl/spid_jedec.sv' or '../src/lowrisc_ip_spi_device_0.1/rtl/spid_jedec.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
64 |
1 |
1 |
72 |
2 |
2 |
73 |
2 |
2 |
|
|
|
MISSING_ELSE |
78 |
1 |
1 |
82 |
2 |
2 |
83 |
1 |
1 |
84 |
1 |
1 |
|
|
|
MISSING_ELSE |
90 |
1 |
1 |
91 |
1 |
1 |
92 |
1 |
1 |
94 |
1 |
1 |
95 |
1 |
1 |
100 |
1 |
1 |
102 |
1 |
1 |
104 |
1 |
1 |
105 |
1 |
1 |
106 |
1 |
1 |
107 |
1 |
1 |
108 |
1 |
1 |
112 |
1 |
1 |
120 |
2 |
2 |
121 |
2 |
2 |
|
|
|
MISSING_ELSE |
124 |
1 |
1 |
131 |
2 |
2 |
132 |
1 |
1 |
137 |
1 |
1 |
139 |
1 |
1 |
140 |
1 |
1 |
142 |
1 |
1 |
144 |
1 |
1 |
145 |
1 |
1 |
148 |
1 |
1 |
|
|
|
MISSING_ELSE |
159 |
1 |
1 |
160 |
1 |
1 |
|
|
|
MISSING_ELSE |
163 |
1 |
1 |
167 |
1 |
1 |
168 |
1 |
1 |
|
|
|
MISSING_ELSE |
171 |
1 |
1 |
178 |
1 |
1 |
180 |
1 |
1 |
181 |
1 |
1 |
|
|
|
MISSING_ELSE |
Cond Coverage for Module :
spid_jedec
| Total | Covered | Percent |
Conditions | 29 | 29 | 100.00 |
Logical | 29 | 29 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 83
EXPRESSION ((st_q == StCC) && outclk_p2s_sent_i)
-------1------ --------2--------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T5,T7,T9 |
1 | 0 | Covered | T5,T7,T9 |
1 | 1 | Covered | T5,T7,T9 |
LINE 83
SUB-EXPRESSION (st_q == StCC)
-------1------
-1- | Status | Tests |
0 | Covered | T1,T2,T5 |
1 | Covered | T5,T7,T9 |
LINE 102
EXPRESSION (st_q == StIdle)
--------1-------
-1- | Status | Tests |
0 | Covered | T5,T7,T9 |
1 | Covered | T1,T2,T3 |
LINE 104
EXPRESSION (cc_needed ? jedec.cc : jedec.jedec_id)
----1----
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T2,T5,T7 |
LINE 105
EXPRESSION (st_q == StCC)
-------1------
-1- | Status | Tests |
0 | Covered | T5,T7,T9 |
1 | Covered | T5,T7,T9 |
LINE 107
EXPRESSION (st_q == StJedecId)
---------1---------
-1- | Status | Tests |
0 | Covered | T5,T7,T9 |
1 | Covered | T5,T7,T9 |
LINE 112
EXPRESSION ((byte_sel_q >= 2'b10) ? 8'b0 : ((byte_sel_q == 2'b1) ? jedec.device_id[15:8] : jedec.device_id[7:0]))
----------1----------
-1- | Status | Tests |
0 | Covered | T5,T7,T9 |
1 | Covered | T5,T7,T9 |
LINE 112
SUB-EXPRESSION ((byte_sel_q == 2'b1) ? jedec.device_id[15:8] : jedec.device_id[7:0])
----------1---------
-1- | Status | Tests |
0 | Covered | T5,T7,T9 |
1 | Covered | T5,T7,T9 |
LINE 112
SUB-EXPRESSION (byte_sel_q == 2'b1)
----------1---------
-1- | Status | Tests |
0 | Covered | T5,T7,T9 |
1 | Covered | T5,T7,T9 |
LINE 124
EXPRESSION ((byte_sel_q == 2'b10) ? 2'b10 : ((byte_sel_q + 1'b1)))
----------1----------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T5,T7,T9 |
LINE 124
SUB-EXPRESSION (byte_sel_q == 2'b10)
----------1----------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T5,T7,T9 |
LINE 144
EXPRESSION (sel_dp_i == DpReadJEDEC)
------------1------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T5,T7,T9 |
LINE 145
EXPRESSION (cc_needed ? StCC : StJedecId)
----1----
-1- | Status | Tests |
0 | Covered | T5,T7,T9 |
1 | Covered | T5,T7,T9 |
LINE 159
EXPRESSION (cc_count == jedec.num_cc)
-------------1------------
-1- | Status | Tests |
0 | Covered | T5,T7,T9 |
1 | Covered | T5,T9,T11 |
FSM Coverage for Module :
spid_jedec
Summary for FSM :: st_q
| Total | Covered | Percent | |
States |
4 |
4 |
100.00 |
(Not included in score) |
Transitions |
4 |
4 |
100.00 |
|
Sequences |
0 |
0 |
|
|
State, Transition and Sequence Details for FSM :: st_q
states | Line No. | Covered | Tests |
StCC |
145 |
Covered |
T5,T7,T9 |
StDevId |
168 |
Covered |
T5,T7,T9 |
StIdle |
102 |
Covered |
T1,T2,T3 |
StJedecId |
145 |
Covered |
T5,T7,T9 |
transitions | Line No. | Covered | Tests |
StCC->StJedecId |
160 |
Covered |
T5,T9,T11 |
StIdle->StCC |
145 |
Covered |
T5,T7,T9 |
StIdle->StJedecId |
145 |
Covered |
T5,T7,T9 |
StJedecId->StDevId |
168 |
Covered |
T5,T7,T9 |
Branch Coverage for Module :
spid_jedec
| Line No. | Total | Covered | Percent |
Branches |
|
32 |
31 |
96.88 |
TERNARY |
124 |
2 |
2 |
100.00 |
IF |
72 |
3 |
3 |
100.00 |
IF |
82 |
3 |
3 |
100.00 |
IF |
90 |
2 |
2 |
100.00 |
IF |
102 |
7 |
7 |
100.00 |
IF |
120 |
3 |
3 |
100.00 |
IF |
131 |
2 |
2 |
100.00 |
CASE |
142 |
10 |
9 |
90.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_spi_device_0.1/rtl/spid_jedec.sv' or '../src/lowrisc_ip_spi_device_0.1/rtl/spid_jedec.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 124 ((byte_sel_q == 2'b10)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T7,T9 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 72 if ((!rst_ni))
-2-: 73 if (cmd_sync_pulse_i)
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T1,T2,T3 |
0 |
1 |
Covered |
T1,T2,T5 |
0 |
0 |
Covered |
T1,T2,T5 |
LineNo. Expression
-1-: 82 if ((!rst_ni))
-2-: 83 if (((st_q == StCC) && outclk_p2s_sent_i))
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T1,T2,T3 |
0 |
1 |
Covered |
T5,T7,T9 |
0 |
0 |
Covered |
T1,T2,T5 |
LineNo. Expression
-1-: 90 if ((!rst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T5 |
LineNo. Expression
-1-: 102 if ((st_q == StIdle))
-2-: 104 (cc_needed) ?
-3-: 105 if ((st_q == StCC))
-4-: 107 if ((st_q == StJedecId))
-5-: 112 ((byte_sel_q >= 2'b10)) ?
-6-: 112 ((byte_sel_q == 2'b1)) ?
Branches:
-1- | -2- | -3- | -4- | -5- | -6- | Status | Tests |
1 |
1 |
- |
- |
- |
- |
Covered |
T2,T5,T7 |
1 |
0 |
- |
- |
- |
- |
Covered |
T1,T2,T3 |
0 |
- |
1 |
- |
- |
- |
Covered |
T5,T7,T9 |
0 |
- |
0 |
1 |
- |
- |
Covered |
T5,T7,T9 |
0 |
- |
0 |
0 |
1 |
- |
Covered |
T5,T7,T9 |
0 |
- |
0 |
0 |
0 |
1 |
Covered |
T5,T7,T9 |
0 |
- |
0 |
0 |
0 |
0 |
Covered |
T5,T7,T9 |
LineNo. Expression
-1-: 120 if ((!rst_ni))
-2-: 121 if (next_byte)
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T1,T2,T3 |
0 |
1 |
Covered |
T5,T7,T9 |
0 |
0 |
Covered |
T1,T2,T5 |
LineNo. Expression
-1-: 131 if ((!rst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T5 |
LineNo. Expression
-1-: 142 case (st_q)
-2-: 144 if ((sel_dp_i == DpReadJEDEC))
-3-: 145 (cc_needed) ?
-4-: 159 if ((cc_count == jedec.num_cc))
-5-: 167 if (outclk_p2s_sent_i)
-6-: 180 if (outclk_p2s_sent_i)
Branches:
-1- | -2- | -3- | -4- | -5- | -6- | Status | Tests |
StIdle |
1 |
1 |
- |
- |
- |
Covered |
T5,T7,T9 |
StIdle |
1 |
0 |
- |
- |
- |
Covered |
T5,T7,T9 |
StIdle |
0 |
- |
- |
- |
- |
Covered |
T1,T2,T3 |
StCC |
- |
- |
1 |
- |
- |
Covered |
T5,T9,T11 |
StCC |
- |
- |
0 |
- |
- |
Covered |
T5,T7,T9 |
StJedecId |
- |
- |
- |
1 |
- |
Covered |
T5,T7,T9 |
StJedecId |
- |
- |
- |
0 |
- |
Covered |
T5,T7,T9 |
StDevId |
- |
- |
- |
- |
1 |
Covered |
T5,T7,T9 |
StDevId |
- |
- |
- |
- |
0 |
Covered |
T5,T7,T9 |
default |
- |
- |
- |
- |
- |
Not Covered |
|
Assert Coverage for Module :
spid_jedec
Assertion Details
Name | Attempts | Real Successes | Failures | Incomplete |
JedecStKnown_A |
381988954 |
293578611 |
0 |
0 |
JedecStKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
381988954 |
293578611 |
0 |
0 |
T1 |
13408 |
13408 |
0 |
0 |
T2 |
39758 |
38698 |
0 |
0 |
T3 |
1325 |
0 |
0 |
0 |
T5 |
992277 |
973085 |
0 |
0 |
T6 |
360 |
0 |
0 |
0 |
T7 |
749009 |
687436 |
0 |
0 |
T8 |
181176 |
181176 |
0 |
0 |
T9 |
318604 |
262433 |
0 |
0 |
T10 |
19687 |
19687 |
0 |
0 |
T11 |
145674 |
130733 |
0 |
0 |
T12 |
0 |
127130 |
0 |
0 |
T13 |
0 |
115370 |
0 |
0 |