Unified Coverage Report :: Module :: spi_device

Module : spi_device

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.69	94.25	84.31	96.94		87.50	95.45

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_spi_device_0.1/rtl/spi_device.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut	91.69	94.25	84.31	96.94		87.50	95.45

---

Module Instance : tb.dut

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.69	94.25	84.31	96.94		87.50	95.45

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.60	98.38	94.42	98.61	89.36	97.09	95.75

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							tb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_alert_tx[0].u_prim_alert_sender	100.00			100.00
spi_device_csr_assert	100.00						100.00
tlul_assert_device	100.00	100.00				100.00	100.00
u_clk_csb_buf	100.00	100.00
u_clk_csb_mux	64.81	100.00	44.44				50.00
u_clk_spi	85.19	100.00	55.56				100.00
u_clk_spi_in_buf	100.00	100.00
u_clk_spi_in_mux	64.81	100.00	44.44				50.00
u_clk_spi_out_buf	100.00	100.00
u_clk_spi_out_mux	64.81	100.00	44.44				50.00
u_cmdparse	96.74	100.00	87.80		100.00	95.92	100.00
u_csb_buf	100.00	100.00
u_csb_rst_scan_mux	64.81	100.00	44.44				50.00
u_flash_readbuf_flip_pulse_sync	100.00	100.00	100.00			100.00	100.00
u_flash_readbuf_watermark_pulse_sync	100.00	100.00	100.00			100.00	100.00
u_intr_cmdfifo_not_empty	100.00	100.00	100.00			100.00	100.00
u_intr_payload_not_empty	100.00	100.00	100.00			100.00	100.00
u_intr_payload_overflow	100.00	100.00	100.00			100.00	100.00
u_intr_readbuf_flip	100.00	100.00	100.00			100.00	100.00
u_intr_readbuf_watermark	100.00	100.00	100.00			100.00	100.00
u_intr_tpm_cmdaddr_notempty	100.00	100.00	100.00			100.00	100.00
u_intr_tpm_rdfifo_cmd_end	100.00	100.00	100.00			100.00	100.00
u_intr_tpm_rdfifo_drop	97.92	100.00	91.67			100.00	100.00
u_intr_upload_edge	100.00	100.00				100.00
u_jedec	99.38	100.00	100.00		100.00	96.88	100.00
u_p2s	84.73	100.00	71.43			67.50	100.00
u_passthrough	89.66	92.75	89.22		75.00	91.35	100.00
u_read_en_pipe_stg1	100.00	100.00				100.00
u_read_en_pipe_stg2	100.00	100.00				100.00
u_read_pipe_stg1	100.00	100.00				100.00
u_read_pipe_stg2	100.00	100.00				100.00
u_readcmd	89.31	93.63	90.36		87.50	84.15	90.91
u_reg	99.61	99.53	99.20	100.00		99.32	100.00
u_s2p	86.75	100.00	78.57			68.42	100.00
u_scanmode_sync	100.00						100.00
u_spi_tpm	92.68	99.29	84.99		91.67	95.32	92.16
u_spid_addr_4b	86.34	97.59	77.78			95.00	75.00
u_spid_csb_sync	96.97	100.00	100.00			90.91
u_spid_dpram	91.67	100.00	75.00			100.00
u_spid_status	96.26	100.00	89.13			95.89	100.00
u_sys_csb_syncd	100.00	100.00				100.00
u_sys_sram_arbiter	88.22	100.00	70.73			96.43	85.71
u_sys_tpm_csb_sync	100.00	100.00				100.00
u_tlul2sram_egress	71.12	81.67	59.07			62.50	81.25
u_tlul2sram_ingress	86.67	87.92	74.68			84.09	100.00
u_tpm_csb_buf	100.00	100.00
u_tpm_csb_rst_scan_mux	64.81	100.00	44.44				50.00
u_tpm_csb_rst_sync	70.83	88.89	44.44			100.00	50.00
u_upload	91.23	98.60	74.15		100.00	94.12	89.29

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : spi_device

	Line No.	Total	Covered	Percent
TOTAL		226	213	94.25
CONT_ASSIGN	173	1	1	100.00
CONT_ASSIGN	308	1	1	100.00
CONT_ASSIGN	371	1	1	100.00
CONT_ASSIGN	372	1	1	100.00
CONT_ASSIGN	375	1	1	100.00
CONT_ASSIGN	376	1	1	100.00
CONT_ASSIGN	378	1	1	100.00
CONT_ASSIGN	393	1	1	100.00
CONT_ASSIGN	526	1	1	100.00
CONT_ASSIGN	533	1	1	100.00
CONT_ASSIGN	535	1	1	100.00
ALWAYS	538	4	4	100.00
CONT_ASSIGN	546	1	1	100.00
CONT_ASSIGN	552	1	1	100.00
CONT_ASSIGN	553	1	1	100.00
CONT_ASSIGN	558	1	1	100.00
CONT_ASSIGN	559	1	1	100.00
CONT_ASSIGN	563	1	1	100.00
ALWAYS	568	0	0
ALWAYS	568	2	2	100.00
CONT_ASSIGN	573	1	1	100.00
CONT_ASSIGN	574	1	1	100.00
ALWAYS	582	0	0
ALWAYS	582	12	12	100.00
CONT_ASSIGN	646	1	1	100.00
CONT_ASSIGN	647	1	1	100.00
CONT_ASSIGN	648	1	1	100.00
ALWAYS	784	3	3	100.00
ALWAYS	790	8	8	100.00
ALWAYS	828	9	9	100.00
ALWAYS	852	24	24	100.00
CONT_ASSIGN	919	1	1	100.00
CONT_ASSIGN	920	1	1	100.00
ALWAYS	963	5	3	60.00
ALWAYS	974	13	13	100.00
ALWAYS	1011	3	3	100.00
CONT_ASSIGN	1147	1	1	100.00
CONT_ASSIGN	1150	1	1	100.00
CONT_ASSIGN	1154	1	1	100.00
CONT_ASSIGN	1155	1	1	100.00
CONT_ASSIGN	1156	1	1	100.00
CONT_ASSIGN	1158	1	1	100.00
CONT_ASSIGN	1159	1	1	100.00
CONT_ASSIGN	1162	1	1	100.00
CONT_ASSIGN	1208	1	0	0.00
CONT_ASSIGN	1238	1	0	0.00
CONT_ASSIGN	1321	1	1	100.00
CONT_ASSIGN	1322	1	1	100.00
CONT_ASSIGN	1323	1	1	100.00
CONT_ASSIGN	1324	1	1	100.00
CONT_ASSIGN	1325	1	1	100.00
CONT_ASSIGN	1327	1	1	100.00
CONT_ASSIGN	1331	1	1	100.00
CONT_ASSIGN	1338	1	1	100.00
CONT_ASSIGN	1339	1	1	100.00
CONT_ASSIGN	1341	1	1	100.00
CONT_ASSIGN	1345	1	1	100.00
CONT_ASSIGN	1348	1	1	100.00
CONT_ASSIGN	1351	1	1	100.00
CONT_ASSIGN	1354	1	1	100.00
CONT_ASSIGN	1357	1	1	100.00
CONT_ASSIGN	1360	1	1	100.00
CONT_ASSIGN	1367	1	1	100.00
CONT_ASSIGN	1368	1	1	100.00
CONT_ASSIGN	1407	1	1	100.00
CONT_ASSIGN	1508	1	0	0.00
CONT_ASSIGN	1516	1	1	100.00
CONT_ASSIGN	1517	1	1	100.00
CONT_ASSIGN	1518	1	1	100.00
CONT_ASSIGN	1519	1	1	100.00
CONT_ASSIGN	1520	1	1	100.00
CONT_ASSIGN	1523	1	1	100.00
CONT_ASSIGN	1530	1	1	100.00
CONT_ASSIGN	1537	1	1	100.00
CONT_ASSIGN	1537	1	1	100.00
CONT_ASSIGN	1537	1	1	100.00
CONT_ASSIGN	1537	1	1	100.00
CONT_ASSIGN	1537	1	1	100.00
CONT_ASSIGN	1540	1	1	100.00
CONT_ASSIGN	1541	1	1	100.00
CONT_ASSIGN	1542	1	1	100.00
CONT_ASSIGN	1543	1	1	100.00
CONT_ASSIGN	1544	1	1	100.00
CONT_ASSIGN	1545	1	1	100.00
CONT_ASSIGN	1547	1	1	100.00
CONT_ASSIGN	1551	1	1	100.00
CONT_ASSIGN	1553	1	1	100.00
CONT_ASSIGN	1554	1	1	100.00
CONT_ASSIGN	1561	1	1	100.00
CONT_ASSIGN	1563	1	1	100.00
CONT_ASSIGN	1564	1	1	100.00
CONT_ASSIGN	1573	1	1	100.00
CONT_ASSIGN	1574	1	1	100.00
CONT_ASSIGN	1575	1	1	100.00
CONT_ASSIGN	1576	1	1	100.00
CONT_ASSIGN	1629	1	1	100.00
CONT_ASSIGN	1631	1	1	100.00
ALWAYS	1636	4	4	100.00
ALWAYS	1645	0	0
ALWAYS	1645	9	9	100.00
CONT_ASSIGN	1662	1	1	100.00
CONT_ASSIGN	1662	1	1	100.00
CONT_ASSIGN	1662	1	1	100.00
CONT_ASSIGN	1662	1	1	100.00
CONT_ASSIGN	1662	1	1	100.00
CONT_ASSIGN	1663	1	1	100.00
CONT_ASSIGN	1663	1	1	100.00
CONT_ASSIGN	1663	1	0	0.00
CONT_ASSIGN	1663	1	0	0.00
CONT_ASSIGN	1663	1	0	0.00
CONT_ASSIGN	1664	1	1	100.00
CONT_ASSIGN	1664	1	1	100.00
CONT_ASSIGN	1664	1	0	0.00
CONT_ASSIGN	1664	1	0	0.00
CONT_ASSIGN	1664	1	1	100.00
CONT_ASSIGN	1665	1	1	100.00
CONT_ASSIGN	1665	1	1	100.00
CONT_ASSIGN	1665	1	0	0.00
CONT_ASSIGN	1665	1	0	0.00
CONT_ASSIGN	1665	1	0	0.00
CONT_ASSIGN	1667	1	1	100.00
CONT_ASSIGN	1667	1	1	100.00
CONT_ASSIGN	1667	1	1	100.00
CONT_ASSIGN	1667	1	1	100.00
CONT_ASSIGN	1667	1	1	100.00
CONT_ASSIGN	1668	1	1	100.00
CONT_ASSIGN	1668	1	1	100.00
CONT_ASSIGN	1668	1	1	100.00
CONT_ASSIGN	1668	1	1	100.00
CONT_ASSIGN	1668	1	1	100.00
CONT_ASSIGN	1669	1	1	100.00
CONT_ASSIGN	1669	1	1	100.00
CONT_ASSIGN	1669	1	1	100.00
CONT_ASSIGN	1669	1	1	100.00
CONT_ASSIGN	1669	1	1	100.00
CONT_ASSIGN	1710	1	1	100.00
CONT_ASSIGN	1712	1	1	100.00
CONT_ASSIGN	1713	1	1	100.00
CONT_ASSIGN	1714	1	1	100.00
CONT_ASSIGN	1715	1	1	100.00
CONT_ASSIGN	1716	1	1	100.00
CONT_ASSIGN	1718	1	1	100.00
CONT_ASSIGN	1719	1	1	100.00
CONT_ASSIGN	1720	1	1	100.00
CONT_ASSIGN	1776	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_spi_device_0.1/rtl/spi_device.sv' or '../src/lowrisc_ip_spi_device_0.1/rtl/spi_device.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
173	1	1
308	1	1
371	1	1
372	1	1
375	1	1
376	1	1
378	1	1
393	1	1
526	1	1
533	1	1
535	1	1
538	1	1
539	1	1
540	1	1
541	1	1
			MISSING_ELSE
546	1	1
552	1	1
553	1	1
558	1	1
559	1	1
563	1	1
568	1	1
569	1	1
573	1	1
574	1	1
582	1	1
583	1	1
602	1	1
603	1	1
607	1	1
608	1	1
610	1	1
611	1	1
613	1	1
614	1	1
616	1	1
617	1	1
646	1	1
647	1	1
648	1	1
784	2	2
785	1	1
790	1	1
792	1	1
793	1	1
800	1	1
804	1	1
805	1	1
809	1	1
810	1	1
828	1	1
830	1	1
835	1	1
841	1	1
842	1	1
843	1	1
844	1	1
845	1	1
846	1	1
			MISSING_ELSE
852	1	1
853	1	1
854	1	1
855	1	1
857	1	1
859	1	1
861	1	1
863	1	1
867	1	1
869	1	1
870	1	1
871	1	1
874	1	1
876	1	1
877	1	1
878	1	1
883	1	1
885	1	1
886	1	1
887	1	1
891	1	1
893	1	1
894	1	1
895	1	1
919	1	1
920	1	1
963	1	1
964	0	1
965	0	1
967	1	1
968	1	1
974	1	1
975	1	1
977	1	1
979	1	1
980	1	1
984	1	1
986	1	1
987	1	1
991	1	1
992	1	1
993	1	1
995	1	1
996	1	1
1011	2	2
1012	1	1
1147	1	1
1150	1	1
1154	1	1
1155	1	1
1156	1	1
1158	1	1
1159	1	1
1162	1	1
1208	0	1
1238	0	1
1321	1	1
1322	1	1
1323	1	1
1324	1	1
1325	1	1
1327	1	1
1331	1	1
1338	1	1
1339	1	1
1341	1	1
1345	1	1
1348	1	1
1351	1	1
1354	1	1
1357	1	1
1360	1	1
1367	1	1
1368	1	1
1407	1	1
1508	0	1
1516	1	1
1517	1	1
1518	1	1
1519	1	1
1520	1	1
1523	1	1
1530	1	1
1537	5	5
1540	1	1
1541	1	1
1542	1	1
1543	1	1
1544	1	1
1545	1	1
1547	1	1
1551	1	1
1553	1	1
1554	1	1
1561	1	1
1563	1	1
1564	1	1
1573	1	1
1574	1	1
1575	1	1
1576	1	1
1629	1	1
1631	1	1
1636	1	1
1637	1	1
1638	1	1
1639	1	1
			MISSING_ELSE
1645	1	1
1646	1	1
1648	1	1
1651	1	1
1652	1	1
1653	1	1
1654	1	1
1656	1	1
1657	1	1
1662	5	5
1663	2	5
1664	3	5
1665	2	5
1667	5	5
1668	5	5
1669	5	5
1710	1	1
1712	1	1
1713	1	1
1714	1	1
1715	1	1
1716	1	1
1718	1	1
1719	1	1
1720	1	1
1776	1	1

---

Cond Coverage for Module : spi_device

	Total	Covered	Percent
Conditions	51	43	84.31
Logical	51	43	84.31
Non-Logical	0	0
Event	0	0

 LINE       173
 EXPRESSION (payload_depth != '0)
            ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T5,T7,T9

 LINE       701
 EXPRESSION (rst_ni & ((~rst_csb_buf)))
             ---1--   --------2-------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T4

 LINE       712
 EXPRESSION (rst_ni & ((~rst_tpm_csb_buf)))
             ---1--   ----------2---------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T3,T4,T5

 LINE       814
 EXPRESSION (cmd_only_dp_sel == DpUpload)
            --------------1--------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T5,T7,T9

 LINE       841
 EXPRESSION (((!sck_csb)) && ((spi_mode == FlashMode) || (spi_mode == PassThrough)))
             ------1-----    ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T4

 LINE       841
 SUB-EXPRESSION ((spi_mode == FlashMode) || (spi_mode == PassThrough))
                 -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Not Covered
0	1	Covered	T5,T8,T11
1	0	Covered	T1,T2,T3

 LINE       841
 SUB-EXPRESSION (spi_mode == FlashMode)
                -----------1-----------

-1-	Status	Tests
0	Covered	T5,T8,T11
1	Covered	T1,T2,T3

 LINE       841
 SUB-EXPRESSION (spi_mode == PassThrough)
                ------------1------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T5,T8,T11

 LINE       977
 EXPRESSION (cfg_tpm_en && ((!sck_tpm_csb_buf)))
             -----1----    ----------2---------

-1-	-2-	Status	Tests
0	1	Covered	T4,T48,T49
1	0	Covered	T3,T5,T6
1	1	Covered	T3,T5,T6

 LINE       1147
 EXPRESSION (reg2hw.flash_status.busy.qe && reg2hw.flash_status.wel.qe && reg2hw.flash_status.status.qe)
             -------------1-------------    -------------2------------    --------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Covered	T1,T2,T5

 LINE       1158
 EXPRESSION (cmd_only_dp_sel == DpWrEn)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T5,T7,T9

 LINE       1159
 EXPRESSION (cmd_only_dp_sel == DpWrDi)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T5,T7,T9

 LINE       1367
 EXPRESSION (cmd_only_dp_sel == DpEn4B)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T5,T7,T9

 LINE       1368
 EXPRESSION (cmd_only_dp_sel == DpEx4B)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T5,T7,T9

 LINE       1530
 EXPRESSION (reg2hw.tpm_status.wrfifo_pending.qe & ((~reg2hw.tpm_status.wrfifo_pending.q)))
             -----------------1-----------------   -------------------2-------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T5,T7,T9

 LINE       1638
 EXPRESSION ((i != SysSramFwEgress) && (i != SysSramFwIngress))
             -----------1----------    -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       1638
 SUB-EXPRESSION (i != SysSramFwEgress)
                -----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       1638
 SUB-EXPRESSION (i != SysSramFwIngress)
                -----------1-----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       1710
 EXPRESSION (tpm_rst_n | rst_spi_n)
             ----1----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T4
1	0	Covered	T3,T4,T5

 LINE       1776
 SUB-EXPRESSION (reg2hw.alert_test.q & reg2hw.alert_test.qe)
                 ---------1---------   ----------2---------

-1-	-2-	Status	Tests
0	1	Covered	T50,T51,T52
1	0	Covered	T1,T2,T3
1	1	Covered	T50,T51,T52

---

Toggle Coverage for Module : spi_device

	Total	Covered	Percent
Totals	59	54	91.53
Total Bits	458	444	96.94
Total Bits 0->1	229	222	96.94
Total Bits 1->0	229	222	96.94

Ports	59	54	91.53
Port Bits	458	444	96.94
Port Bits 0->1	229	222	96.94
Port Bits 1->0	229	222	96.94

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T28,T48,T49	Yes	T1,T2,T3	INPUT
tl_i.d_ready	Yes	Yes	T1,T2,T4	Yes	T1,T2,T3	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.instr_type[3:0]	Yes	Yes	T7,T10,T12	Yes	T7,T10,T12	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T1,T2,T4	Yes	T1,T2,T5	INPUT
tl_i.a_address[31:0]	Yes	Yes	T1,T2,T5	Yes	T1,T2,T5	INPUT
tl_i.a_source[7:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_size[1:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[2:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_o.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_error	Yes	Yes	T20,T21,T22	Yes	T20,T21,T22	OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T1,T2,T4	Yes	T1,T2,T4	OUTPUT
tl_o.d_user.rsp_intg[5:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_user.rsp_intg[6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T5	OUTPUT
tl_o.d_sink	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_source[7:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_size[1:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T50,T51,T52	Yes	T50,T51,T52	INPUT
alert_rx_i[0].ping_n	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[0].ping_p	Unreachable	Unreachable		Unreachable		INPUT
alert_tx_o[0].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T50,T51,T52	Yes	T50,T51,T52	OUTPUT
cio_sck_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
cio_csb_i	Yes	Yes	T1,T2,T4	Yes	T1,T2,T4	INPUT
cio_sd_o[3:0]	Yes	Yes	T1,T2,T5	Yes	T1,T2,T5	OUTPUT
cio_sd_en_o[3:0]	Yes	Yes	T1,T2,T5	Yes	T1,T2,T5	OUTPUT
cio_sd_i[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
cio_tpm_csb_i	Yes	Yes	T3,T4,T5	Yes	T3,T4,T5	INPUT
passthrough_o.s_en[0]	Yes	Yes	*T5,*T8,*T11	Yes	T5,T8,T11	OUTPUT
passthrough_o.s_en[3:1]	No	No		No		OUTPUT
passthrough_o.s[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
passthrough_o.csb_en	No	No		No		OUTPUT
passthrough_o.csb	Yes	Yes	T1,T2,T4	Yes	T1,T2,T4	OUTPUT
passthrough_o.sck_en	No	No		No		OUTPUT
passthrough_o.sck	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
passthrough_o.passthrough_en	Yes	Yes	T5,T11,T14	Yes	T5,T8,T11	OUTPUT
passthrough_i.s[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
intr_upload_cmdfifo_not_empty_o	Yes	Yes	T28,T49,T53	Yes	T28,T49,T53	OUTPUT
intr_upload_payload_not_empty_o	Yes	Yes	T28,T49,T53	Yes	T28,T49,T53	OUTPUT
intr_upload_payload_overflow_o	Yes	Yes	T28,T49,T53	Yes	T28,T49,T53	OUTPUT
intr_readbuf_watermark_o	Yes	Yes	T28,T49,T53	Yes	T28,T49,T53	OUTPUT
intr_readbuf_flip_o	Yes	Yes	T28,T49,T53	Yes	T28,T49,T53	OUTPUT
intr_tpm_header_not_empty_o	Yes	Yes	T28,T49,T53	Yes	T28,T49,T53	OUTPUT
intr_tpm_rdfifo_cmd_end_o	Yes	Yes	T28,T49,T53	Yes	T28,T49,T53	OUTPUT
intr_tpm_rdfifo_drop_o	Yes	Yes	T28,T49,T53	Yes	T28,T49,T53	OUTPUT
ram_cfg_i.b_ram_lcfg.cfg[3:0]	Yes	Yes	T54,T55,T56	Yes	T54,T55,T56	INPUT
ram_cfg_i.b_ram_lcfg.cfg_en	Yes	Yes	T54,T55,T56	Yes	T54,T55,T56	INPUT
ram_cfg_i.a_ram_lcfg.cfg[3:0]	Yes	Yes	T54,T55,T56	Yes	T54,T55,T56	INPUT
ram_cfg_i.a_ram_lcfg.cfg_en	Yes	Yes	T54,T55,T56	Yes	T54,T55,T56	INPUT
ram_cfg_i.b_ram_fcfg.cfg[3:0]	Yes	Yes	T54,T55,T56	Yes	T54,T55,T56	INPUT
ram_cfg_i.b_ram_fcfg.cfg_en	Yes	Yes	T54,T55,T56	Yes	T54,T55,T56	INPUT
ram_cfg_i.a_ram_fcfg.cfg[3:0]	Yes	Yes	T54,T55,T56	Yes	T54,T55,T56	INPUT
ram_cfg_i.a_ram_fcfg.cfg_en	Yes	Yes	T54,T55,T56	Yes	T54,T55,T56	INPUT
sck_monitor_o	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
mbist_en_i	Unreachable	Unreachable		Unreachable		INPUT
scan_clk_i	No	No		No		INPUT
scan_rst_ni	No	No		No		INPUT
scanmode_i[3:0]	Unreachable	Unreachable		Unreachable		INPUT

*Tests covering at least one bit in the range

---

Branch Coverage for Module : spi_device

	Line No.	Total	Covered	Percent
Branches		32	28	87.50
IF	538	3	3	100.00
IF	784	2	2	100.00
CASE	800	4	4	100.00
IF	841	3	3	100.00
CASE	857	7	5	71.43
IF	963	2	1	50.00
IF	977	5	4	80.00
IF	1011	2	2	100.00
IF	1638	2	2	100.00
IF	1648	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_spi_device_0.1/rtl/spi_device.sv' or '../src/lowrisc_ip_spi_device_0.1/rtl/spi_device.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	538	if ((!rst_ni))
-2-:	540	if (sys_csb_deasserted_pulse)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T5
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	784	if ((!rst_spi_n))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T5

	LineNo.	Expression
-1-:	800	case (cmd_dp_sel)
-2-:	814	if ((cmd_only_dp_sel == DpUpload))

Branches:

-1-	-2-	Status	Tests
DpReadCmd DpReadSFDP	-	Covered	T1,T2,T5
DpUpload	-	Covered	T5,T7,T9
default	1	Covered	T5,T7,T9
default	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	841	if (((!sck_csb) && ((spi_mode == FlashMode) || (spi_mode == PassThrough))))
-2-:	844	if (cfg_tpm_en)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T4
0	1	Covered	T3,T5,T6
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	857	case (spi_mode)
-2-:	859	case (cmd_dp_sel)

Branches:

-1-	-2-	Status	Tests
FlashMode PassThrough	DpNone	Covered	T1,T2,T3
FlashMode PassThrough	DpReadCmd DpReadSFDP	Covered	T1,T2,T5
FlashMode PassThrough	DpReadStatus	Covered	T5,T7,T9
FlashMode PassThrough	DpReadJEDEC	Covered	T5,T7,T9
FlashMode PassThrough	DpUpload	Covered	T5,T7,T9
FlashMode PassThrough	default	Not Covered
default	-	Not Covered

	LineNo.	Expression
-1-:	963	if (cmd_read_pipeline_sel)

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	977	if ((cfg_tpm_en && (!sck_tpm_csb_buf)))
-2-:	984	case (spi_mode)
-3-:	991	if (intercept_en)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T3,T5,T6
0	FlashMode	-	Covered	T1,T2,T3
0	PassThrough	1	Covered	T5,T11,T14
0	PassThrough	0	Covered	T5,T8,T11
0	default	-	Not Covered

	LineNo.	Expression
-1-:	1011	if ((!rst_spi_n))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T5

	LineNo.	Expression
-1-:	1638	if (((i != SysSramFwEgress) && (i != SysSramFwIngress)))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	1648	if (sys_sram_hw_req)

Branches:

-1-	Status	Tests
1	Covered	T5,T7,T9
0	Covered	T1,T2,T3

---

Assert Coverage for Module : spi_device

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	22	22	100.00	21	95.45
Cover properties	0	0		0
Cover sequences	0	0		0
Total	22	22	100.00	21	95.45

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AlertKnownO_A	1203785710	1203617844	0	0
CioSdoEnOKnown	1203785710	1203617844	0	0
CioSdoEnOffWhenInactive	1203785710	1203617844	0	0
FpvSecCmRegWeOnehotCheck_A	1203785710	190	0	0
InterceptLevel_M	381990775	0	0	0
IntrReadbufFlipOKnown	1203785710	1203617844	0	0
IntrReadbufWatermarkOKnown	1203785710	1203617844	0	0
IntrTpmHeaderNotEmptyOKnown	1203785710	1203617844	0	0
IntrTpmRdfifoCmdEndOKnown	1203785710	1203617844	0	0
IntrTpmRdfifoDropOKnown	1203785710	1203617844	0	0
IntrUploadCmdfifoNotEmptyOKnown	1203785710	1203617844	0	0
IntrUploadPayloadNotEmptyOKnown	1203785710	1203617844	0	0
IntrUploadPayloadOverflowOKnown	1203785710	1203617844	0	0
PayloadStartIdxWidthMatch_A	1852	1852	0	0
SpiModeKnown_A	1203785710	1203617844	0	0
TpmEnableWhenTpmCsbIdle_M	1203785710	692	0	0
g_sram_connect[0].ReqAlwaysAccepted_A	1203785710	4382224	0	0
g_sram_connect[1].ReqAlwaysAccepted_A	1203785710	423299	0	0
g_sram_connect[2].ReqAlwaysAccepted_A	1203785710	4724	0	0
g_sram_connect[3].ReqAlwaysAccepted_A	1203785710	3508	0	0
g_sram_connect[4].ReqAlwaysAccepted_A	1203785710	555548	0	0
scanmodeKnown	1203785710	1203785710	0	0

AlertKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1203785710	1203617844	0	0
T1	110812	110733	0	0
T2	208167	208073	0	0
T3	5602	5524	0	0
T4	1518	1428	0	0
T5	405811	405804	0	0
T6	1762	1664	0	0
T7	232174	232167	0	0
T8	365507	365413	0	0
T9	127203	127197	0	0
T10	42843	42770	0	0

CioSdoEnOKnown

Name	Attempts	Real Successes	Failures	Incomplete
Total	1203785710	1203617844	0	0
T1	110812	110733	0	0
T2	208167	208073	0	0
T3	5602	5524	0	0
T4	1518	1428	0	0
T5	405811	405804	0	0
T6	1762	1664	0	0
T7	232174	232167	0	0
T8	365507	365413	0	0
T9	127203	127197	0	0
T10	42843	42770	0	0

CioSdoEnOffWhenInactive

Name	Attempts	Real Successes	Failures	Incomplete
Total	1203785710	1203617844	0	0
T1	110812	110733	0	0
T2	208167	208073	0	0
T3	5602	5524	0	0
T4	1518	1428	0	0
T5	405811	405804	0	0
T6	1762	1664	0	0
T7	232174	232167	0	0
T8	365507	365413	0	0
T9	127203	127197	0	0
T10	42843	42770	0	0

FpvSecCmRegWeOnehotCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1203785710	190	0	0
T57	5458	20	0	0
T58	0	30	0	0
T59	0	20	0	0
T60	0	10	0	0
T61	0	10	0	0
T62	0	20	0	0
T63	0	20	0	0
T64	0	10	0	0
T65	0	20	0	0
T66	0	30	0	0
T67	2292	0	0	0
T68	1091	0	0	0
T69	2718	0	0	0
T70	273514	0	0	0
T71	46418	0	0	0
T72	9377	0	0	0
T73	65436	0	0	0
T74	24540	0	0	0
T75	125481	0	0	0

InterceptLevel_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	381990775	0	0	0

IntrReadbufFlipOKnown

Name	Attempts	Real Successes	Failures	Incomplete
Total	1203785710	1203617844	0	0
T1	110812	110733	0	0
T2	208167	208073	0	0
T3	5602	5524	0	0
T4	1518	1428	0	0
T5	405811	405804	0	0
T6	1762	1664	0	0
T7	232174	232167	0	0
T8	365507	365413	0	0
T9	127203	127197	0	0
T10	42843	42770	0	0

IntrReadbufWatermarkOKnown

Name	Attempts	Real Successes	Failures	Incomplete
Total	1203785710	1203617844	0	0
T1	110812	110733	0	0
T2	208167	208073	0	0
T3	5602	5524	0	0
T4	1518	1428	0	0
T5	405811	405804	0	0
T6	1762	1664	0	0
T7	232174	232167	0	0
T8	365507	365413	0	0
T9	127203	127197	0	0
T10	42843	42770	0	0

IntrTpmHeaderNotEmptyOKnown

Name	Attempts	Real Successes	Failures	Incomplete
Total	1203785710	1203617844	0	0
T1	110812	110733	0	0
T2	208167	208073	0	0
T3	5602	5524	0	0
T4	1518	1428	0	0
T5	405811	405804	0	0
T6	1762	1664	0	0
T7	232174	232167	0	0
T8	365507	365413	0	0
T9	127203	127197	0	0
T10	42843	42770	0	0

IntrTpmRdfifoCmdEndOKnown

Name	Attempts	Real Successes	Failures	Incomplete
Total	1203785710	1203617844	0	0
T1	110812	110733	0	0
T2	208167	208073	0	0
T3	5602	5524	0	0
T4	1518	1428	0	0
T5	405811	405804	0	0
T6	1762	1664	0	0
T7	232174	232167	0	0
T8	365507	365413	0	0
T9	127203	127197	0	0
T10	42843	42770	0	0

IntrTpmRdfifoDropOKnown

Name	Attempts	Real Successes	Failures	Incomplete
Total	1203785710	1203617844	0	0
T1	110812	110733	0	0
T2	208167	208073	0	0
T3	5602	5524	0	0
T4	1518	1428	0	0
T5	405811	405804	0	0
T6	1762	1664	0	0
T7	232174	232167	0	0
T8	365507	365413	0	0
T9	127203	127197	0	0
T10	42843	42770	0	0

IntrUploadCmdfifoNotEmptyOKnown

Name	Attempts	Real Successes	Failures	Incomplete
Total	1203785710	1203617844	0	0
T1	110812	110733	0	0
T2	208167	208073	0	0
T3	5602	5524	0	0
T4	1518	1428	0	0
T5	405811	405804	0	0
T6	1762	1664	0	0
T7	232174	232167	0	0
T8	365507	365413	0	0
T9	127203	127197	0	0
T10	42843	42770	0	0

IntrUploadPayloadNotEmptyOKnown

Name	Attempts	Real Successes	Failures	Incomplete
Total	1203785710	1203617844	0	0
T1	110812	110733	0	0
T2	208167	208073	0	0
T3	5602	5524	0	0
T4	1518	1428	0	0
T5	405811	405804	0	0
T6	1762	1664	0	0
T7	232174	232167	0	0
T8	365507	365413	0	0
T9	127203	127197	0	0
T10	42843	42770	0	0

IntrUploadPayloadOverflowOKnown

Name	Attempts	Real Successes	Failures	Incomplete
Total	1203785710	1203617844	0	0
T1	110812	110733	0	0
T2	208167	208073	0	0
T3	5602	5524	0	0
T4	1518	1428	0	0
T5	405811	405804	0	0
T6	1762	1664	0	0
T7	232174	232167	0	0
T8	365507	365413	0	0
T9	127203	127197	0	0
T10	42843	42770	0	0

PayloadStartIdxWidthMatch_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1852	1852	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

SpiModeKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1203785710	1203617844	0	0
T1	110812	110733	0	0
T2	208167	208073	0	0
T3	5602	5524	0	0
T4	1518	1428	0	0
T5	405811	405804	0	0
T6	1762	1664	0	0
T7	232174	232167	0	0
T8	365507	365413	0	0
T9	127203	127197	0	0
T10	42843	42770	0	0

TpmEnableWhenTpmCsbIdle_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	1203785710	692	0	0
T3	5602	1	0	0
T4	1518	0	0	0
T5	405811	1	0	0
T6	1762	1	0	0
T7	232174	1	0	0
T8	365507	0	0	0
T9	127203	1	0	0
T10	42843	0	0	0
T11	664506	1	0	0
T12	68526	0	0	0
T14	0	1	0	0
T15	0	1	0	0
T16	0	1	0	0
T24	0	1	0	0

g_sram_connect[0].ReqAlwaysAccepted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1203785710	4382224	0	0
T1	110812	832	0	0
T2	208167	832	0	0
T3	5602	0	0	0
T4	1518	0	0	0
T5	405811	10816	0	0
T6	1762	0	0	0
T7	232174	14144	0	0
T8	365507	832	0	0
T9	127203	5824	0	0
T10	42843	832	0	0
T11	0	14976	0	0
T12	0	832	0	0
T13	0	832	0	0

g_sram_connect[1].ReqAlwaysAccepted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1203785710	423299	0	0
T5	405811	795	0	0
T6	1762	0	0	0
T7	232174	1036	0	0
T8	365507	0	0	0
T9	127203	417	0	0
T10	42843	0	0	0
T11	664506	993	0	0
T12	68526	0	0	0
T13	131303	0	0	0
T14	0	1197	0	0
T15	0	1086	0	0
T16	0	512	0	0
T23	0	224	0	0
T24	0	59	0	0
T25	0	125	0	0
T26	15735	0	0	0

g_sram_connect[2].ReqAlwaysAccepted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1203785710	4724	0	0
T5	405811	22	0	0
T6	1762	0	0	0
T7	232174	28	0	0
T8	365507	0	0	0
T9	127203	7	0	0
T10	42843	0	0	0
T11	664506	25	0	0
T12	68526	0	0	0
T13	131303	0	0	0
T14	0	12	0	0
T15	0	34	0	0
T16	0	19	0	0
T23	0	8	0	0
T25	0	4	0	0
T26	15735	0	0	0
T27	0	8	0	0

g_sram_connect[3].ReqAlwaysAccepted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1203785710	3508	0	0
T5	405811	15	0	0
T6	1762	0	0	0
T7	232174	21	0	0
T8	365507	0	0	0
T9	127203	6	0	0
T10	42843	0	0	0
T11	664506	18	0	0
T12	68526	0	0	0
T13	131303	0	0	0
T14	0	9	0	0
T15	0	26	0	0
T16	0	14	0	0
T23	0	4	0	0
T25	0	4	0	0
T26	15735	0	0	0
T27	0	5	0	0

g_sram_connect[4].ReqAlwaysAccepted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1203785710	555548	0	0
T5	405811	195	0	0
T6	1762	0	0	0
T7	232174	441	0	0
T8	365507	0	0	0
T9	127203	427	0	0
T10	42843	0	0	0
T11	664506	486	0	0
T12	68526	0	0	0
T13	131303	0	0	0
T14	0	1905	0	0
T15	0	392	0	0
T16	0	98	0	0
T24	0	44	0	0
T26	15735	0	0	0
T28	0	200	0	0
T34	0	1017	0	0

scanmodeKnown

Name	Attempts	Real Successes	Failures	Incomplete
Total	1203785710	1203785710	0	0
T1	110812	110812	0	0
T2	208167	208167	0	0
T3	5602	5602	0	0
T4	1518	1518	0	0
T5	405811	405811	0	0
T6	1762	1762	0	0
T7	232174	232174	0	0
T8	365507	365507	0	0
T9	127203	127203	0	0
T10	42843	42843	0	0