SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
tb.dut.u_spid_dpram.gen_ram1r1w.u_sys2spi_mem.u_mem.gen_generic.u_impl_generic | 100.00 | 100.00 | 100.00 | ||||
tb.dut.u_spid_dpram.gen_ram1r1w.u_spi2sys_mem.u_mem.gen_generic.u_impl_generic | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
u_mem |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
no children |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
u_mem |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
no children |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 11 | 11 | 100.00 | |
CONT_ASSIGN | 45 | 1 | 1 | 100.00 |
CONT_ASSIGN | 54 | 1 | 1 | 100.00 |
CONT_ASSIGN | 54 | 1 | 1 | 100.00 |
CONT_ASSIGN | 54 | 1 | 1 | 100.00 |
CONT_ASSIGN | 54 | 1 | 1 | 100.00 |
ALWAYS | 66 | 4 | 4 | 100.00 |
ALWAYS | 77 | 2 | 2 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
45 | 1 | 1 | |
54 | 4 | 4 | |
66 | 1 | 1 | |
67 | 1 | 1 | |
68 | 1 | 1 | |
69 | 1 | 1 | |
MISSING_ELSE | |||
MISSING_ELSE | |||
77 | 1 | 1 | |
78 | 1 | 1 | |
MISSING_ELSE |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
Branches | 4 | 4 | 100.00 | |
IF | 66 | 2 | 2 | 100.00 |
IF | 77 | 2 | 2 | 100.00 |
LineNo. Expression -1-: 66 if (a_req_i)
-1- | Status | Tests |
---|---|---|
1 | Covered | T7,T10,T13 |
0 | Covered | T3,T4,T7 |
LineNo. Expression -1-: 77 if (b_req_i)
-1- | Status | Tests |
---|---|---|
1 | Covered | T7,T10,T13 |
0 | Covered | T3,T4,T7 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 11 | 11 | 100.00 | |
CONT_ASSIGN | 45 | 1 | 1 | 100.00 |
CONT_ASSIGN | 54 | 1 | 1 | 100.00 |
CONT_ASSIGN | 54 | 1 | 1 | 100.00 |
CONT_ASSIGN | 54 | 1 | 1 | 100.00 |
CONT_ASSIGN | 54 | 1 | 1 | 100.00 |
ALWAYS | 66 | 4 | 4 | 100.00 |
ALWAYS | 77 | 2 | 2 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
45 | 1 | 1 | |
54 | 4 | 4 | |
66 | 1 | 1 | |
67 | 1 | 1 | |
68 | 1 | 1 | |
69 | 1 | 1 | |
==> MISSING_ELSE | |||
MISSING_ELSE | |||
77 | 1 | 1 | |
78 | 1 | 1 | |
MISSING_ELSE |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
Branches | 4 | 4 | 100.00 | |
IF | 66 | 2 | 2 | 100.00 |
IF | 77 | 2 | 2 | 100.00 |
LineNo. Expression -1-: 66 if (a_req_i)
-1- | Status | Tests |
---|---|---|
1 | Covered | T7,T10,T13 |
0 | Covered | T3,T4,T7 |
LineNo. Expression -1-: 77 if (b_req_i)
-1- | Status | Tests |
---|---|---|
1 | Covered | T7,T10,T13 |
0 | Covered | T3,T7,T10 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 11 | 11 | 100.00 | |
CONT_ASSIGN | 45 | 1 | 1 | 100.00 |
CONT_ASSIGN | 54 | 1 | 1 | 100.00 |
CONT_ASSIGN | 54 | 1 | 1 | 100.00 |
CONT_ASSIGN | 54 | 1 | 1 | 100.00 |
CONT_ASSIGN | 54 | 1 | 1 | 100.00 |
ALWAYS | 66 | 4 | 4 | 100.00 |
ALWAYS | 77 | 2 | 2 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
45 | 1 | 1 | |
54 | 4 | 4 | |
66 | 1 | 1 | |
67 | 1 | 1 | |
68 | 1 | 1 | |
69 | 1 | 1 | |
MISSING_ELSE | |||
MISSING_ELSE | |||
77 | 1 | 1 | |
78 | 1 | 1 | |
MISSING_ELSE |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
Branches | 4 | 4 | 100.00 | |
IF | 66 | 2 | 2 | 100.00 |
IF | 77 | 2 | 2 | 100.00 |
LineNo. Expression -1-: 66 if (a_req_i)
-1- | Status | Tests |
---|---|---|
1 | Covered | T7,T16,T24 |
0 | Covered | T3,T7,T10 |
LineNo. Expression -1-: 77 if (b_req_i)
-1- | Status | Tests |
---|---|---|
1 | Covered | T7,T16,T24 |
0 | Covered | T3,T4,T7 |
0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |