Module Definition
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Module Instance : tb.dut.u_spid_dpram.gen_ram1r1w.u_sys2spi_mem.u_mem.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_mem


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_spid_dpram.gen_ram1r1w.u_spi2sys_mem.u_mem.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_mem


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children

Line Coverage for Module : prim_generic_ram_1r1w
Line No.TotalCoveredPercent
TOTAL1111100.00
CONT_ASSIGN4511100.00
CONT_ASSIGN5411100.00
CONT_ASSIGN5411100.00
CONT_ASSIGN5411100.00
CONT_ASSIGN5411100.00
ALWAYS6644100.00
ALWAYS7722100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_ram_1r1w_0/rtl/prim_generic_ram_1r1w.sv' or '../src/lowrisc_prim_generic_ram_1r1w_0/rtl/prim_generic_ram_1r1w.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
45 1 1
54 4 4
66 1 1
67 1 1
68 1 1
69 1 1
MISSING_ELSE
MISSING_ELSE
77 1 1
78 1 1
MISSING_ELSE


Branch Coverage for Module : prim_generic_ram_1r1w
Line No.TotalCoveredPercent
Branches 4 4 100.00
IF 66 2 2 100.00
IF 77 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_ram_1r1w_0/rtl/prim_generic_ram_1r1w.sv' or '../src/lowrisc_prim_generic_ram_1r1w_0/rtl/prim_generic_ram_1r1w.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 66 if (a_req_i)

Branches:
-1-StatusTests
1 Covered T7,T10,T13
0 Covered T3,T4,T7


LineNo. Expression -1-: 77 if (b_req_i)

Branches:
-1-StatusTests
1 Covered T7,T10,T13
0 Covered T3,T4,T7

Line Coverage for Instance : tb.dut.u_spid_dpram.gen_ram1r1w.u_sys2spi_mem.u_mem.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL1111100.00
CONT_ASSIGN4511100.00
CONT_ASSIGN5411100.00
CONT_ASSIGN5411100.00
CONT_ASSIGN5411100.00
CONT_ASSIGN5411100.00
ALWAYS6644100.00
ALWAYS7722100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_ram_1r1w_0/rtl/prim_generic_ram_1r1w.sv' or '../src/lowrisc_prim_generic_ram_1r1w_0/rtl/prim_generic_ram_1r1w.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
45 1 1
54 4 4
66 1 1
67 1 1
68 1 1
69 1 1
==> MISSING_ELSE
MISSING_ELSE
77 1 1
78 1 1
MISSING_ELSE


Branch Coverage for Instance : tb.dut.u_spid_dpram.gen_ram1r1w.u_sys2spi_mem.u_mem.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
Branches 4 4 100.00
IF 66 2 2 100.00
IF 77 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_ram_1r1w_0/rtl/prim_generic_ram_1r1w.sv' or '../src/lowrisc_prim_generic_ram_1r1w_0/rtl/prim_generic_ram_1r1w.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 66 if (a_req_i)

Branches:
-1-StatusTests
1 Covered T7,T10,T13
0 Covered T3,T4,T7


LineNo. Expression -1-: 77 if (b_req_i)

Branches:
-1-StatusTests
1 Covered T7,T10,T13
0 Covered T3,T7,T10

Line Coverage for Instance : tb.dut.u_spid_dpram.gen_ram1r1w.u_spi2sys_mem.u_mem.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL1111100.00
CONT_ASSIGN4511100.00
CONT_ASSIGN5411100.00
CONT_ASSIGN5411100.00
CONT_ASSIGN5411100.00
CONT_ASSIGN5411100.00
ALWAYS6644100.00
ALWAYS7722100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_ram_1r1w_0/rtl/prim_generic_ram_1r1w.sv' or '../src/lowrisc_prim_generic_ram_1r1w_0/rtl/prim_generic_ram_1r1w.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
45 1 1
54 4 4
66 1 1
67 1 1
68 1 1
69 1 1
MISSING_ELSE
MISSING_ELSE
77 1 1
78 1 1
MISSING_ELSE


Branch Coverage for Instance : tb.dut.u_spid_dpram.gen_ram1r1w.u_spi2sys_mem.u_mem.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
Branches 4 4 100.00
IF 66 2 2 100.00
IF 77 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_ram_1r1w_0/rtl/prim_generic_ram_1r1w.sv' or '../src/lowrisc_prim_generic_ram_1r1w_0/rtl/prim_generic_ram_1r1w.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 66 if (a_req_i)

Branches:
-1-StatusTests
1 Covered T7,T16,T24
0 Covered T3,T7,T10


LineNo. Expression -1-: 77 if (b_req_i)

Branches:
-1-StatusTests
1 Covered T7,T16,T24
0 Covered T3,T4,T7

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%