SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
tb.dut.u_spid_dpram.gen_ram1r1w.u_sys2spi_mem.u_mem | |||||||
tb.dut.u_spid_dpram.gen_ram1r1w.u_spi2sys_mem.u_mem |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
100.00 | 100.00 | 100.00 | gen_ram1r1w.u_sys2spi_mem |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_generic.u_impl_generic | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
100.00 | 100.00 | 100.00 | gen_ram1r1w.u_spi2sys_mem |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_generic.u_impl_generic | 100.00 | 100.00 | 100.00 |
0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |