Unified Coverage Report :: Module :: prim_fifo_async

Module : prim_fifo_async

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.53	100.00	78.46			91.67	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_async.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_spi_tpm.u_cmdaddr_buffer	92.15	100.00	76.92			91.67	100.00
tb.dut.u_spid_status.u_sw_status_update_sync	92.92	100.00	80.00			91.67	100.00

---

Module Instance : tb.dut.u_spi_tpm.u_cmdaddr_buffer

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.15	100.00	76.92			91.67	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.67	100.00	76.92			93.75	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.66	99.29	91.20		91.67	96.13	100.00	u_spi_tpm

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
sync_rptr	100.00	100.00				100.00
sync_wptr	100.00	100.00				100.00

---

Module Instance : tb.dut.u_spid_status.u_sw_status_update_sync

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.92	100.00	80.00			91.67	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.44	100.00	80.00			93.75	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.31	100.00	100.00			97.22	100.00	u_spid_status

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
sync_rptr	100.00	100.00				100.00
sync_wptr	100.00	100.00				100.00

Line Coverage for Module : prim_fifo_async

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	53	1	1	100.00
CONT_ASSIGN	56	1	1	100.00
ALWAYS	59	4	4	100.00
ALWAYS	68	4	4	100.00
CONT_ASSIGN	86	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	92	4	4	100.00
ALWAYS	101	4	4	100.00
ALWAYS	117	3	3	100.00
CONT_ASSIGN	130	1	1	100.00
CONT_ASSIGN	131	1	1	100.00
CONT_ASSIGN	132	1	1	100.00
CONT_ASSIGN	142	1	1	100.00
CONT_ASSIGN	143	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	146	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	157	1	1	100.00
CONT_ASSIGN	158	1	1	100.00
CONT_ASSIGN	159	1	1	100.00
CONT_ASSIGN	160	1	1	100.00
CONT_ASSIGN	171	1	1	100.00
CONT_ASSIGN	172	1	1	100.00
ALWAYS	182	2	2	100.00
CONT_ASSIGN	187	1	1	100.00
CONT_ASSIGN	207	1	1	100.00
CONT_ASSIGN	276	1	1	100.00
CONT_ASSIGN	277	1	1	100.00
CONT_ASSIGN	279	1	1	100.00
CONT_ASSIGN	280	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_async.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_async.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
53	1	1
56	1	1
59	1	1
60	1	1
61	1	1
62	1	1
			MISSING_ELSE
68	1	1
69	1	1
70	1	1
71	1	1
			MISSING_ELSE
86	1	1
89	1	1
92	1	1
93	1	1
94	1	1
95	1	1
			MISSING_ELSE
101	1	1
102	1	1
103	1	1
104	1	1
			MISSING_ELSE
117	1	1
118	1	1
120	1	1
130	1	1
131	1	1
132	1	1
142	1	1
143	1	1
144	1	1
145	1	1
146	1	1
156	1	1
157	1	1
158	1	1
159	1	1
160	1	1
171	1	1
172	1	1
182	1	1
183	1	1
			MISSING_ELSE
187	1	1
207	1	1
276	1	1
277	1	1
279	1	1
280	1	1

---

Cond Coverage for Module : prim_fifo_async ( parameter Width=24,Depth=2,OutputZeroIfEmpty=1,OutputZeroIfInvalid=0,DepthW=2,PTRV_W=1,PTR_WIDTH=2 )
Cond Coverage for Module self-instances :

SCORE	COND
92.92	80.00

tb.dut.u_spid_status.u_sw_status_update_sync

	Total	Covered	Percent
Conditions	25	20	80.00
Logical	25	20	80.00
Non-Logical	0	0
Event	0	0

 LINE       53
 EXPRESSION (wvalid_i & wready_o)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T5

 LINE       86
 EXPRESSION (rvalid_o & rready_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Covered	T1,T2,T5

 LINE       130
 EXPRESSION (fifo_wptr_q == (fifo_rptr_sync_q ^ xor_mask))
            -----------------------1----------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       131
 EXPRESSION (fifo_wptr_sync_combi == (fifo_rptr_q ^ xor_mask))
            -------------------------1------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       132
 EXPRESSION (fifo_wptr_sync_combi == fifo_rptr_q)
            ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       146
 EXPRESSION 
 Number  Term
      1  full_wclk ? (2'(Depth)) : ((g_depth_calc.wptr_msb == g_depth_calc.rptr_sync_msb) ? ((2'(g_depth_calc.wptr_value) - 2'(g_depth_calc.rptr_sync_value))) : (((2'(Depth) - 2'(g_depth_calc.rptr_sync_value)) + 2'(g_depth_calc.wptr_value)))))

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       146
 SUB-EXPRESSION 
 Number  Term
      1  (g_depth_calc.wptr_msb == g_depth_calc.rptr_sync_msb) ? ((2'(g_depth_calc.wptr_value) - 2'(g_depth_calc.rptr_sync_value))) : (((2'(Depth) - 2'(g_depth_calc.rptr_sync_value)) + 2'(g_depth_calc.wptr_value))))

-1-	Status	Tests
0	Covered	T1,T2,T5
1	Covered	T1,T2,T3

 LINE       146
 SUB-EXPRESSION (g_depth_calc.wptr_msb == g_depth_calc.rptr_sync_msb)
                --------------------------1--------------------------

-1-	Status	Tests
0	Covered	T1,T2,T5
1	Covered	T1,T2,T3

 LINE       160
 EXPRESSION 
 Number  Term
      1  full_rclk ? (2'(Depth)) : ((g_depth_calc.wptr_sync_msb == g_depth_calc.rptr_msb) ? ((2'(g_depth_calc.wptr_sync_value) - 2'(g_depth_calc.rptr_value))) : (((2'(Depth) - 2'(g_depth_calc.rptr_value)) + 2'(g_depth_calc.wptr_sync_value)))))

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       160
 SUB-EXPRESSION 
 Number  Term
      1  (g_depth_calc.wptr_sync_msb == g_depth_calc.rptr_msb) ? ((2'(g_depth_calc.wptr_sync_value) - 2'(g_depth_calc.rptr_value))) : (((2'(Depth) - 2'(g_depth_calc.rptr_value)) + 2'(g_depth_calc.wptr_sync_value))))

-1-	Status	Tests
0	Covered	T1,T2,T5
1	Covered	T1,T2,T3

 LINE       160
 SUB-EXPRESSION (g_depth_calc.wptr_sync_msb == g_depth_calc.rptr_msb)
                --------------------------1--------------------------

-1-	Status	Tests
0	Covered	T1,T2,T5
1	Covered	T1,T2,T3

 LINE       207
 EXPRESSION (empty_rclk ? '0 : rdata_int)
             -----1----

-1-	Status	Tests
0	Covered	T1,T2,T5
1	Covered	T1,T2,T3

---

Cond Coverage for Module : prim_fifo_async ( parameter Width=32,Depth=2,OutputZeroIfEmpty=1,OutputZeroIfInvalid=0,DepthW=2,PTRV_W=1,PTR_WIDTH=2 )
Cond Coverage for Module self-instances :

SCORE	COND
92.15	76.92

tb.dut.u_spi_tpm.u_cmdaddr_buffer

	Total	Covered	Percent
Conditions	26	20	76.92
Logical	26	20	76.92
Non-Logical	0	0
Event	0	0

 LINE       53
 EXPRESSION (wvalid_i & wready_o)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T5,T7,T9

 LINE       86
 EXPRESSION (rvalid_o & rready_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T5,T7,T9
1	1	Covered	T5,T7,T9

 LINE       130
 EXPRESSION (fifo_wptr_q == (fifo_rptr_sync_q ^ xor_mask))
            -----------------------1----------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       131
 EXPRESSION (fifo_wptr_sync_combi == (fifo_rptr_q ^ xor_mask))
            -------------------------1------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       132
 EXPRESSION (fifo_wptr_sync_combi == fifo_rptr_q)
            ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       146
 EXPRESSION 
 Number  Term
      1  full_wclk ? (2'(Depth)) : ((g_depth_calc.wptr_msb == g_depth_calc.rptr_sync_msb) ? ((2'(g_depth_calc.wptr_value) - 2'(g_depth_calc.rptr_sync_value))) : (((2'(Depth) - 2'(g_depth_calc.rptr_sync_value)) + 2'(g_depth_calc.wptr_value)))))

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       146
 SUB-EXPRESSION 
 Number  Term
      1  (g_depth_calc.wptr_msb == g_depth_calc.rptr_sync_msb) ? ((2'(g_depth_calc.wptr_value) - 2'(g_depth_calc.rptr_sync_value))) : (((2'(Depth) - 2'(g_depth_calc.rptr_sync_value)) + 2'(g_depth_calc.wptr_value))))

-1-	Status	Tests
0	Covered	T5,T7,T9
1	Covered	T1,T2,T3

 LINE       146
 SUB-EXPRESSION (g_depth_calc.wptr_msb == g_depth_calc.rptr_sync_msb)
                --------------------------1--------------------------

-1-	Status	Tests
0	Covered	T5,T7,T9
1	Covered	T1,T2,T3

 LINE       160
 EXPRESSION 
 Number  Term
      1  full_rclk ? (2'(Depth)) : ((g_depth_calc.wptr_sync_msb == g_depth_calc.rptr_msb) ? ((2'(g_depth_calc.wptr_sync_value) - 2'(g_depth_calc.rptr_value))) : (((2'(Depth) - 2'(g_depth_calc.rptr_value)) + 2'(g_depth_calc.wptr_sync_value)))))

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       160
 SUB-EXPRESSION 
 Number  Term
      1  (g_depth_calc.wptr_sync_msb == g_depth_calc.rptr_msb) ? ((2'(g_depth_calc.wptr_sync_value) - 2'(g_depth_calc.rptr_value))) : (((2'(Depth) - 2'(g_depth_calc.rptr_value)) + 2'(g_depth_calc.wptr_sync_value))))

-1-	Status	Tests
0	Covered	T5,T7,T9
1	Covered	T1,T2,T3

 LINE       160
 SUB-EXPRESSION (g_depth_calc.wptr_sync_msb == g_depth_calc.rptr_msb)
                --------------------------1--------------------------

-1-	Status	Tests
0	Covered	T5,T7,T9
1	Covered	T1,T2,T3

 LINE       207
 EXPRESSION (empty_rclk ? '0 : rdata_int)
             -----1----

-1-	Status	Tests
0	Covered	T5,T7,T9
1	Covered	T1,T2,T3

---

Branch Coverage for Module : prim_fifo_async

	Line No.	Total	Covered	Percent
Branches		24	22	91.67
TERNARY	146	3	2	66.67
TERNARY	160	3	2	66.67
TERNARY	207	2	2	100.00
IF	59	3	3	100.00
IF	68	3	3	100.00
IF	92	3	3	100.00
IF	101	3	3	100.00
IF	117	2	2	100.00
IF	182	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_async.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_async.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	146	(full_wclk) ? 
-2-:	146	((g_depth_calc.wptr_msb == g_depth_calc.rptr_sync_msb)) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Not Covered
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T5

	LineNo.	Expression
-1-:	160	(full_rclk) ? 
-2-:	160	((g_depth_calc.wptr_sync_msb == g_depth_calc.rptr_msb)) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Not Covered
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T5

	LineNo.	Expression
-1-:	207	(empty_rclk) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T5

	LineNo.	Expression
-1-:	59	if ((!rst_wr_ni))
-2-:	61	if (fifo_incr_wptr)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T5
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	68	if ((!rst_wr_ni))
-2-:	70	if (fifo_incr_wptr)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T5
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	92	if ((!rst_rd_ni))
-2-:	94	if (fifo_incr_rptr)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T5
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	101	if ((!rst_rd_ni))
-2-:	103	if (fifo_incr_rptr)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T5
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	117	if ((!rst_wr_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	182	if (fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T5
0	Covered	T1,T2,T3

---

Assert Coverage for Module : prim_fifo_async

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
GrayRptr_A	1585774664	1585602982	0	0
GrayWptr_A	1585774664	1585602982	0	0
ParamCheckDepth_A	3704	3704	0	0

GrayRptr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1585774664	1585602982	0	0
T1	124220	124139	0	0
T2	247925	247829	0	0
T3	6927	6847	0	0
T4	1518	1427	0	0
T5	1398088	1398080	0	0
T6	2122	2022	0	0
T7	981183	981175	0	0
T8	546683	546587	0	0
T9	445807	445800	0	0
T10	62530	62455	0	0
T11	145674	145674	0	0

GrayWptr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1585774664	1585602982	0	0
T1	124220	124139	0	0
T2	247925	247829	0	0
T3	6927	6847	0	0
T4	1518	1427	0	0
T5	1398088	1398080	0	0
T6	2122	2022	0	0
T7	981183	981175	0	0
T8	546683	546587	0	0
T9	445807	445800	0	0
T10	62530	62455	0	0
T11	145674	145674	0	0

ParamCheckDepth_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	3704	3704	0	0
T1	2	2	0	0
T2	2	2	0	0
T3	2	2	0	0
T4	2	2	0	0
T5	2	2	0	0
T6	2	2	0	0
T7	2	2	0	0
T8	2	2	0	0
T9	2	2	0	0
T10	2	2	0	0

Line Coverage for Instance : tb.dut.u_spi_tpm.u_cmdaddr_buffer

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	53	1	1	100.00
CONT_ASSIGN	56	1	1	100.00
ALWAYS	59	4	4	100.00
ALWAYS	68	4	4	100.00
CONT_ASSIGN	86	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	92	4	4	100.00
ALWAYS	101	4	4	100.00
ALWAYS	117	3	3	100.00
CONT_ASSIGN	130	1	1	100.00
CONT_ASSIGN	131	1	1	100.00
CONT_ASSIGN	132	1	1	100.00
CONT_ASSIGN	142	1	1	100.00
CONT_ASSIGN	143	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	146	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	157	1	1	100.00
CONT_ASSIGN	158	1	1	100.00
CONT_ASSIGN	159	1	1	100.00
CONT_ASSIGN	160	1	1	100.00
CONT_ASSIGN	171	1	1	100.00
CONT_ASSIGN	172	1	1	100.00
ALWAYS	182	2	2	100.00
CONT_ASSIGN	187	1	1	100.00
CONT_ASSIGN	207	1	1	100.00
CONT_ASSIGN	276	1	1	100.00
CONT_ASSIGN	277	1	1	100.00
CONT_ASSIGN	279	1	1	100.00
CONT_ASSIGN	280	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_async.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_async.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
53	1	1
56	1	1
59	1	1
60	1	1
61	1	1
62	1	1
			MISSING_ELSE
68	1	1
69	1	1
70	1	1
71	1	1
			MISSING_ELSE
86	1	1
89	1	1
92	1	1
93	1	1
94	1	1
95	1	1
			MISSING_ELSE
101	1	1
102	1	1
103	1	1
104	1	1
			MISSING_ELSE
117	1	1
118	1	1
120	1	1
130	1	1
131	1	1
132	1	1
142	1	1
143	1	1
144	1	1
145	1	1
146	1	1
156	1	1
157	1	1
158	1	1
159	1	1
160	1	1
171	1	1
172	1	1
182	1	1
183	1	1
			MISSING_ELSE
187	1	1
207	1	1
276	1	1
277	1	1
279	1	1
280	1	1

---

Cond Coverage for Instance : tb.dut.u_spi_tpm.u_cmdaddr_buffer

	Total	Covered	Percent
Conditions	26	20	76.92
Logical	26	20	76.92
Non-Logical	0	0
Event	0	0

 LINE       53
 EXPRESSION (wvalid_i & wready_o)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T5,T7,T9

 LINE       86
 EXPRESSION (rvalid_o & rready_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T5,T7,T9
1	1	Covered	T5,T7,T9

 LINE       130
 EXPRESSION (fifo_wptr_q == (fifo_rptr_sync_q ^ xor_mask))
            -----------------------1----------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       131
 EXPRESSION (fifo_wptr_sync_combi == (fifo_rptr_q ^ xor_mask))
            -------------------------1------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       132
 EXPRESSION (fifo_wptr_sync_combi == fifo_rptr_q)
            ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       146
 EXPRESSION 
 Number  Term
      1  full_wclk ? (2'(Depth)) : ((g_depth_calc.wptr_msb == g_depth_calc.rptr_sync_msb) ? ((2'(g_depth_calc.wptr_value) - 2'(g_depth_calc.rptr_sync_value))) : (((2'(Depth) - 2'(g_depth_calc.rptr_sync_value)) + 2'(g_depth_calc.wptr_value)))))

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       146
 SUB-EXPRESSION 
 Number  Term
      1  (g_depth_calc.wptr_msb == g_depth_calc.rptr_sync_msb) ? ((2'(g_depth_calc.wptr_value) - 2'(g_depth_calc.rptr_sync_value))) : (((2'(Depth) - 2'(g_depth_calc.rptr_sync_value)) + 2'(g_depth_calc.wptr_value))))

-1-	Status	Tests
0	Covered	T5,T7,T9
1	Covered	T1,T2,T3

 LINE       146
 SUB-EXPRESSION (g_depth_calc.wptr_msb == g_depth_calc.rptr_sync_msb)
                --------------------------1--------------------------

-1-	Status	Tests
0	Covered	T5,T7,T9
1	Covered	T1,T2,T3

 LINE       160
 EXPRESSION 
 Number  Term
      1  full_rclk ? (2'(Depth)) : ((g_depth_calc.wptr_sync_msb == g_depth_calc.rptr_msb) ? ((2'(g_depth_calc.wptr_sync_value) - 2'(g_depth_calc.rptr_value))) : (((2'(Depth) - 2'(g_depth_calc.rptr_value)) + 2'(g_depth_calc.wptr_sync_value)))))

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       160
 SUB-EXPRESSION 
 Number  Term
      1  (g_depth_calc.wptr_sync_msb == g_depth_calc.rptr_msb) ? ((2'(g_depth_calc.wptr_sync_value) - 2'(g_depth_calc.rptr_value))) : (((2'(Depth) - 2'(g_depth_calc.rptr_value)) + 2'(g_depth_calc.wptr_sync_value))))

-1-	Status	Tests
0	Covered	T5,T7,T9
1	Covered	T1,T2,T3

 LINE       160
 SUB-EXPRESSION (g_depth_calc.wptr_sync_msb == g_depth_calc.rptr_msb)
                --------------------------1--------------------------

-1-	Status	Tests
0	Covered	T5,T7,T9
1	Covered	T1,T2,T3

 LINE       207
 EXPRESSION (empty_rclk ? '0 : rdata_int)
             -----1----

-1-	Status	Tests
0	Covered	T5,T7,T9
1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_spi_tpm.u_cmdaddr_buffer

	Line No.	Total	Covered	Percent
Branches		24	22	91.67
TERNARY	146	3	2	66.67
TERNARY	160	3	2	66.67
TERNARY	207	2	2	100.00
IF	59	3	3	100.00
IF	68	3	3	100.00
IF	92	3	3	100.00
IF	101	3	3	100.00
IF	117	2	2	100.00
IF	182	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_async.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_async.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	146	(full_wclk) ? 
-2-:	146	((g_depth_calc.wptr_msb == g_depth_calc.rptr_sync_msb)) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Not Covered
0	1	Covered	T1,T2,T3
0	0	Covered	T5,T7,T9

	LineNo.	Expression
-1-:	160	(full_rclk) ? 
-2-:	160	((g_depth_calc.wptr_sync_msb == g_depth_calc.rptr_msb)) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Not Covered
0	1	Covered	T1,T2,T3
0	0	Covered	T5,T7,T9

	LineNo.	Expression
-1-:	207	(empty_rclk) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T5,T7,T9

	LineNo.	Expression
-1-:	59	if ((!rst_wr_ni))
-2-:	61	if (fifo_incr_wptr)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T5,T7,T9
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	68	if ((!rst_wr_ni))
-2-:	70	if (fifo_incr_wptr)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T5,T7,T9
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	92	if ((!rst_rd_ni))
-2-:	94	if (fifo_incr_rptr)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T5,T7,T9
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	101	if ((!rst_rd_ni))
-2-:	103	if (fifo_incr_rptr)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T5,T7,T9
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	117	if ((!rst_wr_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	182	if (fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T5,T7,T9
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_spi_tpm.u_cmdaddr_buffer

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
GrayRptr_A	1203785710	1203615611	0	0
GrayWptr_A	381988954	381987371	0	0
ParamCheckDepth_A	1852	1852	0	0

GrayRptr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1203785710	1203615611	0	0
T1	110812	110732	0	0
T2	208167	208072	0	0
T3	5602	5523	0	0
T4	1518	1427	0	0
T5	405811	405804	0	0
T6	1762	1663	0	0
T7	232174	232167	0	0
T8	365507	365412	0	0
T9	127203	127197	0	0
T10	42843	42769	0	0

GrayWptr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	381988954	381987371	0	0
T1	13408	13407	0	0
T2	39758	39757	0	0
T3	1325	1324	0	0
T5	992277	992276	0	0
T6	360	359	0	0
T7	749009	749008	0	0
T8	181176	181175	0	0
T9	318604	318603	0	0
T10	19687	19686	0	0
T11	145674	145674	0	0

ParamCheckDepth_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1852	1852	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_spid_status.u_sw_status_update_sync

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	53	1	1	100.00
CONT_ASSIGN	56	1	1	100.00
ALWAYS	59	4	4	100.00
ALWAYS	68	4	4	100.00
CONT_ASSIGN	86	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	92	4	4	100.00
ALWAYS	101	4	4	100.00
ALWAYS	117	3	3	100.00
CONT_ASSIGN	130	1	1	100.00
CONT_ASSIGN	131	1	1	100.00
CONT_ASSIGN	132	1	1	100.00
CONT_ASSIGN	142	1	1	100.00
CONT_ASSIGN	143	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	146	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	157	1	1	100.00
CONT_ASSIGN	158	1	1	100.00
CONT_ASSIGN	159	1	1	100.00
CONT_ASSIGN	160	1	1	100.00
CONT_ASSIGN	171	1	1	100.00
CONT_ASSIGN	172	1	1	100.00
ALWAYS	182	2	2	100.00
CONT_ASSIGN	187	1	1	100.00
CONT_ASSIGN	207	1	1	100.00
CONT_ASSIGN	276	1	1	100.00
CONT_ASSIGN	277	1	1	100.00
CONT_ASSIGN	279	1	1	100.00
CONT_ASSIGN	280	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_async.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_async.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
53	1	1
56	1	1
59	1	1
60	1	1
61	1	1
62	1	1
			MISSING_ELSE
68	1	1
69	1	1
70	1	1
71	1	1
			MISSING_ELSE
86	1	1
89	1	1
92	1	1
93	1	1
94	1	1
95	1	1
			MISSING_ELSE
101	1	1
102	1	1
103	1	1
104	1	1
			MISSING_ELSE
117	1	1
118	1	1
120	1	1
130	1	1
131	1	1
132	1	1
142	1	1
143	1	1
144	1	1
145	1	1
146	1	1
156	1	1
157	1	1
158	1	1
159	1	1
160	1	1
171	1	1
172	1	1
182	1	1
183	1	1
			MISSING_ELSE
187	1	1
207	1	1
276	1	1
277	1	1
279	1	1
280	1	1

---

Cond Coverage for Instance : tb.dut.u_spid_status.u_sw_status_update_sync

	Total	Covered	Percent
Conditions	25	20	80.00
Logical	25	20	80.00
Non-Logical	0	0
Event	0	0

 LINE       53
 EXPRESSION (wvalid_i & wready_o)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T5

 LINE       86
 EXPRESSION (rvalid_o & rready_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Covered	T1,T2,T5

 LINE       130
 EXPRESSION (fifo_wptr_q == (fifo_rptr_sync_q ^ xor_mask))
            -----------------------1----------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       131
 EXPRESSION (fifo_wptr_sync_combi == (fifo_rptr_q ^ xor_mask))
            -------------------------1------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       132
 EXPRESSION (fifo_wptr_sync_combi == fifo_rptr_q)
            ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       146
 EXPRESSION 
 Number  Term
      1  full_wclk ? (2'(Depth)) : ((g_depth_calc.wptr_msb == g_depth_calc.rptr_sync_msb) ? ((2'(g_depth_calc.wptr_value) - 2'(g_depth_calc.rptr_sync_value))) : (((2'(Depth) - 2'(g_depth_calc.rptr_sync_value)) + 2'(g_depth_calc.wptr_value)))))

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       146
 SUB-EXPRESSION 
 Number  Term
      1  (g_depth_calc.wptr_msb == g_depth_calc.rptr_sync_msb) ? ((2'(g_depth_calc.wptr_value) - 2'(g_depth_calc.rptr_sync_value))) : (((2'(Depth) - 2'(g_depth_calc.rptr_sync_value)) + 2'(g_depth_calc.wptr_value))))

-1-	Status	Tests
0	Covered	T1,T2,T5
1	Covered	T1,T2,T3

 LINE       146
 SUB-EXPRESSION (g_depth_calc.wptr_msb == g_depth_calc.rptr_sync_msb)
                --------------------------1--------------------------

-1-	Status	Tests
0	Covered	T1,T2,T5
1	Covered	T1,T2,T3

 LINE       160
 EXPRESSION 
 Number  Term
      1  full_rclk ? (2'(Depth)) : ((g_depth_calc.wptr_sync_msb == g_depth_calc.rptr_msb) ? ((2'(g_depth_calc.wptr_sync_value) - 2'(g_depth_calc.rptr_value))) : (((2'(Depth) - 2'(g_depth_calc.rptr_value)) + 2'(g_depth_calc.wptr_sync_value)))))

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       160
 SUB-EXPRESSION 
 Number  Term
      1  (g_depth_calc.wptr_sync_msb == g_depth_calc.rptr_msb) ? ((2'(g_depth_calc.wptr_sync_value) - 2'(g_depth_calc.rptr_value))) : (((2'(Depth) - 2'(g_depth_calc.rptr_value)) + 2'(g_depth_calc.wptr_sync_value))))

-1-	Status	Tests
0	Covered	T1,T2,T5
1	Covered	T1,T2,T3

 LINE       160
 SUB-EXPRESSION (g_depth_calc.wptr_sync_msb == g_depth_calc.rptr_msb)
                --------------------------1--------------------------

-1-	Status	Tests
0	Covered	T1,T2,T5
1	Covered	T1,T2,T3

 LINE       207
 EXPRESSION (empty_rclk ? '0 : rdata_int)
             -----1----

-1-	Status	Tests
0	Covered	T1,T2,T5
1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_spid_status.u_sw_status_update_sync

	Line No.	Total	Covered	Percent
Branches		24	22	91.67
TERNARY	146	3	2	66.67
TERNARY	160	3	2	66.67
TERNARY	207	2	2	100.00
IF	59	3	3	100.00
IF	68	3	3	100.00
IF	92	3	3	100.00
IF	101	3	3	100.00
IF	117	2	2	100.00
IF	182	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_async.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_async.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	146	(full_wclk) ? 
-2-:	146	((g_depth_calc.wptr_msb == g_depth_calc.rptr_sync_msb)) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Not Covered
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T5

	LineNo.	Expression
-1-:	160	(full_rclk) ? 
-2-:	160	((g_depth_calc.wptr_sync_msb == g_depth_calc.rptr_msb)) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Not Covered
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T5

	LineNo.	Expression
-1-:	207	(empty_rclk) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T5

	LineNo.	Expression
-1-:	59	if ((!rst_wr_ni))
-2-:	61	if (fifo_incr_wptr)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T5
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	68	if ((!rst_wr_ni))
-2-:	70	if (fifo_incr_wptr)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T5
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	92	if ((!rst_rd_ni))
-2-:	94	if (fifo_incr_rptr)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T5
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	101	if ((!rst_rd_ni))
-2-:	103	if (fifo_incr_rptr)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T5
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	117	if ((!rst_wr_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	182	if (fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T5
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_spid_status.u_sw_status_update_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
GrayRptr_A	381988954	381987371	0	0
GrayWptr_A	1203785710	1203615611	0	0
ParamCheckDepth_A	1852	1852	0	0

GrayRptr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	381988954	381987371	0	0
T1	13408	13407	0	0
T2	39758	39757	0	0
T3	1325	1324	0	0
T5	992277	992276	0	0
T6	360	359	0	0
T7	749009	749008	0	0
T8	181176	181175	0	0
T9	318604	318603	0	0
T10	19687	19686	0	0
T11	145674	145674	0	0

GrayWptr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1203785710	1203615611	0	0
T1	110812	110732	0	0
T2	208167	208072	0	0
T3	5602	5523	0	0
T4	1518	1427	0	0
T5	405811	405804	0	0
T6	1762	1663	0	0
T7	232174	232167	0	0
T8	365507	365412	0	0
T9	127203	127197	0	0
T10	42843	42769	0	0

ParamCheckDepth_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1852	1852	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0