Line Coverage for Module :
spid_status
| Line No. | Total | Covered | Percent |
TOTAL | | 65 | 65 | 100.00 |
CONT_ASSIGN | 87 | 1 | 1 | 100.00 |
CONT_ASSIGN | 90 | 1 | 1 | 100.00 |
ALWAYS | 158 | 6 | 6 | 100.00 |
ALWAYS | 169 | 8 | 8 | 100.00 |
ALWAYS | 182 | 4 | 4 | 100.00 |
ALWAYS | 194 | 7 | 7 | 100.00 |
CONT_ASSIGN | 216 | 1 | 1 | 100.00 |
CONT_ASSIGN | 217 | 1 | 1 | 100.00 |
CONT_ASSIGN | 232 | 1 | 1 | 100.00 |
ALWAYS | 255 | 3 | 3 | 100.00 |
CONT_ASSIGN | 261 | 1 | 1 | 100.00 |
ALWAYS | 292 | 4 | 4 | 100.00 |
ALWAYS | 305 | 5 | 5 | 100.00 |
ALWAYS | 319 | 3 | 3 | 100.00 |
ALWAYS | 327 | 6 | 6 | 100.00 |
CONT_ASSIGN | 341 | 1 | 1 | 100.00 |
ALWAYS | 348 | 3 | 3 | 100.00 |
ALWAYS | 353 | 9 | 9 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_spi_device_0.1/rtl/spid_status.sv' or '../src/lowrisc_ip_spi_device_0.1/rtl/spid_status.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
87 |
1 |
1 |
90 |
1 |
1 |
158 |
1 |
1 |
159 |
1 |
1 |
160 |
1 |
1 |
161 |
1 |
1 |
162 |
1 |
1 |
163 |
1 |
1 |
|
|
|
MISSING_ELSE |
169 |
1 |
1 |
170 |
1 |
1 |
171 |
1 |
1 |
172 |
1 |
1 |
173 |
1 |
1 |
174 |
1 |
1 |
175 |
1 |
1 |
176 |
1 |
1 |
|
|
|
MISSING_ELSE |
182 |
1 |
1 |
183 |
1 |
1 |
184 |
1 |
1 |
185 |
1 |
1 |
|
|
|
MISSING_ELSE |
194 |
1 |
1 |
195 |
1 |
1 |
196 |
1 |
1 |
197 |
1 |
1 |
198 |
1 |
1 |
|
|
|
MISSING_ELSE |
200 |
1 |
1 |
201 |
1 |
1 |
|
|
|
MISSING_ELSE |
216 |
1 |
1 |
217 |
1 |
1 |
232 |
1 |
1 |
255 |
1 |
1 |
256 |
1 |
1 |
258 |
1 |
1 |
261 |
1 |
1 |
292 |
1 |
1 |
293 |
1 |
1 |
294 |
1 |
1 |
295 |
1 |
1 |
|
|
|
MISSING_ELSE |
305 |
1 |
1 |
306 |
1 |
1 |
307 |
1 |
1 |
309 |
1 |
1 |
310 |
1 |
1 |
319 |
1 |
1 |
320 |
1 |
1 |
322 |
1 |
1 |
327 |
1 |
1 |
329 |
1 |
1 |
331 |
1 |
1 |
333 |
1 |
1 |
334 |
1 |
1 |
335 |
1 |
1 |
|
|
|
MISSING_ELSE |
|
|
|
MISSING_ELSE |
341 |
1 |
1 |
348 |
2 |
2 |
349 |
1 |
1 |
353 |
1 |
1 |
355 |
1 |
1 |
357 |
1 |
1 |
359 |
1 |
1 |
361 |
1 |
1 |
362 |
1 |
1 |
364 |
1 |
1 |
365 |
1 |
1 |
|
|
|
MISSING_ELSE |
370 |
1 |
1 |
Cond Coverage for Module :
spid_status
| Total | Covered | Percent |
Conditions | 21 | 21 | 100.00 |
Logical | 21 | 21 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 162
EXPRESSION (sck_sw_we && (sck_sw_status[BitBusy] == 1'b0))
----1---- ----------------2---------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T5 |
1 | 1 | Covered | T2,T5,T7 |
LINE 162
SUB-EXPRESSION (sck_sw_status[BitBusy] == 1'b0)
----------------1---------------
-1- | Status | Tests |
0 | Covered | T1,T2,T5 |
1 | Covered | T1,T2,T3 |
LINE 175
EXPRESSION (sck_sw_we && (sck_sw_status[BitWe] == 1'b0))
----1---- ---------------2--------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T5 |
1 | 1 | Covered | T1,T2,T5 |
LINE 175
SUB-EXPRESSION (sck_sw_status[BitWe] == 1'b0)
---------------1--------------
-1- | Status | Tests |
0 | Covered | T1,T2,T5 |
1 | Covered | T1,T2,T3 |
LINE 261
EXPRESSION (sys_rst_ni & status_fifo_clr_n)
-----1---- --------2--------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T28,T48,T49 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 334
EXPRESSION (cmd_info_idx_i == 5'(StatusCmdIdx[i]))
-------------------1-------------------
-1- | Status | Tests |
0 | Covered | T5,T7,T9 |
1 | Covered | T5,T7,T9 |
LINE 341
EXPRESSION ((st_q == StIdle) ? sck_status_committed[(8 * byte_sel_d)+:8] : sck_status_committed[(8 * byte_sel_q)+:8])
--------1-------
-1- | Status | Tests |
0 | Covered | T5,T7,T9 |
1 | Covered | T1,T2,T3 |
LINE 341
SUB-EXPRESSION (st_q == StIdle)
--------1-------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 361
EXPRESSION (sel_dp_i == DpReadStatus)
-------------1------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T5,T7,T9 |
Branch Coverage for Module :
spid_status
| Line No. | Total | Covered | Percent |
Branches |
|
36 |
35 |
97.22 |
TERNARY |
341 |
2 |
2 |
100.00 |
IF |
158 |
4 |
4 |
100.00 |
IF |
169 |
5 |
5 |
100.00 |
IF |
182 |
3 |
3 |
100.00 |
IF |
195 |
3 |
3 |
100.00 |
IF |
200 |
2 |
2 |
100.00 |
IF |
255 |
2 |
2 |
100.00 |
IF |
292 |
3 |
3 |
100.00 |
IF |
305 |
2 |
2 |
100.00 |
IF |
319 |
2 |
2 |
100.00 |
IF |
329 |
2 |
2 |
100.00 |
IF |
348 |
2 |
2 |
100.00 |
CASE |
359 |
4 |
3 |
75.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_spi_device_0.1/rtl/spid_status.sv' or '../src/lowrisc_ip_spi_device_0.1/rtl/spid_status.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 341 ((st_q == StIdle)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T5,T7,T9 |
LineNo. Expression
-1-: 158 if ((!sys_rst_ni))
-2-: 160 if (inclk_busy_set_i)
-3-: 162 if ((sck_sw_we && (sck_sw_status[BitBusy] == 1'b0)))
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T1,T2,T3 |
0 |
1 |
- |
Covered |
T5,T7,T9 |
0 |
0 |
1 |
Covered |
T2,T5,T7 |
0 |
0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 169 if ((!sys_rst_ni))
-2-: 171 if (inclk_we_set_i)
-3-: 173 if (inclk_we_clr_i)
-4-: 175 if ((sck_sw_we && (sck_sw_status[BitWe] == 1'b0)))
Branches:
-1- | -2- | -3- | -4- | Status | Tests |
1 |
- |
- |
- |
Covered |
T1,T2,T3 |
0 |
1 |
- |
- |
Covered |
T5,T7,T9 |
0 |
0 |
1 |
- |
Covered |
T5,T7,T9 |
0 |
0 |
0 |
1 |
Covered |
T1,T2,T5 |
0 |
0 |
0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 182 if ((!sys_rst_ni))
-2-: 184 if (sck_sw_we)
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T1,T2,T3 |
0 |
1 |
Covered |
T1,T2,T5 |
0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 195 if (inclk_we_set_i)
-2-: 197 if (inclk_we_clr_i)
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T5,T7,T9 |
0 |
1 |
Covered |
T5,T7,T9 |
0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 200 if (inclk_busy_set_i)
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T7,T9 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 255 if ((!sys_rst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 292 if ((!sys_rst_ni))
-2-: 294 if (sys_csb_deasserted_pulse_i)
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T1,T2,T3 |
0 |
1 |
Covered |
T1,T2,T5 |
0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 305 if ((!rst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T5 |
LineNo. Expression
-1-: 319 if ((!rst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T5 |
LineNo. Expression
-1-: 329 if (byte_sel_update)
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T7,T9 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 348 if ((!rst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T5 |
LineNo. Expression
-1-: 359 case (st_q)
-2-: 361 if ((sel_dp_i == DpReadStatus))
Branches:
-1- | -2- | Status | Tests |
StIdle |
1 |
Covered |
T5,T7,T9 |
StIdle |
0 |
Covered |
T1,T2,T3 |
StActive |
- |
Covered |
T5,T7,T9 |
default |
- |
Not Covered |
|
Assert Coverage for Module :
spid_status
Assertion Details
Name | Attempts | Real Successes | Failures | Incomplete |
BusyBitZero_A |
1852 |
1852 |
0 |
0 |
BusyBitZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1852 |
1852 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T3 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T8 |
1 |
1 |
0 |
0 |
T9 |
1 |
1 |
0 |
0 |
T10 |
1 |
1 |
0 |
0 |