Module Definition
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Module : spi_s2p
SCORELINECONDTOGGLEFSMBRANCHASSERT
86.75 100.00 78.57 68.42 100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_spi_device_0.1/rtl/spi_s2p.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.u_s2p 86.75 100.00 78.57 68.42 100.00



Module Instance : tb.dut.u_s2p

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
86.75 100.00 78.57 68.42 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
86.75 100.00 78.57 68.42 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
91.69 94.25 84.31 96.94 87.50 95.45 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Since this is the module's only instance, the coverage report is the same as for the module.
Line Coverage for Module : spi_s2p
Line No.TotalCoveredPercent
TOTAL2020100.00
ALWAYS4344100.00
ALWAYS6333100.00
CONT_ASSIGN7111100.00
ALWAYS7588100.00
ALWAYS9144100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_spi_device_0.1/rtl/spi_s2p.sv' or '../src/lowrisc_ip_spi_device_0.1/rtl/spi_s2p.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
43 1 1
45 1 1
49 1 1
53 1 1
63 1 1
64 1 1
66 1 1
71 1 1
75 1 1
76 1 1
77 1 1
78 1 1
80 1 1
81 1 1
82 1 1
83 1 1
91 1 1
92 1 1
93 1 1
94 1 1


Cond Coverage for Module : spi_s2p
TotalCoveredPercent
Conditions141178.57
Logical141178.57
Non-Logical00
Event00

 LINE       45
 EXPRESSION (order_i ? ({s_i[0], data_q[7:1]}) : ({data_q[6:0], s_i[0]}))
             ---1---
-1-StatusTests
0CoveredT1,T2,T3
1Not Covered

 LINE       49
 EXPRESSION (order_i ? ({s_i[1:0], data_q[7:2]}) : ({data_q[5:0], s_i[1:0]}))
             ---1---
-1-StatusTests
0CoveredT1,T5,T7
1Not Covered

 LINE       53
 EXPRESSION (order_i ? ({s_i[3:0], data_q[7:4]}) : ({data_q[3:0], s_i[3:0]}))
             ---1---
-1-StatusTests
0CoveredT1,T2,T5
1Not Covered

 LINE       77
 EXPRESSION (cnt == '0)
            -----1-----
-1-StatusTests
0CoveredT1,T2,T5
1CoveredT1,T2,T5

 LINE       92
 EXPRESSION (cnt == 3'b0)
            ------1------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T5

 LINE       93
 EXPRESSION (cnt == 3'b1)
            ------1------
-1-StatusTests
0CoveredT1,T5,T7
1CoveredT1,T5,T7

 LINE       94
 EXPRESSION (cnt == 3'h3)
            ------1------
-1-StatusTests
0CoveredT1,T2,T5
1CoveredT1,T2,T5

Branch Coverage for Module : spi_s2p
Line No.TotalCoveredPercent
Branches 19 13 68.42
CASE 43 7 3 42.86
IF 63 2 2 100.00
IF 75 6 5 83.33
CASE 91 4 3 75.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_spi_device_0.1/rtl/spi_s2p.sv' or '../src/lowrisc_ip_spi_device_0.1/rtl/spi_s2p.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 43 case (io_mode_i) -2-: 45 (order_i) ? -3-: 49 (order_i) ? -4-: 53 (order_i) ?

Branches:
-1--2--3--4-StatusTests
SingleIO 1 - - Not Covered
SingleIO 0 - - Covered T1,T2,T3
DualIO - 1 - Not Covered
DualIO - 0 - Covered T1,T5,T7
QuadIO - - 1 Not Covered
QuadIO - - 0 Covered T1,T2,T5
default - - - Not Covered


LineNo. Expression -1-: 63 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T5


LineNo. Expression -1-: 75 if ((!rst_ni)) -2-: 77 if ((cnt == '0)) -3-: 80 case (io_mode_i)

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T2,T3
0 1 - Covered T1,T2,T5
0 0 SingleIO Covered T1,T2,T5
0 0 DualIO Covered T1,T5,T7
0 0 QuadIO Covered T1,T2,T5
0 0 default Not Covered


LineNo. Expression -1-: 91 case (io_mode_i)

Branches:
-1-StatusTests
SingleIO Covered T1,T2,T3
DualIO Covered T1,T5,T7
QuadIO Covered T1,T2,T5
default Not Covered


Assert Coverage for Module : spi_s2p
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
IoModeDefault_A 381988954 58882 0 0


IoModeDefault_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 381988954 58882 0 0
T1 13408 1 0 0
T2 39758 6 0 0
T3 1325 0 0 0
T5 992277 59 0 0
T6 360 0 0 0
T7 749009 153 0 0
T8 181176 1 0 0
T9 318604 138 0 0
T10 19687 1 0 0
T11 145674 104 0 0
T12 0 2 0 0
T13 0 4 0 0

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%