Line Coverage for Module :
prim_fifo_async_sram_adapter ( parameter Width=16,Depth=16,SramAw=10,SramDw=32,SramBaseAddr=960,DepthW=5,PtrVW=4,PtrW=5 )
Line Coverage for Module self-instances :
| Line No. | Total | Covered | Percent |
TOTAL | | 86 | 86 | 100.00 |
CONT_ASSIGN | 121 | 1 | 1 | 100.00 |
CONT_ASSIGN | 123 | 1 | 1 | 100.00 |
ALWAYS | 126 | 6 | 6 | 100.00 |
CONT_ASSIGN | 135 | 1 | 1 | 100.00 |
CONT_ASSIGN | 136 | 1 | 1 | 100.00 |
CONT_ASSIGN | 138 | 1 | 1 | 100.00 |
CONT_ASSIGN | 149 | 1 | 1 | 100.00 |
CONT_ASSIGN | 150 | 1 | 1 | 100.00 |
CONT_ASSIGN | 151 | 1 | 1 | 100.00 |
CONT_ASSIGN | 153 | 1 | 1 | 100.00 |
CONT_ASSIGN | 163 | 1 | 1 | 100.00 |
CONT_ASSIGN | 165 | 1 | 1 | 100.00 |
ALWAYS | 168 | 6 | 6 | 100.00 |
CONT_ASSIGN | 177 | 1 | 1 | 100.00 |
CONT_ASSIGN | 178 | 1 | 1 | 100.00 |
CONT_ASSIGN | 180 | 1 | 1 | 100.00 |
CONT_ASSIGN | 191 | 1 | 1 | 100.00 |
CONT_ASSIGN | 192 | 1 | 1 | 100.00 |
CONT_ASSIGN | 193 | 1 | 1 | 100.00 |
CONT_ASSIGN | 195 | 1 | 1 | 100.00 |
CONT_ASSIGN | 201 | 1 | 1 | 100.00 |
ALWAYS | 204 | 4 | 4 | 100.00 |
CONT_ASSIGN | 211 | 1 | 1 | 100.00 |
CONT_ASSIGN | 217 | 1 | 1 | 100.00 |
CONT_ASSIGN | 218 | 1 | 1 | 100.00 |
CONT_ASSIGN | 219 | 1 | 1 | 100.00 |
CONT_ASSIGN | 222 | 1 | 1 | 100.00 |
CONT_ASSIGN | 224 | 1 | 1 | 100.00 |
CONT_ASSIGN | 225 | 1 | 1 | 100.00 |
CONT_ASSIGN | 245 | 1 | 1 | 100.00 |
CONT_ASSIGN | 247 | 1 | 1 | 100.00 |
CONT_ASSIGN | 248 | 1 | 1 | 100.00 |
CONT_ASSIGN | 251 | 1 | 1 | 100.00 |
CONT_ASSIGN | 252 | 1 | 1 | 100.00 |
CONT_ASSIGN | 254 | 1 | 1 | 100.00 |
CONT_ASSIGN | 256 | 1 | 1 | 100.00 |
CONT_ASSIGN | 260 | 1 | 1 | 100.00 |
ALWAYS | 270 | 4 | 4 | 100.00 |
CONT_ASSIGN | 291 | 1 | 1 | 100.00 |
CONT_ASSIGN | 297 | 1 | 1 | 100.00 |
CONT_ASSIGN | 299 | 1 | 1 | 100.00 |
CONT_ASSIGN | 301 | 1 | 1 | 100.00 |
CONT_ASSIGN | 304 | 1 | 1 | 100.00 |
CONT_ASSIGN | 308 | 1 | 1 | 100.00 |
CONT_ASSIGN | 321 | 1 | 1 | 100.00 |
ALWAYS | 324 | 9 | 9 | 100.00 |
ROUTINE | 347 | 7 | 7 | 100.00 |
ROUTINE | 368 | 9 | 9 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_async_sram_adapter.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_async_sram_adapter.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
121 |
1 |
1 |
123 |
1 |
1 |
126 |
1 |
1 |
127 |
1 |
1 |
128 |
1 |
1 |
129 |
1 |
1 |
130 |
1 |
1 |
131 |
1 |
1 |
|
|
|
MISSING_ELSE |
135 |
1 |
1 |
136 |
1 |
1 |
138 |
1 |
1 |
149 |
1 |
1 |
150 |
1 |
1 |
151 |
1 |
1 |
153 |
1 |
1 |
163 |
1 |
1 |
165 |
1 |
1 |
168 |
1 |
1 |
169 |
1 |
1 |
170 |
1 |
1 |
171 |
1 |
1 |
172 |
1 |
1 |
173 |
1 |
1 |
|
|
|
MISSING_ELSE |
177 |
1 |
1 |
178 |
1 |
1 |
180 |
1 |
1 |
191 |
1 |
1 |
192 |
1 |
1 |
193 |
1 |
1 |
195 |
1 |
1 |
201 |
1 |
1 |
204 |
1 |
1 |
205 |
1 |
1 |
206 |
1 |
1 |
207 |
1 |
1 |
|
|
|
MISSING_ELSE |
211 |
1 |
1 |
217 |
1 |
1 |
218 |
1 |
1 |
219 |
1 |
1 |
222 |
1 |
1 |
224 |
1 |
1 |
225 |
1 |
1 |
245 |
1 |
1 |
247 |
1 |
1 |
248 |
1 |
1 |
251 |
1 |
1 |
252 |
1 |
1 |
254 |
1 |
1 |
256 |
1 |
1 |
260 |
1 |
1 |
270 |
1 |
1 |
279 |
1 |
1 |
282 |
1 |
1 |
287 |
1 |
1 |
291 |
1 |
1 |
297 |
1 |
1 |
299 |
1 |
1 |
301 |
1 |
1 |
304 |
1 |
1 |
308 |
1 |
1 |
321 |
1 |
1 |
324 |
1 |
1 |
325 |
1 |
1 |
326 |
1 |
1 |
327 |
1 |
1 |
328 |
1 |
1 |
329 |
1 |
1 |
330 |
1 |
1 |
332 |
1 |
1 |
333 |
1 |
1 |
|
|
|
MISSING_ELSE |
347 |
1 |
1 |
349 |
1 |
1 |
352 |
1 |
1 |
353 |
1 |
1 |
356 |
1 |
1 |
357 |
1 |
1 |
360 |
1 |
1 |
368 |
1 |
1 |
369 |
1 |
1 |
370 |
1 |
1 |
372 |
1 |
1 |
373 |
1 |
1 |
374 |
1 |
1 |
376 |
1 |
1 |
377 |
1 |
1 |
379 |
1 |
1 |
Line Coverage for Module :
prim_fifo_async_sram_adapter ( parameter Width=32,Depth=16,SramAw=10,SramDw=32,SramBaseAddr=976,DepthW=5,PtrVW=4,PtrW=5 )
Line Coverage for Module self-instances :
| Line No. | Total | Covered | Percent |
TOTAL | | 85 | 85 | 100.00 |
CONT_ASSIGN | 121 | 1 | 1 | 100.00 |
CONT_ASSIGN | 123 | 1 | 1 | 100.00 |
ALWAYS | 126 | 6 | 6 | 100.00 |
CONT_ASSIGN | 135 | 1 | 1 | 100.00 |
CONT_ASSIGN | 136 | 1 | 1 | 100.00 |
CONT_ASSIGN | 138 | 1 | 1 | 100.00 |
CONT_ASSIGN | 149 | 1 | 1 | 100.00 |
CONT_ASSIGN | 150 | 1 | 1 | 100.00 |
CONT_ASSIGN | 151 | 1 | 1 | 100.00 |
CONT_ASSIGN | 153 | 1 | 1 | 100.00 |
CONT_ASSIGN | 163 | 1 | 1 | 100.00 |
CONT_ASSIGN | 165 | 1 | 1 | 100.00 |
ALWAYS | 168 | 6 | 6 | 100.00 |
CONT_ASSIGN | 177 | 1 | 1 | 100.00 |
CONT_ASSIGN | 178 | 1 | 1 | 100.00 |
CONT_ASSIGN | 180 | 1 | 1 | 100.00 |
CONT_ASSIGN | 191 | 1 | 1 | 100.00 |
CONT_ASSIGN | 192 | 1 | 1 | 100.00 |
CONT_ASSIGN | 193 | 1 | 1 | 100.00 |
CONT_ASSIGN | 195 | 1 | 1 | 100.00 |
CONT_ASSIGN | 201 | 1 | 1 | 100.00 |
ALWAYS | 204 | 4 | 4 | 100.00 |
CONT_ASSIGN | 211 | 1 | 1 | 100.00 |
CONT_ASSIGN | 217 | 1 | 1 | 100.00 |
CONT_ASSIGN | 218 | 1 | 1 | 100.00 |
CONT_ASSIGN | 219 | 1 | 1 | 100.00 |
CONT_ASSIGN | 222 | 1 | 1 | 100.00 |
CONT_ASSIGN | 224 | 1 | 1 | 100.00 |
CONT_ASSIGN | 225 | 1 | 1 | 100.00 |
CONT_ASSIGN | 245 | 1 | 1 | 100.00 |
CONT_ASSIGN | 247 | 1 | 1 | 100.00 |
CONT_ASSIGN | 248 | 1 | 1 | 100.00 |
CONT_ASSIGN | 251 | 1 | 1 | 100.00 |
CONT_ASSIGN | 252 | 1 | 1 | 100.00 |
CONT_ASSIGN | 254 | 1 | 1 | 100.00 |
CONT_ASSIGN | 256 | 1 | 1 | 100.00 |
CONT_ASSIGN | 260 | 1 | 1 | 100.00 |
ALWAYS | 270 | 4 | 4 | 100.00 |
CONT_ASSIGN | 291 | 1 | 1 | 100.00 |
CONT_ASSIGN | 297 | 1 | 1 | 100.00 |
CONT_ASSIGN | 299 | 1 | 1 | 100.00 |
CONT_ASSIGN | 301 | 1 | 1 | 100.00 |
CONT_ASSIGN | 304 | 1 | 1 | 100.00 |
CONT_ASSIGN | 321 | 1 | 1 | 100.00 |
ALWAYS | 324 | 9 | 9 | 100.00 |
ROUTINE | 347 | 7 | 7 | 100.00 |
ROUTINE | 368 | 9 | 9 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_async_sram_adapter.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_async_sram_adapter.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
121 |
1 |
1 |
123 |
1 |
1 |
126 |
1 |
1 |
127 |
1 |
1 |
128 |
1 |
1 |
129 |
1 |
1 |
130 |
1 |
1 |
131 |
1 |
1 |
|
|
|
MISSING_ELSE |
135 |
1 |
1 |
136 |
1 |
1 |
138 |
1 |
1 |
149 |
1 |
1 |
150 |
1 |
1 |
151 |
1 |
1 |
153 |
1 |
1 |
163 |
1 |
1 |
165 |
1 |
1 |
168 |
1 |
1 |
169 |
1 |
1 |
170 |
1 |
1 |
171 |
1 |
1 |
172 |
1 |
1 |
173 |
1 |
1 |
|
|
|
MISSING_ELSE |
177 |
1 |
1 |
178 |
1 |
1 |
180 |
1 |
1 |
191 |
1 |
1 |
192 |
1 |
1 |
193 |
1 |
1 |
195 |
1 |
1 |
201 |
1 |
1 |
204 |
1 |
1 |
205 |
1 |
1 |
206 |
1 |
1 |
207 |
1 |
1 |
|
|
|
MISSING_ELSE |
211 |
1 |
1 |
217 |
1 |
1 |
218 |
1 |
1 |
219 |
1 |
1 |
222 |
1 |
1 |
224 |
1 |
1 |
225 |
1 |
1 |
245 |
1 |
1 |
247 |
1 |
1 |
248 |
1 |
1 |
251 |
1 |
1 |
252 |
1 |
1 |
254 |
1 |
1 |
256 |
1 |
1 |
260 |
1 |
1 |
270 |
1 |
1 |
279 |
1 |
1 |
282 |
1 |
1 |
287 |
1 |
1 |
291 |
1 |
1 |
297 |
1 |
1 |
299 |
1 |
1 |
301 |
1 |
1 |
304 |
1 |
1 |
321 |
1 |
1 |
324 |
1 |
1 |
325 |
1 |
1 |
326 |
1 |
1 |
327 |
1 |
1 |
328 |
1 |
1 |
329 |
1 |
1 |
330 |
1 |
1 |
332 |
1 |
1 |
333 |
1 |
1 |
|
|
|
MISSING_ELSE |
347 |
1 |
1 |
349 |
1 |
1 |
352 |
1 |
1 |
353 |
1 |
1 |
356 |
1 |
1 |
357 |
1 |
1 |
360 |
1 |
1 |
368 |
1 |
1 |
369 |
1 |
1 |
370 |
1 |
1 |
372 |
1 |
1 |
373 |
1 |
1 |
374 |
1 |
1 |
376 |
1 |
1 |
377 |
1 |
1 |
379 |
1 |
1 |
Cond Coverage for Module :
prim_fifo_async_sram_adapter ( parameter Width=16,Depth=16,SramAw=10,SramDw=32,SramBaseAddr=960,DepthW=5,PtrVW=4,PtrW=5 )
Cond Coverage for Module self-instances :
| Total | Covered | Percent |
Conditions | 68 | 51 | 75.00 |
Logical | 68 | 51 | 75.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 121
EXPRESSION (wvalid_i & wready_o)
----1--- ----2---
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Not Covered | |
1 | 1 | Covered | T5,T7,T9 |
LINE 153
EXPRESSION ((w_wptr_p == w_rptr_p) ? (5'((w_wptr_v - w_rptr_v))) : (5'(({1'b1, w_wptr_v} - {1'b0, w_rptr_v}))))
-----------1----------
-1- | Status | Tests |
0 | Covered | T5,T7,T11 |
1 | Covered | T1,T2,T3 |
LINE 153
SUB-EXPRESSION (w_wptr_p == w_rptr_p)
-----------1----------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 195
EXPRESSION ((r_wptr_p == r_rptr_p) ? (5'((r_wptr_v - r_rptr_v))) : (5'(({1'b1, r_wptr_v} - {1'b0, r_rptr_v}))))
-----------1----------
-1- | Status | Tests |
0 | Covered | T5,T7,T11 |
1 | Covered | T1,T2,T3 |
LINE 195
SUB-EXPRESSION (r_wptr_p == r_rptr_p)
-----------1----------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 211
EXPRESSION (r_wptr == r_sram_rptr)
-----------1-----------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 217
EXPRESSION (w_wptr_q == (w_rptr ^ XorMask))
----------------1---------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Not Covered | |
LINE 218
EXPRESSION (r_wptr == (r_rptr_q ^ XorMask))
----------------1---------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Not Covered | |
LINE 219
EXPRESSION (r_wptr == r_rptr_q)
----------1---------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 247
EXPRESSION (r_sram_req_o && r_sram_gnt_i)
------1----- ------2-----
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Not Covered | |
1 | 1 | Covered | T5,T7,T9 |
LINE 248
EXPRESSION (rvalid_o && rready_i)
----1--- ----2---
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T5,T7,T9 |
1 | 1 | Covered | T5,T7,T9 |
LINE 251
EXPRESSION (wvalid_i && ((!w_full)))
----1--- -----2-----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
1 | 1 | Covered | T5,T7,T9 |
LINE 252
EXPRESSION (((!w_full)) && w_sram_gnt_i)
-----1----- ------2-----
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T5,T7,T9 |
LINE 282
EXPRESSION (((!r_sramrptr_empty)) && rfifo_ack)
----------1---------- ----2----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T5,T7,T9 |
1 | 0 | Not Covered | |
1 | 1 | Not Covered | |
LINE 287
EXPRESSION (((!r_sramrptr_empty)) && ( ! (r_sram_rvalid_i ^ rfifo_ack) ))
----------1---------- -----------------2-----------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
1 | 1 | Covered | T5,T7,T9 |
LINE 287
SUB-EXPRESSION ( ! (r_sram_rvalid_i ^ rfifo_ack) )
--------------1--------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T5,T7,T9 |
LINE 287
SUB-EXPRESSION (r_sram_rvalid_i ^ rfifo_ack)
-------1------- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Not Covered | |
1 | 0 | Covered | T5,T7,T9 |
1 | 1 | Not Covered | |
LINE 291
EXPRESSION (stored || r_sram_rvalid_i)
---1-- -------2-------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T5,T7,T9 |
1 | 0 | Covered | T5,T7,T9 |
LINE 299
EXPRESSION (r_sram_rvalid_i ? r_sram_rdata_i[0+:Width] : (16'(0)))
-------1-------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T5,T7,T9 |
LINE 301
EXPRESSION (stored ? rdata_q : rdata_d)
---1--
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T5,T7,T9 |
LINE 321
EXPRESSION (r_sram_rvalid_i && ( ! (stored ^ rfifo_ack) ))
-------1------- -------------2------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
1 | 1 | Covered | T5,T7,T9 |
LINE 321
SUB-EXPRESSION ( ! (stored ^ rfifo_ack) )
----------1---------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T5,T7,T9 |
LINE 321
SUB-EXPRESSION (stored ^ rfifo_ack)
---1-- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Not Covered | |
1 | 0 | Covered | T5,T7,T9 |
1 | 1 | Covered | T5,T7,T9 |
LINE 330
EXPRESSION (((!r_sram_rvalid_i)) && rfifo_ack)
----------1--------- ----2----
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T5,T7,T9 |
LINE 349
EXPRESSION (decval[(PtrW - 1)] ? decval_sub : decval)
---------1--------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T5,T7,T11 |
LINE 370
EXPRESSION (dec_tmp[(i + 1)] ^ grayval[i])
--------1------- -----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T5,T7,T9 |
1 | 0 | Covered | T5,T7,T9 |
1 | 1 | Covered | T5,T7,T9 |
Cond Coverage for Module :
prim_fifo_async_sram_adapter ( parameter Width=32,Depth=16,SramAw=10,SramDw=32,SramBaseAddr=976,DepthW=5,PtrVW=4,PtrW=5 )
Cond Coverage for Module self-instances :
| Total | Covered | Percent |
Conditions | 68 | 51 | 75.00 |
Logical | 68 | 51 | 75.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 121
EXPRESSION (wvalid_i & wready_o)
----1--- ----2---
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Not Covered | |
1 | 1 | Covered | T5,T7,T9 |
LINE 153
EXPRESSION ((w_wptr_p == w_rptr_p) ? (5'((w_wptr_v - w_rptr_v))) : (5'(({1'b1, w_wptr_v} - {1'b0, w_rptr_v}))))
-----------1----------
-1- | Status | Tests |
0 | Covered | T7,T11,T15 |
1 | Covered | T1,T2,T3 |
LINE 153
SUB-EXPRESSION (w_wptr_p == w_rptr_p)
-----------1----------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 195
EXPRESSION ((r_wptr_p == r_rptr_p) ? (5'((r_wptr_v - r_rptr_v))) : (5'(({1'b1, r_wptr_v} - {1'b0, r_rptr_v}))))
-----------1----------
-1- | Status | Tests |
0 | Covered | T7,T11,T15 |
1 | Covered | T1,T2,T3 |
LINE 195
SUB-EXPRESSION (r_wptr_p == r_rptr_p)
-----------1----------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 211
EXPRESSION (r_wptr == r_sram_rptr)
-----------1-----------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 217
EXPRESSION (w_wptr_q == (w_rptr ^ XorMask))
----------------1---------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Not Covered | |
LINE 218
EXPRESSION (r_wptr == (r_rptr_q ^ XorMask))
----------------1---------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Not Covered | |
LINE 219
EXPRESSION (r_wptr == r_rptr_q)
----------1---------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 247
EXPRESSION (r_sram_req_o && r_sram_gnt_i)
------1----- ------2-----
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Not Covered | |
1 | 1 | Covered | T5,T7,T9 |
LINE 248
EXPRESSION (rvalid_o && rready_i)
----1--- ----2---
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T5,T7,T9 |
1 | 1 | Covered | T5,T7,T9 |
LINE 251
EXPRESSION (wvalid_i && ((!w_full)))
----1--- -----2-----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
1 | 1 | Covered | T5,T7,T9 |
LINE 252
EXPRESSION (((!w_full)) && w_sram_gnt_i)
-----1----- ------2-----
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T5,T7,T9 |
LINE 282
EXPRESSION (((!r_sramrptr_empty)) && rfifo_ack)
----------1---------- ----2----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T5,T7,T9 |
1 | 0 | Not Covered | |
1 | 1 | Not Covered | |
LINE 287
EXPRESSION (((!r_sramrptr_empty)) && ( ! (r_sram_rvalid_i ^ rfifo_ack) ))
----------1---------- -----------------2-----------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
1 | 1 | Covered | T5,T7,T9 |
LINE 287
SUB-EXPRESSION ( ! (r_sram_rvalid_i ^ rfifo_ack) )
--------------1--------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T5,T7,T9 |
LINE 287
SUB-EXPRESSION (r_sram_rvalid_i ^ rfifo_ack)
-------1------- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Not Covered | |
1 | 0 | Covered | T5,T7,T9 |
1 | 1 | Not Covered | |
LINE 291
EXPRESSION (stored || r_sram_rvalid_i)
---1-- -------2-------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T5,T7,T9 |
1 | 0 | Covered | T5,T7,T9 |
LINE 299
EXPRESSION (r_sram_rvalid_i ? r_sram_rdata_i[0+:Width] : (32'(0)))
-------1-------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T5,T7,T9 |
LINE 301
EXPRESSION (stored ? rdata_q : rdata_d)
---1--
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T5,T7,T9 |
LINE 321
EXPRESSION (r_sram_rvalid_i && ( ! (stored ^ rfifo_ack) ))
-------1------- -------------2------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
1 | 1 | Covered | T5,T7,T9 |
LINE 321
SUB-EXPRESSION ( ! (stored ^ rfifo_ack) )
----------1---------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T5,T7,T9 |
LINE 321
SUB-EXPRESSION (stored ^ rfifo_ack)
---1-- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Not Covered | |
1 | 0 | Covered | T5,T7,T9 |
1 | 1 | Covered | T5,T7,T9 |
LINE 330
EXPRESSION (((!r_sram_rvalid_i)) && rfifo_ack)
----------1--------- ----2----
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T5,T7,T9 |
LINE 349
EXPRESSION (decval[(PtrW - 1)] ? decval_sub : decval)
---------1--------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T5,T7,T11 |
LINE 370
EXPRESSION (dec_tmp[(i + 1)] ^ grayval[i])
--------1------- -----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T5,T7,T9 |
1 | 0 | Covered | T5,T7,T9 |
1 | 1 | Covered | T5,T7,T9 |
Branch Coverage for Module :
prim_fifo_async_sram_adapter
| Line No. | Total | Covered | Percent |
Branches |
|
27 |
27 |
100.00 |
TERNARY |
153 |
2 |
2 |
100.00 |
TERNARY |
195 |
2 |
2 |
100.00 |
TERNARY |
299 |
2 |
2 |
100.00 |
TERNARY |
301 |
2 |
2 |
100.00 |
IF |
126 |
3 |
3 |
100.00 |
IF |
168 |
3 |
3 |
100.00 |
IF |
204 |
3 |
3 |
100.00 |
IF |
279 |
2 |
2 |
100.00 |
IF |
324 |
4 |
4 |
100.00 |
TERNARY |
349 |
2 |
2 |
100.00 |
IF |
373 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_async_sram_adapter.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_async_sram_adapter.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 153 ((w_wptr_p == w_rptr_p)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T5,T7,T11 |
LineNo. Expression
-1-: 195 ((r_wptr_p == r_rptr_p)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T5,T7,T11 |
LineNo. Expression
-1-: 299 (r_sram_rvalid_i) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T7,T9 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 301 (stored) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T7,T9 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 126 if ((!rst_wr_ni))
-2-: 129 if (w_wptr_inc)
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T1,T2,T3 |
0 |
1 |
Covered |
T5,T7,T9 |
0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 168 if ((!rst_rd_ni))
-2-: 171 if (r_rptr_inc)
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T1,T2,T3 |
0 |
1 |
Covered |
T5,T7,T9 |
0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 204 if ((!rst_rd_ni))
-2-: 206 if (r_sram_rptr_inc)
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T1,T2,T3 |
0 |
1 |
Covered |
T5,T7,T9 |
0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 279 if (stored)
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T7,T9 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 324 if ((!rst_rd_ni))
-2-: 327 if (store_en)
-3-: 330 if (((!r_sram_rvalid_i) && rfifo_ack))
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T1,T2,T3 |
0 |
1 |
- |
Covered |
T5,T7,T9 |
0 |
0 |
1 |
Covered |
T5,T7,T9 |
0 |
0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 349 (decval[(PtrW - 1)]) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T7,T11 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 373 if (grayval[(PtrW - 1)])
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T7,T11 |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Module :
prim_fifo_async_sram_adapter
Assertion Details
MinDepth_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
3704 |
3704 |
0 |
0 |
T1 |
2 |
2 |
0 |
0 |
T2 |
2 |
2 |
0 |
0 |
T3 |
2 |
2 |
0 |
0 |
T4 |
2 |
2 |
0 |
0 |
T5 |
2 |
2 |
0 |
0 |
T6 |
2 |
2 |
0 |
0 |
T7 |
2 |
2 |
0 |
0 |
T8 |
2 |
2 |
0 |
0 |
T9 |
2 |
2 |
0 |
0 |
T10 |
2 |
2 |
0 |
0 |
NoRAckInEmpty_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
8232 |
0 |
0 |
T5 |
811622 |
37 |
0 |
0 |
T6 |
3524 |
0 |
0 |
0 |
T7 |
464348 |
49 |
0 |
0 |
T8 |
731014 |
0 |
0 |
0 |
T9 |
254406 |
13 |
0 |
0 |
T10 |
85686 |
0 |
0 |
0 |
T11 |
1329012 |
43 |
0 |
0 |
T12 |
137052 |
0 |
0 |
0 |
T13 |
262606 |
0 |
0 |
0 |
T14 |
0 |
21 |
0 |
0 |
T15 |
0 |
60 |
0 |
0 |
T16 |
0 |
33 |
0 |
0 |
T23 |
0 |
12 |
0 |
0 |
T25 |
0 |
8 |
0 |
0 |
T26 |
31470 |
0 |
0 |
0 |
T27 |
0 |
13 |
0 |
0 |
NoWAckInFull_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
763977908 |
8232 |
0 |
0 |
T5 |
1984554 |
37 |
0 |
0 |
T6 |
720 |
0 |
0 |
0 |
T7 |
1498018 |
49 |
0 |
0 |
T8 |
362352 |
0 |
0 |
0 |
T9 |
637208 |
13 |
0 |
0 |
T10 |
39374 |
0 |
0 |
0 |
T11 |
291348 |
43 |
0 |
0 |
T12 |
255108 |
0 |
0 |
0 |
T13 |
233222 |
0 |
0 |
0 |
T14 |
0 |
21 |
0 |
0 |
T15 |
0 |
60 |
0 |
0 |
T16 |
0 |
33 |
0 |
0 |
T23 |
0 |
12 |
0 |
0 |
T25 |
0 |
8 |
0 |
0 |
T26 |
8544 |
0 |
0 |
0 |
T27 |
0 |
13 |
0 |
0 |
ParamCheckDepth_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
3704 |
3704 |
0 |
0 |
T1 |
2 |
2 |
0 |
0 |
T2 |
2 |
2 |
0 |
0 |
T3 |
2 |
2 |
0 |
0 |
T4 |
2 |
2 |
0 |
0 |
T5 |
2 |
2 |
0 |
0 |
T6 |
2 |
2 |
0 |
0 |
T7 |
2 |
2 |
0 |
0 |
T8 |
2 |
2 |
0 |
0 |
T9 |
2 |
2 |
0 |
0 |
T10 |
2 |
2 |
0 |
0 |
RSramRvalidOneCycle_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
8232 |
0 |
0 |
T5 |
811622 |
37 |
0 |
0 |
T6 |
3524 |
0 |
0 |
0 |
T7 |
464348 |
49 |
0 |
0 |
T8 |
731014 |
0 |
0 |
0 |
T9 |
254406 |
13 |
0 |
0 |
T10 |
85686 |
0 |
0 |
0 |
T11 |
1329012 |
43 |
0 |
0 |
T12 |
137052 |
0 |
0 |
0 |
T13 |
262606 |
0 |
0 |
0 |
T14 |
0 |
21 |
0 |
0 |
T15 |
0 |
60 |
0 |
0 |
T16 |
0 |
33 |
0 |
0 |
T23 |
0 |
12 |
0 |
0 |
T25 |
0 |
8 |
0 |
0 |
T26 |
31470 |
0 |
0 |
0 |
T27 |
0 |
13 |
0 |
0 |
RptrGrayOneBitAtATime_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
8232 |
0 |
0 |
T5 |
811622 |
37 |
0 |
0 |
T6 |
3524 |
0 |
0 |
0 |
T7 |
464348 |
49 |
0 |
0 |
T8 |
731014 |
0 |
0 |
0 |
T9 |
254406 |
13 |
0 |
0 |
T10 |
85686 |
0 |
0 |
0 |
T11 |
1329012 |
43 |
0 |
0 |
T12 |
137052 |
0 |
0 |
0 |
T13 |
262606 |
0 |
0 |
0 |
T14 |
0 |
21 |
0 |
0 |
T15 |
0 |
60 |
0 |
0 |
T16 |
0 |
33 |
0 |
0 |
T23 |
0 |
12 |
0 |
0 |
T25 |
0 |
8 |
0 |
0 |
T26 |
31470 |
0 |
0 |
0 |
T27 |
0 |
13 |
0 |
0 |
RptrIncDataValid_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
8232 |
0 |
0 |
T5 |
811622 |
37 |
0 |
0 |
T6 |
3524 |
0 |
0 |
0 |
T7 |
464348 |
49 |
0 |
0 |
T8 |
731014 |
0 |
0 |
0 |
T9 |
254406 |
13 |
0 |
0 |
T10 |
85686 |
0 |
0 |
0 |
T11 |
1329012 |
43 |
0 |
0 |
T12 |
137052 |
0 |
0 |
0 |
T13 |
262606 |
0 |
0 |
0 |
T14 |
0 |
21 |
0 |
0 |
T15 |
0 |
60 |
0 |
0 |
T16 |
0 |
33 |
0 |
0 |
T23 |
0 |
12 |
0 |
0 |
T25 |
0 |
8 |
0 |
0 |
T26 |
31470 |
0 |
0 |
0 |
T27 |
0 |
13 |
0 |
0 |
RptrIncrease_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
8232 |
0 |
0 |
T5 |
811622 |
37 |
0 |
0 |
T6 |
3524 |
0 |
0 |
0 |
T7 |
464348 |
49 |
0 |
0 |
T8 |
731014 |
0 |
0 |
0 |
T9 |
254406 |
13 |
0 |
0 |
T10 |
85686 |
0 |
0 |
0 |
T11 |
1329012 |
43 |
0 |
0 |
T12 |
137052 |
0 |
0 |
0 |
T13 |
262606 |
0 |
0 |
0 |
T14 |
0 |
21 |
0 |
0 |
T15 |
0 |
60 |
0 |
0 |
T16 |
0 |
33 |
0 |
0 |
T23 |
0 |
12 |
0 |
0 |
T25 |
0 |
8 |
0 |
0 |
T26 |
31470 |
0 |
0 |
0 |
T27 |
0 |
13 |
0 |
0 |
SramRvalid_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
8232 |
0 |
0 |
T5 |
811622 |
37 |
0 |
0 |
T6 |
3524 |
0 |
0 |
0 |
T7 |
464348 |
49 |
0 |
0 |
T8 |
731014 |
0 |
0 |
0 |
T9 |
254406 |
13 |
0 |
0 |
T10 |
85686 |
0 |
0 |
0 |
T11 |
1329012 |
43 |
0 |
0 |
T12 |
137052 |
0 |
0 |
0 |
T13 |
262606 |
0 |
0 |
0 |
T14 |
0 |
21 |
0 |
0 |
T15 |
0 |
60 |
0 |
0 |
T16 |
0 |
33 |
0 |
0 |
T23 |
0 |
12 |
0 |
0 |
T25 |
0 |
8 |
0 |
0 |
T26 |
31470 |
0 |
0 |
0 |
T27 |
0 |
13 |
0 |
0 |
WSramRvalid_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
763977908 |
763977908 |
0 |
0 |
T1 |
26816 |
26816 |
0 |
0 |
T2 |
79516 |
79516 |
0 |
0 |
T3 |
2650 |
2650 |
0 |
0 |
T5 |
1984554 |
1984554 |
0 |
0 |
T6 |
720 |
720 |
0 |
0 |
T7 |
1498018 |
1498018 |
0 |
0 |
T8 |
362352 |
362352 |
0 |
0 |
T9 |
637208 |
637208 |
0 |
0 |
T10 |
39374 |
39374 |
0 |
0 |
T11 |
291348 |
291348 |
0 |
0 |
WidthMatch_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
3704 |
3704 |
0 |
0 |
T1 |
2 |
2 |
0 |
0 |
T2 |
2 |
2 |
0 |
0 |
T3 |
2 |
2 |
0 |
0 |
T4 |
2 |
2 |
0 |
0 |
T5 |
2 |
2 |
0 |
0 |
T6 |
2 |
2 |
0 |
0 |
T7 |
2 |
2 |
0 |
0 |
T8 |
2 |
2 |
0 |
0 |
T9 |
2 |
2 |
0 |
0 |
T10 |
2 |
2 |
0 |
0 |
WptrGrayOneBitAtATime_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
763977908 |
8232 |
0 |
0 |
T5 |
1984554 |
37 |
0 |
0 |
T6 |
720 |
0 |
0 |
0 |
T7 |
1498018 |
49 |
0 |
0 |
T8 |
362352 |
0 |
0 |
0 |
T9 |
637208 |
13 |
0 |
0 |
T10 |
39374 |
0 |
0 |
0 |
T11 |
291348 |
43 |
0 |
0 |
T12 |
255108 |
0 |
0 |
0 |
T13 |
233222 |
0 |
0 |
0 |
T14 |
0 |
21 |
0 |
0 |
T15 |
0 |
60 |
0 |
0 |
T16 |
0 |
33 |
0 |
0 |
T23 |
0 |
12 |
0 |
0 |
T25 |
0 |
8 |
0 |
0 |
T26 |
8544 |
0 |
0 |
0 |
T27 |
0 |
13 |
0 |
0 |
WptrIncrease_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
763977908 |
8232 |
0 |
0 |
T5 |
1984554 |
37 |
0 |
0 |
T6 |
720 |
0 |
0 |
0 |
T7 |
1498018 |
49 |
0 |
0 |
T8 |
362352 |
0 |
0 |
0 |
T9 |
637208 |
13 |
0 |
0 |
T10 |
39374 |
0 |
0 |
0 |
T11 |
291348 |
43 |
0 |
0 |
T12 |
255108 |
0 |
0 |
0 |
T13 |
233222 |
0 |
0 |
0 |
T14 |
0 |
21 |
0 |
0 |
T15 |
0 |
60 |
0 |
0 |
T16 |
0 |
33 |
0 |
0 |
T23 |
0 |
12 |
0 |
0 |
T25 |
0 |
8 |
0 |
0 |
T26 |
8544 |
0 |
0 |
0 |
T27 |
0 |
13 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_upload.u_cmdfifo
| Line No. | Total | Covered | Percent |
TOTAL | | 86 | 86 | 100.00 |
CONT_ASSIGN | 121 | 1 | 1 | 100.00 |
CONT_ASSIGN | 123 | 1 | 1 | 100.00 |
ALWAYS | 126 | 6 | 6 | 100.00 |
CONT_ASSIGN | 135 | 1 | 1 | 100.00 |
CONT_ASSIGN | 136 | 1 | 1 | 100.00 |
CONT_ASSIGN | 138 | 1 | 1 | 100.00 |
CONT_ASSIGN | 149 | 1 | 1 | 100.00 |
CONT_ASSIGN | 150 | 1 | 1 | 100.00 |
CONT_ASSIGN | 151 | 1 | 1 | 100.00 |
CONT_ASSIGN | 153 | 1 | 1 | 100.00 |
CONT_ASSIGN | 163 | 1 | 1 | 100.00 |
CONT_ASSIGN | 165 | 1 | 1 | 100.00 |
ALWAYS | 168 | 6 | 6 | 100.00 |
CONT_ASSIGN | 177 | 1 | 1 | 100.00 |
CONT_ASSIGN | 178 | 1 | 1 | 100.00 |
CONT_ASSIGN | 180 | 1 | 1 | 100.00 |
CONT_ASSIGN | 191 | 1 | 1 | 100.00 |
CONT_ASSIGN | 192 | 1 | 1 | 100.00 |
CONT_ASSIGN | 193 | 1 | 1 | 100.00 |
CONT_ASSIGN | 195 | 1 | 1 | 100.00 |
CONT_ASSIGN | 201 | 1 | 1 | 100.00 |
ALWAYS | 204 | 4 | 4 | 100.00 |
CONT_ASSIGN | 211 | 1 | 1 | 100.00 |
CONT_ASSIGN | 217 | 1 | 1 | 100.00 |
CONT_ASSIGN | 218 | 1 | 1 | 100.00 |
CONT_ASSIGN | 219 | 1 | 1 | 100.00 |
CONT_ASSIGN | 222 | 1 | 1 | 100.00 |
CONT_ASSIGN | 224 | 1 | 1 | 100.00 |
CONT_ASSIGN | 225 | 1 | 1 | 100.00 |
CONT_ASSIGN | 245 | 1 | 1 | 100.00 |
CONT_ASSIGN | 247 | 1 | 1 | 100.00 |
CONT_ASSIGN | 248 | 1 | 1 | 100.00 |
CONT_ASSIGN | 251 | 1 | 1 | 100.00 |
CONT_ASSIGN | 252 | 1 | 1 | 100.00 |
CONT_ASSIGN | 254 | 1 | 1 | 100.00 |
CONT_ASSIGN | 256 | 1 | 1 | 100.00 |
CONT_ASSIGN | 260 | 1 | 1 | 100.00 |
ALWAYS | 270 | 4 | 4 | 100.00 |
CONT_ASSIGN | 291 | 1 | 1 | 100.00 |
CONT_ASSIGN | 297 | 1 | 1 | 100.00 |
CONT_ASSIGN | 299 | 1 | 1 | 100.00 |
CONT_ASSIGN | 301 | 1 | 1 | 100.00 |
CONT_ASSIGN | 304 | 1 | 1 | 100.00 |
CONT_ASSIGN | 308 | 1 | 1 | 100.00 |
CONT_ASSIGN | 321 | 1 | 1 | 100.00 |
ALWAYS | 324 | 9 | 9 | 100.00 |
ROUTINE | 347 | 7 | 7 | 100.00 |
ROUTINE | 368 | 9 | 9 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_async_sram_adapter.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_async_sram_adapter.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
121 |
1 |
1 |
123 |
1 |
1 |
126 |
1 |
1 |
127 |
1 |
1 |
128 |
1 |
1 |
129 |
1 |
1 |
130 |
1 |
1 |
131 |
1 |
1 |
|
|
|
MISSING_ELSE |
135 |
1 |
1 |
136 |
1 |
1 |
138 |
1 |
1 |
149 |
1 |
1 |
150 |
1 |
1 |
151 |
1 |
1 |
153 |
1 |
1 |
163 |
1 |
1 |
165 |
1 |
1 |
168 |
1 |
1 |
169 |
1 |
1 |
170 |
1 |
1 |
171 |
1 |
1 |
172 |
1 |
1 |
173 |
1 |
1 |
|
|
|
MISSING_ELSE |
177 |
1 |
1 |
178 |
1 |
1 |
180 |
1 |
1 |
191 |
1 |
1 |
192 |
1 |
1 |
193 |
1 |
1 |
195 |
1 |
1 |
201 |
1 |
1 |
204 |
1 |
1 |
205 |
1 |
1 |
206 |
1 |
1 |
207 |
1 |
1 |
|
|
|
MISSING_ELSE |
211 |
1 |
1 |
217 |
1 |
1 |
218 |
1 |
1 |
219 |
1 |
1 |
222 |
1 |
1 |
224 |
1 |
1 |
225 |
1 |
1 |
245 |
1 |
1 |
247 |
1 |
1 |
248 |
1 |
1 |
251 |
1 |
1 |
252 |
1 |
1 |
254 |
1 |
1 |
256 |
1 |
1 |
260 |
1 |
1 |
270 |
1 |
1 |
279 |
1 |
1 |
282 |
1 |
1 |
287 |
1 |
1 |
291 |
1 |
1 |
297 |
1 |
1 |
299 |
1 |
1 |
301 |
1 |
1 |
304 |
1 |
1 |
308 |
1 |
1 |
321 |
1 |
1 |
324 |
1 |
1 |
325 |
1 |
1 |
326 |
1 |
1 |
327 |
1 |
1 |
328 |
1 |
1 |
329 |
1 |
1 |
330 |
1 |
1 |
332 |
1 |
1 |
333 |
1 |
1 |
|
|
|
MISSING_ELSE |
347 |
1 |
1 |
349 |
1 |
1 |
352 |
1 |
1 |
353 |
1 |
1 |
356 |
1 |
1 |
357 |
1 |
1 |
360 |
1 |
1 |
368 |
1 |
1 |
369 |
1 |
1 |
370 |
1 |
1 |
372 |
1 |
1 |
373 |
1 |
1 |
374 |
1 |
1 |
376 |
1 |
1 |
377 |
1 |
1 |
379 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_upload.u_cmdfifo
| Total | Covered | Percent |
Conditions | 68 | 51 | 75.00 |
Logical | 68 | 51 | 75.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 121
EXPRESSION (wvalid_i & wready_o)
----1--- ----2---
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Not Covered | |
1 | 1 | Covered | T5,T7,T9 |
LINE 153
EXPRESSION ((w_wptr_p == w_rptr_p) ? (5'((w_wptr_v - w_rptr_v))) : (5'(({1'b1, w_wptr_v} - {1'b0, w_rptr_v}))))
-----------1----------
-1- | Status | Tests |
0 | Covered | T5,T7,T11 |
1 | Covered | T1,T2,T3 |
LINE 153
SUB-EXPRESSION (w_wptr_p == w_rptr_p)
-----------1----------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 195
EXPRESSION ((r_wptr_p == r_rptr_p) ? (5'((r_wptr_v - r_rptr_v))) : (5'(({1'b1, r_wptr_v} - {1'b0, r_rptr_v}))))
-----------1----------
-1- | Status | Tests |
0 | Covered | T5,T7,T11 |
1 | Covered | T1,T2,T3 |
LINE 195
SUB-EXPRESSION (r_wptr_p == r_rptr_p)
-----------1----------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 211
EXPRESSION (r_wptr == r_sram_rptr)
-----------1-----------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 217
EXPRESSION (w_wptr_q == (w_rptr ^ XorMask))
----------------1---------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Not Covered | |
LINE 218
EXPRESSION (r_wptr == (r_rptr_q ^ XorMask))
----------------1---------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Not Covered | |
LINE 219
EXPRESSION (r_wptr == r_rptr_q)
----------1---------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 247
EXPRESSION (r_sram_req_o && r_sram_gnt_i)
------1----- ------2-----
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Not Covered | |
1 | 1 | Covered | T5,T7,T9 |
LINE 248
EXPRESSION (rvalid_o && rready_i)
----1--- ----2---
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T5,T7,T9 |
1 | 1 | Covered | T5,T7,T9 |
LINE 251
EXPRESSION (wvalid_i && ((!w_full)))
----1--- -----2-----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
1 | 1 | Covered | T5,T7,T9 |
LINE 252
EXPRESSION (((!w_full)) && w_sram_gnt_i)
-----1----- ------2-----
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T5,T7,T9 |
LINE 282
EXPRESSION (((!r_sramrptr_empty)) && rfifo_ack)
----------1---------- ----2----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T5,T7,T9 |
1 | 0 | Not Covered | |
1 | 1 | Not Covered | |
LINE 287
EXPRESSION (((!r_sramrptr_empty)) && ( ! (r_sram_rvalid_i ^ rfifo_ack) ))
----------1---------- -----------------2-----------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
1 | 1 | Covered | T5,T7,T9 |
LINE 287
SUB-EXPRESSION ( ! (r_sram_rvalid_i ^ rfifo_ack) )
--------------1--------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T5,T7,T9 |
LINE 287
SUB-EXPRESSION (r_sram_rvalid_i ^ rfifo_ack)
-------1------- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Not Covered | |
1 | 0 | Covered | T5,T7,T9 |
1 | 1 | Not Covered | |
LINE 291
EXPRESSION (stored || r_sram_rvalid_i)
---1-- -------2-------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T5,T7,T9 |
1 | 0 | Covered | T5,T7,T9 |
LINE 299
EXPRESSION (r_sram_rvalid_i ? r_sram_rdata_i[0+:Width] : (16'(0)))
-------1-------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T5,T7,T9 |
LINE 301
EXPRESSION (stored ? rdata_q : rdata_d)
---1--
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T5,T7,T9 |
LINE 321
EXPRESSION (r_sram_rvalid_i && ( ! (stored ^ rfifo_ack) ))
-------1------- -------------2------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
1 | 1 | Covered | T5,T7,T9 |
LINE 321
SUB-EXPRESSION ( ! (stored ^ rfifo_ack) )
----------1---------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T5,T7,T9 |
LINE 321
SUB-EXPRESSION (stored ^ rfifo_ack)
---1-- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Not Covered | |
1 | 0 | Covered | T5,T7,T9 |
1 | 1 | Covered | T5,T7,T9 |
LINE 330
EXPRESSION (((!r_sram_rvalid_i)) && rfifo_ack)
----------1--------- ----2----
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T5,T7,T9 |
LINE 349
EXPRESSION (decval[(PtrW - 1)] ? decval_sub : decval)
---------1--------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T5,T7,T11 |
LINE 370
EXPRESSION (dec_tmp[(i + 1)] ^ grayval[i])
--------1------- -----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T5,T7,T9 |
1 | 0 | Covered | T5,T7,T9 |
1 | 1 | Covered | T5,T7,T9 |
Branch Coverage for Instance : tb.dut.u_upload.u_cmdfifo
| Line No. | Total | Covered | Percent |
Branches |
|
27 |
27 |
100.00 |
TERNARY |
153 |
2 |
2 |
100.00 |
TERNARY |
195 |
2 |
2 |
100.00 |
TERNARY |
299 |
2 |
2 |
100.00 |
TERNARY |
301 |
2 |
2 |
100.00 |
IF |
126 |
3 |
3 |
100.00 |
IF |
168 |
3 |
3 |
100.00 |
IF |
204 |
3 |
3 |
100.00 |
IF |
279 |
2 |
2 |
100.00 |
IF |
324 |
4 |
4 |
100.00 |
TERNARY |
349 |
2 |
2 |
100.00 |
IF |
373 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_async_sram_adapter.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_async_sram_adapter.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 153 ((w_wptr_p == w_rptr_p)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T5,T7,T11 |
LineNo. Expression
-1-: 195 ((r_wptr_p == r_rptr_p)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T5,T7,T11 |
LineNo. Expression
-1-: 299 (r_sram_rvalid_i) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T7,T9 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 301 (stored) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T7,T9 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 126 if ((!rst_wr_ni))
-2-: 129 if (w_wptr_inc)
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T1,T2,T3 |
0 |
1 |
Covered |
T5,T7,T9 |
0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 168 if ((!rst_rd_ni))
-2-: 171 if (r_rptr_inc)
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T1,T2,T3 |
0 |
1 |
Covered |
T5,T7,T9 |
0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 204 if ((!rst_rd_ni))
-2-: 206 if (r_sram_rptr_inc)
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T1,T2,T3 |
0 |
1 |
Covered |
T5,T7,T9 |
0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 279 if (stored)
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T7,T9 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 324 if ((!rst_rd_ni))
-2-: 327 if (store_en)
-3-: 330 if (((!r_sram_rvalid_i) && rfifo_ack))
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T1,T2,T3 |
0 |
1 |
- |
Covered |
T5,T7,T9 |
0 |
0 |
1 |
Covered |
T5,T7,T9 |
0 |
0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 349 (decval[(PtrW - 1)]) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T7,T11 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 373 if (grayval[(PtrW - 1)])
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T7,T11 |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_upload.u_cmdfifo
Assertion Details
MinDepth_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1852 |
1852 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T3 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T8 |
1 |
1 |
0 |
0 |
T9 |
1 |
1 |
0 |
0 |
T10 |
1 |
1 |
0 |
0 |
NoRAckInEmpty_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1203785710 |
4724 |
0 |
0 |
T5 |
405811 |
22 |
0 |
0 |
T6 |
1762 |
0 |
0 |
0 |
T7 |
232174 |
28 |
0 |
0 |
T8 |
365507 |
0 |
0 |
0 |
T9 |
127203 |
7 |
0 |
0 |
T10 |
42843 |
0 |
0 |
0 |
T11 |
664506 |
25 |
0 |
0 |
T12 |
68526 |
0 |
0 |
0 |
T13 |
131303 |
0 |
0 |
0 |
T14 |
0 |
12 |
0 |
0 |
T15 |
0 |
34 |
0 |
0 |
T16 |
0 |
19 |
0 |
0 |
T23 |
0 |
8 |
0 |
0 |
T25 |
0 |
4 |
0 |
0 |
T26 |
15735 |
0 |
0 |
0 |
T27 |
0 |
8 |
0 |
0 |
NoWAckInFull_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
381988954 |
4724 |
0 |
0 |
T5 |
992277 |
22 |
0 |
0 |
T6 |
360 |
0 |
0 |
0 |
T7 |
749009 |
28 |
0 |
0 |
T8 |
181176 |
0 |
0 |
0 |
T9 |
318604 |
7 |
0 |
0 |
T10 |
19687 |
0 |
0 |
0 |
T11 |
145674 |
25 |
0 |
0 |
T12 |
127554 |
0 |
0 |
0 |
T13 |
116611 |
0 |
0 |
0 |
T14 |
0 |
12 |
0 |
0 |
T15 |
0 |
34 |
0 |
0 |
T16 |
0 |
19 |
0 |
0 |
T23 |
0 |
8 |
0 |
0 |
T25 |
0 |
4 |
0 |
0 |
T26 |
4272 |
0 |
0 |
0 |
T27 |
0 |
8 |
0 |
0 |
ParamCheckDepth_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1852 |
1852 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T3 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T8 |
1 |
1 |
0 |
0 |
T9 |
1 |
1 |
0 |
0 |
T10 |
1 |
1 |
0 |
0 |
RSramRvalidOneCycle_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1203785710 |
4724 |
0 |
0 |
T5 |
405811 |
22 |
0 |
0 |
T6 |
1762 |
0 |
0 |
0 |
T7 |
232174 |
28 |
0 |
0 |
T8 |
365507 |
0 |
0 |
0 |
T9 |
127203 |
7 |
0 |
0 |
T10 |
42843 |
0 |
0 |
0 |
T11 |
664506 |
25 |
0 |
0 |
T12 |
68526 |
0 |
0 |
0 |
T13 |
131303 |
0 |
0 |
0 |
T14 |
0 |
12 |
0 |
0 |
T15 |
0 |
34 |
0 |
0 |
T16 |
0 |
19 |
0 |
0 |
T23 |
0 |
8 |
0 |
0 |
T25 |
0 |
4 |
0 |
0 |
T26 |
15735 |
0 |
0 |
0 |
T27 |
0 |
8 |
0 |
0 |
RptrGrayOneBitAtATime_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1203785710 |
4724 |
0 |
0 |
T5 |
405811 |
22 |
0 |
0 |
T6 |
1762 |
0 |
0 |
0 |
T7 |
232174 |
28 |
0 |
0 |
T8 |
365507 |
0 |
0 |
0 |
T9 |
127203 |
7 |
0 |
0 |
T10 |
42843 |
0 |
0 |
0 |
T11 |
664506 |
25 |
0 |
0 |
T12 |
68526 |
0 |
0 |
0 |
T13 |
131303 |
0 |
0 |
0 |
T14 |
0 |
12 |
0 |
0 |
T15 |
0 |
34 |
0 |
0 |
T16 |
0 |
19 |
0 |
0 |
T23 |
0 |
8 |
0 |
0 |
T25 |
0 |
4 |
0 |
0 |
T26 |
15735 |
0 |
0 |
0 |
T27 |
0 |
8 |
0 |
0 |
RptrIncDataValid_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1203785710 |
4724 |
0 |
0 |
T5 |
405811 |
22 |
0 |
0 |
T6 |
1762 |
0 |
0 |
0 |
T7 |
232174 |
28 |
0 |
0 |
T8 |
365507 |
0 |
0 |
0 |
T9 |
127203 |
7 |
0 |
0 |
T10 |
42843 |
0 |
0 |
0 |
T11 |
664506 |
25 |
0 |
0 |
T12 |
68526 |
0 |
0 |
0 |
T13 |
131303 |
0 |
0 |
0 |
T14 |
0 |
12 |
0 |
0 |
T15 |
0 |
34 |
0 |
0 |
T16 |
0 |
19 |
0 |
0 |
T23 |
0 |
8 |
0 |
0 |
T25 |
0 |
4 |
0 |
0 |
T26 |
15735 |
0 |
0 |
0 |
T27 |
0 |
8 |
0 |
0 |
RptrIncrease_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1203785710 |
4724 |
0 |
0 |
T5 |
405811 |
22 |
0 |
0 |
T6 |
1762 |
0 |
0 |
0 |
T7 |
232174 |
28 |
0 |
0 |
T8 |
365507 |
0 |
0 |
0 |
T9 |
127203 |
7 |
0 |
0 |
T10 |
42843 |
0 |
0 |
0 |
T11 |
664506 |
25 |
0 |
0 |
T12 |
68526 |
0 |
0 |
0 |
T13 |
131303 |
0 |
0 |
0 |
T14 |
0 |
12 |
0 |
0 |
T15 |
0 |
34 |
0 |
0 |
T16 |
0 |
19 |
0 |
0 |
T23 |
0 |
8 |
0 |
0 |
T25 |
0 |
4 |
0 |
0 |
T26 |
15735 |
0 |
0 |
0 |
T27 |
0 |
8 |
0 |
0 |
SramRvalid_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1203785710 |
4724 |
0 |
0 |
T5 |
405811 |
22 |
0 |
0 |
T6 |
1762 |
0 |
0 |
0 |
T7 |
232174 |
28 |
0 |
0 |
T8 |
365507 |
0 |
0 |
0 |
T9 |
127203 |
7 |
0 |
0 |
T10 |
42843 |
0 |
0 |
0 |
T11 |
664506 |
25 |
0 |
0 |
T12 |
68526 |
0 |
0 |
0 |
T13 |
131303 |
0 |
0 |
0 |
T14 |
0 |
12 |
0 |
0 |
T15 |
0 |
34 |
0 |
0 |
T16 |
0 |
19 |
0 |
0 |
T23 |
0 |
8 |
0 |
0 |
T25 |
0 |
4 |
0 |
0 |
T26 |
15735 |
0 |
0 |
0 |
T27 |
0 |
8 |
0 |
0 |
WSramRvalid_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
381988954 |
381988954 |
0 |
0 |
T1 |
13408 |
13408 |
0 |
0 |
T2 |
39758 |
39758 |
0 |
0 |
T3 |
1325 |
1325 |
0 |
0 |
T5 |
992277 |
992277 |
0 |
0 |
T6 |
360 |
360 |
0 |
0 |
T7 |
749009 |
749009 |
0 |
0 |
T8 |
181176 |
181176 |
0 |
0 |
T9 |
318604 |
318604 |
0 |
0 |
T10 |
19687 |
19687 |
0 |
0 |
T11 |
145674 |
145674 |
0 |
0 |
WidthMatch_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1852 |
1852 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T3 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T8 |
1 |
1 |
0 |
0 |
T9 |
1 |
1 |
0 |
0 |
T10 |
1 |
1 |
0 |
0 |
WptrGrayOneBitAtATime_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
381988954 |
4724 |
0 |
0 |
T5 |
992277 |
22 |
0 |
0 |
T6 |
360 |
0 |
0 |
0 |
T7 |
749009 |
28 |
0 |
0 |
T8 |
181176 |
0 |
0 |
0 |
T9 |
318604 |
7 |
0 |
0 |
T10 |
19687 |
0 |
0 |
0 |
T11 |
145674 |
25 |
0 |
0 |
T12 |
127554 |
0 |
0 |
0 |
T13 |
116611 |
0 |
0 |
0 |
T14 |
0 |
12 |
0 |
0 |
T15 |
0 |
34 |
0 |
0 |
T16 |
0 |
19 |
0 |
0 |
T23 |
0 |
8 |
0 |
0 |
T25 |
0 |
4 |
0 |
0 |
T26 |
4272 |
0 |
0 |
0 |
T27 |
0 |
8 |
0 |
0 |
WptrIncrease_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
381988954 |
4724 |
0 |
0 |
T5 |
992277 |
22 |
0 |
0 |
T6 |
360 |
0 |
0 |
0 |
T7 |
749009 |
28 |
0 |
0 |
T8 |
181176 |
0 |
0 |
0 |
T9 |
318604 |
7 |
0 |
0 |
T10 |
19687 |
0 |
0 |
0 |
T11 |
145674 |
25 |
0 |
0 |
T12 |
127554 |
0 |
0 |
0 |
T13 |
116611 |
0 |
0 |
0 |
T14 |
0 |
12 |
0 |
0 |
T15 |
0 |
34 |
0 |
0 |
T16 |
0 |
19 |
0 |
0 |
T23 |
0 |
8 |
0 |
0 |
T25 |
0 |
4 |
0 |
0 |
T26 |
4272 |
0 |
0 |
0 |
T27 |
0 |
8 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_upload.u_addrfifo
| Line No. | Total | Covered | Percent |
TOTAL | | 85 | 85 | 100.00 |
CONT_ASSIGN | 121 | 1 | 1 | 100.00 |
CONT_ASSIGN | 123 | 1 | 1 | 100.00 |
ALWAYS | 126 | 6 | 6 | 100.00 |
CONT_ASSIGN | 135 | 1 | 1 | 100.00 |
CONT_ASSIGN | 136 | 1 | 1 | 100.00 |
CONT_ASSIGN | 138 | 1 | 1 | 100.00 |
CONT_ASSIGN | 149 | 1 | 1 | 100.00 |
CONT_ASSIGN | 150 | 1 | 1 | 100.00 |
CONT_ASSIGN | 151 | 1 | 1 | 100.00 |
CONT_ASSIGN | 153 | 1 | 1 | 100.00 |
CONT_ASSIGN | 163 | 1 | 1 | 100.00 |
CONT_ASSIGN | 165 | 1 | 1 | 100.00 |
ALWAYS | 168 | 6 | 6 | 100.00 |
CONT_ASSIGN | 177 | 1 | 1 | 100.00 |
CONT_ASSIGN | 178 | 1 | 1 | 100.00 |
CONT_ASSIGN | 180 | 1 | 1 | 100.00 |
CONT_ASSIGN | 191 | 1 | 1 | 100.00 |
CONT_ASSIGN | 192 | 1 | 1 | 100.00 |
CONT_ASSIGN | 193 | 1 | 1 | 100.00 |
CONT_ASSIGN | 195 | 1 | 1 | 100.00 |
CONT_ASSIGN | 201 | 1 | 1 | 100.00 |
ALWAYS | 204 | 4 | 4 | 100.00 |
CONT_ASSIGN | 211 | 1 | 1 | 100.00 |
CONT_ASSIGN | 217 | 1 | 1 | 100.00 |
CONT_ASSIGN | 218 | 1 | 1 | 100.00 |
CONT_ASSIGN | 219 | 1 | 1 | 100.00 |
CONT_ASSIGN | 222 | 1 | 1 | 100.00 |
CONT_ASSIGN | 224 | 1 | 1 | 100.00 |
CONT_ASSIGN | 225 | 1 | 1 | 100.00 |
CONT_ASSIGN | 245 | 1 | 1 | 100.00 |
CONT_ASSIGN | 247 | 1 | 1 | 100.00 |
CONT_ASSIGN | 248 | 1 | 1 | 100.00 |
CONT_ASSIGN | 251 | 1 | 1 | 100.00 |
CONT_ASSIGN | 252 | 1 | 1 | 100.00 |
CONT_ASSIGN | 254 | 1 | 1 | 100.00 |
CONT_ASSIGN | 256 | 1 | 1 | 100.00 |
CONT_ASSIGN | 260 | 1 | 1 | 100.00 |
ALWAYS | 270 | 4 | 4 | 100.00 |
CONT_ASSIGN | 291 | 1 | 1 | 100.00 |
CONT_ASSIGN | 297 | 1 | 1 | 100.00 |
CONT_ASSIGN | 299 | 1 | 1 | 100.00 |
CONT_ASSIGN | 301 | 1 | 1 | 100.00 |
CONT_ASSIGN | 304 | 1 | 1 | 100.00 |
CONT_ASSIGN | 321 | 1 | 1 | 100.00 |
ALWAYS | 324 | 9 | 9 | 100.00 |
ROUTINE | 347 | 7 | 7 | 100.00 |
ROUTINE | 368 | 9 | 9 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_async_sram_adapter.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_async_sram_adapter.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
121 |
1 |
1 |
123 |
1 |
1 |
126 |
1 |
1 |
127 |
1 |
1 |
128 |
1 |
1 |
129 |
1 |
1 |
130 |
1 |
1 |
131 |
1 |
1 |
|
|
|
MISSING_ELSE |
135 |
1 |
1 |
136 |
1 |
1 |
138 |
1 |
1 |
149 |
1 |
1 |
150 |
1 |
1 |
151 |
1 |
1 |
153 |
1 |
1 |
163 |
1 |
1 |
165 |
1 |
1 |
168 |
1 |
1 |
169 |
1 |
1 |
170 |
1 |
1 |
171 |
1 |
1 |
172 |
1 |
1 |
173 |
1 |
1 |
|
|
|
MISSING_ELSE |
177 |
1 |
1 |
178 |
1 |
1 |
180 |
1 |
1 |
191 |
1 |
1 |
192 |
1 |
1 |
193 |
1 |
1 |
195 |
1 |
1 |
201 |
1 |
1 |
204 |
1 |
1 |
205 |
1 |
1 |
206 |
1 |
1 |
207 |
1 |
1 |
|
|
|
MISSING_ELSE |
211 |
1 |
1 |
217 |
1 |
1 |
218 |
1 |
1 |
219 |
1 |
1 |
222 |
1 |
1 |
224 |
1 |
1 |
225 |
1 |
1 |
245 |
1 |
1 |
247 |
1 |
1 |
248 |
1 |
1 |
251 |
1 |
1 |
252 |
1 |
1 |
254 |
1 |
1 |
256 |
1 |
1 |
260 |
1 |
1 |
270 |
1 |
1 |
279 |
1 |
1 |
282 |
1 |
1 |
287 |
1 |
1 |
291 |
1 |
1 |
297 |
1 |
1 |
299 |
1 |
1 |
301 |
1 |
1 |
304 |
1 |
1 |
321 |
1 |
1 |
324 |
1 |
1 |
325 |
1 |
1 |
326 |
1 |
1 |
327 |
1 |
1 |
328 |
1 |
1 |
329 |
1 |
1 |
330 |
1 |
1 |
332 |
1 |
1 |
333 |
1 |
1 |
|
|
|
MISSING_ELSE |
347 |
1 |
1 |
349 |
1 |
1 |
352 |
1 |
1 |
353 |
1 |
1 |
356 |
1 |
1 |
357 |
1 |
1 |
360 |
1 |
1 |
368 |
1 |
1 |
369 |
1 |
1 |
370 |
1 |
1 |
372 |
1 |
1 |
373 |
1 |
1 |
374 |
1 |
1 |
376 |
1 |
1 |
377 |
1 |
1 |
379 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_upload.u_addrfifo
| Total | Covered | Percent |
Conditions | 68 | 51 | 75.00 |
Logical | 68 | 51 | 75.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 121
EXPRESSION (wvalid_i & wready_o)
----1--- ----2---
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Not Covered | |
1 | 1 | Covered | T5,T7,T9 |
LINE 153
EXPRESSION ((w_wptr_p == w_rptr_p) ? (5'((w_wptr_v - w_rptr_v))) : (5'(({1'b1, w_wptr_v} - {1'b0, w_rptr_v}))))
-----------1----------
-1- | Status | Tests |
0 | Covered | T7,T11,T15 |
1 | Covered | T1,T2,T3 |
LINE 153
SUB-EXPRESSION (w_wptr_p == w_rptr_p)
-----------1----------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 195
EXPRESSION ((r_wptr_p == r_rptr_p) ? (5'((r_wptr_v - r_rptr_v))) : (5'(({1'b1, r_wptr_v} - {1'b0, r_rptr_v}))))
-----------1----------
-1- | Status | Tests |
0 | Covered | T7,T11,T15 |
1 | Covered | T1,T2,T3 |
LINE 195
SUB-EXPRESSION (r_wptr_p == r_rptr_p)
-----------1----------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 211
EXPRESSION (r_wptr == r_sram_rptr)
-----------1-----------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 217
EXPRESSION (w_wptr_q == (w_rptr ^ XorMask))
----------------1---------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Not Covered | |
LINE 218
EXPRESSION (r_wptr == (r_rptr_q ^ XorMask))
----------------1---------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Not Covered | |
LINE 219
EXPRESSION (r_wptr == r_rptr_q)
----------1---------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 247
EXPRESSION (r_sram_req_o && r_sram_gnt_i)
------1----- ------2-----
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Not Covered | |
1 | 1 | Covered | T5,T7,T9 |
LINE 248
EXPRESSION (rvalid_o && rready_i)
----1--- ----2---
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T5,T7,T9 |
1 | 1 | Covered | T5,T7,T9 |
LINE 251
EXPRESSION (wvalid_i && ((!w_full)))
----1--- -----2-----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
1 | 1 | Covered | T5,T7,T9 |
LINE 252
EXPRESSION (((!w_full)) && w_sram_gnt_i)
-----1----- ------2-----
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T5,T7,T9 |
LINE 282
EXPRESSION (((!r_sramrptr_empty)) && rfifo_ack)
----------1---------- ----2----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T5,T7,T9 |
1 | 0 | Not Covered | |
1 | 1 | Not Covered | |
LINE 287
EXPRESSION (((!r_sramrptr_empty)) && ( ! (r_sram_rvalid_i ^ rfifo_ack) ))
----------1---------- -----------------2-----------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
1 | 1 | Covered | T5,T7,T9 |
LINE 287
SUB-EXPRESSION ( ! (r_sram_rvalid_i ^ rfifo_ack) )
--------------1--------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T5,T7,T9 |
LINE 287
SUB-EXPRESSION (r_sram_rvalid_i ^ rfifo_ack)
-------1------- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Not Covered | |
1 | 0 | Covered | T5,T7,T9 |
1 | 1 | Not Covered | |
LINE 291
EXPRESSION (stored || r_sram_rvalid_i)
---1-- -------2-------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T5,T7,T9 |
1 | 0 | Covered | T5,T7,T9 |
LINE 299
EXPRESSION (r_sram_rvalid_i ? r_sram_rdata_i[0+:Width] : (32'(0)))
-------1-------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T5,T7,T9 |
LINE 301
EXPRESSION (stored ? rdata_q : rdata_d)
---1--
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T5,T7,T9 |
LINE 321
EXPRESSION (r_sram_rvalid_i && ( ! (stored ^ rfifo_ack) ))
-------1------- -------------2------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
1 | 1 | Covered | T5,T7,T9 |
LINE 321
SUB-EXPRESSION ( ! (stored ^ rfifo_ack) )
----------1---------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T5,T7,T9 |
LINE 321
SUB-EXPRESSION (stored ^ rfifo_ack)
---1-- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Not Covered | |
1 | 0 | Covered | T5,T7,T9 |
1 | 1 | Covered | T5,T7,T9 |
LINE 330
EXPRESSION (((!r_sram_rvalid_i)) && rfifo_ack)
----------1--------- ----2----
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T5,T7,T9 |
LINE 349
EXPRESSION (decval[(PtrW - 1)] ? decval_sub : decval)
---------1--------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T5,T7,T11 |
LINE 370
EXPRESSION (dec_tmp[(i + 1)] ^ grayval[i])
--------1------- -----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T5,T7,T9 |
1 | 0 | Covered | T5,T7,T9 |
1 | 1 | Covered | T5,T7,T9 |
Branch Coverage for Instance : tb.dut.u_upload.u_addrfifo
| Line No. | Total | Covered | Percent |
Branches |
|
27 |
27 |
100.00 |
TERNARY |
153 |
2 |
2 |
100.00 |
TERNARY |
195 |
2 |
2 |
100.00 |
TERNARY |
299 |
2 |
2 |
100.00 |
TERNARY |
301 |
2 |
2 |
100.00 |
IF |
126 |
3 |
3 |
100.00 |
IF |
168 |
3 |
3 |
100.00 |
IF |
204 |
3 |
3 |
100.00 |
IF |
279 |
2 |
2 |
100.00 |
IF |
324 |
4 |
4 |
100.00 |
TERNARY |
349 |
2 |
2 |
100.00 |
IF |
373 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_async_sram_adapter.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_async_sram_adapter.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 153 ((w_wptr_p == w_rptr_p)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T7,T11,T15 |
LineNo. Expression
-1-: 195 ((r_wptr_p == r_rptr_p)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T7,T11,T15 |
LineNo. Expression
-1-: 299 (r_sram_rvalid_i) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T7,T9 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 301 (stored) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T7,T9 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 126 if ((!rst_wr_ni))
-2-: 129 if (w_wptr_inc)
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T1,T2,T3 |
0 |
1 |
Covered |
T5,T7,T9 |
0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 168 if ((!rst_rd_ni))
-2-: 171 if (r_rptr_inc)
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T1,T2,T3 |
0 |
1 |
Covered |
T5,T7,T9 |
0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 204 if ((!rst_rd_ni))
-2-: 206 if (r_sram_rptr_inc)
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T1,T2,T3 |
0 |
1 |
Covered |
T5,T7,T9 |
0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 279 if (stored)
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T7,T9 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 324 if ((!rst_rd_ni))
-2-: 327 if (store_en)
-3-: 330 if (((!r_sram_rvalid_i) && rfifo_ack))
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T1,T2,T3 |
0 |
1 |
- |
Covered |
T5,T7,T9 |
0 |
0 |
1 |
Covered |
T5,T7,T9 |
0 |
0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 349 (decval[(PtrW - 1)]) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T7,T11 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 373 if (grayval[(PtrW - 1)])
Branches:
-1- | Status | Tests |
1 |
Covered |
T7,T11,T15 |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_upload.u_addrfifo
Assertion Details
MinDepth_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1852 |
1852 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T3 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T8 |
1 |
1 |
0 |
0 |
T9 |
1 |
1 |
0 |
0 |
T10 |
1 |
1 |
0 |
0 |
NoRAckInEmpty_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1203785710 |
3508 |
0 |
0 |
T5 |
405811 |
15 |
0 |
0 |
T6 |
1762 |
0 |
0 |
0 |
T7 |
232174 |
21 |
0 |
0 |
T8 |
365507 |
0 |
0 |
0 |
T9 |
127203 |
6 |
0 |
0 |
T10 |
42843 |
0 |
0 |
0 |
T11 |
664506 |
18 |
0 |
0 |
T12 |
68526 |
0 |
0 |
0 |
T13 |
131303 |
0 |
0 |
0 |
T14 |
0 |
9 |
0 |
0 |
T15 |
0 |
26 |
0 |
0 |
T16 |
0 |
14 |
0 |
0 |
T23 |
0 |
4 |
0 |
0 |
T25 |
0 |
4 |
0 |
0 |
T26 |
15735 |
0 |
0 |
0 |
T27 |
0 |
5 |
0 |
0 |
NoWAckInFull_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
381988954 |
3508 |
0 |
0 |
T5 |
992277 |
15 |
0 |
0 |
T6 |
360 |
0 |
0 |
0 |
T7 |
749009 |
21 |
0 |
0 |
T8 |
181176 |
0 |
0 |
0 |
T9 |
318604 |
6 |
0 |
0 |
T10 |
19687 |
0 |
0 |
0 |
T11 |
145674 |
18 |
0 |
0 |
T12 |
127554 |
0 |
0 |
0 |
T13 |
116611 |
0 |
0 |
0 |
T14 |
0 |
9 |
0 |
0 |
T15 |
0 |
26 |
0 |
0 |
T16 |
0 |
14 |
0 |
0 |
T23 |
0 |
4 |
0 |
0 |
T25 |
0 |
4 |
0 |
0 |
T26 |
4272 |
0 |
0 |
0 |
T27 |
0 |
5 |
0 |
0 |
ParamCheckDepth_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1852 |
1852 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T3 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T8 |
1 |
1 |
0 |
0 |
T9 |
1 |
1 |
0 |
0 |
T10 |
1 |
1 |
0 |
0 |
RSramRvalidOneCycle_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1203785710 |
3508 |
0 |
0 |
T5 |
405811 |
15 |
0 |
0 |
T6 |
1762 |
0 |
0 |
0 |
T7 |
232174 |
21 |
0 |
0 |
T8 |
365507 |
0 |
0 |
0 |
T9 |
127203 |
6 |
0 |
0 |
T10 |
42843 |
0 |
0 |
0 |
T11 |
664506 |
18 |
0 |
0 |
T12 |
68526 |
0 |
0 |
0 |
T13 |
131303 |
0 |
0 |
0 |
T14 |
0 |
9 |
0 |
0 |
T15 |
0 |
26 |
0 |
0 |
T16 |
0 |
14 |
0 |
0 |
T23 |
0 |
4 |
0 |
0 |
T25 |
0 |
4 |
0 |
0 |
T26 |
15735 |
0 |
0 |
0 |
T27 |
0 |
5 |
0 |
0 |
RptrGrayOneBitAtATime_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1203785710 |
3508 |
0 |
0 |
T5 |
405811 |
15 |
0 |
0 |
T6 |
1762 |
0 |
0 |
0 |
T7 |
232174 |
21 |
0 |
0 |
T8 |
365507 |
0 |
0 |
0 |
T9 |
127203 |
6 |
0 |
0 |
T10 |
42843 |
0 |
0 |
0 |
T11 |
664506 |
18 |
0 |
0 |
T12 |
68526 |
0 |
0 |
0 |
T13 |
131303 |
0 |
0 |
0 |
T14 |
0 |
9 |
0 |
0 |
T15 |
0 |
26 |
0 |
0 |
T16 |
0 |
14 |
0 |
0 |
T23 |
0 |
4 |
0 |
0 |
T25 |
0 |
4 |
0 |
0 |
T26 |
15735 |
0 |
0 |
0 |
T27 |
0 |
5 |
0 |
0 |
RptrIncDataValid_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1203785710 |
3508 |
0 |
0 |
T5 |
405811 |
15 |
0 |
0 |
T6 |
1762 |
0 |
0 |
0 |
T7 |
232174 |
21 |
0 |
0 |
T8 |
365507 |
0 |
0 |
0 |
T9 |
127203 |
6 |
0 |
0 |
T10 |
42843 |
0 |
0 |
0 |
T11 |
664506 |
18 |
0 |
0 |
T12 |
68526 |
0 |
0 |
0 |
T13 |
131303 |
0 |
0 |
0 |
T14 |
0 |
9 |
0 |
0 |
T15 |
0 |
26 |
0 |
0 |
T16 |
0 |
14 |
0 |
0 |
T23 |
0 |
4 |
0 |
0 |
T25 |
0 |
4 |
0 |
0 |
T26 |
15735 |
0 |
0 |
0 |
T27 |
0 |
5 |
0 |
0 |
RptrIncrease_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1203785710 |
3508 |
0 |
0 |
T5 |
405811 |
15 |
0 |
0 |
T6 |
1762 |
0 |
0 |
0 |
T7 |
232174 |
21 |
0 |
0 |
T8 |
365507 |
0 |
0 |
0 |
T9 |
127203 |
6 |
0 |
0 |
T10 |
42843 |
0 |
0 |
0 |
T11 |
664506 |
18 |
0 |
0 |
T12 |
68526 |
0 |
0 |
0 |
T13 |
131303 |
0 |
0 |
0 |
T14 |
0 |
9 |
0 |
0 |
T15 |
0 |
26 |
0 |
0 |
T16 |
0 |
14 |
0 |
0 |
T23 |
0 |
4 |
0 |
0 |
T25 |
0 |
4 |
0 |
0 |
T26 |
15735 |
0 |
0 |
0 |
T27 |
0 |
5 |
0 |
0 |
SramRvalid_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1203785710 |
3508 |
0 |
0 |
T5 |
405811 |
15 |
0 |
0 |
T6 |
1762 |
0 |
0 |
0 |
T7 |
232174 |
21 |
0 |
0 |
T8 |
365507 |
0 |
0 |
0 |
T9 |
127203 |
6 |
0 |
0 |
T10 |
42843 |
0 |
0 |
0 |
T11 |
664506 |
18 |
0 |
0 |
T12 |
68526 |
0 |
0 |
0 |
T13 |
131303 |
0 |
0 |
0 |
T14 |
0 |
9 |
0 |
0 |
T15 |
0 |
26 |
0 |
0 |
T16 |
0 |
14 |
0 |
0 |
T23 |
0 |
4 |
0 |
0 |
T25 |
0 |
4 |
0 |
0 |
T26 |
15735 |
0 |
0 |
0 |
T27 |
0 |
5 |
0 |
0 |
WSramRvalid_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
381988954 |
381988954 |
0 |
0 |
T1 |
13408 |
13408 |
0 |
0 |
T2 |
39758 |
39758 |
0 |
0 |
T3 |
1325 |
1325 |
0 |
0 |
T5 |
992277 |
992277 |
0 |
0 |
T6 |
360 |
360 |
0 |
0 |
T7 |
749009 |
749009 |
0 |
0 |
T8 |
181176 |
181176 |
0 |
0 |
T9 |
318604 |
318604 |
0 |
0 |
T10 |
19687 |
19687 |
0 |
0 |
T11 |
145674 |
145674 |
0 |
0 |
WidthMatch_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1852 |
1852 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T3 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T8 |
1 |
1 |
0 |
0 |
T9 |
1 |
1 |
0 |
0 |
T10 |
1 |
1 |
0 |
0 |
WptrGrayOneBitAtATime_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
381988954 |
3508 |
0 |
0 |
T5 |
992277 |
15 |
0 |
0 |
T6 |
360 |
0 |
0 |
0 |
T7 |
749009 |
21 |
0 |
0 |
T8 |
181176 |
0 |
0 |
0 |
T9 |
318604 |
6 |
0 |
0 |
T10 |
19687 |
0 |
0 |
0 |
T11 |
145674 |
18 |
0 |
0 |
T12 |
127554 |
0 |
0 |
0 |
T13 |
116611 |
0 |
0 |
0 |
T14 |
0 |
9 |
0 |
0 |
T15 |
0 |
26 |
0 |
0 |
T16 |
0 |
14 |
0 |
0 |
T23 |
0 |
4 |
0 |
0 |
T25 |
0 |
4 |
0 |
0 |
T26 |
4272 |
0 |
0 |
0 |
T27 |
0 |
5 |
0 |
0 |
WptrIncrease_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
381988954 |
3508 |
0 |
0 |
T5 |
992277 |
15 |
0 |
0 |
T6 |
360 |
0 |
0 |
0 |
T7 |
749009 |
21 |
0 |
0 |
T8 |
181176 |
0 |
0 |
0 |
T9 |
318604 |
6 |
0 |
0 |
T10 |
19687 |
0 |
0 |
0 |
T11 |
145674 |
18 |
0 |
0 |
T12 |
127554 |
0 |
0 |
0 |
T13 |
116611 |
0 |
0 |
0 |
T14 |
0 |
9 |
0 |
0 |
T15 |
0 |
26 |
0 |
0 |
T16 |
0 |
14 |
0 |
0 |
T23 |
0 |
4 |
0 |
0 |
T25 |
0 |
4 |
0 |
0 |
T26 |
4272 |
0 |
0 |
0 |
T27 |
0 |
5 |
0 |
0 |