Module Definition
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Module : spid_upload
SCORELINECONDTOGGLEFSMBRANCHASSERT
96.37 100.00 86.11 100.00 95.74 100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_spi_device_0.1/rtl/spid_upload.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.u_upload 96.37 100.00 86.11 100.00 95.74 100.00



Module Instance : tb.dut.u_upload

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
96.37 100.00 86.11 100.00 95.74 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
91.23 98.60 74.15 100.00 94.12 89.29


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
91.69 94.25 84.31 96.94 87.50 95.45 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_addrfifo 93.75 100.00 75.00 100.00 100.00
u_arbiter 71.57 92.21 51.22 71.43 71.43
u_cmdfifo 93.75 100.00 75.00 100.00 100.00
u_payload_buffer 96.15 100.00 84.62 100.00 100.00
u_payloadptr_clr_psync 100.00 100.00 100.00 100.00 100.00
u_sys_cmdfifo_set 100.00 100.00 100.00 100.00


Since this is the module's only instance, the coverage report is the same as for the module.
Line Coverage for Module : spid_upload
Line No.TotalCoveredPercent
TOTAL109109100.00
CONT_ASSIGN13411100.00
CONT_ASSIGN13711100.00
CONT_ASSIGN14311100.00
CONT_ASSIGN19411100.00
CONT_ASSIGN20611100.00
CONT_ASSIGN21311100.00
CONT_ASSIGN23411100.00
CONT_ASSIGN24111100.00
CONT_ASSIGN24211100.00
CONT_ASSIGN24411100.00
CONT_ASSIGN24611100.00
CONT_ASSIGN25111100.00
CONT_ASSIGN25211100.00
ALWAYS25666100.00
ALWAYS26233100.00
ALWAYS26844100.00
CONT_ASSIGN30711100.00
ALWAYS32233100.00
ALWAYS3461010100.00
ALWAYS36788100.00
ALWAYS39088100.00
ALWAYS40866100.00
ALWAYS41866100.00
CONT_ASSIGN42511100.00
ALWAYS42833100.00
ALWAYS4382626100.00
CONT_ASSIGN57011100.00
CONT_ASSIGN57711100.00
CONT_ASSIGN57811100.00
CONT_ASSIGN57911100.00
CONT_ASSIGN58011100.00
CONT_ASSIGN63011100.00
CONT_ASSIGN63711100.00
CONT_ASSIGN63811100.00
CONT_ASSIGN63911100.00
CONT_ASSIGN64011100.00
CONT_ASSIGN70711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_spi_device_0.1/rtl/spid_upload.sv' or '../src/lowrisc_ip_spi_device_0.1/rtl/spid_upload.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
134 1 1
137 1 1
143 1 1
194 1 1
206 1 1
213 1 1
234 1 1
241 1 1
242 1 1
244 1 1
246 1 1
251 1 1
252 1 1
256 2 2
257 2 2
258 2 2
MISSING_ELSE
262 1 1
263 1 1
264 1 1
MISSING_ELSE
268 1 1
269 1 1
270 1 1
271 1 1
MISSING_ELSE
307 1 1
322 1 1
323 1 1
325 1 1
346 1 1
347 1 1
348 1 1
349 1 1
350 1 1
351 1 1
352 1 1
353 1 1
355 1 1
MISSING_ELSE
357 1 1
MISSING_ELSE
367 2 2
368 2 2
369 1 1
370 1 1
371 1 1
372 1 1
MISSING_ELSE
390 2 2
391 2 2
392 1 1
395 1 1
396 1 1
399 1 1
MISSING_ELSE
408 2 2
409 2 2
410 1 1
411 1 1
MISSING_ELSE
418 2 2
419 2 2
420 1 1
421 1 1
MISSING_ELSE
425 1 1
428 1 1
429 1 1
431 1 1
438 1 1
440 1 1
441 1 1
442 1 1
444 1 1
445 1 1
447 1 1
449 1 1
450 1 1
452 1 1
454 1 1
455 1 1
456 1 1
459 1 1
461 1 1
465 1 1
469 1 1
471 1 1
==> MISSING_ELSE
475 1 1
MISSING_ELSE
481 1 1
483 1 1
484 1 1
486 1 1
MISSING_ELSE
492 1 1
493 1 1
494 1 1
MISSING_ELSE
570 1 1
577 1 1
578 1 1
579 1 1
580 1 1
630 1 1
637 1 1
638 1 1
639 1 1
640 1 1
707 1 1


Cond Coverage for Module : spid_upload
TotalCoveredPercent
Conditions363186.11
Logical363186.11
Non-Logical00
Event00

 LINE       242
 EXPRESSION (cmdinfo_addr_mode != AddrDisabled)
            -----------------1-----------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T5

 LINE       244
 EXPRESSION (cmdinfo_addr_mode == Addr4B)
            --------------1--------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T5

 LINE       257
 EXPRESSION (cmdinfo_addr_4b_en ? 5'd31 : 5'd23)
             ---------1--------
-1-StatusTests
0CoveredT5,T7,T11
1CoveredT5,T7,T9

 LINE       270
 EXPRESSION (s2p_valid_i && addr_shift)
             -----1-----    -----2----
-1--2-StatusTests
01CoveredT5,T7,T9
10CoveredT1,T2,T5
11CoveredT5,T7,T9

 LINE       307
 EXPRESSION (cmdfifo_wvalid && cmdfifo_wready)
             -------1------    -------2------
-1--2-StatusTests
01Not Covered
10Not Covered
11CoveredT5,T7,T9

 LINE       353
 EXPRESSION (payloadptr == 8'((PayloadByte - 1)))
            ------------------1------------------
-1-StatusTests
0CoveredT5,T7,T9
1CoveredT5,T7,T11

 LINE       369
 EXPRESSION (sys_cmdfifo_set && payload_max)
             -------1-------    -----2-----
-1--2-StatusTests
01CoveredT5,T7,T11
10CoveredT5,T7,T9
11CoveredT5,T7,T11

 LINE       371
 EXPRESSION (sys_cmdfifo_set && ((!payload_max)))
             -------1-------    --------2-------
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11CoveredT5,T7,T9

 LINE       392
 EXPRESSION (sys_cmdfifo_set && payload_max)
             -------1-------    -----2-----
-1--2-StatusTests
01CoveredT5,T7,T11
10CoveredT5,T7,T9
11CoveredT5,T7,T11

 LINE       396
 EXPRESSION (sys_cmdfifo_set && ((!payload_max)))
             -------1-------    --------2-------
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11CoveredT5,T7,T9

 LINE       410
 EXPRESSION (payloadptr_inc && payload_max)
             -------1------    -----2-----
-1--2-StatusTests
01CoveredT5,T7,T11
10CoveredT5,T7,T9
11CoveredT5,T7,T11

 LINE       454
 EXPRESSION (s2p_valid_i && (cmd_only_sel_dp_i == DpUpload))
             -----1-----    ---------------2---------------
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T5
11CoveredT5,T7,T9

 LINE       454
 SUB-EXPRESSION (cmd_only_sel_dp_i == DpUpload)
                ---------------1---------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT5,T7,T9

 LINE       483
 EXPRESSION (addrcnt == '0)
            -------1-------
-1-StatusTests
0CoveredT5,T7,T9
1CoveredT5,T7,T9

FSM Coverage for Module : spid_upload
Summary for FSM :: st_q
TotalCoveredPercent
States 3 3 100.00 (Not included in score)
Transitions 3 3 100.00
Sequences 0 0

State, Transition and Sequence Details for FSM :: st_q
statesLine No.CoveredTests
StAddress 456 Covered T5,T7,T9
StIdle 453 Covered T1,T2,T3
StPayload 461 Covered T5,T7,T9


transitionsLine No.CoveredTests
StAddress->StPayload 484 Covered T5,T7,T9
StIdle->StAddress 456 Covered T5,T7,T9
StIdle->StPayload 461 Covered T5,T7,T9



Branch Coverage for Module : spid_upload
Line No.TotalCoveredPercent
Branches 47 45 95.74
IF 256 5 5 100.00
IF 263 2 2 100.00
IF 268 3 3 100.00
IF 322 2 2 100.00
IF 346 5 5 100.00
IF 367 5 5 100.00
IF 390 5 5 100.00
IF 408 4 4 100.00
IF 418 4 4 100.00
IF 428 2 2 100.00
CASE 452 10 8 80.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_spi_device_0.1/rtl/spid_upload.sv' or '../src/lowrisc_ip_spi_device_0.1/rtl/spid_upload.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 256 if ((!rst_ni)) -2-: 257 if (addr_update) -3-: 257 (cmdinfo_addr_4b_en) ? -4-: 258 if (addr_shift)

Branches:
-1--2--3--4-StatusTests
1 - - - Covered T1,T2,T3
0 1 1 - Covered T5,T7,T9
0 1 0 - Covered T5,T7,T11
0 0 - 1 Covered T5,T7,T9
0 0 - 0 Covered T1,T2,T5


LineNo. Expression -1-: 263 if (addr_shift)

Branches:
-1-StatusTests
1 Covered T5,T7,T9
0 Covered T1,T2,T3


LineNo. Expression -1-: 268 if ((!rst_ni)) -2-: 270 if ((s2p_valid_i && addr_shift))

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T5,T7,T9
0 0 Covered T1,T2,T5


LineNo. Expression -1-: 322 if ((!sys_rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 346 if ((!sys_rst_ni)) -2-: 349 if (payloadptr_clr) -3-: 352 if (payloadptr_inc) -4-: 353 if ((payloadptr == 8'((PayloadByte - 1))))

Branches:
-1--2--3--4-StatusTests
1 - - - Covered T1,T2,T3
0 1 - - Covered T5,T7,T9
0 0 1 1 Covered T5,T7,T11
0 0 1 0 Covered T5,T7,T9
0 0 0 - Covered T1,T2,T3


LineNo. Expression -1-: 367 if ((!sys_rst_ni)) -2-: 368 if (sys_payloadptr_clr_posedge) -3-: 369 if ((sys_cmdfifo_set && payload_max)) -4-: 371 if ((sys_cmdfifo_set && (!payload_max)))

Branches:
-1--2--3--4-StatusTests
1 - - - Covered T1,T2,T3
0 1 - - Covered T5,T7,T9
0 0 1 - Covered T5,T7,T11
0 0 0 1 Covered T5,T7,T9
0 0 0 0 Covered T1,T2,T3


LineNo. Expression -1-: 390 if ((!sys_rst_ni)) -2-: 391 if (sys_payloadptr_clr_posedge) -3-: 392 if ((sys_cmdfifo_set && payload_max)) -4-: 396 if ((sys_cmdfifo_set && (!payload_max)))

Branches:
-1--2--3--4-StatusTests
1 - - - Covered T1,T2,T3
0 1 - - Covered T5,T7,T9
0 0 1 - Covered T5,T7,T11
0 0 0 1 Covered T5,T7,T9
0 0 0 0 Covered T1,T2,T3


LineNo. Expression -1-: 408 if ((!sys_rst_ni)) -2-: 409 if (payloadptr_clr) -3-: 410 if ((payloadptr_inc && payload_max))

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T2,T3
0 1 - Covered T5,T7,T9
0 0 1 Covered T5,T7,T11
0 0 0 Covered T1,T2,T3


LineNo. Expression -1-: 418 if ((!sys_rst_ni)) -2-: 419 if (sys_payloadptr_clr_posedge) -3-: 420 if (sys_cmdfifo_set)

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T2,T3
0 1 - Covered T5,T7,T9
0 0 1 Covered T5,T7,T9
0 0 0 Covered T1,T2,T3


LineNo. Expression -1-: 428 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T5


LineNo. Expression -1-: 452 case (st_q) -2-: 454 if ((s2p_valid_i && (cmd_only_sel_dp_i == DpUpload))) -3-: 455 if (cmdinfo_addr_en) -4-: 469 if (cmd_only_info_i.busy) -5-: 483 if ((addrcnt == '0)) -6-: 492 if (s2p_valid_i)

Branches:
-1--2--3--4--5--6-StatusTests
StIdle 1 1 - - - Covered T5,T7,T9
StIdle 1 0 - - - Covered T5,T7,T9
StIdle 1 - 1 - - Covered T5,T7,T9
StIdle 1 - 0 - - Not Covered
StIdle 0 - - - - Covered T1,T2,T3
StAddress - - - 1 - Covered T5,T7,T9
StAddress - - - 0 - Covered T5,T7,T9
StPayload - - - - 1 Covered T5,T7,T9
StPayload - - - - 0 Covered T5,T7,T9
default - - - - - Not Covered


Assert Coverage for Module : spid_upload
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 5 5 100.00 5 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 5 5 100.00 5 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
AddrFifoNeverFull_M 381988954 3508 0 0
CmdFifoNeverFull_M 381988954 4724 0 0
CmdFifoPush_A 381988954 4724 0 0
FifosOnlyOneValid_A 381988954 293578611 0 0
PayloadNeverFull_M 381988954 1384051 0 0


AddrFifoNeverFull_M
NameAttemptsReal SuccessesFailuresIncomplete
Total 381988954 3508 0 0
T5 992277 15 0 0
T6 360 0 0 0
T7 749009 21 0 0
T8 181176 0 0 0
T9 318604 6 0 0
T10 19687 0 0 0
T11 145674 18 0 0
T12 127554 0 0 0
T13 116611 0 0 0
T14 0 9 0 0
T15 0 26 0 0
T16 0 14 0 0
T23 0 4 0 0
T25 0 4 0 0
T26 4272 0 0 0
T27 0 5 0 0

CmdFifoNeverFull_M
NameAttemptsReal SuccessesFailuresIncomplete
Total 381988954 4724 0 0
T5 992277 22 0 0
T6 360 0 0 0
T7 749009 28 0 0
T8 181176 0 0 0
T9 318604 7 0 0
T10 19687 0 0 0
T11 145674 25 0 0
T12 127554 0 0 0
T13 116611 0 0 0
T14 0 12 0 0
T15 0 34 0 0
T16 0 19 0 0
T23 0 8 0 0
T25 0 4 0 0
T26 4272 0 0 0
T27 0 8 0 0

CmdFifoPush_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 381988954 4724 0 0
T5 992277 22 0 0
T6 360 0 0 0
T7 749009 28 0 0
T8 181176 0 0 0
T9 318604 7 0 0
T10 19687 0 0 0
T11 145674 25 0 0
T12 127554 0 0 0
T13 116611 0 0 0
T14 0 12 0 0
T15 0 34 0 0
T16 0 19 0 0
T23 0 8 0 0
T25 0 4 0 0
T26 4272 0 0 0
T27 0 8 0 0

FifosOnlyOneValid_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 381988954 293578611 0 0
T1 13408 13408 0 0
T2 39758 38698 0 0
T3 1325 0 0 0
T5 992277 973085 0 0
T6 360 0 0 0
T7 749009 687436 0 0
T8 181176 181176 0 0
T9 318604 262433 0 0
T10 19687 19687 0 0
T11 145674 130733 0 0
T12 0 127130 0 0
T13 0 115370 0 0

PayloadNeverFull_M
NameAttemptsReal SuccessesFailuresIncomplete
Total 381988954 1384051 0 0
T5 992277 10248 0 0
T6 360 0 0 0
T7 749009 4911 0 0
T8 181176 0 0 0
T9 318604 380 0 0
T10 19687 0 0 0
T11 145674 11130 0 0
T12 127554 0 0 0
T13 116611 0 0 0
T14 0 6564 0 0
T15 0 7776 0 0
T16 0 2488 0 0
T23 0 896 0 0
T25 0 757 0 0
T26 4272 0 0 0
T27 0 4474 0 0

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%