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Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 gen_dfifo[2].fifo_d


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
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Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 gen_dfifo[2].fifo_d


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
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Module Instances:
tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo
tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo
Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo
Line No.TotalCoveredPercent
TOTAL44100.00
CONT_ASSIGN4411100.00
CONT_ASSIGN4511100.00
CONT_ASSIGN4811100.00
CONT_ASSIGN4911100.00
CONT_ASSIGN5300
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
44 1 1
45 1 1
48 1 1
49 1 1
53 unreachable


Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 5 5 100.00 5 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 5 5 100.00 5 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DataKnown_A 1208498655 23346532 0 0
DepthKnown_A 1208498655 1208236562 0 0
RvalidKnown_A 1208498655 1208236562 0 0
WreadyKnown_A 1208498655 1208236562 0 0
gen_passthru_fifo.paramCheckPass 2202 2202 0 0


DataKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1208498655 23346532 0 0
T1 110812 86 0 0
T2 208167 1991 0 0
T3 5602 56 0 0
T4 1518 63 0 0
T5 405811 52675 0 0
T6 1762 17 0 0
T7 232174 39127 0 0
T8 365507 71 0 0
T9 127203 33812 0 0
T10 42843 83 0 0

DepthKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1208498655 1208236562 0 0
T1 110812 110733 0 0
T2 208167 208073 0 0
T3 5602 5524 0 0
T4 1518 1428 0 0
T5 405811 405804 0 0
T6 1762 1664 0 0
T7 232174 232167 0 0
T8 365507 365413 0 0
T9 127203 127197 0 0
T10 42843 42770 0 0

RvalidKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1208498655 1208236562 0 0
T1 110812 110733 0 0
T2 208167 208073 0 0
T3 5602 5524 0 0
T4 1518 1428 0 0
T5 405811 405804 0 0
T6 1762 1664 0 0
T7 232174 232167 0 0
T8 365507 365413 0 0
T9 127203 127197 0 0
T10 42843 42770 0 0

WreadyKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1208498655 1208236562 0 0
T1 110812 110733 0 0
T2 208167 208073 0 0
T3 5602 5524 0 0
T4 1518 1428 0 0
T5 405811 405804 0 0
T6 1762 1664 0 0
T7 232174 232167 0 0
T8 365507 365413 0 0
T9 127203 127197 0 0
T10 42843 42770 0 0

gen_passthru_fifo.paramCheckPass
NameAttemptsReal SuccessesFailuresIncomplete
Total 2202 2202 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T7 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo
Line No.TotalCoveredPercent
TOTAL44100.00
CONT_ASSIGN4411100.00
CONT_ASSIGN4511100.00
CONT_ASSIGN4811100.00
CONT_ASSIGN4911100.00
CONT_ASSIGN5300
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
44 1 1
45 1 1
48 1 1
49 1 1
53 unreachable


Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 5 5 100.00 5 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 5 5 100.00 5 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DataKnown_A 1208498655 51694073 0 0
DepthKnown_A 1208498655 1208236562 0 0
RvalidKnown_A 1208498655 1208236562 0 0
WreadyKnown_A 1208498655 1208236562 0 0
gen_passthru_fifo.paramCheckPass 2202 2202 0 0


DataKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1208498655 51694073 0 0
T1 110812 86 0 0
T2 208167 1990 0 0
T3 5602 56 0 0
T4 1518 300 0 0
T5 405811 52537 0 0
T6 1762 76 0 0
T7 232174 115516 0 0
T8 365507 71 0 0
T9 127203 133281 0 0
T10 42843 228 0 0

DepthKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1208498655 1208236562 0 0
T1 110812 110733 0 0
T2 208167 208073 0 0
T3 5602 5524 0 0
T4 1518 1428 0 0
T5 405811 405804 0 0
T6 1762 1664 0 0
T7 232174 232167 0 0
T8 365507 365413 0 0
T9 127203 127197 0 0
T10 42843 42770 0 0

RvalidKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1208498655 1208236562 0 0
T1 110812 110733 0 0
T2 208167 208073 0 0
T3 5602 5524 0 0
T4 1518 1428 0 0
T5 405811 405804 0 0
T6 1762 1664 0 0
T7 232174 232167 0 0
T8 365507 365413 0 0
T9 127203 127197 0 0
T10 42843 42770 0 0

WreadyKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1208498655 1208236562 0 0
T1 110812 110733 0 0
T2 208167 208073 0 0
T3 5602 5524 0 0
T4 1518 1428 0 0
T5 405811 405804 0 0
T6 1762 1664 0 0
T7 232174 232167 0 0
T8 365507 365413 0 0
T9 127203 127197 0 0
T10 42843 42770 0 0

gen_passthru_fifo.paramCheckPass
NameAttemptsReal SuccessesFailuresIncomplete
Total 2202 2202 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T7 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0

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