Module Definition
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Module : prim_fifo_sync
SCORELINECONDTOGGLEFSMBRANCHASSERT
91.73 100.00 69.69 97.22 100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.u_tlul2sram_egress.u_sramreqfifo 62.17 86.36 42.31 60.00 60.00
tb.dut.u_tlul2sram_egress.u_rspfifo 62.60 90.91 41.18 58.33 60.00
tb.dut.u_upload.u_arbiter.u_req_fifo 63.30 90.91 42.31 60.00 60.00
tb.dut.u_spi_tpm.u_arbiter.u_req_fifo 88.85 100.00 65.38 90.00 100.00
tb.dut.u_sys_sram_arbiter.u_req_fifo 88.85 100.00 65.38 90.00 100.00
tb.dut.u_tlul2sram_ingress.u_sramreqfifo 89.81 100.00 69.23 90.00 100.00
tb.dut.u_tlul2sram_egress.u_reqfifo 90.77 100.00 73.08 90.00 100.00
tb.dut.u_tlul2sram_ingress.u_reqfifo 90.77 100.00 73.08 90.00 100.00
tb.dut.u_readcmd.u_readsram.u_sram_fifo 91.25 100.00 75.00 90.00 100.00
tb.dut.u_spi_tpm.u_sram_fifo 92.03 100.00 78.12 90.00 100.00
tb.dut.u_tlul2sram_ingress.u_rspfifo 92.03 100.00 76.47 91.67 100.00
tb.dut.u_readcmd.u_readsram.u_fifo 96.88 100.00 87.50 100.00 100.00
tb.dut.u_reg.u_socket.fifo_h.reqfifo 100.00 100.00 100.00
tb.dut.u_reg.u_socket.fifo_h.rspfifo 100.00 100.00 100.00
tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo 100.00 100.00 100.00
tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo 100.00 100.00 100.00
tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo 100.00 100.00 100.00
tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo 100.00 100.00 100.00
tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo 100.00 100.00 100.00
tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo 100.00 100.00 100.00

Line Coverage for Module : prim_fifo_sync ( parameter Width=32,Pass=1,Depth=1,OutputZeroIfEmpty=0,Secure=0,DepthW=1,gen_normal_fifo.PTRV_W=1,gen_normal_fifo.PTR_WIDTH=2 )
Line Coverage for Module self-instances :
SCORELINE
91.25 100.00
tb.dut.u_readcmd.u_readsram.u_sram_fifo

SCORELINE
92.03 100.00
tb.dut.u_spi_tpm.u_sram_fifo

Line No.TotalCoveredPercent
TOTAL2222100.00
ALWAYS7044100.00
CONT_ASSIGN8411100.00
CONT_ASSIGN8511100.00
CONT_ASSIGN8611100.00
CONT_ASSIGN8711100.00
CONT_ASSIGN8811100.00
CONT_ASSIGN9211100.00
CONT_ASSIGN9311100.00
CONT_ASSIGN9811100.00
CONT_ASSIGN9911100.00
CONT_ASSIGN10011100.00
CONT_ASSIGN14511100.00
CONT_ASSIGN14611100.00
CONT_ASSIGN15411100.00
ALWAYS15722100.00
CONT_ASSIGN17211100.00
CONT_ASSIGN17311100.00
CONT_ASSIGN18211100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
70 1 1
71 1 1
72 1 1
73 1 1
MISSING_ELSE
84 1 1
85 1 1
86 1 1
87 1 1
88 1 1
92 1 1
93 1 1
98 1 1
99 1 1
100 1 1
145 1 1
146 1 1
154 1 1
157 1 1
158 1 1
MISSING_ELSE
172 1 1
173 1 1
182 1 1

Line Coverage for Module : prim_fifo_sync ( parameter Width=8,Pass=1,Depth=2,OutputZeroIfEmpty=0,Secure=0,DepthW=2,gen_normal_fifo.PTRV_W=1,gen_normal_fifo.PTR_WIDTH=2 )
Line Coverage for Module self-instances :
SCORELINE
96.88 100.00
tb.dut.u_readcmd.u_readsram.u_fifo

Line No.TotalCoveredPercent
TOTAL2222100.00
ALWAYS7044100.00
CONT_ASSIGN8411100.00
CONT_ASSIGN8511100.00
CONT_ASSIGN8611100.00
CONT_ASSIGN8711100.00
CONT_ASSIGN8811100.00
CONT_ASSIGN9211100.00
CONT_ASSIGN9311100.00
CONT_ASSIGN9811100.00
CONT_ASSIGN9911100.00
CONT_ASSIGN10011100.00
CONT_ASSIGN14511100.00
CONT_ASSIGN14611100.00
CONT_ASSIGN16211100.00
ALWAYS16522100.00
CONT_ASSIGN17211100.00
CONT_ASSIGN17311100.00
CONT_ASSIGN18211100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
70 1 1
71 1 1
72 1 1
73 1 1
MISSING_ELSE
84 1 1
85 1 1
86 1 1
87 1 1
88 1 1
92 1 1
93 1 1
98 1 1
99 1 1
100 1 1
145 1 1
146 1 1
162 1 1
165 1 1
166 1 1
MISSING_ELSE
172 1 1
173 1 1
182 1 1

Line Coverage for Module : prim_fifo_sync ( parameter Width=3,Pass=0,Depth=4,OutputZeroIfEmpty=1,Secure=0,DepthW=3,gen_normal_fifo.PTRV_W=2,gen_normal_fifo.PTR_WIDTH=3 + Width=2,Pass=0,Depth=4,OutputZeroIfEmpty=1,Secure=0,DepthW=3,gen_normal_fifo.PTRV_W=2,gen_normal_fifo.PTR_WIDTH=3 + Width=5,Pass=0,Depth=4,OutputZeroIfEmpty=1,Secure=0,DepthW=3,gen_normal_fifo.PTRV_W=2,gen_normal_fifo.PTR_WIDTH=3 )
Line Coverage for Module self-instances :
SCORELINE
63.30 90.91
tb.dut.u_upload.u_arbiter.u_req_fifo

SCORELINE
88.85 100.00
tb.dut.u_spi_tpm.u_arbiter.u_req_fifo

SCORELINE
88.85 100.00
tb.dut.u_sys_sram_arbiter.u_req_fifo

Line No.TotalCoveredPercent
TOTAL2222100.00
ALWAYS7044100.00
CONT_ASSIGN8411100.00
CONT_ASSIGN8511100.00
CONT_ASSIGN8611100.00
CONT_ASSIGN8711100.00
CONT_ASSIGN8811100.00
CONT_ASSIGN9211100.00
CONT_ASSIGN9311100.00
CONT_ASSIGN9811100.00
CONT_ASSIGN9911100.00
CONT_ASSIGN10011100.00
CONT_ASSIGN14511100.00
CONT_ASSIGN14611100.00
CONT_ASSIGN16211100.00
ALWAYS16522100.00
CONT_ASSIGN17511100.00
CONT_ASSIGN17611100.00
CONT_ASSIGN18011100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
70 1 1
71 1 1
72 1 1
73 1 1
MISSING_ELSE
84 1 1
85 1 1
86 1 1
87 1 1
88 1 1
92 1 1
93 1 1
98 1 1
99 1 1
100 1 1
145 1 1
146 1 1
162 1 1
165 1 1
166 1 1
MISSING_ELSE
175 1 1
176 1 1
180 1 1

Line Coverage for Module : prim_fifo_sync ( parameter Width=17,Pass=0,Depth=1,OutputZeroIfEmpty=1,Secure=0,DepthW=1,gen_normal_fifo.PTRV_W=1,gen_normal_fifo.PTR_WIDTH=2 + Width=5,Pass=0,Depth=1,OutputZeroIfEmpty=1,Secure=0,DepthW=1,gen_normal_fifo.PTRV_W=1,gen_normal_fifo.PTR_WIDTH=2 )
Line Coverage for Module self-instances :
SCORELINE
90.77 100.00
tb.dut.u_tlul2sram_egress.u_reqfifo

SCORELINE
62.17 86.36
tb.dut.u_tlul2sram_egress.u_sramreqfifo

SCORELINE
90.77 100.00
tb.dut.u_tlul2sram_ingress.u_reqfifo

SCORELINE
89.81 100.00
tb.dut.u_tlul2sram_ingress.u_sramreqfifo

Line No.TotalCoveredPercent
TOTAL2222100.00
ALWAYS7044100.00
CONT_ASSIGN8411100.00
CONT_ASSIGN8511100.00
CONT_ASSIGN8611100.00
CONT_ASSIGN8711100.00
CONT_ASSIGN8811100.00
CONT_ASSIGN9211100.00
CONT_ASSIGN9311100.00
CONT_ASSIGN9811100.00
CONT_ASSIGN9911100.00
CONT_ASSIGN10011100.00
CONT_ASSIGN14511100.00
CONT_ASSIGN14611100.00
CONT_ASSIGN15411100.00
ALWAYS15722100.00
CONT_ASSIGN17511100.00
CONT_ASSIGN17611100.00
CONT_ASSIGN18011100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
70 1 1
71 1 1
72 1 1
73 1 1
MISSING_ELSE
84 1 1
85 1 1
86 1 1
87 1 1
88 1 1
92 1 1
93 1 1
98 1 1
99 1 1
100 1 1
145 1 1
146 1 1
154 1 1
157 1 1
158 1 1
MISSING_ELSE
175 1 1
176 1 1
180 1 1

Line Coverage for Module : prim_fifo_sync ( parameter Width=40,Pass=1,Depth=1,OutputZeroIfEmpty=1,Secure=0,DepthW=1,gen_normal_fifo.PTRV_W=1,gen_normal_fifo.PTR_WIDTH=2 )
Line Coverage for Module self-instances :
SCORELINE
62.60 90.91
tb.dut.u_tlul2sram_egress.u_rspfifo

SCORELINE
92.03 100.00
tb.dut.u_tlul2sram_ingress.u_rspfifo

Line No.TotalCoveredPercent
TOTAL2222100.00
ALWAYS7044100.00
CONT_ASSIGN8411100.00
CONT_ASSIGN8511100.00
CONT_ASSIGN8611100.00
CONT_ASSIGN8711100.00
CONT_ASSIGN8811100.00
CONT_ASSIGN9211100.00
CONT_ASSIGN9311100.00
CONT_ASSIGN9811100.00
CONT_ASSIGN9911100.00
CONT_ASSIGN10011100.00
CONT_ASSIGN14511100.00
CONT_ASSIGN14611100.00
CONT_ASSIGN15411100.00
ALWAYS15722100.00
CONT_ASSIGN17211100.00
CONT_ASSIGN17311100.00
CONT_ASSIGN18011100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
70 1 1
71 1 1
72 1 1
73 1 1
MISSING_ELSE
84 1 1
85 1 1
86 1 1
87 1 1
88 1 1
92 1 1
93 1 1
98 1 1
99 1 1
100 1 1
145 1 1
146 1 1
154 1 1
157 1 1
158 1 1
MISSING_ELSE
172 1 1
173 1 1
180 1 1

Line Coverage for Module : prim_fifo_sync ( parameter Width=109,Pass=1,Depth=0,OutputZeroIfEmpty=1,Secure=0,DepthW=1 + Width=65,Pass=1,Depth=0,OutputZeroIfEmpty=1,Secure=0,DepthW=1 + Width=108,Pass=1,Depth=0,OutputZeroIfEmpty=1,Secure=0,DepthW=1 )
Line Coverage for Module self-instances :
SCORELINE
100.00 100.00
tb.dut.u_reg.u_socket.fifo_h.reqfifo

SCORELINE
100.00 100.00
tb.dut.u_reg.u_socket.fifo_h.rspfifo

SCORELINE
100.00 100.00
tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

SCORELINE
100.00 100.00
tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo

SCORELINE
100.00 100.00
tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

SCORELINE
100.00 100.00
tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo

SCORELINE
100.00 100.00
tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo

SCORELINE
100.00 100.00
tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo

Line No.TotalCoveredPercent
TOTAL44100.00
CONT_ASSIGN4411100.00
CONT_ASSIGN4511100.00
CONT_ASSIGN4811100.00
CONT_ASSIGN4911100.00
CONT_ASSIGN5300
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
44 1 1
45 1 1
48 1 1
49 1 1
53 unreachable

Cond Coverage for Module : prim_fifo_sync ( parameter Width=2,Pass=0,Depth=4,OutputZeroIfEmpty=1,Secure=0,DepthW=3,gen_normal_fifo.PTRV_W=2,gen_normal_fifo.PTR_WIDTH=3 )
Cond Coverage for Module self-instances :
SCORECOND
88.85 65.38
tb.dut.u_spi_tpm.u_arbiter.u_req_fifo

TotalCoveredPercent
Conditions261765.38
Logical261765.38
Non-Logical00
Event00

 LINE       88
 EXPRESSION 
 Number  Term
      1  gen_normal_fifo.full ? (3'(Depth)) : ((gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb) ? ((3'(gen_normal_fifo.wptr_value) - 3'(gen_normal_fifo.rptr_value))) : (((3'(Depth) - 3'(gen_normal_fifo.rptr_value)) + 3'(gen_normal_fifo.wptr_value)))))
-1-StatusTests
0CoveredT1,T2,T3
1Not Covered 

 LINE       88
 SUB-EXPRESSION 
 Number  Term
      1  (gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb) ? ((3'(gen_normal_fifo.wptr_value) - 3'(gen_normal_fifo.rptr_value))) : (((3'(Depth) - 3'(gen_normal_fifo.rptr_value)) + 3'(gen_normal_fifo.wptr_value))))
-1-StatusTests
0CoveredT5,T7,T9
1CoveredT1,T2,T3 

 LINE       88
 SUB-EXPRESSION (gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb)
                ---------------------------1--------------------------
-1-StatusTests
0CoveredT5,T7,T9
1CoveredT1,T2,T3 

 LINE       92
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------
-1--2--3-StatusTests
011CoveredT3,T5,T6
101Not Covered
110Not Covered
111CoveredT5,T7,T9 

 LINE       93
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------
-1--2--3-StatusTests
011Not Covered
101Not Covered
110Not Covered
111CoveredT5,T7,T9 

 LINE       98
 EXPRESSION (((~gen_normal_fifo.full)) & ((~gen_normal_fifo.under_rst)))
             ------------1------------   ---------------2--------------
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11CoveredT3,T5,T6 

 LINE       100
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------
-1--2-StatusTests
01CoveredT3,T5,T6
10Not Covered
11CoveredT5,T7,T9 

 LINE       145
 EXPRESSION (gen_normal_fifo.fifo_wptr == (gen_normal_fifo.fifo_rptr ^ {1'b1, {(gen_normal_fifo.PTR_WIDTH - 1) {1'b0}}}))
            ------------------------------------------------------1------------------------------------------------------
-1-StatusTests
0CoveredT1,T2,T3
1Not Covered 

 LINE       146
 EXPRESSION (gen_normal_fifo.fifo_wptr == gen_normal_fifo.fifo_rptr)
            ----------------------------1---------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3 

 LINE       180
 EXPRESSION (gen_normal_fifo.empty ? 'b0 : gen_normal_fifo.rdata_int)
             ----------1----------
-1-StatusTests
0CoveredT5,T7,T9
1CoveredT1,T2,T3
Cond Coverage for Module : prim_fifo_sync ( parameter Width=3,Pass=0,Depth=4,OutputZeroIfEmpty=1,Secure=0,DepthW=3,gen_normal_fifo.PTRV_W=2,gen_normal_fifo.PTR_WIDTH=3 )
Cond Coverage for Module self-instances :
SCORECOND
63.30 42.31
tb.dut.u_upload.u_arbiter.u_req_fifo

TotalCoveredPercent
Conditions261142.31
Logical261142.31
Non-Logical00
Event00

 LINE       88
 EXPRESSION 
 Number  Term
      1  gen_normal_fifo.full ? (3'(Depth)) : ((gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb) ? ((3'(gen_normal_fifo.wptr_value) - 3'(gen_normal_fifo.rptr_value))) : (((3'(Depth) - 3'(gen_normal_fifo.rptr_value)) + 3'(gen_normal_fifo.wptr_value)))))
-1-StatusTests
0CoveredT1,T2,T3
1Not Covered 

 LINE       88
 SUB-EXPRESSION 
 Number  Term
      1  (gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb) ? ((3'(gen_normal_fifo.wptr_value) - 3'(gen_normal_fifo.rptr_value))) : (((3'(Depth) - 3'(gen_normal_fifo.rptr_value)) + 3'(gen_normal_fifo.wptr_value))))
-1-StatusTests
0Not Covered
1CoveredT1,T2,T3 

 LINE       88
 SUB-EXPRESSION (gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb)
                ---------------------------1--------------------------
-1-StatusTests
0Not Covered
1CoveredT1,T2,T3 

 LINE       92
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------
-1--2--3-StatusTests
011CoveredT1,T2,T5
101Not Covered
110Not Covered
111Not Covered 

 LINE       93
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------
-1--2--3-StatusTests
011Not Covered
101Not Covered
110Not Covered
111Not Covered 

 LINE       98
 EXPRESSION (((~gen_normal_fifo.full)) & ((~gen_normal_fifo.under_rst)))
             ------------1------------   ---------------2--------------
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11CoveredT1,T2,T5 

 LINE       100
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------
-1--2-StatusTests
01CoveredT1,T2,T5
10Not Covered
11Not Covered 

 LINE       145
 EXPRESSION (gen_normal_fifo.fifo_wptr == (gen_normal_fifo.fifo_rptr ^ {1'b1, {(gen_normal_fifo.PTR_WIDTH - 1) {1'b0}}}))
            ------------------------------------------------------1------------------------------------------------------
-1-StatusTests
0CoveredT1,T2,T3
1Not Covered 

 LINE       146
 EXPRESSION (gen_normal_fifo.fifo_wptr == gen_normal_fifo.fifo_rptr)
            ----------------------------1---------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3 

 LINE       180
 EXPRESSION (gen_normal_fifo.empty ? 'b0 : gen_normal_fifo.rdata_int)
             ----------1----------
-1-StatusTests
0Not Covered
1CoveredT1,T2,T3
Cond Coverage for Module : prim_fifo_sync ( parameter Width=32,Pass=1,Depth=1,OutputZeroIfEmpty=0,Secure=0,DepthW=1,gen_normal_fifo.PTRV_W=1,gen_normal_fifo.PTR_WIDTH=2 )
Cond Coverage for Module self-instances :
SCORECOND
91.25 75.00
tb.dut.u_readcmd.u_readsram.u_sram_fifo

SCORECOND
92.03 78.12
tb.dut.u_spi_tpm.u_sram_fifo

TotalCoveredPercent
Conditions322578.12
Logical322578.12
Non-Logical00
Event00

 LINE       88
 EXPRESSION 
 Number  Term
      1  gen_normal_fifo.full ? (1'(Depth)) : ((gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb) ? ((1'(gen_normal_fifo.wptr_value) - 1'(gen_normal_fifo.rptr_value))) : (((1'(Depth) - 1'(gen_normal_fifo.rptr_value)) + 1'(gen_normal_fifo.wptr_value)))))
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T5 

 LINE       88
 SUB-EXPRESSION 
 Number  Term
      1  (gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb) ? ((1'(gen_normal_fifo.wptr_value) - 1'(gen_normal_fifo.rptr_value))) : (((1'(Depth) - 1'(gen_normal_fifo.rptr_value)) + 1'(gen_normal_fifo.wptr_value))))
-1-StatusTests
0Not Covered
1CoveredT1,T2,T3 

 LINE       88
 SUB-EXPRESSION (gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb)
                ---------------------------1--------------------------
-1-StatusTests
0Not Covered
1CoveredT1,T2,T3 

 LINE       92
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101Not Covered
110Not Covered
111CoveredT1,T2,T5 

 LINE       93
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------
-1--2--3-StatusTests
011CoveredT5,T7,T9
101CoveredT1,T2,T5
110Not Covered
111CoveredT1,T2,T5 

 LINE       98
 EXPRESSION (((~gen_normal_fifo.full)) & ((~gen_normal_fifo.under_rst)))
             ------------1------------   ---------------2--------------
-1--2-StatusTests
01CoveredT1,T2,T5
10CoveredT1,T2,T3
11CoveredT1,T2,T3 

 LINE       100
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11CoveredT1,T2,T5 

 LINE       145
 EXPRESSION (gen_normal_fifo.fifo_wptr == (gen_normal_fifo.fifo_rptr ^ {1'b1, {(gen_normal_fifo.PTR_WIDTH - 1) {1'b0}}}))
            ------------------------------------------------------1------------------------------------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T5 

 LINE       146
 EXPRESSION (gen_normal_fifo.fifo_wptr == gen_normal_fifo.fifo_rptr)
            ----------------------------1---------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3 

 LINE       172
 EXPRESSION ((gen_normal_fifo.fifo_empty && wvalid_i) ? wdata_i : gen_normal_fifo.storage_rdata)
             --------------------1-------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T5 

 LINE       172
 SUB-EXPRESSION (gen_normal_fifo.fifo_empty && wvalid_i)
                 -------------1------------    ----2---
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11CoveredT1,T2,T5 

 LINE       173
 EXPRESSION (gen_normal_fifo.fifo_empty & ((~wvalid_i)))
             -------------1------------   ------2------
-1--2-StatusTests
01CoveredT1,T2,T5
10CoveredT1,T2,T5
11CoveredT1,T2,T3
Cond Coverage for Module : prim_fifo_sync ( parameter Width=40,Pass=1,Depth=1,OutputZeroIfEmpty=1,Secure=0,DepthW=1,gen_normal_fifo.PTRV_W=1,gen_normal_fifo.PTR_WIDTH=2 )
Cond Coverage for Module self-instances :
SCORECOND
62.60 41.18
tb.dut.u_tlul2sram_egress.u_rspfifo

SCORECOND
92.03 76.47
tb.dut.u_tlul2sram_ingress.u_rspfifo

TotalCoveredPercent
Conditions342676.47
Logical342676.47
Non-Logical00
Event00

 LINE       88
 EXPRESSION 
 Number  Term
      1  gen_normal_fifo.full ? (1'(Depth)) : ((gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb) ? ((1'(gen_normal_fifo.wptr_value) - 1'(gen_normal_fifo.rptr_value))) : (((1'(Depth) - 1'(gen_normal_fifo.rptr_value)) + 1'(gen_normal_fifo.wptr_value)))))
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT7,T9,T11 

 LINE       88
 SUB-EXPRESSION 
 Number  Term
      1  (gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb) ? ((1'(gen_normal_fifo.wptr_value) - 1'(gen_normal_fifo.rptr_value))) : (((1'(Depth) - 1'(gen_normal_fifo.rptr_value)) + 1'(gen_normal_fifo.wptr_value))))
-1-StatusTests
0Not Covered
1CoveredT1,T2,T3 

 LINE       88
 SUB-EXPRESSION (gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb)
                ---------------------------1--------------------------
-1-StatusTests
0Not Covered
1CoveredT1,T2,T3 

 LINE       92
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101Not Covered
110Not Covered
111CoveredT5,T7,T9 

 LINE       93
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------
-1--2--3-StatusTests
011Not Covered
101CoveredT7,T9,T11
110Not Covered
111CoveredT5,T7,T9 

 LINE       98
 EXPRESSION (((~gen_normal_fifo.full)) & ((~gen_normal_fifo.under_rst)))
             ------------1------------   ---------------2--------------
-1--2-StatusTests
01CoveredT7,T9,T11
10CoveredT1,T2,T3
11CoveredT1,T2,T3 

 LINE       100
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11CoveredT5,T7,T9 

 LINE       145
 EXPRESSION (gen_normal_fifo.fifo_wptr == (gen_normal_fifo.fifo_rptr ^ {1'b1, {(gen_normal_fifo.PTR_WIDTH - 1) {1'b0}}}))
            ------------------------------------------------------1------------------------------------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT7,T9,T11 

 LINE       146
 EXPRESSION (gen_normal_fifo.fifo_wptr == gen_normal_fifo.fifo_rptr)
            ----------------------------1---------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3 

 LINE       172
 EXPRESSION ((gen_normal_fifo.fifo_empty && wvalid_i) ? wdata_i : gen_normal_fifo.storage_rdata)
             --------------------1-------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT5,T7,T9 

 LINE       172
 SUB-EXPRESSION (gen_normal_fifo.fifo_empty && wvalid_i)
                 -------------1------------    ----2---
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11CoveredT5,T7,T9 

 LINE       173
 EXPRESSION (gen_normal_fifo.fifo_empty & ((~wvalid_i)))
             -------------1------------   ------2------
-1--2-StatusTests
01CoveredT7,T9,T11
10CoveredT5,T7,T9
11CoveredT1,T2,T3 

 LINE       180
 EXPRESSION (gen_normal_fifo.empty ? 'b0 : gen_normal_fifo.rdata_int)
             ----------1----------
-1-StatusTests
0CoveredT5,T7,T9
1CoveredT1,T2,T3
Cond Coverage for Module : prim_fifo_sync ( parameter Width=5,Pass=0,Depth=1,OutputZeroIfEmpty=1,Secure=0,DepthW=1,gen_normal_fifo.PTRV_W=1,gen_normal_fifo.PTR_WIDTH=2 )
Cond Coverage for Module self-instances :
SCORECOND
62.17 42.31
tb.dut.u_tlul2sram_egress.u_sramreqfifo

SCORECOND
89.81 69.23
tb.dut.u_tlul2sram_ingress.u_sramreqfifo

TotalCoveredPercent
Conditions261869.23
Logical261869.23
Non-Logical00
Event00

 LINE       88
 EXPRESSION 
 Number  Term
      1  gen_normal_fifo.full ? (1'(Depth)) : ((gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb) ? ((1'(gen_normal_fifo.wptr_value) - 1'(gen_normal_fifo.rptr_value))) : (((1'(Depth) - 1'(gen_normal_fifo.rptr_value)) + 1'(gen_normal_fifo.wptr_value)))))
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT5,T7,T9 

 LINE       88
 SUB-EXPRESSION 
 Number  Term
      1  (gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb) ? ((1'(gen_normal_fifo.wptr_value) - 1'(gen_normal_fifo.rptr_value))) : (((1'(Depth) - 1'(gen_normal_fifo.rptr_value)) + 1'(gen_normal_fifo.wptr_value))))
-1-StatusTests
0Not Covered
1CoveredT1,T2,T3 

 LINE       88
 SUB-EXPRESSION (gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb)
                ---------------------------1--------------------------
-1-StatusTests
0Not Covered
1CoveredT1,T2,T3 

 LINE       92
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101Not Covered
110Not Covered
111CoveredT5,T7,T9 

 LINE       93
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------
-1--2--3-StatusTests
011Not Covered
101Not Covered
110Not Covered
111CoveredT5,T7,T9 

 LINE       98
 EXPRESSION (((~gen_normal_fifo.full)) & ((~gen_normal_fifo.under_rst)))
             ------------1------------   ---------------2--------------
-1--2-StatusTests
01CoveredT5,T7,T9
10CoveredT1,T2,T3
11CoveredT1,T2,T3 

 LINE       100
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11CoveredT5,T7,T9 

 LINE       145
 EXPRESSION (gen_normal_fifo.fifo_wptr == (gen_normal_fifo.fifo_rptr ^ {1'b1, {(gen_normal_fifo.PTR_WIDTH - 1) {1'b0}}}))
            ------------------------------------------------------1------------------------------------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT5,T7,T9 

 LINE       146
 EXPRESSION (gen_normal_fifo.fifo_wptr == gen_normal_fifo.fifo_rptr)
            ----------------------------1---------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3 

 LINE       180
 EXPRESSION (gen_normal_fifo.empty ? 'b0 : gen_normal_fifo.rdata_int)
             ----------1----------
-1-StatusTests
0CoveredT5,T7,T9
1CoveredT1,T2,T3
Cond Coverage for Module : prim_fifo_sync ( parameter Width=8,Pass=1,Depth=2,OutputZeroIfEmpty=0,Secure=0,DepthW=2,gen_normal_fifo.PTRV_W=1,gen_normal_fifo.PTR_WIDTH=2 )
Cond Coverage for Module self-instances :
SCORECOND
96.88 87.50
tb.dut.u_readcmd.u_readsram.u_fifo

TotalCoveredPercent
Conditions322887.50
Logical322887.50
Non-Logical00
Event00

 LINE       88
 EXPRESSION 
 Number  Term
      1  gen_normal_fifo.full ? (2'(Depth)) : ((gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb) ? ((2'(gen_normal_fifo.wptr_value) - 2'(gen_normal_fifo.rptr_value))) : (((2'(Depth) - 2'(gen_normal_fifo.rptr_value)) + 2'(gen_normal_fifo.wptr_value)))))
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T5 

 LINE       88
 SUB-EXPRESSION 
 Number  Term
      1  (gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb) ? ((2'(gen_normal_fifo.wptr_value) - 2'(gen_normal_fifo.rptr_value))) : (((2'(Depth) - 2'(gen_normal_fifo.rptr_value)) + 2'(gen_normal_fifo.wptr_value))))
-1-StatusTests
0CoveredT1,T2,T5
1CoveredT1,T2,T3 

 LINE       88
 SUB-EXPRESSION (gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb)
                ---------------------------1--------------------------
-1-StatusTests
0CoveredT1,T2,T5
1CoveredT1,T2,T3 

 LINE       92
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------
-1--2--3-StatusTests
011CoveredT1,T2,T5
101CoveredT1,T2,T5
110Not Covered
111CoveredT1,T2,T5 

 LINE       93
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------
-1--2--3-StatusTests
011Not Covered
101CoveredT1,T2,T5
110Not Covered
111CoveredT1,T2,T5 

 LINE       98
 EXPRESSION (((~gen_normal_fifo.full)) & ((~gen_normal_fifo.under_rst)))
             ------------1------------   ---------------2--------------
-1--2-StatusTests
01CoveredT1,T2,T5
10CoveredT1,T2,T3
11CoveredT1,T2,T5 

 LINE       100
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------
-1--2-StatusTests
01CoveredT1,T2,T5
10Not Covered
11CoveredT1,T2,T5 

 LINE       145
 EXPRESSION (gen_normal_fifo.fifo_wptr == (gen_normal_fifo.fifo_rptr ^ {1'b1, {(gen_normal_fifo.PTR_WIDTH - 1) {1'b0}}}))
            ------------------------------------------------------1------------------------------------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T5 

 LINE       146
 EXPRESSION (gen_normal_fifo.fifo_wptr == gen_normal_fifo.fifo_rptr)
            ----------------------------1---------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3 

 LINE       172
 EXPRESSION ((gen_normal_fifo.fifo_empty && wvalid_i) ? wdata_i : gen_normal_fifo.storage_rdata)
             --------------------1-------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T5 

 LINE       172
 SUB-EXPRESSION (gen_normal_fifo.fifo_empty && wvalid_i)
                 -------------1------------    ----2---
-1--2-StatusTests
01CoveredT1,T2,T5
10CoveredT1,T2,T3
11CoveredT1,T2,T5 

 LINE       173
 EXPRESSION (gen_normal_fifo.fifo_empty & ((~wvalid_i)))
             -------------1------------   ------2------
-1--2-StatusTests
01CoveredT1,T2,T5
10CoveredT1,T2,T5
11CoveredT1,T2,T3
Cond Coverage for Module : prim_fifo_sync ( parameter Width=5,Pass=0,Depth=4,OutputZeroIfEmpty=1,Secure=0,DepthW=3,gen_normal_fifo.PTRV_W=2,gen_normal_fifo.PTR_WIDTH=3 )
Cond Coverage for Module self-instances :
SCORECOND
88.85 65.38
tb.dut.u_sys_sram_arbiter.u_req_fifo

TotalCoveredPercent
Conditions261765.38
Logical261765.38
Non-Logical00
Event00

 LINE       88
 EXPRESSION 
 Number  Term
      1  gen_normal_fifo.full ? (3'(Depth)) : ((gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb) ? ((3'(gen_normal_fifo.wptr_value) - 3'(gen_normal_fifo.rptr_value))) : (((3'(Depth) - 3'(gen_normal_fifo.rptr_value)) + 3'(gen_normal_fifo.wptr_value)))))
-1-StatusTests
0CoveredT1,T2,T3
1Not Covered 

 LINE       88
 SUB-EXPRESSION 
 Number  Term
      1  (gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb) ? ((3'(gen_normal_fifo.wptr_value) - 3'(gen_normal_fifo.rptr_value))) : (((3'(Depth) - 3'(gen_normal_fifo.rptr_value)) + 3'(gen_normal_fifo.wptr_value))))
-1-StatusTests
0CoveredT5,T7,T9
1CoveredT1,T2,T3 

 LINE       88
 SUB-EXPRESSION (gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb)
                ---------------------------1--------------------------
-1-StatusTests
0CoveredT5,T7,T9
1CoveredT1,T2,T3 

 LINE       92
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101Not Covered
110Not Covered
111CoveredT5,T7,T9 

 LINE       93
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------
-1--2--3-StatusTests
011Not Covered
101Not Covered
110Not Covered
111CoveredT5,T7,T9 

 LINE       98
 EXPRESSION (((~gen_normal_fifo.full)) & ((~gen_normal_fifo.under_rst)))
             ------------1------------   ---------------2--------------
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11CoveredT1,T2,T3 

 LINE       100
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11CoveredT5,T7,T9 

 LINE       145
 EXPRESSION (gen_normal_fifo.fifo_wptr == (gen_normal_fifo.fifo_rptr ^ {1'b1, {(gen_normal_fifo.PTR_WIDTH - 1) {1'b0}}}))
            ------------------------------------------------------1------------------------------------------------------
-1-StatusTests
0CoveredT1,T2,T3
1Not Covered 

 LINE       146
 EXPRESSION (gen_normal_fifo.fifo_wptr == gen_normal_fifo.fifo_rptr)
            ----------------------------1---------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3 

 LINE       180
 EXPRESSION (gen_normal_fifo.empty ? 'b0 : gen_normal_fifo.rdata_int)
             ----------1----------
-1-StatusTests
0CoveredT5,T7,T9
1CoveredT1,T2,T3
Cond Coverage for Module : prim_fifo_sync ( parameter Width=17,Pass=0,Depth=1,OutputZeroIfEmpty=1,Secure=0,DepthW=1,gen_normal_fifo.PTRV_W=1,gen_normal_fifo.PTR_WIDTH=2 )
Cond Coverage for Module self-instances :
SCORECOND
90.77 73.08
tb.dut.u_tlul2sram_egress.u_reqfifo

SCORECOND
90.77 73.08
tb.dut.u_tlul2sram_ingress.u_reqfifo

TotalCoveredPercent
Conditions261973.08
Logical261973.08
Non-Logical00
Event00

 LINE       88
 EXPRESSION 
 Number  Term
      1  gen_normal_fifo.full ? (1'(Depth)) : ((gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb) ? ((1'(gen_normal_fifo.wptr_value) - 1'(gen_normal_fifo.rptr_value))) : (((1'(Depth) - 1'(gen_normal_fifo.rptr_value)) + 1'(gen_normal_fifo.wptr_value)))))
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T5 

 LINE       88
 SUB-EXPRESSION 
 Number  Term
      1  (gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb) ? ((1'(gen_normal_fifo.wptr_value) - 1'(gen_normal_fifo.rptr_value))) : (((1'(Depth) - 1'(gen_normal_fifo.rptr_value)) + 1'(gen_normal_fifo.wptr_value))))
-1-StatusTests
0Not Covered
1CoveredT1,T2,T3 

 LINE       88
 SUB-EXPRESSION (gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb)
                ---------------------------1--------------------------
-1-StatusTests
0Not Covered
1CoveredT1,T2,T3 

 LINE       92
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101Not Covered
110Not Covered
111CoveredT1,T2,T5 

 LINE       93
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------
-1--2--3-StatusTests
011Not Covered
101CoveredT7,T9,T10
110Not Covered
111CoveredT1,T2,T5 

 LINE       98
 EXPRESSION (((~gen_normal_fifo.full)) & ((~gen_normal_fifo.under_rst)))
             ------------1------------   ---------------2--------------
-1--2-StatusTests
01CoveredT1,T2,T5
10CoveredT1,T2,T3
11CoveredT1,T2,T3 

 LINE       100
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11CoveredT1,T2,T5 

 LINE       145
 EXPRESSION (gen_normal_fifo.fifo_wptr == (gen_normal_fifo.fifo_rptr ^ {1'b1, {(gen_normal_fifo.PTR_WIDTH - 1) {1'b0}}}))
            ------------------------------------------------------1------------------------------------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T5 

 LINE       146
 EXPRESSION (gen_normal_fifo.fifo_wptr == gen_normal_fifo.fifo_rptr)
            ----------------------------1---------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3 

 LINE       180
 EXPRESSION (gen_normal_fifo.empty ? 'b0 : gen_normal_fifo.rdata_int)
             ----------1----------
-1-StatusTests
0CoveredT1,T2,T5
1CoveredT1,T2,T3
Branch Coverage for Module : prim_fifo_sync ( parameter Width=32,Pass=1,Depth=1,OutputZeroIfEmpty=0,Secure=0,DepthW=1,gen_normal_fifo.PTRV_W=1,gen_normal_fifo.PTR_WIDTH=2 + Width=8,Pass=1,Depth=2,OutputZeroIfEmpty=0,Secure=0,DepthW=2,gen_normal_fifo.PTRV_W=1,gen_normal_fifo.PTR_WIDTH=2 )
Branch Coverage for Module self-instances :
SCOREBRANCH
91.25 90.00
tb.dut.u_readcmd.u_readsram.u_sram_fifo

SCOREBRANCH
92.03 90.00
tb.dut.u_spi_tpm.u_sram_fifo

SCOREBRANCH
96.88 100.00
tb.dut.u_readcmd.u_readsram.u_fifo

Line No.TotalCoveredPercent
Branches 10 10 100.00
TERNARY 88 3 3 100.00
TERNARY 172 2 2 100.00
IF 70 3 3 100.00
IF 157 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.


	LineNo.	Expression
-1-:	88	(gen_normal_fifo.full) ? 
-2-:	88	((gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb)) ?

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T5
0 1 Covered T1,T2,T3
0 0 Covered T1,T2,T5 



	LineNo.	Expression
-1-:	172	((gen_normal_fifo.fifo_empty && wvalid_i)) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T5
0 Covered T1,T2,T3 



	LineNo.	Expression
-1-:	70	if ((!rst_ni))
-2-:	72	if (gen_normal_fifo.under_rst)

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T1,T2,T3
0 0 Covered T1,T2,T3 



	LineNo.	Expression
-1-:	157	if (gen_normal_fifo.fifo_incr_wptr)

Branches:
-1-StatusTests
1 Covered T1,T2,T5
0 Covered T1,T2,T3

Branch Coverage for Module : prim_fifo_sync ( parameter Width=3,Pass=0,Depth=4,OutputZeroIfEmpty=1,Secure=0,DepthW=3,gen_normal_fifo.PTRV_W=2,gen_normal_fifo.PTR_WIDTH=3 + Width=2,Pass=0,Depth=4,OutputZeroIfEmpty=1,Secure=0,DepthW=3,gen_normal_fifo.PTRV_W=2,gen_normal_fifo.PTR_WIDTH=3 + Width=17,Pass=0,Depth=1,OutputZeroIfEmpty=1,Secure=0,DepthW=1,gen_normal_fifo.PTRV_W=1,gen_normal_fifo.PTR_WIDTH=2 + Width=5,Pass=0,Depth=1,OutputZeroIfEmpty=1,Secure=0,DepthW=1,gen_normal_fifo.PTRV_W=1,gen_normal_fifo.PTR_WIDTH=2 + Width=5,Pass=0,Depth=4,OutputZeroIfEmpty=1,Secure=0,DepthW=3,gen_normal_fifo.PTRV_W=2,gen_normal_fifo.PTR_WIDTH=3 )
Branch Coverage for Module self-instances :
SCOREBRANCH
63.30 60.00
tb.dut.u_upload.u_arbiter.u_req_fifo

SCOREBRANCH
88.85 90.00
tb.dut.u_spi_tpm.u_arbiter.u_req_fifo

SCOREBRANCH
90.77 90.00
tb.dut.u_tlul2sram_egress.u_reqfifo

SCOREBRANCH
90.77 90.00
tb.dut.u_tlul2sram_ingress.u_reqfifo

SCOREBRANCH
62.17 60.00
tb.dut.u_tlul2sram_egress.u_sramreqfifo

SCOREBRANCH
89.81 90.00
tb.dut.u_tlul2sram_ingress.u_sramreqfifo

SCOREBRANCH
88.85 90.00
tb.dut.u_sys_sram_arbiter.u_req_fifo

Line No.TotalCoveredPercent
Branches 10 10 100.00
TERNARY 88 3 3 100.00
TERNARY 180 2 2 100.00
IF 70 3 3 100.00
IF 165 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.


	LineNo.	Expression
-1-:	88	(gen_normal_fifo.full) ? 
-2-:	88	((gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb)) ?

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T5
0 1 Covered T1,T2,T3
0 0 Covered T5,T7,T9 



	LineNo.	Expression
-1-:	180	(gen_normal_fifo.empty) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T5 



	LineNo.	Expression
-1-:	70	if ((!rst_ni))
-2-:	72	if (gen_normal_fifo.under_rst)

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T1,T2,T3
0 0 Covered T1,T2,T3 



	LineNo.	Expression
-1-:	165	if (gen_normal_fifo.fifo_incr_wptr)

Branches:
-1-StatusTests
1 Covered T1,T2,T5
0 Covered T1,T2,T3

Branch Coverage for Module : prim_fifo_sync ( parameter Width=40,Pass=1,Depth=1,OutputZeroIfEmpty=1,Secure=0,DepthW=1,gen_normal_fifo.PTRV_W=1,gen_normal_fifo.PTR_WIDTH=2 )
Branch Coverage for Module self-instances :
SCOREBRANCH
62.60 58.33
tb.dut.u_tlul2sram_egress.u_rspfifo

SCOREBRANCH
92.03 91.67
tb.dut.u_tlul2sram_ingress.u_rspfifo

Line No.TotalCoveredPercent
Branches 12 11 91.67
TERNARY 88 3 2 66.67
TERNARY 172 2 2 100.00
TERNARY 180 2 2 100.00
IF 70 3 3 100.00
IF 157 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.


	LineNo.	Expression
-1-:	88	(gen_normal_fifo.full) ? 
-2-:	88	((gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb)) ?

Branches:
-1--2-StatusTests
1 - Covered T7,T9,T11
0 1 Covered T1,T2,T3
0 0 Not Covered 



	LineNo.	Expression
-1-:	172	((gen_normal_fifo.fifo_empty && wvalid_i)) ?

Branches:
-1-StatusTests
1 Covered T5,T7,T9
0 Covered T1,T2,T3 



	LineNo.	Expression
-1-:	180	(gen_normal_fifo.empty) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T5,T7,T9 



	LineNo.	Expression
-1-:	70	if ((!rst_ni))
-2-:	72	if (gen_normal_fifo.under_rst)

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T1,T2,T3
0 0 Covered T1,T2,T3 



	LineNo.	Expression
-1-:	157	if (gen_normal_fifo.fifo_incr_wptr)

Branches:
-1-StatusTests
1 Covered T5,T7,T9
0 Covered T1,T2,T3

Assert Coverage for Module : prim_fifo_sync
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 6 6 100.00 6 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 6 6 100.00 6 100.00



Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DataKnown_A 2147483647 325852413 0 0
DepthKnown_A 2147483647 2147483647 0 0
RvalidKnown_A 2147483647 2147483647 0 0
WreadyKnown_A 2147483647 2147483647 0 0
gen_normal_fifo.depthShallNotExceedParamDepth 2147483647 144179677 0 0
gen_passthru_fifo.paramCheckPass 17616 17616 0 0


DataKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 325852413 0 0
T1 802500 30673 0 0
T2 1536685 20244 0 0
T3 41864 224 0 0
T4 10626 726 0 0
T5 9244651 688959 0 0
T6 24346 186 0 0
T7 6014298 536046 0 0
T8 5476295 21582 0 0
T9 2928055 431516 0 0
T10 635707 43601 0 0
T11 4569732 767733 0 0
T12 666264 174104 0 0
T13 1021040 6531 0 0
T14 0 8722 0 0
T15 0 2564 0 0
T16 0 1122 0 0
T23 0 448 0 0
T24 0 162 0 0
T25 0 540 0 0
T26 102954 0 0 0
T28 0 200 0 0
T34 0 1017 0 0

DepthKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 2147483647 0 0
T1 1702404 1701219 0 0
T2 3241779 3237189 0 0
T3 90655 85452 0 0
T4 22770 21420 0 0
T5 11048550 9036235 0 0
T6 28230 25680 0 0
T7 7227655 5656061 0 0
T8 6388485 6024723 0 0
T9 3501065 2797958 0 0
T10 741080 700611 0 0
T11 728370 679175 0 0
T12 255108 381390 0 0
T13 233222 346110 0 0
T14 0 747408 0 0
T15 0 124304 0 0
T16 0 30272 0 0
T24 0 9248 0 0

RvalidKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 2147483647 0 0
T1 1702404 1701219 0 0
T2 3241779 3237189 0 0
T3 90655 85452 0 0
T4 22770 21420 0 0
T5 11048550 9036235 0 0
T6 28230 25680 0 0
T7 7227655 5656061 0 0
T8 6388485 6024723 0 0
T9 3501065 2797958 0 0
T10 741080 700611 0 0
T11 728370 679175 0 0
T12 255108 381390 0 0
T13 233222 346110 0 0
T14 0 747408 0 0
T15 0 124304 0 0
T16 0 30272 0 0
T24 0 9248 0 0

WreadyKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 2147483647 0 0
T1 1702404 1701219 0 0
T2 3241779 3237189 0 0
T3 90655 85452 0 0
T4 22770 21420 0 0
T5 11048550 9036235 0 0
T6 28230 25680 0 0
T7 7227655 5656061 0 0
T8 6388485 6024723 0 0
T9 3501065 2797958 0 0
T10 741080 700611 0 0
T11 728370 679175 0 0
T12 255108 381390 0 0
T13 233222 346110 0 0
T14 0 747408 0 0
T15 0 124304 0 0
T16 0 30272 0 0
T24 0 9248 0 0

gen_normal_fifo.depthShallNotExceedParamDepth
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 144179677 0 0
T1 137628 26171 0 0
T2 287683 8123 0 0
T3 8252 0 0 0
T4 1518 0 0 0
T5 5998163 438841 0 0
T6 10250 0 0 0
T7 4156906 167310 0 0
T8 2552239 17140 0 0
T9 1910431 71726 0 0
T10 292963 38821 0 0
T11 3240720 766012 0 0
T12 529212 173272 0 0
T13 758434 4868 0 0
T14 0 74476 0 0
T15 0 16986 0 0
T16 0 5240 0 0
T23 0 908 0 0
T24 0 1652 0 0
T25 0 1088 0 0
T26 71484 0 0 0
T28 0 6371 0 0
T34 0 32757 0 0

gen_passthru_fifo.paramCheckPass
NameAttemptsReal SuccessesFailuresIncomplete
Total 17616 17616 0 0
T1 8 8 0 0
T2 8 8 0 0
T3 8 8 0 0
T4 8 8 0 0
T5 8 8 0 0
T6 8 8 0 0
T7 8 8 0 0
T8 8 8 0 0
T9 8 8 0 0
T10 8 8 0 0

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%