Module Definition
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Module : spi_passthrough
SCORELINECONDTOGGLEFSMBRANCHASSERT
89.32 92.31 88.66 75.00 90.62 100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_spi_device_0.1/rtl/spi_passthrough.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.u_passthrough 89.32 92.31 88.66 75.00 90.62 100.00



Module Instance : tb.dut.u_passthrough

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
89.32 92.31 88.66 75.00 90.62 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
89.66 92.75 89.22 75.00 91.35 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
91.69 94.25 84.31 96.94 87.50 95.45 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_pt_sck_cg 100.00 100.00 100.00 100.00
u_read_half_cycle 100.00 100.00 100.00
u_read_pipe_stg1 100.00 100.00 100.00
u_read_pipe_stg2 100.00 100.00 100.00


Since this is the module's only instance, the coverage report is the same as for the module.
Line Coverage for Module : spi_passthrough
Line No.TotalCoveredPercent
TOTAL19518092.31
CONT_ASSIGN27011100.00
CONT_ASSIGN27511100.00
CONT_ASSIGN32511100.00
CONT_ASSIGN33211100.00
ALWAYS33544100.00
ALWAYS34444100.00
ALWAYS34833100.00
CONT_ASSIGN35411100.00
ALWAYS35944100.00
CONT_ASSIGN37111100.00
CONT_ASSIGN37211100.00
ALWAYS37544100.00
ALWAYS39988100.00
ALWAYS41344100.00
ALWAYS42444100.00
CONT_ASSIGN43800
ALWAYS44844100.00
CONT_ASSIGN46211100.00
ALWAYS46533100.00
CONT_ASSIGN47411100.00
ALWAYS47733100.00
ALWAYS48566100.00
CONT_ASSIGN49611100.00
ALWAYS50533100.00
ALWAYS51944100.00
ALWAYS52733100.00
ALWAYS53266100.00
ALWAYS53833100.00
CONT_ASSIGN54211100.00
CONT_ASSIGN54511100.00
ALWAYS56055100.00
CONT_ASSIGN56911100.00
CONT_ASSIGN57111100.00
CONT_ASSIGN57411100.00
CONT_ASSIGN57511100.00
ALWAYS58166100.00
CONT_ASSIGN58811100.00
ALWAYS5956466.67
CONT_ASSIGN60311100.00
CONT_ASSIGN60811100.00
ALWAYS61233100.00
CONT_ASSIGN61511100.00
ALWAYS6618450.00
ALWAYS68233100.00
CONT_ASSIGN69711100.00
CONT_ASSIGN70311100.00
CONT_ASSIGN70611100.00
ALWAYS71433100.00
ALWAYS722685986.76
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_spi_device_0.1/rtl/spi_passthrough.sv' or '../src/lowrisc_ip_spi_device_0.1/rtl/spi_passthrough.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
270 1 1
275 1 1
325 1 1
332 1 1
335 1 1
336 1 1
337 1 1
338 1 1
MISSING_ELSE
344 2 2
345 2 2
MISSING_ELSE
348 2 2
349 1 1
354 1 1
359 1 1
360 1 1
361 1 1
362 1 1
MISSING_ELSE
371 1 1
372 1 1
375 1 1
376 1 1
377 1 1
385 1 1
MISSING_ELSE
399 1 1
400 1 1
401 1 1
402 1 1
403 1 1
404 1 1
405 1 1
406 1 1
MISSING_ELSE
MISSING_ELSE
MISSING_ELSE
413 1 1
414 1 1
415 1 1
418 1 1
MISSING_ELSE
424 1 1
425 1 1
426 1 1
429 1 1
MISSING_ELSE
438 unreachable
448 1 1
450 1 1
453 1 1
455 1 1
MISSING_ELSE
462 1 1
465 1 1
466 1 1
467 1 1
MISSING_ELSE
474 1 1
477 1 1
478 1 1
480 1 1
485 1 1
486 1 1
487 1 1
488 1 1
489 1 1
490 1 1
MISSING_ELSE
496 1 1
505 2 2
506 1 1
519 1 1
520 1 1
521 1 1
522 1 1
MISSING_ELSE
527 2 2
528 1 1
532 2 2
533 2 2
534 2 2
MISSING_ELSE
538 2 2
539 1 1
542 1 1
545 1 1
560 1 1
561 1 1
562 1 1
564 1 1
565 1 1
569 1 1
571 1 1
574 1 1
575 1 1
581 2 2
582 1 1
583 1 1
584 1 1
585 1 1
MISSING_ELSE
588 1 1
595 1 1
596 1 1
597 1 1
598 0 1
599 1 1
600 0 1
MISSING_ELSE
603 1 1
608 1 1
612 2 2
613 1 1
615 1 1
661 1 1
662 1 1
663 1 1
665 1 1
667 0 1
668 0 1
671 0 1
672 0 1
682 2 2
683 1 1
697 1 1
703 1 1
706 1 1
714 1 1
715 1 1
717 1 1
722 1 1
725 1 1
728 1 1
731 1 1
734 1 1
737 1 1
740 1 1
741 1 1
744 1 1
745 1 1
747 1 1
749 1 1
750 1 1
751 1 1
752 1 1
753 1 1
756 1 1
757 1 1
767 1 1
768 1 1
770 1 1
771 1 1
772 1 1
774 1 1
775 1 1
776 1 1
778 1 1
779 1 1
781 1 1
783 1 1
MISSING_ELSE
787 1 1
789 1 1
790 1 1
MISSING_ELSE
795 0 1
796 0 1
798 0 1
799 0 1
801 0 1
807 1 1
808 1 1
809 1 1
814 1 1
817 1 1
818 1 1
823 1 1
826 1 1
827 1 1
831 1 1
832 1 1
833 1 1
835 1 1
836 1 1
837 0 1
839 0 1
MISSING_ELSE
845 1 1
846 1 1
847 0 1
849 0 1
850 1 1
851 1 1
853 1 1
854 1 1
855 1 1
857 1 1
858 1 1
860 1 1
862 1 1
865 1 1
MISSING_ELSE


Cond Coverage for Module : spi_passthrough
TotalCoveredPercent
Conditions978688.66
Logical978688.66
Non-Logical00
Event00

 LINE       270
 EXPRESSION (spi_mode_i == PassThrough)
            -------------1-------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT5,T8,T11

 LINE       354
 SUB-EXPRESSION (filter | csb_deassert)
                 ---1--   ------2-----
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT5,T8,T11
10CoveredT5,T8,T11

 LINE       361
 EXPRESSION (bitcnt != '1)
            -------1------
-1-StatusTests
0CoveredT1,T2,T5
1CoveredT1,T2,T5

 LINE       371
 EXPRESSION (bitcnt == 6'(6))
            --------1--------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T5

 LINE       372
 EXPRESSION (bitcnt == 6'(7))
            --------1--------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T5

 LINE       403
 EXPRESSION (cmd_info_i[i].opcode == {opcode_d[6:0], 1'b1})
            -----------------------1-----------------------
-1-StatusTests
0CoveredT1,T2,T5
1CoveredT1,T2,T5

 LINE       405
 EXPRESSION (cmd_info_i[i].opcode == {opcode_d[6:0], 1'b0})
            -----------------------1-----------------------
-1-StatusTests
0CoveredT1,T2,T5
1CoveredT2,T5,T7

 LINE       466
 EXPRESSION (addr_mode == Addr4B)
            ----------1----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT5,T8,T11

 LINE       474
 EXPRESSION (st == StAddress)
            --------1--------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT5,T8,T11

 LINE       489
 EXPRESSION (addrcnt_outclk != '0)
            -----------1----------
-1-StatusTests
0CoveredT1,T2,T5
1CoveredT5,T8,T11

 LINE       496
 EXPRESSION (cfg_addr_mask_i[addrcnt_outclk] ? cfg_addr_value_i[addrcnt_outclk] : host_s_i[0])
             ---------------1---------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T5,T7

 LINE       521
 EXPRESSION ((payloadcnt != '0) && payload_replace)
             ---------1--------    -------2-------
-1--2-StatusTests
01CoveredT5,T8,T11
10CoveredT1,T2,T5
11CoveredT5,T8,T11

 LINE       521
 SUB-EXPRESSION (payloadcnt != '0)
                ---------1--------
-1-StatusTests
0CoveredT5,T8,T11
1CoveredT1,T2,T5

 LINE       542
 EXPRESSION (payloadcnt == '0)
            ---------1--------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT5,T8,T11

 LINE       545
 EXPRESSION (cfg_payload_mask_i[payloadcnt_outclk] ? cfg_payload_data_i[payloadcnt_outclk] : host_s_i[0])
             ------------------1------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T5

 LINE       569
 EXPRESSION (addr_phase_outclk & cmd_info_addr_swap_en_outclk)
             --------1--------   --------------2-------------
-1--2-StatusTests
01CoveredT5,T11,T13
10CoveredT5,T8,T11
11CoveredT5,T11,T13

 LINE       571
 EXPRESSION (payload_replace_outclk & cmd_info_payload_swap_en_outclk)
             -----------1----------   ---------------2---------------
-1--2-StatusTests
01CoveredT5,T11,T14
10CoveredT5,T8,T11
11CoveredT5,T11,T14

 LINE       574
 EXPRESSION (addr_swap_en | payload_swap_en)
             ------1-----   -------2-------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT5,T11,T14
10CoveredT5,T11,T13

 LINE       575
 EXPRESSION (addr_swap_en ? addr_swap : payload_swap)
             ------1-----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT5,T11,T13

 LINE       584
 EXPRESSION (st == StHighZ)
            -------1-------
-1-StatusTests
0CoveredT1,T2,T5
1CoveredT5,T8,T11

 LINE       588
 EXPRESSION (dummycnt == '0)
            --------1-------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       599
 EXPRESSION (st == StMByte)
            -------1-------
-1-StatusTests
0CoveredT1,T2,T5
1Not Covered

 LINE       603
 EXPRESSION (mbyte_cnt == '0)
            --------1--------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       608
 EXPRESSION (swap_en ? ({host_s_i[3:1], swap_data}) : host_s_i)
             ---1---
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT5,T11,T13

 LINE       703
 EXPRESSION (host_csb_i | csb_deassert_outclk)
             -----1----   ---------2---------
-1--2-StatusTests
00CoveredT1,T2,T4
01CoveredT5,T8,T11
10CoveredT1,T2,T3

 LINE       706
 EXPRESSION (is_active && ((!passthrough_block_i)))
             ----1----    ------------2-----------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT5,T11,T14
11CoveredT5,T8,T11

 LINE       751
 EXPRESSION (cmd_8th && cmd_filter[host_s_i[0]])
             ---1---    -----------2-----------
-1--2-StatusTests
01Not Covered
10CoveredT5,T8,T11
11CoveredT5,T8,T11

 LINE       756
 EXPRESSION (cmd_8th && cmd_info_d.valid)
             ---1---    --------2-------
-1--2-StatusTests
01Not Covered
10CoveredT5,T8,T11
11CoveredT5,T8,T11

 LINE       767
 EXPRESSION (cmd_info_d.addr_mode != AddrDisabled)
            -------------------1------------------
-1-StatusTests
0CoveredT5,T8,T11
1CoveredT5,T8,T11

 LINE       776
 EXPRESSION (cmd_info_d.payload_en != 4'b0)
            ---------------1---------------
-1-StatusTests
0CoveredT5,T8,T11
1CoveredT5,T8,T11

 LINE       778
 EXPRESSION (cmd_info_d.payload_dir == PayloadOut)
            -------------------1------------------
-1-StatusTests
0CoveredT5,T11,T14
1CoveredT5,T8,T11

 LINE       833
 EXPRESSION (dummycnt_zero && (cmd_info.payload_dir == PayloadOut))
             ------1------    ------------------2-----------------
-1--2-StatusTests
01CoveredT5,T8,T11
10Not Covered
11CoveredT5,T8,T11

 LINE       833
 SUB-EXPRESSION (cmd_info.payload_dir == PayloadOut)
                ------------------1-----------------
-1-StatusTests
0Not Covered
1CoveredT5,T8,T11

 LINE       836
 EXPRESSION (dummycnt_zero && (cmd_info.payload_dir == PayloadIn))
             ------1------    -----------------2-----------------
-1--2-StatusTests
01Not Covered
10Not Covered
11Not Covered

 LINE       836
 SUB-EXPRESSION (cmd_info.payload_dir == PayloadIn)
                -----------------1-----------------
-1-StatusTests
0CoveredT5,T8,T11
1Not Covered

 LINE       845
 EXPRESSION (addrcnt_outclk == '0)
            -----------1----------
-1-StatusTests
0CoveredT5,T8,T11
1CoveredT5,T8,T11

 LINE       855
 EXPRESSION ((cmd_info.payload_en != 4'b0) && (cmd_info.payload_dir == PayloadOut))
             --------------1--------------    ------------------2-----------------
-1--2-StatusTests
01CoveredT5,T11,T14
10CoveredT5,T8,T11
11CoveredT5,T8,T11

 LINE       855
 SUB-EXPRESSION (cmd_info.payload_en != 4'b0)
                --------------1--------------
-1-StatusTests
0CoveredT5,T11,T14
1CoveredT5,T8,T11

 LINE       855
 SUB-EXPRESSION (cmd_info.payload_dir == PayloadOut)
                ------------------1-----------------
-1-StatusTests
0CoveredT5,T8,T11
1CoveredT5,T8,T11

 LINE       858
 EXPRESSION ((cmd_info.payload_en != 4'b0) && (cmd_info.payload_dir == PayloadIn))
             --------------1--------------    -----------------2-----------------
-1--2-StatusTests
01Not Covered
10Not Covered
11CoveredT5,T8,T11

 LINE       858
 SUB-EXPRESSION (cmd_info.payload_en != 4'b0)
                --------------1--------------
-1-StatusTests
0CoveredT5,T11,T14
1CoveredT5,T8,T11

 LINE       858
 SUB-EXPRESSION (cmd_info.payload_dir == PayloadIn)
                -----------------1-----------------
-1-StatusTests
0CoveredT5,T11,T14
1CoveredT5,T8,T11

FSM Coverage for Module : spi_passthrough
Summary for FSM :: st
TotalCoveredPercent
States 7 6 85.71 (Not included in score)
Transitions 12 9 75.00
Sequences 0 0

State, Transition and Sequence Details for FSM :: st
statesLine No.CoveredTests
StAddress 768 Covered T5,T8,T11
StDriving 781 Covered T5,T8,T11
StFilter 752 Covered T5,T8,T11
StHighZ 772 Covered T5,T8,T11
StIdle 750 Covered T1,T2,T3
StMByte 801 Not Covered
StWait 779 Covered T5,T8,T11


transitionsLine No.CoveredTests
StAddress->StDriving 860 Covered T5,T8,T11
StAddress->StHighZ 851 Covered T5,T8,T11
StAddress->StMByte 847 Not Covered
StAddress->StWait 857 Covered T5,T8,T11
StHighZ->StDriving 837 Not Covered
StHighZ->StWait 835 Covered T5,T8,T11
StIdle->StAddress 768 Covered T5,T8,T11
StIdle->StDriving 781 Covered T5,T11,T14
StIdle->StFilter 752 Covered T5,T8,T11
StIdle->StHighZ 772 Covered T5,T8,T11
StIdle->StWait 779 Covered T5,T8,T11
StMByte->StHighZ 796 Not Covered



Branch Coverage for Module : spi_passthrough
Line No.TotalCoveredPercent
Branches 96 87 90.62
TERNARY 496 2 2 100.00
TERNARY 545 2 2 100.00
TERNARY 575 2 2 100.00
TERNARY 608 2 2 100.00
IF 335 3 3 100.00
IF 344 3 3 100.00
IF 348 2 2 100.00
IF 359 3 3 100.00
IF 375 3 3 100.00
IF 400 2 2 100.00
IF 413 3 3 100.00
IF 424 3 3 100.00
IF 450 2 2 100.00
IF 466 2 2 100.00
IF 477 2 2 100.00
IF 485 4 4 100.00
IF 505 2 2 100.00
IF 519 3 3 100.00
IF 527 2 2 100.00
IF 532 4 4 100.00
IF 538 2 2 100.00
IF 560 2 2 100.00
IF 581 4 4 100.00
IF 595 4 2 50.00
IF 612 2 2 100.00
CASE 665 3 1 33.33
IF 682 2 2 100.00
IF 714 2 2 100.00
CASE 747 24 19 79.17

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_spi_device_0.1/rtl/spi_passthrough.sv' or '../src/lowrisc_ip_spi_device_0.1/rtl/spi_passthrough.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 496 (cfg_addr_mask_i[addrcnt_outclk]) ?

Branches:
-1-StatusTests
1 Covered T1,T5,T7
0 Covered T1,T2,T3


LineNo. Expression -1-: 545 (cfg_payload_mask_i[payloadcnt_outclk]) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T5
0 Covered T1,T2,T3


LineNo. Expression -1-: 575 (addr_swap_en) ?

Branches:
-1-StatusTests
1 Covered T5,T11,T13
0 Covered T1,T2,T3


LineNo. Expression -1-: 608 (swap_en) ?

Branches:
-1-StatusTests
1 Covered T5,T11,T13
0 Covered T1,T2,T3


LineNo. Expression -1-: 335 if ((!rst_ni)) -2-: 337 if ((bitcnt < 6'(8)))

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T1,T2,T5
0 0 Covered T1,T2,T5


LineNo. Expression -1-: 344 if ((!rst_ni)) -2-: 345 if (filter)

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T5,T8,T11
0 0 Covered T1,T2,T5


LineNo. Expression -1-: 348 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T5


LineNo. Expression -1-: 359 if ((!rst_ni)) -2-: 361 if ((bitcnt != '1))

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T1,T2,T5
0 0 Covered T1,T2,T5


LineNo. Expression -1-: 375 if ((!rst_ni)) -2-: 377 if (cmd_7th)

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T1,T2,T5
0 0 Covered T1,T2,T5


LineNo. Expression -1-: 400 if (cmd_7th)

Branches:
-1-StatusTests
1 Covered T1,T2,T5
0 Covered T1,T2,T3


LineNo. Expression -1-: 413 if ((!rst_ni)) -2-: 415 if (cmd_7th)

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T1,T2,T5
0 0 Covered T1,T2,T5


LineNo. Expression -1-: 424 if ((!rst_ni)) -2-: 426 if (cmd_info_latch)

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T5,T8,T11
0 0 Covered T1,T2,T5


LineNo. Expression -1-: 450 if (cmd_8th)

Branches:
-1-StatusTests
1 Covered T1,T2,T5
0 Covered T1,T2,T3


LineNo. Expression -1-: 466 if ((addr_mode == Addr4B))

Branches:
-1-StatusTests
1 Covered T5,T8,T11
0 Covered T1,T2,T3


LineNo. Expression -1-: 477 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T5


LineNo. Expression -1-: 485 if ((!rst_ni)) -2-: 487 if (addr_set_q) -3-: 489 if ((addrcnt_outclk != '0))

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T2,T3
0 1 - Covered T5,T8,T11
0 0 1 Covered T5,T8,T11
0 0 0 Covered T1,T2,T5


LineNo. Expression -1-: 505 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T5


LineNo. Expression -1-: 519 if ((!rst_ni)) -2-: 521 if (((payloadcnt != '0) && payload_replace))

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T5,T8,T11
0 0 Covered T1,T2,T5


LineNo. Expression -1-: 527 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T5


LineNo. Expression -1-: 532 if ((!rst_ni)) -2-: 533 if (payload_replace_set) -3-: 534 if (payload_replace_clr)

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T2,T3
0 1 - Covered T5,T8,T11
0 0 1 Covered T5,T8,T11
0 0 0 Covered T1,T2,T5


LineNo. Expression -1-: 538 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T5


LineNo. Expression -1-: 560 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T5


LineNo. Expression -1-: 581 if ((!rst_ni)) -2-: 582 if (dummy_set) -3-: 584 if ((st == StHighZ))

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T2,T3
0 1 - Covered T5,T8,T11
0 0 1 Covered T5,T8,T11
0 0 0 Covered T1,T2,T5


LineNo. Expression -1-: 595 if ((!rst_ni)) -2-: 597 if (mbyte_set) -3-: 599 if ((st == StMByte))

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T2,T3
0 1 - Not Covered
0 0 1 Not Covered
0 0 0 Covered T1,T2,T5


LineNo. Expression -1-: 612 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T5


LineNo. Expression -1-: 665 case (cmd_info.read_pipeline_mode)

Branches:
-1-StatusTests
RdPipeTwoStageFullCycle Not Covered
RdPipeTwoStageHalfCycle Not Covered
default Covered T1,T2,T3


LineNo. Expression -1-: 682 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T5


LineNo. Expression -1-: 714 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T5


LineNo. Expression -1-: 747 case (st) -2-: 749 if ((!is_active)) -3-: 751 if ((cmd_8th && cmd_filter[host_s_i[0]])) -4-: 756 if ((cmd_8th && cmd_info_d.valid)) -5-: 767 if ((cmd_info_d.addr_mode != AddrDisabled)) -6-: 771 if (cmd_info_d.dummy_en) -7-: 776 if ((cmd_info_d.payload_en != 4'b0)) -8-: 778 if ((cmd_info_d.payload_dir == PayloadOut)) -9-: 787 if (cmd_8th) -10-: 795 if (mbytecnt_zero) -11-: 833 if ((dummycnt_zero && (cmd_info.payload_dir == PayloadOut))) -12-: 836 if ((dummycnt_zero && (cmd_info.payload_dir == PayloadIn))) -13-: 845 if ((addrcnt_outclk == '0)) -14-: 846 if (cmd_info.mbyte_en) -15-: 850 if (cmd_info.dummy_en) -16-: 855 if (((cmd_info.payload_en != 4'b0) && (cmd_info.payload_dir == PayloadOut))) -17-: 858 if (((cmd_info.payload_en != 4'b0) && (cmd_info.payload_dir == PayloadIn)))

Branches:
-1--2--3--4--5--6--7--8--9--10--11--12--13--14--15--16--17-StatusTests
StIdle 1 - - - - - - - - - - - - - - - Covered T1,T2,T3
StIdle 0 1 - - - - - - - - - - - - - - Covered T5,T8,T11
StIdle 0 0 1 1 - - - - - - - - - - - - Covered T5,T8,T11
StIdle 0 0 1 0 1 - - - - - - - - - - - Covered T5,T8,T11
StIdle 0 0 1 0 0 1 1 - - - - - - - - - Covered T5,T8,T11
StIdle 0 0 1 0 0 1 0 - - - - - - - - - Covered T5,T11,T14
StIdle 0 0 1 0 0 0 - - - - - - - - - - Covered T5,T8,T11
StIdle 0 0 0 - - - - 1 - - - - - - - - Covered T5,T8,T11
StIdle 0 0 0 - - - - 0 - - - - - - - - Covered T5,T8,T11
StMByte - - - - - - - - 1 - - - - - - - Not Covered
StMByte - - - - - - - - 0 - - - - - - - Not Covered
StFilter - - - - - - - - - - - - - - - - Covered T5,T8,T11
StWait - - - - - - - - - - - - - - - - Covered T5,T8,T11
StDriving - - - - - - - - - - - - - - - - Covered T5,T8,T11
StHighZ - - - - - - - - - 1 - - - - - - Covered T5,T8,T11
StHighZ - - - - - - - - - 0 1 - - - - - Not Covered
StHighZ - - - - - - - - - 0 0 - - - - - Covered T5,T8,T11
StAddress - - - - - - - - - - - 1 1 - - - Not Covered
StAddress - - - - - - - - - - - 1 0 1 - - Covered T5,T8,T11
StAddress - - - - - - - - - - - 1 0 0 1 - Covered T5,T8,T11
StAddress - - - - - - - - - - - 1 0 0 0 1 Covered T5,T8,T11
StAddress - - - - - - - - - - - 1 0 0 0 0 Covered T5,T11,T14
StAddress - - - - - - - - - - - 0 - - - - Covered T5,T8,T11
default - - - - - - - - - - - - - - - - Not Covered


Assert Coverage for Module : spi_passthrough
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
PassThroughStKnown_A 381988954 293578611 0 0
PayloadSwapConstraint_M 381988954 3929000 0 0


PassThroughStKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 381988954 293578611 0 0
T1 13408 13408 0 0
T2 39758 38698 0 0
T3 1325 0 0 0
T5 992277 973085 0 0
T6 360 0 0 0
T7 749009 687436 0 0
T8 181176 181176 0 0
T9 318604 262433 0 0
T10 19687 19687 0 0
T11 145674 130733 0 0
T12 0 127130 0 0
T13 0 115370 0 0

PayloadSwapConstraint_M
NameAttemptsReal SuccessesFailuresIncomplete
Total 381988954 3929000 0 0
T5 992277 4160 0 0
T6 360 0 0 0
T7 749009 0 0 0
T8 181176 0 0 0
T9 318604 0 0 0
T10 19687 0 0 0
T11 145674 77048 0 0
T12 127554 0 0 0
T13 116611 0 0 0
T14 0 376 0 0
T23 0 5184 0 0
T26 4272 0 0 0
T27 0 7936 0 0
T28 0 14384 0 0
T29 0 38424 0 0
T30 0 48 0 0
T31 0 19128 0 0
T32 0 4096 0 0

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%