Unified Coverage Report :: Module :: prim_arbiter_ppc

Module : prim_arbiter_ppc

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.61	100.00	85.19			100.00	81.25

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb	85.69	100.00	77.78			90.00	75.00
tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb	90.97	100.00	88.89			100.00	75.00
tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb	92.53	100.00	88.89			100.00	81.25

---

Module Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.69	100.00	77.78			90.00	75.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.69	100.00	77.78			90.00	75.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
91.67	100.00	83.33					u_arbiter

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.97	100.00	88.89			100.00	75.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.97	100.00	88.89			100.00	75.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
66.67	100.00	33.33					u_arbiter

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.53	100.00	88.89			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.53	100.00	88.89			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
83.33	100.00	66.67					u_sys_sram_arbiter

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_arbiter_ppc ( parameter N=3,DW=75,EnDataPort=1,IdxW=2 + N=5,DW=75,EnDataPort=1,IdxW=3 )
Line Coverage for Module self-instances :

SCORE	LINE
90.97	100.00

tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

SCORE	LINE
92.53	100.00

tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Line Coverage for Module : prim_arbiter_ppc ( parameter N=2,DW=75,EnDataPort=1,IdxW=1 )
Line Coverage for Module self-instances :

SCORE	LINE
85.69	100.00

tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=2,DW=75,EnDataPort=1,IdxW=1 )
Cond Coverage for Module self-instances :

SCORE	COND
85.69	77.78

tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	7	77.78
Logical	9	7	77.78
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T5,T7,T9
1	0	Covered	T5,T7,T9

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T3,T5,T6
1	0	Unreachable
1	1	Covered	T5,T7,T9

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=3,DW=75,EnDataPort=1,IdxW=2 )
Cond Coverage for Module self-instances :

SCORE	COND
90.97	88.89

tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T5,T7,T9

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T5,T7,T9
1	0	Covered	T5,T7,T9

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T5
1	0	Unreachable
1	1	Covered	T5,T7,T9

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=5,DW=75,EnDataPort=1,IdxW=3 )
Cond Coverage for Module self-instances :

SCORE	COND
92.53	88.89

tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T5,T7,T9

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T5,T7,T9
1	0	Covered	T1,T2,T5

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Covered	T1,T2,T5

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Module : prim_arbiter_ppc

	Line No.	Total	Covered	Percent
Branches		10	10	100.00
TERNARY	76	2	2	100.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T5,T7,T9
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T5
0	0	1	Unreachable
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T5
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T5
0	Covered	T1,T2,T3

---

Assert Coverage for Module : prim_arbiter_ppc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	1967763618	1581993542	0	0
CheckNGreaterZero_A	5556	5556	0	0
GntImpliesReady_A	1967763618	8595207	0	0
GntImpliesValid_A	1967763618	8595207	0	0
GrantKnown_A	1967763618	1581993542	0	0
IdxKnown_A	1967763618	1581993542	0	0
IndexIsCorrect_A	1967763618	8595207	0	0
LockArbDecision_A	1967763618	0	0	0
NoReadyValidNoGrant_A	1967763618	0	0	0
ReadyAndValidImplyGrant_A	1967763618	8595207	0	0
ReqAndReadyImplyGrant_A	1967763618	8595207	0	0
ReqImpliesValid_A	1967763618	8595207	0	0
ReqStaysHighUntilGranted0_M	1967763618	0	0	0
RoundRobin_A	1967763618	11	0	1852
ValidKnown_A	1967763618	1581993542	0	0
gen_data_port_assertion.DataFlow_A	1967763618	8595207	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1967763618	1581993542	0	0
T1	124220	124141	0	0
T2	247925	246771	0	0
T3	8252	6820	0	0
T4	1518	1428	0	0
T5	2390365	1393849	0	0
T6	2482	2024	0	0
T7	1730192	975227	0	0
T8	727859	546589	0	0
T9	764411	440982	0	0
T10	82217	62457	0	0
T11	291348	274221	0	0
T12	127554	127130	0	0
T13	116611	115370	0	0
T14	0	373704	0	0
T15	0	62152	0	0
T16	0	15136	0	0
T24	0	4624	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5556	5556	0	0
T1	3	3	0	0
T2	3	3	0	0
T3	3	3	0	0
T4	3	3	0	0
T5	3	3	0	0
T6	3	3	0	0
T7	3	3	0	0
T8	3	3	0	0
T9	3	3	0	0
T10	3	3	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1967763618	8595207	0	0
T1	110812	832	0	0
T2	208167	832	0	0
T3	5602	0	0	0
T4	1518	0	0	0
T5	2390365	22825	0	0
T6	2482	0	0	0
T7	1730192	22774	0	0
T8	727859	832	0	0
T9	764411	8786	0	0
T10	82217	832	0	0
T11	291348	28992	0	0
T12	255108	832	0	0
T13	233222	832	0	0
T14	0	12101	0	0
T15	0	9485	0	0
T16	0	2885	0	0
T23	0	908	0	0
T24	0	287	0	0
T25	0	765	0	0
T26	8544	0	0	0
T27	0	4487	0	0
T28	0	999	0	0
T34	0	4714	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1967763618	8595207	0	0
T1	110812	832	0	0
T2	208167	832	0	0
T3	5602	0	0	0
T4	1518	0	0	0
T5	2390365	22825	0	0
T6	2482	0	0	0
T7	1730192	22774	0	0
T8	727859	832	0	0
T9	764411	8786	0	0
T10	82217	832	0	0
T11	291348	28992	0	0
T12	255108	832	0	0
T13	233222	832	0	0
T14	0	12101	0	0
T15	0	9485	0	0
T16	0	2885	0	0
T23	0	908	0	0
T24	0	287	0	0
T25	0	765	0	0
T26	8544	0	0	0
T27	0	4487	0	0
T28	0	999	0	0
T34	0	4714	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1967763618	1581993542	0	0
T1	124220	124141	0	0
T2	247925	246771	0	0
T3	8252	6820	0	0
T4	1518	1428	0	0
T5	2390365	1393849	0	0
T6	2482	2024	0	0
T7	1730192	975227	0	0
T8	727859	546589	0	0
T9	764411	440982	0	0
T10	82217	62457	0	0
T11	291348	274221	0	0
T12	127554	127130	0	0
T13	116611	115370	0	0
T14	0	373704	0	0
T15	0	62152	0	0
T16	0	15136	0	0
T24	0	4624	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1967763618	1581993542	0	0
T1	124220	124141	0	0
T2	247925	246771	0	0
T3	8252	6820	0	0
T4	1518	1428	0	0
T5	2390365	1393849	0	0
T6	2482	2024	0	0
T7	1730192	975227	0	0
T8	727859	546589	0	0
T9	764411	440982	0	0
T10	82217	62457	0	0
T11	291348	274221	0	0
T12	127554	127130	0	0
T13	116611	115370	0	0
T14	0	373704	0	0
T15	0	62152	0	0
T16	0	15136	0	0
T24	0	4624	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1967763618	8595207	0	0
T1	110812	832	0	0
T2	208167	832	0	0
T3	5602	0	0	0
T4	1518	0	0	0
T5	2390365	22825	0	0
T6	2482	0	0	0
T7	1730192	22774	0	0
T8	727859	832	0	0
T9	764411	8786	0	0
T10	82217	832	0	0
T11	291348	28992	0	0
T12	255108	832	0	0
T13	233222	832	0	0
T14	0	12101	0	0
T15	0	9485	0	0
T16	0	2885	0	0
T23	0	908	0	0
T24	0	287	0	0
T25	0	765	0	0
T26	8544	0	0	0
T27	0	4487	0	0
T28	0	999	0	0
T34	0	4714	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1967763618	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1967763618	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1967763618	8595207	0	0
T1	110812	832	0	0
T2	208167	832	0	0
T3	5602	0	0	0
T4	1518	0	0	0
T5	2390365	22825	0	0
T6	2482	0	0	0
T7	1730192	22774	0	0
T8	727859	832	0	0
T9	764411	8786	0	0
T10	82217	832	0	0
T11	291348	28992	0	0
T12	255108	832	0	0
T13	233222	832	0	0
T14	0	12101	0	0
T15	0	9485	0	0
T16	0	2885	0	0
T23	0	908	0	0
T24	0	287	0	0
T25	0	765	0	0
T26	8544	0	0	0
T27	0	4487	0	0
T28	0	999	0	0
T34	0	4714	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1967763618	8595207	0	0
T1	110812	832	0	0
T2	208167	832	0	0
T3	5602	0	0	0
T4	1518	0	0	0
T5	2390365	22825	0	0
T6	2482	0	0	0
T7	1730192	22774	0	0
T8	727859	832	0	0
T9	764411	8786	0	0
T10	82217	832	0	0
T11	291348	28992	0	0
T12	255108	832	0	0
T13	233222	832	0	0
T14	0	12101	0	0
T15	0	9485	0	0
T16	0	2885	0	0
T23	0	908	0	0
T24	0	287	0	0
T25	0	765	0	0
T26	8544	0	0	0
T27	0	4487	0	0
T28	0	999	0	0
T34	0	4714	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1967763618	8595207	0	0
T1	110812	832	0	0
T2	208167	832	0	0
T3	5602	0	0	0
T4	1518	0	0	0
T5	2390365	22825	0	0
T6	2482	0	0	0
T7	1730192	22774	0	0
T8	727859	832	0	0
T9	764411	8786	0	0
T10	82217	832	0	0
T11	291348	28992	0	0
T12	255108	832	0	0
T13	233222	832	0	0
T14	0	12101	0	0
T15	0	9485	0	0
T16	0	2885	0	0
T23	0	908	0	0
T24	0	287	0	0
T25	0	765	0	0
T26	8544	0	0	0
T27	0	4487	0	0
T28	0	999	0	0
T34	0	4714	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	1967763618	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1967763618	11	0	1852
T14	575266	1	0	1
T15	814316	0	0	1
T16	773392	0	0	1
T23	167274	0	0	1
T24	6412	0	0	1
T25	126177	0	0	1
T35	0	1	0	0
T36	0	1	0	0
T37	0	1	0	0
T38	0	1	0	0
T39	0	1	0	0
T40	0	1	0	0
T41	0	1	0	0
T42	0	1	0	0
T43	0	1	0	0
T44	3977	0	0	1
T45	3010	0	0	1
T46	512359	0	0	1
T47	56178	0	0	1

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1967763618	1581993542	0	0
T1	124220	124141	0	0
T2	247925	246771	0	0
T3	8252	6820	0	0
T4	1518	1428	0	0
T5	2390365	1393849	0	0
T6	2482	2024	0	0
T7	1730192	975227	0	0
T8	727859	546589	0	0
T9	764411	440982	0	0
T10	82217	62457	0	0
T11	291348	274221	0	0
T12	127554	127130	0	0
T13	116611	115370	0	0
T14	0	373704	0	0
T15	0	62152	0	0
T16	0	15136	0	0
T24	0	4624	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1967763618	8595207	0	0
T1	110812	832	0	0
T2	208167	832	0	0
T3	5602	0	0	0
T4	1518	0	0	0
T5	2390365	22825	0	0
T6	2482	0	0	0
T7	1730192	22774	0	0
T8	727859	832	0	0
T9	764411	8786	0	0
T10	82217	832	0	0
T11	291348	28992	0	0
T12	255108	832	0	0
T13	233222	832	0	0
T14	0	12101	0	0
T15	0	9485	0	0
T16	0	2885	0	0
T23	0	908	0	0
T24	0	287	0	0
T25	0	765	0	0
T26	8544	0	0	0
T27	0	4487	0	0
T28	0	999	0	0
T34	0	4714	0	0

Line Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	7	77.78
Logical	9	7	77.78
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T5,T7,T9
1	0	Covered	T5,T7,T9

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T3,T5,T6
1	0	Unreachable
1	1	Covered	T5,T7,T9

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		10	9	90.00
TERNARY	76	2	1	50.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T5,T7,T9
0	0	1	Unreachable
0	0	0	Covered	T3,T5,T6

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T5,T7,T9
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T5,T7,T9
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	12	75.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	12	75.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	381988954	84797087	0	0
CheckNGreaterZero_A	1852	1852	0	0
GntImpliesReady_A	381988954	1833621	0	0
GntImpliesValid_A	381988954	1833621	0	0
GrantKnown_A	381988954	84797087	0	0
IdxKnown_A	381988954	84797087	0	0
IndexIsCorrect_A	381988954	1833621	0	0
LockArbDecision_A	381988954	0	0	0
NoReadyValidNoGrant_A	381988954	0	0	0
ReadyAndValidImplyGrant_A	381988954	1833621	0	0
ReqAndReadyImplyGrant_A	381988954	1833621	0	0
ReqImpliesValid_A	381988954	1833621	0	0
ReqStaysHighUntilGranted0_M	381988954	0	0	0
RoundRobin_A	381988954	0	0	0
ValidKnown_A	381988954	84797087	0	0
gen_data_port_assertion.DataFlow_A	381988954	1833621	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	381988954	84797087	0	0
T3	1325	1296	0	0
T5	992277	14960	0	0
T6	360	360	0	0
T7	749009	55624	0	0
T8	181176	0	0	0
T9	318604	51352	0	0
T10	19687	0	0	0
T11	145674	143488	0	0
T12	127554	0	0	0
T13	116611	0	0	0
T14	0	373704	0	0
T15	0	62152	0	0
T16	0	15136	0	0
T24	0	4624	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1852	1852	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	381988954	1833621	0	0
T5	992277	697	0	0
T6	360	0	0	0
T7	749009	2144	0	0
T8	181176	0	0	0
T9	318604	1712	0	0
T10	19687	0	0	0
T11	145674	1321	0	0
T12	127554	0	0	0
T13	116611	0	0	0
T14	0	5516	0	0
T15	0	1649	0	0
T16	0	364	0	0
T24	0	287	0	0
T26	4272	0	0	0
T28	0	999	0	0
T34	0	4714	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	381988954	1833621	0	0
T5	992277	697	0	0
T6	360	0	0	0
T7	749009	2144	0	0
T8	181176	0	0	0
T9	318604	1712	0	0
T10	19687	0	0	0
T11	145674	1321	0	0
T12	127554	0	0	0
T13	116611	0	0	0
T14	0	5516	0	0
T15	0	1649	0	0
T16	0	364	0	0
T24	0	287	0	0
T26	4272	0	0	0
T28	0	999	0	0
T34	0	4714	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	381988954	84797087	0	0
T3	1325	1296	0	0
T5	992277	14960	0	0
T6	360	360	0	0
T7	749009	55624	0	0
T8	181176	0	0	0
T9	318604	51352	0	0
T10	19687	0	0	0
T11	145674	143488	0	0
T12	127554	0	0	0
T13	116611	0	0	0
T14	0	373704	0	0
T15	0	62152	0	0
T16	0	15136	0	0
T24	0	4624	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	381988954	84797087	0	0
T3	1325	1296	0	0
T5	992277	14960	0	0
T6	360	360	0	0
T7	749009	55624	0	0
T8	181176	0	0	0
T9	318604	51352	0	0
T10	19687	0	0	0
T11	145674	143488	0	0
T12	127554	0	0	0
T13	116611	0	0	0
T14	0	373704	0	0
T15	0	62152	0	0
T16	0	15136	0	0
T24	0	4624	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	381988954	1833621	0	0
T5	992277	697	0	0
T6	360	0	0	0
T7	749009	2144	0	0
T8	181176	0	0	0
T9	318604	1712	0	0
T10	19687	0	0	0
T11	145674	1321	0	0
T12	127554	0	0	0
T13	116611	0	0	0
T14	0	5516	0	0
T15	0	1649	0	0
T16	0	364	0	0
T24	0	287	0	0
T26	4272	0	0	0
T28	0	999	0	0
T34	0	4714	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	381988954	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	381988954	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	381988954	1833621	0	0
T5	992277	697	0	0
T6	360	0	0	0
T7	749009	2144	0	0
T8	181176	0	0	0
T9	318604	1712	0	0
T10	19687	0	0	0
T11	145674	1321	0	0
T12	127554	0	0	0
T13	116611	0	0	0
T14	0	5516	0	0
T15	0	1649	0	0
T16	0	364	0	0
T24	0	287	0	0
T26	4272	0	0	0
T28	0	999	0	0
T34	0	4714	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	381988954	1833621	0	0
T5	992277	697	0	0
T6	360	0	0	0
T7	749009	2144	0	0
T8	181176	0	0	0
T9	318604	1712	0	0
T10	19687	0	0	0
T11	145674	1321	0	0
T12	127554	0	0	0
T13	116611	0	0	0
T14	0	5516	0	0
T15	0	1649	0	0
T16	0	364	0	0
T24	0	287	0	0
T26	4272	0	0	0
T28	0	999	0	0
T34	0	4714	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	381988954	1833621	0	0
T5	992277	697	0	0
T6	360	0	0	0
T7	749009	2144	0	0
T8	181176	0	0	0
T9	318604	1712	0	0
T10	19687	0	0	0
T11	145674	1321	0	0
T12	127554	0	0	0
T13	116611	0	0	0
T14	0	5516	0	0
T15	0	1649	0	0
T16	0	364	0	0
T24	0	287	0	0
T26	4272	0	0	0
T28	0	999	0	0
T34	0	4714	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	381988954	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	381988954	0	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	381988954	84797087	0	0
T3	1325	1296	0	0
T5	992277	14960	0	0
T6	360	360	0	0
T7	749009	55624	0	0
T8	181176	0	0	0
T9	318604	51352	0	0
T10	19687	0	0	0
T11	145674	143488	0	0
T12	127554	0	0	0
T13	116611	0	0	0
T14	0	373704	0	0
T15	0	62152	0	0
T16	0	15136	0	0
T24	0	4624	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	381988954	1833621	0	0
T5	992277	697	0	0
T6	360	0	0	0
T7	749009	2144	0	0
T8	181176	0	0	0
T9	318604	1712	0	0
T10	19687	0	0	0
T11	145674	1321	0	0
T12	127554	0	0	0
T13	116611	0	0	0
T14	0	5516	0	0
T15	0	1649	0	0
T16	0	364	0	0
T24	0	287	0	0
T26	4272	0	0	0
T28	0	999	0	0
T34	0	4714	0	0

Line Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T5,T7,T9

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T5,T7,T9
1	0	Covered	T5,T7,T9

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T5
1	0	Unreachable
1	1	Covered	T5,T7,T9

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		10	10	100.00
TERNARY	76	2	2	100.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T5,T7,T9
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T5,T7,T9
0	0	1	Unreachable
0	0	0	Covered	T1,T2,T5

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T5,T7,T9
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T5,T7,T9
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	12	75.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	12	75.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	381988954	293578611	0	0
CheckNGreaterZero_A	1852	1852	0	0
GntImpliesReady_A	381988954	1392283	0	0
GntImpliesValid_A	381988954	1392283	0	0
GrantKnown_A	381988954	293578611	0	0
IdxKnown_A	381988954	293578611	0	0
IndexIsCorrect_A	381988954	1392283	0	0
LockArbDecision_A	381988954	0	0	0
NoReadyValidNoGrant_A	381988954	0	0	0
ReadyAndValidImplyGrant_A	381988954	1392283	0	0
ReqAndReadyImplyGrant_A	381988954	1392283	0	0
ReqImpliesValid_A	381988954	1392283	0	0
ReqStaysHighUntilGranted0_M	381988954	0	0	0
RoundRobin_A	381988954	0	0	0
ValidKnown_A	381988954	293578611	0	0
gen_data_port_assertion.DataFlow_A	381988954	1392283	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	381988954	293578611	0	0
T1	13408	13408	0	0
T2	39758	38698	0	0
T3	1325	0	0	0
T5	992277	973085	0	0
T6	360	0	0	0
T7	749009	687436	0	0
T8	181176	181176	0	0
T9	318604	262433	0	0
T10	19687	19687	0	0
T11	145674	130733	0	0
T12	0	127130	0	0
T13	0	115370	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1852	1852	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	381988954	1392283	0	0
T5	992277	10285	0	0
T6	360	0	0	0
T7	749009	4960	0	0
T8	181176	0	0	0
T9	318604	393	0	0
T10	19687	0	0	0
T11	145674	11173	0	0
T12	127554	0	0	0
T13	116611	0	0	0
T14	0	6585	0	0
T15	0	7836	0	0
T16	0	2521	0	0
T23	0	908	0	0
T25	0	765	0	0
T26	4272	0	0	0
T27	0	4487	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	381988954	1392283	0	0
T5	992277	10285	0	0
T6	360	0	0	0
T7	749009	4960	0	0
T8	181176	0	0	0
T9	318604	393	0	0
T10	19687	0	0	0
T11	145674	11173	0	0
T12	127554	0	0	0
T13	116611	0	0	0
T14	0	6585	0	0
T15	0	7836	0	0
T16	0	2521	0	0
T23	0	908	0	0
T25	0	765	0	0
T26	4272	0	0	0
T27	0	4487	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	381988954	293578611	0	0
T1	13408	13408	0	0
T2	39758	38698	0	0
T3	1325	0	0	0
T5	992277	973085	0	0
T6	360	0	0	0
T7	749009	687436	0	0
T8	181176	181176	0	0
T9	318604	262433	0	0
T10	19687	19687	0	0
T11	145674	130733	0	0
T12	0	127130	0	0
T13	0	115370	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	381988954	293578611	0	0
T1	13408	13408	0	0
T2	39758	38698	0	0
T3	1325	0	0	0
T5	992277	973085	0	0
T6	360	0	0	0
T7	749009	687436	0	0
T8	181176	181176	0	0
T9	318604	262433	0	0
T10	19687	19687	0	0
T11	145674	130733	0	0
T12	0	127130	0	0
T13	0	115370	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	381988954	1392283	0	0
T5	992277	10285	0	0
T6	360	0	0	0
T7	749009	4960	0	0
T8	181176	0	0	0
T9	318604	393	0	0
T10	19687	0	0	0
T11	145674	11173	0	0
T12	127554	0	0	0
T13	116611	0	0	0
T14	0	6585	0	0
T15	0	7836	0	0
T16	0	2521	0	0
T23	0	908	0	0
T25	0	765	0	0
T26	4272	0	0	0
T27	0	4487	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	381988954	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	381988954	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	381988954	1392283	0	0
T5	992277	10285	0	0
T6	360	0	0	0
T7	749009	4960	0	0
T8	181176	0	0	0
T9	318604	393	0	0
T10	19687	0	0	0
T11	145674	11173	0	0
T12	127554	0	0	0
T13	116611	0	0	0
T14	0	6585	0	0
T15	0	7836	0	0
T16	0	2521	0	0
T23	0	908	0	0
T25	0	765	0	0
T26	4272	0	0	0
T27	0	4487	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	381988954	1392283	0	0
T5	992277	10285	0	0
T6	360	0	0	0
T7	749009	4960	0	0
T8	181176	0	0	0
T9	318604	393	0	0
T10	19687	0	0	0
T11	145674	11173	0	0
T12	127554	0	0	0
T13	116611	0	0	0
T14	0	6585	0	0
T15	0	7836	0	0
T16	0	2521	0	0
T23	0	908	0	0
T25	0	765	0	0
T26	4272	0	0	0
T27	0	4487	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	381988954	1392283	0	0
T5	992277	10285	0	0
T6	360	0	0	0
T7	749009	4960	0	0
T8	181176	0	0	0
T9	318604	393	0	0
T10	19687	0	0	0
T11	145674	11173	0	0
T12	127554	0	0	0
T13	116611	0	0	0
T14	0	6585	0	0
T15	0	7836	0	0
T16	0	2521	0	0
T23	0	908	0	0
T25	0	765	0	0
T26	4272	0	0	0
T27	0	4487	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	381988954	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	381988954	0	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	381988954	293578611	0	0
T1	13408	13408	0	0
T2	39758	38698	0	0
T3	1325	0	0	0
T5	992277	973085	0	0
T6	360	0	0	0
T7	749009	687436	0	0
T8	181176	181176	0	0
T9	318604	262433	0	0
T10	19687	19687	0	0
T11	145674	130733	0	0
T12	0	127130	0	0
T13	0	115370	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	381988954	1392283	0	0
T5	992277	10285	0	0
T6	360	0	0	0
T7	749009	4960	0	0
T8	181176	0	0	0
T9	318604	393	0	0
T10	19687	0	0	0
T11	145674	11173	0	0
T12	127554	0	0	0
T13	116611	0	0	0
T14	0	6585	0	0
T15	0	7836	0	0
T16	0	2521	0	0
T23	0	908	0	0
T25	0	765	0	0
T26	4272	0	0	0
T27	0	4487	0	0

Line Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T5,T7,T9

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T5,T7,T9
1	0	Covered	T1,T2,T5

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Covered	T1,T2,T5

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		10	10	100.00
TERNARY	76	2	2	100.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T5,T7,T9
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T5
0	0	1	Unreachable
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T5
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T5
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	1203785710	1203617844	0	0
CheckNGreaterZero_A	1852	1852	0	0
GntImpliesReady_A	1203785710	5369303	0	0
GntImpliesValid_A	1203785710	5369303	0	0
GrantKnown_A	1203785710	1203617844	0	0
IdxKnown_A	1203785710	1203617844	0	0
IndexIsCorrect_A	1203785710	5369303	0	0
LockArbDecision_A	1203785710	0	0	0
NoReadyValidNoGrant_A	1203785710	0	0	0
ReadyAndValidImplyGrant_A	1203785710	5369303	0	0
ReqAndReadyImplyGrant_A	1203785710	5369303	0	0
ReqImpliesValid_A	1203785710	5369303	0	0
ReqStaysHighUntilGranted0_M	1203785710	0	0	0
RoundRobin_A	1203785710	11	0	1852
ValidKnown_A	1203785710	1203617844	0	0
gen_data_port_assertion.DataFlow_A	1203785710	5369303	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1203785710	1203617844	0	0
T1	110812	110733	0	0
T2	208167	208073	0	0
T3	5602	5524	0	0
T4	1518	1428	0	0
T5	405811	405804	0	0
T6	1762	1664	0	0
T7	232174	232167	0	0
T8	365507	365413	0	0
T9	127203	127197	0	0
T10	42843	42770	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1852	1852	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1203785710	5369303	0	0
T1	110812	832	0	0
T2	208167	832	0	0
T3	5602	0	0	0
T4	1518	0	0	0
T5	405811	11843	0	0
T6	1762	0	0	0
T7	232174	15670	0	0
T8	365507	832	0	0
T9	127203	6681	0	0
T10	42843	832	0	0
T11	0	16498	0	0
T12	0	832	0	0
T13	0	832	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1203785710	5369303	0	0
T1	110812	832	0	0
T2	208167	832	0	0
T3	5602	0	0	0
T4	1518	0	0	0
T5	405811	11843	0	0
T6	1762	0	0	0
T7	232174	15670	0	0
T8	365507	832	0	0
T9	127203	6681	0	0
T10	42843	832	0	0
T11	0	16498	0	0
T12	0	832	0	0
T13	0	832	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1203785710	1203617844	0	0
T1	110812	110733	0	0
T2	208167	208073	0	0
T3	5602	5524	0	0
T4	1518	1428	0	0
T5	405811	405804	0	0
T6	1762	1664	0	0
T7	232174	232167	0	0
T8	365507	365413	0	0
T9	127203	127197	0	0
T10	42843	42770	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1203785710	1203617844	0	0
T1	110812	110733	0	0
T2	208167	208073	0	0
T3	5602	5524	0	0
T4	1518	1428	0	0
T5	405811	405804	0	0
T6	1762	1664	0	0
T7	232174	232167	0	0
T8	365507	365413	0	0
T9	127203	127197	0	0
T10	42843	42770	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1203785710	5369303	0	0
T1	110812	832	0	0
T2	208167	832	0	0
T3	5602	0	0	0
T4	1518	0	0	0
T5	405811	11843	0	0
T6	1762	0	0	0
T7	232174	15670	0	0
T8	365507	832	0	0
T9	127203	6681	0	0
T10	42843	832	0	0
T11	0	16498	0	0
T12	0	832	0	0
T13	0	832	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1203785710	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1203785710	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1203785710	5369303	0	0
T1	110812	832	0	0
T2	208167	832	0	0
T3	5602	0	0	0
T4	1518	0	0	0
T5	405811	11843	0	0
T6	1762	0	0	0
T7	232174	15670	0	0
T8	365507	832	0	0
T9	127203	6681	0	0
T10	42843	832	0	0
T11	0	16498	0	0
T12	0	832	0	0
T13	0	832	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1203785710	5369303	0	0
T1	110812	832	0	0
T2	208167	832	0	0
T3	5602	0	0	0
T4	1518	0	0	0
T5	405811	11843	0	0
T6	1762	0	0	0
T7	232174	15670	0	0
T8	365507	832	0	0
T9	127203	6681	0	0
T10	42843	832	0	0
T11	0	16498	0	0
T12	0	832	0	0
T13	0	832	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1203785710	5369303	0	0
T1	110812	832	0	0
T2	208167	832	0	0
T3	5602	0	0	0
T4	1518	0	0	0
T5	405811	11843	0	0
T6	1762	0	0	0
T7	232174	15670	0	0
T8	365507	832	0	0
T9	127203	6681	0	0
T10	42843	832	0	0
T11	0	16498	0	0
T12	0	832	0	0
T13	0	832	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	1203785710	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1203785710	11	0	1852
T14	575266	1	0	1
T15	814316	0	0	1
T16	773392	0	0	1
T23	167274	0	0	1
T24	6412	0	0	1
T25	126177	0	0	1
T35	0	1	0	0
T36	0	1	0	0
T37	0	1	0	0
T38	0	1	0	0
T39	0	1	0	0
T40	0	1	0	0
T41	0	1	0	0
T42	0	1	0	0
T43	0	1	0	0
T44	3977	0	0	1
T45	3010	0	0	1
T46	512359	0	0	1
T47	56178	0	0	1

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1203785710	1203617844	0	0
T1	110812	110733	0	0
T2	208167	208073	0	0
T3	5602	5524	0	0
T4	1518	1428	0	0
T5	405811	405804	0	0
T6	1762	1664	0	0
T7	232174	232167	0	0
T8	365507	365413	0	0
T9	127203	127197	0	0
T10	42843	42770	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1203785710	5369303	0	0
T1	110812	832	0	0
T2	208167	832	0	0
T3	5602	0	0	0
T4	1518	0	0	0
T5	405811	11843	0	0
T6	1762	0	0	0
T7	232174	15670	0	0
T8	365507	832	0	0
T9	127203	6681	0	0
T10	42843	832	0	0
T11	0	16498	0	0
T12	0	832	0	0
T13	0	832	0	0