Module Definition
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Module : prim_sram_arbiter
SCORELINECONDTOGGLEFSMBRANCHASSERT
91.67 100.00 83.33

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_sram_arbiter.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.u_upload.u_arbiter 66.67 100.00 33.33
tb.dut.u_sys_sram_arbiter 83.33 100.00 66.67
tb.dut.u_spi_tpm.u_arbiter 91.67 100.00 83.33



Module Instance : tb.dut.u_upload.u_arbiter

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
66.67 100.00 33.33


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
71.57 92.21 51.22 71.43 71.43


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
96.37 100.00 86.11 100.00 95.74 100.00 u_upload


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_arb_ppc.u_reqarb 90.97 100.00 88.89 100.00 75.00
u_req_fifo 60.72 85.00 42.31 55.56 60.00



Module Instance : tb.dut.u_sys_sram_arbiter

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
83.33 100.00 66.67


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
88.22 100.00 70.73 96.43 85.71


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
91.69 94.25 84.31 96.94 87.50 95.45 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_arb_ppc.u_reqarb 92.53 100.00 88.89 100.00 81.25
u_req_fifo 89.96 100.00 65.38 94.44 100.00



Module Instance : tb.dut.u_spi_tpm.u_arbiter

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
91.67 100.00 83.33


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
86.14 100.00 70.73 92.86 80.95


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
95.66 99.29 91.20 91.67 96.13 100.00 u_spi_tpm


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_arb_ppc.u_reqarb 85.69 100.00 77.78 90.00 75.00
u_req_fifo 89.96 100.00 65.38 94.44 100.00

Line Coverage for Module : prim_sram_arbiter ( parameter N=3,SramDw=32,SramAw=10,ArbiterImpl="PPC",EnMask=1 )
Line Coverage for Module self-instances :
SCORELINE
66.67 100.00
tb.dut.u_upload.u_arbiter

Line No.TotalCoveredPercent
TOTAL1515100.00
CONT_ASSIGN5611100.00
CONT_ASSIGN5611100.00
CONT_ASSIGN5611100.00
CONT_ASSIGN6711100.00
CONT_ASSIGN6811100.00
CONT_ASSIGN6911100.00
CONT_ASSIGN7011100.00
CONT_ASSIGN12511100.00
CONT_ASSIGN14711100.00
CONT_ASSIGN15011100.00
CONT_ASSIGN15011100.00
CONT_ASSIGN15011100.00
CONT_ASSIGN15111100.00
CONT_ASSIGN15111100.00
CONT_ASSIGN15111100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_sram_arbiter.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_sram_arbiter.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
56 3 3
67 1 1
68 1 1
69 1 1
70 1 1
125 1 1
147 1 1
150 3 3
151 3 3


Line Coverage for Module : prim_sram_arbiter ( parameter N=2,SramDw=32,SramAw=10,ArbiterImpl="PPC",EnMask=1 )
Line Coverage for Module self-instances :
SCORELINE
91.67 100.00
tb.dut.u_spi_tpm.u_arbiter

Line No.TotalCoveredPercent
TOTAL1212100.00
CONT_ASSIGN5611100.00
CONT_ASSIGN5611100.00
CONT_ASSIGN6711100.00
CONT_ASSIGN6811100.00
CONT_ASSIGN6911100.00
CONT_ASSIGN7011100.00
CONT_ASSIGN12511100.00
CONT_ASSIGN14711100.00
CONT_ASSIGN15011100.00
CONT_ASSIGN15011100.00
CONT_ASSIGN15111100.00
CONT_ASSIGN15111100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_sram_arbiter.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_sram_arbiter.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
56 2 2
67 1 1
68 1 1
69 1 1
70 1 1
125 1 1
147 1 1
150 2 2
151 2 2


Line Coverage for Module : prim_sram_arbiter ( parameter N=5,SramDw=32,SramAw=10,ArbiterImpl="PPC",EnMask=1 )
Line Coverage for Module self-instances :
SCORELINE
83.33 100.00
tb.dut.u_sys_sram_arbiter

Line No.TotalCoveredPercent
TOTAL2121100.00
CONT_ASSIGN5611100.00
CONT_ASSIGN5611100.00
CONT_ASSIGN5611100.00
CONT_ASSIGN5611100.00
CONT_ASSIGN5611100.00
CONT_ASSIGN6711100.00
CONT_ASSIGN6811100.00
CONT_ASSIGN6911100.00
CONT_ASSIGN7011100.00
CONT_ASSIGN12511100.00
CONT_ASSIGN14711100.00
CONT_ASSIGN15011100.00
CONT_ASSIGN15011100.00
CONT_ASSIGN15011100.00
CONT_ASSIGN15011100.00
CONT_ASSIGN15011100.00
CONT_ASSIGN15111100.00
CONT_ASSIGN15111100.00
CONT_ASSIGN15111100.00
CONT_ASSIGN15111100.00
CONT_ASSIGN15111100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_sram_arbiter.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_sram_arbiter.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
56 5 5
67 1 1
68 1 1
69 1 1
70 1 1
125 1 1
147 1 1
150 5 5
151 5 5


Cond Coverage for Module : prim_sram_arbiter
TotalCoveredPercent
Conditions6583.33
Logical6583.33
Non-Logical00
Event00

 LINE       125
 EXPRESSION (sram_rvalid_i & ((|steer)))
             ------1------   -----2----
-1--2-StatusTests
01Not Covered
10CoveredT5,T7,T9
11CoveredT5,T7,T9

 LINE       132
 EXPRESSION (sram_req_o & ((~sram_write_o)))
             -----1----   --------2--------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T5
11CoveredT5,T7,T9
Line Coverage for Instance : tb.dut.u_upload.u_arbiter
Line No.TotalCoveredPercent
TOTAL1515100.00
CONT_ASSIGN5611100.00
CONT_ASSIGN5611100.00
CONT_ASSIGN5611100.00
CONT_ASSIGN6711100.00
CONT_ASSIGN6811100.00
CONT_ASSIGN6911100.00
CONT_ASSIGN7011100.00
CONT_ASSIGN12511100.00
CONT_ASSIGN14711100.00
CONT_ASSIGN15011100.00
CONT_ASSIGN15011100.00
CONT_ASSIGN15011100.00
CONT_ASSIGN15111100.00
CONT_ASSIGN15111100.00
CONT_ASSIGN15111100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_sram_arbiter.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_sram_arbiter.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
56 3 3
67 1 1
68 1 1
69 1 1
70 1 1
125 1 1
147 1 1
150 3 3
151 3 3


Cond Coverage for Instance : tb.dut.u_upload.u_arbiter
TotalCoveredPercent
Conditions6233.33
Logical6233.33
Non-Logical00
Event00

 LINE       125
 EXPRESSION (sram_rvalid_i & ((|steer)))
             ------1------   -----2----
-1--2-StatusTests
01Not Covered
10Not Covered
11Not Covered

 LINE       132
 EXPRESSION (sram_req_o & ((~sram_write_o)))
             -----1----   --------2--------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT5,T7,T9
11Not Covered
Line Coverage for Instance : tb.dut.u_sys_sram_arbiter
Line No.TotalCoveredPercent
TOTAL2121100.00
CONT_ASSIGN5611100.00
CONT_ASSIGN5611100.00
CONT_ASSIGN5611100.00
CONT_ASSIGN5611100.00
CONT_ASSIGN5611100.00
CONT_ASSIGN6711100.00
CONT_ASSIGN6811100.00
CONT_ASSIGN6911100.00
CONT_ASSIGN7011100.00
CONT_ASSIGN12511100.00
CONT_ASSIGN14711100.00
CONT_ASSIGN15011100.00
CONT_ASSIGN15011100.00
CONT_ASSIGN15011100.00
CONT_ASSIGN15011100.00
CONT_ASSIGN15011100.00
CONT_ASSIGN15111100.00
CONT_ASSIGN15111100.00
CONT_ASSIGN15111100.00
CONT_ASSIGN15111100.00
CONT_ASSIGN15111100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_sram_arbiter.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_sram_arbiter.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
56 5 5
67 1 1
68 1 1
69 1 1
70 1 1
125 1 1
147 1 1
150 5 5
151 5 5


Cond Coverage for Instance : tb.dut.u_sys_sram_arbiter
TotalCoveredPercent
Conditions6466.67
Logical6466.67
Non-Logical00
Event00

 LINE       125
 EXPRESSION (sram_rvalid_i & ((|steer)))
             ------1------   -----2----
-1--2-StatusTests
01Not Covered
10Not Covered
11CoveredT5,T7,T9

 LINE       132
 EXPRESSION (sram_req_o & ((~sram_write_o)))
             -----1----   --------2--------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T5
11CoveredT5,T7,T9
Line Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter
Line No.TotalCoveredPercent
TOTAL1212100.00
CONT_ASSIGN5611100.00
CONT_ASSIGN5611100.00
CONT_ASSIGN6711100.00
CONT_ASSIGN6811100.00
CONT_ASSIGN6911100.00
CONT_ASSIGN7011100.00
CONT_ASSIGN12511100.00
CONT_ASSIGN14711100.00
CONT_ASSIGN15011100.00
CONT_ASSIGN15011100.00
CONT_ASSIGN15111100.00
CONT_ASSIGN15111100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_sram_arbiter.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_sram_arbiter.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
56 2 2
67 1 1
68 1 1
69 1 1
70 1 1
125 1 1
147 1 1
150 2 2
151 2 2


Cond Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter
TotalCoveredPercent
Conditions6583.33
Logical6583.33
Non-Logical00
Event00

 LINE       125
 EXPRESSION (sram_rvalid_i & ((|steer)))
             ------1------   -----2----
-1--2-StatusTests
01Not Covered
10CoveredT5,T7,T9
11CoveredT5,T7,T9

 LINE       132
 EXPRESSION (sram_req_o & ((~sram_write_o)))
             -----1----   --------2--------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT5,T7,T9
11CoveredT5,T7,T9
0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%