Line Coverage for Module :
prim_sram_arbiter ( parameter N=3,SramDw=32,SramAw=10,ArbiterImpl="PPC",EnMask=1 )
Line Coverage for Module self-instances :
| Line No. | Total | Covered | Percent |
TOTAL | | 15 | 15 | 100.00 |
CONT_ASSIGN | 56 | 1 | 1 | 100.00 |
CONT_ASSIGN | 56 | 1 | 1 | 100.00 |
CONT_ASSIGN | 56 | 1 | 1 | 100.00 |
CONT_ASSIGN | 67 | 1 | 1 | 100.00 |
CONT_ASSIGN | 68 | 1 | 1 | 100.00 |
CONT_ASSIGN | 69 | 1 | 1 | 100.00 |
CONT_ASSIGN | 70 | 1 | 1 | 100.00 |
CONT_ASSIGN | 125 | 1 | 1 | 100.00 |
CONT_ASSIGN | 147 | 1 | 1 | 100.00 |
CONT_ASSIGN | 150 | 1 | 1 | 100.00 |
CONT_ASSIGN | 150 | 1 | 1 | 100.00 |
CONT_ASSIGN | 150 | 1 | 1 | 100.00 |
CONT_ASSIGN | 151 | 1 | 1 | 100.00 |
CONT_ASSIGN | 151 | 1 | 1 | 100.00 |
CONT_ASSIGN | 151 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_sram_arbiter.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_sram_arbiter.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
56 |
3 |
3 |
67 |
1 |
1 |
68 |
1 |
1 |
69 |
1 |
1 |
70 |
1 |
1 |
125 |
1 |
1 |
147 |
1 |
1 |
150 |
3 |
3 |
151 |
3 |
3 |
Line Coverage for Module :
prim_sram_arbiter ( parameter N=2,SramDw=32,SramAw=10,ArbiterImpl="PPC",EnMask=1 )
Line Coverage for Module self-instances :
| Line No. | Total | Covered | Percent |
TOTAL | | 12 | 12 | 100.00 |
CONT_ASSIGN | 56 | 1 | 1 | 100.00 |
CONT_ASSIGN | 56 | 1 | 1 | 100.00 |
CONT_ASSIGN | 67 | 1 | 1 | 100.00 |
CONT_ASSIGN | 68 | 1 | 1 | 100.00 |
CONT_ASSIGN | 69 | 1 | 1 | 100.00 |
CONT_ASSIGN | 70 | 1 | 1 | 100.00 |
CONT_ASSIGN | 125 | 1 | 1 | 100.00 |
CONT_ASSIGN | 147 | 1 | 1 | 100.00 |
CONT_ASSIGN | 150 | 1 | 1 | 100.00 |
CONT_ASSIGN | 150 | 1 | 1 | 100.00 |
CONT_ASSIGN | 151 | 1 | 1 | 100.00 |
CONT_ASSIGN | 151 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_sram_arbiter.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_sram_arbiter.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
56 |
2 |
2 |
67 |
1 |
1 |
68 |
1 |
1 |
69 |
1 |
1 |
70 |
1 |
1 |
125 |
1 |
1 |
147 |
1 |
1 |
150 |
2 |
2 |
151 |
2 |
2 |
Line Coverage for Module :
prim_sram_arbiter ( parameter N=5,SramDw=32,SramAw=10,ArbiterImpl="PPC",EnMask=1 )
Line Coverage for Module self-instances :
| Line No. | Total | Covered | Percent |
TOTAL | | 21 | 21 | 100.00 |
CONT_ASSIGN | 56 | 1 | 1 | 100.00 |
CONT_ASSIGN | 56 | 1 | 1 | 100.00 |
CONT_ASSIGN | 56 | 1 | 1 | 100.00 |
CONT_ASSIGN | 56 | 1 | 1 | 100.00 |
CONT_ASSIGN | 56 | 1 | 1 | 100.00 |
CONT_ASSIGN | 67 | 1 | 1 | 100.00 |
CONT_ASSIGN | 68 | 1 | 1 | 100.00 |
CONT_ASSIGN | 69 | 1 | 1 | 100.00 |
CONT_ASSIGN | 70 | 1 | 1 | 100.00 |
CONT_ASSIGN | 125 | 1 | 1 | 100.00 |
CONT_ASSIGN | 147 | 1 | 1 | 100.00 |
CONT_ASSIGN | 150 | 1 | 1 | 100.00 |
CONT_ASSIGN | 150 | 1 | 1 | 100.00 |
CONT_ASSIGN | 150 | 1 | 1 | 100.00 |
CONT_ASSIGN | 150 | 1 | 1 | 100.00 |
CONT_ASSIGN | 150 | 1 | 1 | 100.00 |
CONT_ASSIGN | 151 | 1 | 1 | 100.00 |
CONT_ASSIGN | 151 | 1 | 1 | 100.00 |
CONT_ASSIGN | 151 | 1 | 1 | 100.00 |
CONT_ASSIGN | 151 | 1 | 1 | 100.00 |
CONT_ASSIGN | 151 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_sram_arbiter.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_sram_arbiter.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
56 |
5 |
5 |
67 |
1 |
1 |
68 |
1 |
1 |
69 |
1 |
1 |
70 |
1 |
1 |
125 |
1 |
1 |
147 |
1 |
1 |
150 |
5 |
5 |
151 |
5 |
5 |
Cond Coverage for Module :
prim_sram_arbiter
| Total | Covered | Percent |
Conditions | 6 | 5 | 83.33 |
Logical | 6 | 5 | 83.33 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 125
EXPRESSION (sram_rvalid_i & ((|steer)))
------1------ -----2----
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T5,T7,T9 |
1 | 1 | Covered | T5,T7,T9 |
LINE 132
EXPRESSION (sram_req_o & ((~sram_write_o)))
-----1---- --------2--------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T5 |
1 | 1 | Covered | T5,T7,T9 |
Line Coverage for Instance : tb.dut.u_upload.u_arbiter
| Line No. | Total | Covered | Percent |
TOTAL | | 15 | 15 | 100.00 |
CONT_ASSIGN | 56 | 1 | 1 | 100.00 |
CONT_ASSIGN | 56 | 1 | 1 | 100.00 |
CONT_ASSIGN | 56 | 1 | 1 | 100.00 |
CONT_ASSIGN | 67 | 1 | 1 | 100.00 |
CONT_ASSIGN | 68 | 1 | 1 | 100.00 |
CONT_ASSIGN | 69 | 1 | 1 | 100.00 |
CONT_ASSIGN | 70 | 1 | 1 | 100.00 |
CONT_ASSIGN | 125 | 1 | 1 | 100.00 |
CONT_ASSIGN | 147 | 1 | 1 | 100.00 |
CONT_ASSIGN | 150 | 1 | 1 | 100.00 |
CONT_ASSIGN | 150 | 1 | 1 | 100.00 |
CONT_ASSIGN | 150 | 1 | 1 | 100.00 |
CONT_ASSIGN | 151 | 1 | 1 | 100.00 |
CONT_ASSIGN | 151 | 1 | 1 | 100.00 |
CONT_ASSIGN | 151 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_sram_arbiter.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_sram_arbiter.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
56 |
3 |
3 |
67 |
1 |
1 |
68 |
1 |
1 |
69 |
1 |
1 |
70 |
1 |
1 |
125 |
1 |
1 |
147 |
1 |
1 |
150 |
3 |
3 |
151 |
3 |
3 |
Cond Coverage for Instance : tb.dut.u_upload.u_arbiter
| Total | Covered | Percent |
Conditions | 6 | 2 | 33.33 |
Logical | 6 | 2 | 33.33 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 125
EXPRESSION (sram_rvalid_i & ((|steer)))
------1------ -----2----
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Not Covered | |
1 | 1 | Not Covered | |
LINE 132
EXPRESSION (sram_req_o & ((~sram_write_o)))
-----1---- --------2--------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T5,T7,T9 |
1 | 1 | Not Covered | |
Line Coverage for Instance : tb.dut.u_sys_sram_arbiter
| Line No. | Total | Covered | Percent |
TOTAL | | 21 | 21 | 100.00 |
CONT_ASSIGN | 56 | 1 | 1 | 100.00 |
CONT_ASSIGN | 56 | 1 | 1 | 100.00 |
CONT_ASSIGN | 56 | 1 | 1 | 100.00 |
CONT_ASSIGN | 56 | 1 | 1 | 100.00 |
CONT_ASSIGN | 56 | 1 | 1 | 100.00 |
CONT_ASSIGN | 67 | 1 | 1 | 100.00 |
CONT_ASSIGN | 68 | 1 | 1 | 100.00 |
CONT_ASSIGN | 69 | 1 | 1 | 100.00 |
CONT_ASSIGN | 70 | 1 | 1 | 100.00 |
CONT_ASSIGN | 125 | 1 | 1 | 100.00 |
CONT_ASSIGN | 147 | 1 | 1 | 100.00 |
CONT_ASSIGN | 150 | 1 | 1 | 100.00 |
CONT_ASSIGN | 150 | 1 | 1 | 100.00 |
CONT_ASSIGN | 150 | 1 | 1 | 100.00 |
CONT_ASSIGN | 150 | 1 | 1 | 100.00 |
CONT_ASSIGN | 150 | 1 | 1 | 100.00 |
CONT_ASSIGN | 151 | 1 | 1 | 100.00 |
CONT_ASSIGN | 151 | 1 | 1 | 100.00 |
CONT_ASSIGN | 151 | 1 | 1 | 100.00 |
CONT_ASSIGN | 151 | 1 | 1 | 100.00 |
CONT_ASSIGN | 151 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_sram_arbiter.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_sram_arbiter.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
56 |
5 |
5 |
67 |
1 |
1 |
68 |
1 |
1 |
69 |
1 |
1 |
70 |
1 |
1 |
125 |
1 |
1 |
147 |
1 |
1 |
150 |
5 |
5 |
151 |
5 |
5 |
Cond Coverage for Instance : tb.dut.u_sys_sram_arbiter
| Total | Covered | Percent |
Conditions | 6 | 4 | 66.67 |
Logical | 6 | 4 | 66.67 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 125
EXPRESSION (sram_rvalid_i & ((|steer)))
------1------ -----2----
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Not Covered | |
1 | 1 | Covered | T5,T7,T9 |
LINE 132
EXPRESSION (sram_req_o & ((~sram_write_o)))
-----1---- --------2--------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T5 |
1 | 1 | Covered | T5,T7,T9 |
Line Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter
| Line No. | Total | Covered | Percent |
TOTAL | | 12 | 12 | 100.00 |
CONT_ASSIGN | 56 | 1 | 1 | 100.00 |
CONT_ASSIGN | 56 | 1 | 1 | 100.00 |
CONT_ASSIGN | 67 | 1 | 1 | 100.00 |
CONT_ASSIGN | 68 | 1 | 1 | 100.00 |
CONT_ASSIGN | 69 | 1 | 1 | 100.00 |
CONT_ASSIGN | 70 | 1 | 1 | 100.00 |
CONT_ASSIGN | 125 | 1 | 1 | 100.00 |
CONT_ASSIGN | 147 | 1 | 1 | 100.00 |
CONT_ASSIGN | 150 | 1 | 1 | 100.00 |
CONT_ASSIGN | 150 | 1 | 1 | 100.00 |
CONT_ASSIGN | 151 | 1 | 1 | 100.00 |
CONT_ASSIGN | 151 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_sram_arbiter.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_sram_arbiter.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
56 |
2 |
2 |
67 |
1 |
1 |
68 |
1 |
1 |
69 |
1 |
1 |
70 |
1 |
1 |
125 |
1 |
1 |
147 |
1 |
1 |
150 |
2 |
2 |
151 |
2 |
2 |
Cond Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter
| Total | Covered | Percent |
Conditions | 6 | 5 | 83.33 |
Logical | 6 | 5 | 83.33 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 125
EXPRESSION (sram_rvalid_i & ((|steer)))
------1------ -----2----
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T5,T7,T9 |
1 | 1 | Covered | T5,T7,T9 |
LINE 132
EXPRESSION (sram_req_o & ((~sram_write_o)))
-----1---- --------2--------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T5,T7,T9 |
1 | 1 | Covered | T5,T7,T9 |