Module Definition
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Module : spid_readbuffer
SCORELINECONDTOGGLEFSMBRANCHASSERT
89.97 87.76 97.14 75.00 100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_spi_device_0.1/rtl/spid_readbuffer.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.u_readcmd.u_readbuffer 89.97 87.76 97.14 75.00 100.00



Module Instance : tb.dut.u_readcmd.u_readbuffer

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
89.97 87.76 97.14 75.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
68.17 83.51 82.93 72.92 33.33


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
92.19 96.32 100.00 80.00 84.62 100.00 u_readcmd


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_sys2spi_clr 37.29 79.17 0.00 70.00 0.00


Since this is the module's only instance, the coverage report is the same as for the module.
Line Coverage for Module : spid_readbuffer
Line No.TotalCoveredPercent
TOTAL494387.76
ALWAYS1056466.67
ALWAYS1306583.33
CONT_ASSIGN14011100.00
CONT_ASSIGN14111100.00
ALWAYS1476583.33
CONT_ASSIGN15611100.00
CONT_ASSIGN15911100.00
ALWAYS1638787.50
ALWAYS1776583.33
ALWAYS19655100.00
ALWAYS20588100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_spi_device_0.1/rtl/spid_readbuffer.sv' or '../src/lowrisc_ip_spi_device_0.1/rtl/spid_readbuffer.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
105 1 1
106 1 1
107 1 1
108 0 1
109 1 1
110 0 1
MISSING_ELSE
130 1 1
131 1 1
132 1 1
133 0 1
134 1 1
135 1 1
MISSING_ELSE
140 1 1
141 1 1
147 1 1
148 1 1
149 1 1
150 0 1
151 1 1
152 1 1
MISSING_ELSE
156 1 1
159 1 1
163 1 1
164 1 1
165 1 1
166 0 1
167 1 1
170 1 1
171 1 1
172 1 1
MISSING_ELSE
177 1 1
179 1 1
180 1 1
181 1 1
182 1 1
187 0 1
MISSING_ELSE
MISSING_ELSE
196 2 2
197 1 1
198 1 1
200 1 1
205 1 1
207 1 1
209 1 1
211 1 1
213 1 1
215 1 1
MISSING_ELSE
221 1 1
223 1 1


Cond Coverage for Module : spid_readbuffer
TotalCoveredPercent
Conditions353497.14
Logical353497.14
Non-Logical00
Event00

 LINE       134
 EXPRESSION (active && flip)
             ---1--    --2-
-1--2-StatusTests
01CoveredT11,T14,T28
10CoveredT1,T2,T10
11CoveredT1,T10,T33

 LINE       141
 EXPRESSION (current_buffer_idx == next_buffer_addr)
            --------------------1-------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T10,T11

 LINE       156
 EXPRESSION (active && flip && ((!flip_q)))
             ---1--    --2-    -----3-----
-1--2--3-StatusTests
011CoveredT11,T14,T28
101CoveredT1,T2,T10
110Not Covered
111CoveredT1,T10,T33

 LINE       159
 EXPRESSION ((current_address_i[(spi_device_pkg::SramBufferAw - 1):0] >= threshold_i) && ((|threshold_i)))
             ------------------------------------1-----------------------------------    --------2-------
-1--2-StatusTests
01CoveredT1,T2,T5
10CoveredT1,T2,T3
11CoveredT1,T2,T5

 LINE       167
 EXPRESSION (active && watermark_cross)
             ---1--    -------2-------
-1--2-StatusTests
01CoveredT1,T2,T5
10CoveredT1,T2,T10
11CoveredT1,T2,T10

 LINE       171
 EXPRESSION (active && flip)
             ---1--    --2-
-1--2-StatusTests
01CoveredT11,T14,T28
10CoveredT1,T2,T10
11CoveredT1,T10,T33

 LINE       179
 EXPRESSION (active && watermark_cross)
             ---1--    -------2-------
-1--2-StatusTests
01CoveredT1,T2,T5
10CoveredT1,T2,T10
11CoveredT1,T2,T10

 LINE       197
 EXPRESSION (spi_mode_i != FlashMode)
            ------------1------------
-1-StatusTests
0CoveredT1,T2,T7
1CoveredT5,T8,T11

 LINE       211
 EXPRESSION (start_i && (spi_mode_i == FlashMode) && ((!sfdp_hit_i)) && ( ! (mailbox_en_i && mailbox_hit_i) ))
             ---1---    ------------2------------    -------3-------    ------------------4------------------
-1--2--3--4-StatusTests
0111CoveredT1,T2,T3
1011CoveredT5,T8,T11
1101CoveredT7,T9,T15
1110CoveredT2,T7,T9
1111CoveredT1,T2,T10

 LINE       211
 SUB-EXPRESSION (spi_mode_i == FlashMode)
                ------------1------------
-1-StatusTests
0CoveredT5,T8,T11
1CoveredT1,T2,T3

 LINE       211
 SUB-EXPRESSION ( ! (mailbox_en_i && mailbox_hit_i) )
                    ---------------1---------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT2,T5,T7

 LINE       211
 SUB-EXPRESSION (mailbox_en_i && mailbox_hit_i)
                 ------1-----    ------2------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T5
11CoveredT2,T5,T7

Branch Coverage for Module : spid_readbuffer
Line No.TotalCoveredPercent
Branches 28 21 75.00
IF 105 4 2 50.00
IF 130 4 3 75.00
IF 147 4 3 75.00
IF 163 5 4 80.00
IF 179 4 3 75.00
IF 196 3 3 100.00
CASE 209 4 3 75.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_spi_device_0.1/rtl/spid_readbuffer.sv' or '../src/lowrisc_ip_spi_device_0.1/rtl/spid_readbuffer.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 105 if ((!sys_rst_ni)) -2-: 107 if (sys_clr_i) -3-: 109 if (sys_clr_ack)

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T2,T3
0 1 - Not Covered
0 0 1 Not Covered
0 0 0 Covered T1,T2,T3


LineNo. Expression -1-: 130 if ((!sys_rst_ni)) -2-: 132 if (spi_clr) -3-: 134 if ((active && flip))

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T2,T3
0 1 - Not Covered
0 0 1 Covered T1,T10,T33
0 0 0 Covered T1,T2,T3


LineNo. Expression -1-: 147 if ((!sys_rst_ni)) -2-: 149 if (spi_clr) -3-: 151 if (active)

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T2,T3
0 1 - Not Covered
0 0 1 Covered T1,T2,T10
0 0 0 Covered T1,T2,T3


LineNo. Expression -1-: 163 if ((!sys_rst_ni)) -2-: 165 if (spi_clr) -3-: 167 if ((active && watermark_cross)) -4-: 171 if ((active && flip))

Branches:
-1--2--3--4-StatusTests
1 - - - Covered T1,T2,T3
0 1 - - Not Covered
0 0 1 - Covered T1,T2,T10
0 0 0 1 Covered T1,T10,T33
0 0 0 0 Covered T1,T2,T3


LineNo. Expression -1-: 179 if ((active && watermark_cross)) -2-: 180 if ((!watermark_crossed)) -3-: 182 if (flip)

Branches:
-1--2--3-StatusTests
1 1 - Covered T1,T2,T10
1 0 1 Not Covered
1 0 0 Covered T1,T2,T10
0 - - Covered T1,T2,T3


LineNo. Expression -1-: 196 if ((!rst_ni)) -2-: 197 if ((spi_mode_i != FlashMode))

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T5,T8,T11
0 0 Covered T1,T2,T7


LineNo. Expression -1-: 209 case (st_q) -2-: 211 if ((((start_i && (spi_mode_i == FlashMode)) && (!sfdp_hit_i)) && (!(mailbox_en_i && mailbox_hit_i))))

Branches:
-1--2-StatusTests
StIdle 1 Covered T1,T2,T10
StIdle 0 Covered T1,T2,T3
StActive - Covered T1,T2,T10
default - Not Covered


Assert Coverage for Module : spid_readbuffer
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
StartWithAddressUpdate_A 381988954 19936 0 0


StartWithAddressUpdate_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 381988954 19936 0 0
T1 13408 8 0 0
T2 39758 4 0 0
T3 1325 0 0 0
T5 992277 61 0 0
T6 360 0 0 0
T7 749009 47 0 0
T8 181176 2 0 0
T9 318604 13 0 0
T10 19687 8 0 0
T11 145674 91 0 0
T12 0 8 0 0
T13 0 2 0 0

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%