Module Definition
dashboard | hierarchy | modlist | groups | tests | asserts

Module : spi_readcmd
SCORELINECONDTOGGLEFSMBRANCHASSERT
92.19 96.32 100.00 80.00 84.62 100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_spi_device_0.1/rtl/spi_readcmd.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.u_readcmd 92.19 96.32 100.00 80.00 84.62 100.00



Module Instance : tb.dut.u_readcmd

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
92.19 96.32 100.00 80.00 84.62 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
89.31 93.63 90.36 87.50 84.15 90.91


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
91.69 94.25 84.31 96.94 87.50 95.45 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_addr_latch_pulse 100.00 100.00 100.00 100.00
u_readbuffer 68.17 83.51 82.93 72.92 33.33
u_readsram 94.94 97.81 85.71 100.00 91.18 100.00


Since this is the module's only instance, the coverage report is the same as for the module.
Line Coverage for Module : spi_readcmd
Line No.TotalCoveredPercent
TOTAL13613196.32
CONT_ASSIGN18311100.00
CONT_ASSIGN18611100.00
CONT_ASSIGN18911100.00
CONT_ASSIGN19211100.00
CONT_ASSIGN33311100.00
CONT_ASSIGN34011100.00
ALWAYS35344100.00
ALWAYS36944100.00
CONT_ASSIGN37811100.00
ALWAYS3811212100.00
CONT_ASSIGN40411100.00
CONT_ASSIGN40511100.00
CONT_ASSIGN40811100.00
CONT_ASSIGN42411100.00
ALWAYS42733100.00
ALWAYS43577100.00
ALWAYS45666100.00
CONT_ASSIGN46511100.00
ALWAYS4691212100.00
CONT_ASSIGN49611100.00
CONT_ASSIGN49711100.00
CONT_ASSIGN50011100.00
CONT_ASSIGN50111100.00
ALWAYS51388100.00
CONT_ASSIGN52911100.00
ALWAYS53455100.00
ALWAYS55244100.00
CONT_ASSIGN56511100.00
ALWAYS57533100.00
ALWAYS583484389.58
CONT_ASSIGN72011100.00
CONT_ASSIGN72111100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_spi_device_0.1/rtl/spi_readcmd.sv' or '../src/lowrisc_ip_spi_device_0.1/rtl/spi_readcmd.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
183 1 1
186 1 1
189 1 1
192 1 1
333 1 1
340 1 1
353 1 1
354 1 1
355 1 1
356 1 1
MISSING_ELSE
369 1 1
370 1 1
371 1 1
374 1 1
MISSING_ELSE
378 1 1
381 1 1
382 1 1
384 1 1
386 1 1
387 1 1
390 1 1
391 1 1
393 1 1
394 1 1
395 1 1
397 1 1
398 1 1
MISSING_ELSE
404 1 1
405 1 1
408 1 1
424 1 1
427 1 1
428 1 1
430 1 1
435 1 1
436 1 1
443 1 1
445 1 1
446 1 1
447 1 1
449 1 1
==> MISSING_ELSE
456 1 1
457 1 1
458 1 1
460 1 1
461 1 1
462 1 1
MISSING_ELSE
465 1 1
469 1 1
470 1 1
471 1 1
472 1 1
473 1 1
474 1 1
475 1 1
478 1 1
479 1 1
480 1 1
481 1 1
482 1 1
MISSING_ELSE
496 1 1
497 1 1
500 1 1
501 1 1
513 2 2
514 1 1
516 1 1
517 1 1
520 1 1
521 1 1
523 1 1
MISSING_ELSE
529 1 1
534 1 1
535 1 1
536 1 1
538 1 1
539 1 1
552 1 1
553 1 1
554 1 1
560 1 1
MISSING_ELSE
565 1 1
575 1 1
576 1 1
578 1 1
583 1 1
585 1 1
588 1 1
589 1 1
590 1 1
591 1 1
593 1 1
594 1 1
596 1 1
597 1 1
599 1 1
601 1 1
602 1 1
604 1 1
606 1 1
609 1 1
611 1 1
MISSING_ELSE
616 1 1
618 1 1
619 1 1
MISSING_ELSE
622 1 1
625 1 1
631 1 1
634 1 1
635 1 1
636 1 1
641 1 1
643 1 1
648 0 1
MISSING_ELSE
659 0 1
660 0 1
662 0 1
==> MISSING_ELSE
667 1 1
668 1 1
669 1 1
670 1 1
MISSING_ELSE
675 1 1
679 1 1
684 1 1
685 1 1
686 1 1
687 1 1
691 1 1
693 1 1
696 1 1
699 1 1
700 1 1
MISSING_ELSE
705 0 1
720 1 1
721 1 1


Cond Coverage for Module : spi_readcmd
TotalCoveredPercent
Conditions6666100.00
Logical6666100.00
Non-Logical00
Event00

 LINE       333
 EXPRESSION (sel_dp_i == DpReadSFDP)
            ------------1-----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT5,T7,T9

 LINE       340
 EXPRESSION (spi_mode_i == FlashMode)
            ------------1------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       371
 EXPRESSION ((main_st == MainOutput) && (sel_dp_i == DpReadCmd) && addr_latch_en && ( ! (mailbox_en_i && addr_q_in_mailbox) ) && spid_in_flashmode)
             -----------1-----------    -----------2-----------    ------3------    --------------------4--------------------    --------5--------
-1--2--3--4--5-StatusTests
01111CoveredT1,T2,T7
10111CoveredT7,T9,T15
11011CoveredT1,T2,T10
11101CoveredT2,T7,T9
11110CoveredT5,T8,T11
11111CoveredT1,T2,T10

 LINE       371
 SUB-EXPRESSION (main_st == MainOutput)
                -----------1-----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T5

 LINE       371
 SUB-EXPRESSION (sel_dp_i == DpReadCmd)
                -----------1-----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T5

 LINE       371
 SUB-EXPRESSION ( ! (mailbox_en_i && addr_q_in_mailbox) )
                    -----------------1-----------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT2,T5,T7

 LINE       371
 SUB-EXPRESSION (mailbox_en_i && addr_q_in_mailbox)
                 ------1-----    --------2--------
-1--2-StatusTests
01CoveredT3,T5,T6
10CoveredT1,T2,T5
11CoveredT2,T5,T7

 LINE       391
 EXPRESSION (addr_shift_en && s2p_valid_i)
             ------1------    -----2-----
-1--2-StatusTests
01CoveredT1,T2,T5
10CoveredT1,T2,T5
11CoveredT1,T2,T5

 LINE       404
 EXPRESSION (addr_cnt_d == 5'd2)
            ----------1---------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T5

 LINE       405
 EXPRESSION (addr_cnt_d == 5'b1)
            ----------1---------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T5

 LINE       408
 EXPRESSION (addr_cnt_d == 5'b0)
            ----------1---------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       443
 EXPRESSION ((cmdinfo_addr_mode == Addr4B) ? 5'd31 : 5'd23)
             --------------1--------------
-1-StatusTests
0CoveredT1,T5,T7
1CoveredT1,T2,T5

 LINE       443
 SUB-EXPRESSION (cmdinfo_addr_mode == Addr4B)
                --------------1--------------
-1-StatusTests
0CoveredT1,T5,T7
1CoveredT1,T2,T5

 LINE       445
 EXPRESSION (addr_cnt_q == '0)
            ---------1--------
-1-StatusTests
0CoveredT1,T2,T5
1CoveredT1,T2,T3

 LINE       500
 EXPRESSION (mailbox_masked_addr_d == mailbox_addr_i)
            --------------------1--------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       501
 EXPRESSION (mailbox_masked_addr_q == mailbox_addr_i)
            --------------------1--------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       514
 EXPRESSION (sram_req && mailbox_en_i && cfg_intercept_en_mbx_i && addr_d_in_mailbox)
             ----1---    ------2-----    -----------3----------    --------4--------
-1--2--3--4-StatusTests
0111CoveredT5,T7,T9
1011CoveredT5,T14,T27
1101CoveredT2,T7,T11
1110CoveredT1,T5,T7
1111CoveredT5,T7,T9

 LINE       517
 EXPRESSION (mailbox_en_i && cfg_intercept_en_mbx_i && addr_d_in_mailbox && (bitcnt == 3'b0))
             ------1-----    -----------2----------    --------3--------    --------4-------
-1--2--3--4-StatusTests
0111CoveredT5,T11,T14
1011CoveredT2,T7,T11
1101CoveredT1,T5,T7
1110CoveredT5,T7,T9
1111CoveredT5,T7,T9

 LINE       517
 SUB-EXPRESSION (bitcnt == 3'b0)
                --------1-------
-1-StatusTests
0CoveredT1,T2,T5
1CoveredT1,T2,T5

 LINE       521
 EXPRESSION (((!addr_d_in_mailbox)) && (bitcnt == 3'b0))
             -----------1----------    --------2-------
-1--2-StatusTests
01CoveredT2,T5,T7
10CoveredT1,T2,T5
11CoveredT1,T2,T5

 LINE       521
 SUB-EXPRESSION (bitcnt == 3'b0)
                --------1-------
-1-StatusTests
0CoveredT1,T2,T5
1CoveredT1,T2,T5

 LINE       565
 EXPRESSION ((main_st == MainOutput) && (addr_q[9:0] == '1))
             -----------1-----------    ---------2---------
-1--2-StatusTests
01CoveredT1,T10,T27
10CoveredT1,T2,T5
11CoveredT1,T5,T7

 LINE       565
 SUB-EXPRESSION (main_st == MainOutput)
                -----------1-----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T5

 LINE       565
 SUB-EXPRESSION (addr_q[9:0] == '1)
                ---------1---------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T5,T7

 LINE       691
 EXPRESSION (bitcnt == 3'b0)
            --------1-------
-1-StatusTests
0CoveredT1,T2,T5
1CoveredT1,T2,T5

 LINE       734
 EXPRESSION (sel_dp_i == DpReadSFDP)
            ------------1-----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT5,T7,T9

FSM Coverage for Module : spi_readcmd
Summary for FSM :: main_st
TotalCoveredPercent
States 5 4 80.00 (Not included in score)
Transitions 5 4 80.00
Sequences 0 0

State, Transition and Sequence Details for FSM :: main_st
statesLine No.CoveredTests
MainAddress 609 Covered T1,T2,T5
MainDummy 641 Covered T1,T2,T5
MainError 652 Not Covered
MainMByte 648 Excluded
MainOutput 634 Covered T1,T2,T5
MainReset 605 Covered T1,T2,T3


transitionsLine No.CoveredTests
MainAddress->MainDummy 641 Covered T1,T2,T5
MainAddress->MainError 652 Not Covered
MainAddress->MainMByte 648 Excluded
MainAddress->MainOutput 634 Covered T5,T7,T10
MainDummy->MainOutput 668 Covered T1,T2,T5
MainMByte->MainDummy 660 Excluded
MainReset->MainAddress 609 Covered T1,T2,T5



Branch Coverage for Module : spi_readcmd
Line No.TotalCoveredPercent
Branches 65 55 84.62
IF 353 3 3 100.00
IF 369 3 3 100.00
IF 384 5 5 100.00
IF 427 2 2 100.00
IF 436 5 4 80.00
IF 456 4 4 100.00
IF 469 10 8 80.00
IF 513 5 5 100.00
IF 534 2 2 100.00
IF 552 3 3 100.00
IF 575 2 2 100.00
CASE 604 21 14 66.67

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_spi_device_0.1/rtl/spi_readcmd.sv' or '../src/lowrisc_ip_spi_device_0.1/rtl/spi_readcmd.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 353 if ((!rst_ni)) -2-: 355 if (addr_latch_en)

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T1,T2,T5
0 0 Covered T1,T2,T5


LineNo. Expression -1-: 369 if ((!sys_rst_ni)) -2-: 371 if ((((((main_st == MainOutput) && (sel_dp_i == DpReadCmd)) && addr_latch_en) && (!(mailbox_en_i && addr_q_in_mailbox))) && spid_in_flashmode))

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T1,T2,T10
0 0 Covered T1,T2,T3


LineNo. Expression -1-: 384 if (addr_ready_in_word) -2-: 387 if (addr_ready_in_halfword) -3-: 391 if ((addr_shift_en && s2p_valid_i)) -4-: 395 if (addr_inc)

Branches:
-1--2--3--4-StatusTests
1 - - - Covered T1,T2,T5
0 1 - - Covered T1,T2,T5
0 0 1 - Covered T1,T2,T5
0 0 0 1 Covered T1,T2,T5
0 0 0 0 Covered T1,T2,T3


LineNo. Expression -1-: 427 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T5


LineNo. Expression -1-: 436 if (addr_cnt_set) -2-: 443 ((cmdinfo_addr_mode == Addr4B)) ? -3-: 445 if ((addr_cnt_q == '0)) -4-: 447 if (addr_shift_en)

Branches:
-1--2--3--4-StatusTests
1 1 - - Covered T1,T2,T5
1 0 - - Covered T1,T5,T7
0 - 1 - Covered T1,T2,T3
0 - 0 1 Covered T1,T2,T5
0 - 0 0 Not Covered


LineNo. Expression -1-: 456 if ((!rst_ni)) -2-: 458 if (load_dummycnt) -3-: 461 if ((!dummycnt_eq_zero))

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T2,T3
0 1 - Covered T1,T2,T5
0 0 1 Covered T1,T2,T5
0 0 0 Covered T1,T2,T5


LineNo. Expression -1-: 469 if ((!rst_ni)) -2-: 471 if (bitcnt_update) -3-: 472 case (cmd_info_i.payload_en) -4-: 478 if (bitcnt_dec) -5-: 479 case (cmd_info_i.payload_en)

Branches:
-1--2--3--4--5-StatusTests
1 - - - - Covered T1,T2,T3
0 1 4'b0010 - - Covered T1,T5,T7
0 1 4'b0011 - - Covered T1,T5,T7
0 1 4'b1111 - - Covered T1,T2,T5
0 1 default - - Not Covered
0 0 - 1 4'b0010 Covered T1,T5,T7
0 0 - 1 4'b0011 Covered T1,T5,T7
0 0 - 1 4'b1111 Covered T1,T2,T5
0 0 - 1 default Not Covered
0 0 - 0 - Covered T1,T2,T5


LineNo. Expression -1-: 513 if ((!rst_ni)) -2-: 514 if ((((sram_req && mailbox_en_i) && cfg_intercept_en_mbx_i) && addr_d_in_mailbox)) -3-: 517 if ((((mailbox_en_i && cfg_intercept_en_mbx_i) && addr_d_in_mailbox) && (bitcnt == 3'b0))) -4-: 521 if (((!addr_d_in_mailbox) && (bitcnt == 3'b0)))

Branches:
-1--2--3--4-StatusTests
1 - - - Covered T1,T2,T3
0 1 - - Covered T5,T7,T9
0 0 1 - Covered T5,T7,T9
0 0 0 1 Covered T1,T2,T5
0 0 0 0 Covered T1,T2,T5


LineNo. Expression -1-: 534 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T5


LineNo. Expression -1-: 552 if ((!sys_rst_ni)) -2-: 554 if (readbuf_flip)

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T1,T5,T7
0 0 Covered T1,T2,T3


LineNo. Expression -1-: 575 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T5


LineNo. Expression -1-: 604 case (main_st) -2-: 606 if ((sel_dp_i inside {DpReadCmd, DpReadSFDP})) -3-: 618 if (addr_ready_in_word) -4-: 622 if (addr_latched) -5-: 631 case ({cmd_info_i.mbyte_en, cmd_info_i.dummy_en}) -6-: 659 if (s2p_valid_i) -7-: 667 if (dummycnt_eq_zero) -8-: 684 case (cmd_info_i.payload_en) -9-: 691 if ((bitcnt == 3'b0))

Branches:
-1--2--3--4--5--6--7--8--9-StatusTests
MainReset 1 - - - - - - - Covered T1,T2,T5
MainReset 0 - - - - - - - Covered T1,T2,T3
MainAddress - 1 - - - - - - Covered T1,T2,T5
MainAddress - 0 - - - - - - Covered T1,T2,T5
MainAddress - - 1 2'b00 - - - - Covered T5,T7,T10
MainAddress - - 1 2'b01 - - - - Covered T1,T2,T5
MainAddress - - 1 2'b1z - - - - Not Covered
MainAddress - - 1 default - - - - Not Covered
MainAddress - - 0 - - - - - Covered T1,T2,T5
MainMByte - - - - 1 - - - Not Covered
MainMByte - - - - 0 - - - Not Covered
MainDummy - - - - - 1 - - Covered T1,T2,T5
MainDummy - - - - - 0 - - Covered T1,T2,T5
MainOutput - - - - - - 4'b0010 - Covered T1,T5,T7
MainOutput - - - - - - 4'b0011 - Covered T1,T5,T7
MainOutput - - - - - - 4'b1111 - Covered T1,T2,T5
MainOutput - - - - - - default - Not Covered
MainOutput - - - - - - - 1 Covered T1,T2,T5
MainOutput - - - - - - - 0 Covered T1,T2,T5
MainError - - - - - - - - Not Covered
default - - - - - - - - Not Covered


Assert Coverage for Module : spi_readcmd
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
AddrIncNotAssertInAddressState_A 381988954 11860710 0 0
MailboxSizeMatch_M 381988954 293578611 0 0
ValidCmdConfig_A 381988954 528208 0 0


AddrIncNotAssertInAddressState_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 381988954 11860710 0 0
T1 13408 3782 0 0
T2 39758 1925 0 0
T3 1325 0 0 0
T5 992277 38137 0 0
T6 360 0 0 0
T7 749009 10812 0 0
T8 181176 4344 0 0
T9 318604 2937 0 0
T10 19687 3552 0 0
T11 145674 72644 0 0
T12 0 10950 0 0
T13 0 256 0 0

MailboxSizeMatch_M
NameAttemptsReal SuccessesFailuresIncomplete
Total 381988954 293578611 0 0
T1 13408 13408 0 0
T2 39758 38698 0 0
T3 1325 0 0 0
T5 992277 973085 0 0
T6 360 0 0 0
T7 749009 687436 0 0
T8 181176 181176 0 0
T9 318604 262433 0 0
T10 19687 19687 0 0
T11 145674 130733 0 0
T12 0 127130 0 0
T13 0 115370 0 0

ValidCmdConfig_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 381988954 528208 0 0
T1 13408 200 0 0
T2 39758 124 0 0
T3 1325 0 0 0
T5 992277 1619 0 0
T6 360 0 0 0
T7 749009 1209 0 0
T8 181176 46 0 0
T9 318604 339 0 0
T10 19687 184 0 0
T11 145674 2349 0 0
T12 0 232 0 0
T13 0 46 0 0

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%