Module Definition
dashboard | hierarchy | modlist | groups | tests | asserts

Module : spi_cmdparse
SCORELINECONDTOGGLEFSMBRANCHASSERT
96.74 100.00 87.80 100.00 95.92 100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_spi_device_0.1/rtl/spi_cmdparse.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.u_cmdparse 96.74 100.00 87.80 100.00 95.92 100.00



Module Instance : tb.dut.u_cmdparse

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
96.74 100.00 87.80 100.00 95.92 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
96.74 100.00 87.80 100.00 95.92 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
91.69 94.25 84.31 96.94 87.50 95.45 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Since this is the module's only instance, the coverage report is the same as for the module.
Line Coverage for Module : spi_cmdparse
Line No.TotalCoveredPercent
TOTAL108108100.00
CONT_ASSIGN8111100.00
ALWAYS8633100.00
CONT_ASSIGN15211100.00
CONT_ASSIGN15611100.00
ALWAYS18144100.00
CONT_ASSIGN19011100.00
CONT_ASSIGN19211100.00
CONT_ASSIGN19411100.00
CONT_ASSIGN19611100.00
CONT_ASSIGN19811100.00
CONT_ASSIGN20011100.00
ALWAYS20444100.00
ALWAYS21466100.00
ALWAYS22977100.00
CONT_ASSIGN24911100.00
CONT_ASSIGN25011100.00
ALWAYS25955100.00
CONT_ASSIGN27511100.00
ALWAYS2791111100.00
CONT_ASSIGN29111100.00
CONT_ASSIGN29811100.00
CONT_ASSIGN29911100.00
CONT_ASSIGN30011100.00
ALWAYS30344100.00
ALWAYS3114848100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_spi_device_0.1/rtl/spi_cmdparse.sv' or '../src/lowrisc_ip_spi_device_0.1/rtl/spi_cmdparse.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
81 1 1
86 1 1
87 1 1
88 1 1
152 1 1
156 1 1
181 1 1
182 1 1
183 1 1
185 1 1
MISSING_ELSE
190 1 1
192 1 1
194 1 1
196 1 1
198 1 1
200 1 1
204 1 1
205 1 1
206 1 1
207 1 1
MISSING_ELSE
214 1 1
215 1 1
221 1 1
222 1 1
223 1 1
224 1 1
MISSING_ELSE
229 1 1
235 1 1
236 1 1
237 1 1
238 1 1
239 1 1
240 1 1
MISSING_ELSE
MISSING_ELSE
249 1 1
250 1 1
259 1 1
265 1 1
267 1 1
268 1 1
269 1 1
MISSING_ELSE
275 1 1
279 1 1
280 1 1
281 1 1
282 1 1
283 1 1
284 2 2
MISSING_ELSE
285 2 2
MISSING_ELSE
286 2 2
MISSING_ELSE
MISSING_ELSE
291 1 1
298 1 1
299 1 1
300 1 1
303 1 1
304 1 1
305 1 1
306 1 1
==> MISSING_ELSE
311 1 1
313 1 1
314 1 1
316 1 1
317 1 1
319 1 1
321 1 1
323 1 1
325 1 1
326 1 1
328 1 1
330 1 1
331 1 1
332 1 1
333 1 1
334 1 1
336 1 1
341 1 1
342 1 1
343 1 1
344 1 1
345 1 1
347 1 1
353 1 1
354 1 1
355 1 1
356 1 1
357 1 1
360 1 1
368 1 1
372 1 1
373 1 1
377 1 1
380 1 1
384 1 1
387 1 1
397 1 1
399 1 1
400 1 1
MISSING_ELSE
405 1 1
407 1 1
409 1 1
411 1 1
413 1 1
415 1 1
417 1 1
420 1 1
422 1 1


Cond Coverage for Module : spi_cmdparse
TotalCoveredPercent
Conditions827287.80
Logical827287.80
Non-Logical00
Event00

 LINE       183
 EXPRESSION (cmd_info_i[(CmdInfoReadStatus1 + i)].valid && (data_i == cmd_info_i[(CmdInfoReadStatus1 + i)].opcode))
             ---------------------1--------------------    ---------------------------2---------------------------
-1--2-StatusTests
01CoveredT2,T3,T5
10CoveredT1,T2,T5
11CoveredT1,T2,T5

 LINE       183
 SUB-EXPRESSION (data_i == cmd_info_i[(CmdInfoReadStatus1 + i)].opcode)
                ---------------------------1---------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       190
 EXPRESSION (cmd_info_i[CmdInfoReadJedecId].valid && (data_i == cmd_info_i[CmdInfoReadJedecId].opcode))
             ------------------1-----------------    ------------------------2------------------------
-1--2-StatusTests
01CoveredT2,T3,T5
10CoveredT1,T5,T7
11CoveredT1,T5,T7

 LINE       190
 SUB-EXPRESSION (data_i == cmd_info_i[CmdInfoReadJedecId].opcode)
                ------------------------1------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       192
 EXPRESSION (cmd_info_i[CmdInfoReadSfdp].valid && (data_i == cmd_info_i[CmdInfoReadSfdp].opcode))
             ----------------1----------------    -----------------------2----------------------
-1--2-StatusTests
01CoveredT3,T5,T6
10CoveredT1,T2,T5
11CoveredT1,T2,T5

 LINE       192
 SUB-EXPRESSION (data_i == cmd_info_i[CmdInfoReadSfdp].opcode)
                -----------------------1----------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       194
 EXPRESSION (cmd_info_i[CmdInfoEn4B].valid && (data_i == cmd_info_i[CmdInfoEn4B].opcode))
             --------------1--------------    ---------------------2--------------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT5,T7,T9
11CoveredT5,T7,T9

 LINE       194
 SUB-EXPRESSION (data_i == cmd_info_i[CmdInfoEn4B].opcode)
                ---------------------1--------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       196
 EXPRESSION (cmd_info_i[CmdInfoEx4B].valid && (data_i == cmd_info_i[CmdInfoEx4B].opcode))
             --------------1--------------    ---------------------2--------------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT5,T7,T9
11CoveredT5,T7,T9

 LINE       196
 SUB-EXPRESSION (data_i == cmd_info_i[CmdInfoEx4B].opcode)
                ---------------------1--------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       198
 EXPRESSION (cmd_info_i[CmdInfoWrEn].valid && (data_i == cmd_info_i[CmdInfoWrEn].opcode))
             --------------1--------------    ---------------------2--------------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT5,T7,T9
11CoveredT5,T7,T9

 LINE       198
 SUB-EXPRESSION (data_i == cmd_info_i[CmdInfoWrEn].opcode)
                ---------------------1--------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       200
 EXPRESSION (cmd_info_i[CmdInfoWrDi].valid && (data_i == cmd_info_i[CmdInfoWrDi].opcode))
             --------------1--------------    ---------------------2--------------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT5,T7,T9
11CoveredT5,T7,T9

 LINE       200
 SUB-EXPRESSION (data_i == cmd_info_i[CmdInfoWrDi].opcode)
                ---------------------1--------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       206
 EXPRESSION (cmd_info_i[i].valid && (data_i == cmd_info_i[i].opcode))
             ---------1---------    ----------------2---------------
-1--2-StatusTests
01CoveredT2,T3,T5
10CoveredT1,T2,T5
11CoveredT1,T2,T5

 LINE       206
 SUB-EXPRESSION (data_i == cmd_info_i[i].opcode)
                ----------------1---------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       236
 EXPRESSION ((st == StIdle) && module_active && data_valid_i)
             -------1------    ------2------    ------3-----
-1--2--3-StatusTests
011CoveredT1,T2,T5
101Not Covered
110CoveredT1,T2,T3
111CoveredT1,T2,T5

 LINE       236
 SUB-EXPRESSION (st == StIdle)
                -------1------
-1-StatusTests
0CoveredT1,T2,T5
1CoveredT1,T2,T3

 LINE       238
 EXPRESSION (cmd_info_i[i].valid && (data_i == cmd_info_i[i].opcode))
             ---------1---------    ----------------2---------------
-1--2-StatusTests
01CoveredT2,T12,T13
10CoveredT1,T2,T5
11CoveredT1,T2,T5

 LINE       238
 SUB-EXPRESSION (data_i == cmd_info_i[i].opcode)
                ----------------1---------------
-1-StatusTests
0CoveredT1,T2,T5
1CoveredT1,T2,T5

 LINE       267
 EXPRESSION ((st == StIdle) && module_active && data_valid_i)
             -------1------    ------2------    ------3-----
-1--2--3-StatusTests
011CoveredT1,T2,T5
101Not Covered
110CoveredT1,T2,T3
111CoveredT1,T2,T5

 LINE       267
 SUB-EXPRESSION (st == StIdle)
                -------1------
-1-StatusTests
0CoveredT1,T2,T5
1CoveredT1,T2,T3

 LINE       291
 EXPRESSION ((cmd_info_q.read_pipeline_mode == RdPipeTwoStageHalfCycle) || (cmd_info_q.read_pipeline_mode == RdPipeTwoStageFullCycle))
             -----------------------------1----------------------------    -----------------------------2----------------------------
-1--2-StatusTests
00CoveredT1,T2,T3
01Not Covered
10Not Covered

 LINE       291
 SUB-EXPRESSION (cmd_info_q.read_pipeline_mode == RdPipeTwoStageHalfCycle)
                -----------------------------1----------------------------
-1-StatusTests
0CoveredT1,T2,T3
1Not Covered

 LINE       291
 SUB-EXPRESSION (cmd_info_q.read_pipeline_mode == RdPipeTwoStageFullCycle)
                -----------------------------1----------------------------
-1-StatusTests
0CoveredT1,T2,T3
1Not Covered

 LINE       298
 EXPRESSION (spi_mode_i == FlashMode)
            ------------1------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       299
 EXPRESSION (spi_mode_i == PassThrough)
            -------------1-------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT5,T8,T11

 LINE       300
 EXPRESSION (in_flashmode || in_passthrough)
             ------1-----    -------2------
-1--2-StatusTests
00Not Covered
01CoveredT5,T8,T11
10CoveredT1,T2,T3

 LINE       323
 EXPRESSION (module_active && data_valid_i && cmd_info_d.valid)
             ------1------    ------2-----    --------3-------
-1--2--3-StatusTests
011Not Covered
101Not Covered
110CoveredT2,T5,T7
111CoveredT1,T2,T5

 LINE       380
 EXPRESSION (opcode_en4b ? DpEn4B : DpEx4B)
             -----1-----
-1-StatusTests
0CoveredT5,T7,T9
1CoveredT5,T7,T9

 LINE       387
 EXPRESSION (opcode_wren ? DpWrEn : DpWrDi)
             -----1-----
-1-StatusTests
0CoveredT5,T7,T9
1CoveredT5,T7,T9

 LINE       397
 EXPRESSION (module_active && data_valid_i)
             ------1------    ------2-----
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11CoveredT2,T5,T7

FSM Coverage for Module : spi_cmdparse
Summary for FSM :: st
TotalCoveredPercent
States 9 9 100.00 (Not included in score)
Transitions 8 8 100.00
Sequences 0 0

State, Transition and Sequence Details for FSM :: st
statesLine No.CoveredTests
StAddr4B 377 Covered T5,T7,T9
StIdle 236 Covered T1,T2,T3
StJedec 342 Covered T5,T7,T9
StReadCmd 368 Covered T1,T2,T5
StSfdp 354 Covered T5,T7,T9
StStatus 331 Covered T5,T7,T9
StUpload 372 Covered T5,T7,T9
StWait 336 Covered T2,T5,T7
StWrEn 384 Covered T5,T7,T9


transitionsLine No.CoveredTests
StIdle->StAddr4B 377 Covered T5,T7,T9
StIdle->StJedec 342 Covered T5,T7,T9
StIdle->StReadCmd 368 Covered T1,T2,T5
StIdle->StSfdp 354 Covered T5,T7,T9
StIdle->StStatus 331 Covered T5,T7,T9
StIdle->StUpload 372 Covered T5,T7,T9
StIdle->StWait 336 Covered T2,T5,T7
StIdle->StWrEn 384 Covered T5,T7,T9



Branch Coverage for Module : spi_cmdparse
Line No.TotalCoveredPercent
Branches 49 47 95.92
IF 183 2 2 100.00
IF 206 2 2 100.00
IF 214 3 3 100.00
IF 236 2 2 100.00
IF 267 2 2 100.00
IF 279 8 8 100.00
IF 303 3 2 66.67
CASE 321 27 26 96.30

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_spi_device_0.1/rtl/spi_cmdparse.sv' or '../src/lowrisc_ip_spi_device_0.1/rtl/spi_cmdparse.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 183 if ((cmd_info_i[(CmdInfoReadStatus1 + i)].valid && (data_i == cmd_info_i[(CmdInfoReadStatus1 + i)].opcode)))

Branches:
-1-StatusTests
1 Covered T1,T2,T5
0 Covered T1,T2,T3


LineNo. Expression -1-: 206 if ((cmd_info_i[i].valid && (data_i == cmd_info_i[i].opcode)))

Branches:
-1-StatusTests
1 Covered T1,T2,T5
0 Covered T1,T2,T3


LineNo. Expression -1-: 214 if ((!rst_ni)) -2-: 222 if (latch_cmdinfo)

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T1,T2,T5
0 0 Covered T1,T2,T5


LineNo. Expression -1-: 236 if ((((st == StIdle) && module_active) && data_valid_i))

Branches:
-1-StatusTests
1 Covered T1,T2,T5
0 Covered T1,T2,T3


LineNo. Expression -1-: 267 if ((((st == StIdle) && module_active) && data_valid_i))

Branches:
-1-StatusTests
1 Covered T1,T2,T5
0 Covered T1,T2,T3


LineNo. Expression -1-: 279 if ((!rst_ni)) -2-: 283 if (intercept_d) -3-: 284 if (opcode_readstatus) -4-: 285 if (opcode_readjedec) -5-: 286 if (opcode_readsfdp)

Branches:
-1--2--3--4--5-StatusTests
1 - - - - Covered T1,T2,T3
0 1 1 - - Covered T5,T11,T14
0 1 0 - - Covered T5,T11,T14
0 1 - 1 - Covered T5,T11,T14
0 1 - 0 - Covered T5,T11,T14
0 1 - - 1 Covered T5,T11,T14
0 1 - - 0 Covered T5,T11,T14
0 0 - - - Covered T1,T2,T5


LineNo. Expression -1-: 303 if ((!rst_ni)) -2-: 305 if (module_active)

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T1,T2,T5
0 0 Not Covered


LineNo. Expression -1-: 321 case (st) -2-: 323 if (((module_active && data_valid_i) && cmd_info_d.valid)) -3-: 328 case (1'b1) -4-: 330 if (in_flashmode) -5-: 332 if (cfg_intercept_en_status_i) -6-: 341 if (in_flashmode) -7-: 343 if (cfg_intercept_en_jedec_i) -8-: 353 if (in_flashmode) -9-: 355 if (cfg_intercept_en_sfdp_i) -10-: 380 (opcode_en4b) ? -11-: 387 (opcode_wren) ? -12-: 397 if ((module_active && data_valid_i))

Branches:
-1--2--3--4--5--6--7--8--9--10--11--12-StatusTests
StIdle 1 opcode_readstatus 1 - - - - - - - - Covered T7,T9,T15
StIdle 1 opcode_readstatus 0 1 - - - - - - - Covered T5,T11,T14
StIdle 1 opcode_readstatus 0 0 - - - - - - - Covered T8,T12,T13
StIdle 1 opcode_readjedec - - 1 - - - - - - Covered T7,T9,T15
StIdle 1 opcode_readjedec - - 0 1 - - - - - Covered T5,T11,T14
StIdle 1 opcode_readjedec - - 0 0 - - - - - Covered T5,T11,T14
StIdle 1 opcode_readsfdp - - - - 1 - - - - Covered T7,T9,T15
StIdle 1 opcode_readsfdp - - - - 0 1 - - - Covered T5,T11,T14
StIdle 1 opcode_readsfdp - - - - 0 0 - - - Covered T5,T11,T13
StIdle 1 opcode_readcmd - - - - - - - - - Covered T1,T2,T5
StIdle 1 upload - - - - - - - - - Covered T5,T7,T9
StIdle 1 opcode_en4b opcode_ex4b - - - - - - 1 - - Covered T5,T7,T9
StIdle 1 opcode_en4b opcode_ex4b - - - - - - 0 - - Covered T5,T7,T9
StIdle 1 opcode_wren opcode_wrdi - - - - - - - 1 - Covered T5,T7,T9
StIdle 1 opcode_wren opcode_wrdi - - - - - - - 0 - Covered T5,T7,T9
StIdle 1 default - - - - - - - - - Covered T5,T7,T8
StIdle 0 - - - - - - - - - 1 Covered T2,T5,T7
StIdle 0 - - - - - - - - - 0 Covered T1,T2,T3
StStatus - - - - - - - - - - - Covered T5,T7,T9
StJedec - - - - - - - - - - - Covered T5,T7,T9
StSfdp - - - - - - - - - - - Covered T5,T7,T9
StReadCmd - - - - - - - - - - - Covered T1,T2,T5
StUpload - - - - - - - - - - - Covered T5,T7,T9
StAddr4B - - - - - - - - - - - Covered T5,T7,T9
StWrEn - - - - - - - - - - - Covered T5,T7,T9
StWait - - - - - - - - - - - Covered T2,T5,T7
default - - - - - - - - - - - Not Covered


Assert Coverage for Module : spi_cmdparse
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 4 4 100.00 4 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 4 4 100.00 4 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
CmdOnlySelDpKnown_A 381988954 293578611 0 0
OnlyOneDatapath_A 381988954 144050 0 0
SelDpKnown_A 381988954 293578611 0 0
StKnown_A 381988954 293578611 0 0


CmdOnlySelDpKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 381988954 293578611 0 0
T1 13408 13408 0 0
T2 39758 38698 0 0
T3 1325 0 0 0
T5 992277 973085 0 0
T6 360 0 0 0
T7 749009 687436 0 0
T8 181176 181176 0 0
T9 318604 262433 0 0
T10 19687 19687 0 0
T11 145674 130733 0 0
T12 0 127130 0 0
T13 0 115370 0 0

OnlyOneDatapath_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 381988954 144050 0 0
T1 13408 8 0 0
T2 39758 23 0 0
T3 1325 0 0 0
T5 992277 497 0 0
T6 360 0 0 0
T7 749009 652 0 0
T8 181176 30 0 0
T9 318604 156 0 0
T10 19687 8 0 0
T11 145674 720 0 0
T12 0 24 0 0
T13 0 36 0 0

SelDpKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 381988954 293578611 0 0
T1 13408 13408 0 0
T2 39758 38698 0 0
T3 1325 0 0 0
T5 992277 973085 0 0
T6 360 0 0 0
T7 749009 687436 0 0
T8 181176 181176 0 0
T9 318604 262433 0 0
T10 19687 19687 0 0
T11 145674 130733 0 0
T12 0 127130 0 0
T13 0 115370 0 0

StKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 381988954 293578611 0 0
T1 13408 13408 0 0
T2 39758 38698 0 0
T3 1325 0 0 0
T5 992277 973085 0 0
T6 360 0 0 0
T7 749009 687436 0 0
T8 181176 181176 0 0
T9 318604 262433 0 0
T10 19687 19687 0 0
T11 145674 130733 0 0
T12 0 127130 0 0
T13 0 115370 0 0

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%