Module Definition
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Module : prim_rst_sync
SCORELINECONDTOGGLEFSMBRANCHASSERT
50.00 50.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_rst_sync_0/rtl/prim_rst_sync.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.u_tpm_csb_rst_sync 50.00 50.00



Module Instance : tb.dut.u_tpm_csb_rst_sync

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
50.00 50.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
70.83 88.89 44.44 100.00 50.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
91.69 94.25 84.31 96.94 87.50 95.45 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
g_scan_mux.u_scan_mux 64.81 100.00 44.44 50.00
u_sync 100.00 100.00 100.00


Since this is the module's only instance, the coverage report is the same as for the module.
Line Coverage for Module : prim_rst_sync
Line No.TotalCoveredPercent
TOTAL2150.00
CONT_ASSIGN3511100.00
CONT_ASSIGN36100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_rst_sync_0/rtl/prim_rst_sync.sv' or '../src/lowrisc_prim_rst_sync_0/rtl/prim_rst_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
35 1 1
36 0 1

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%