Unified Coverage Report :: Module :: spid_fifo2sram_adapter

Module : spid_fifo2sram_adapter

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.87	100.00	79.49			100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_spi_device_0.1/rtl/spid_fifo2sram_adapter.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_spi_tpm.u_tpm_rd_buffer	89.74	100.00	69.23			100.00
tb.dut.u_upload.u_payload_buffer	96.15	100.00	84.62			100.00	100.00
tb.dut.u_spi_tpm.u_tpm_wr_buffer	96.15	100.00	84.62			100.00	100.00

---

Module Instance : tb.dut.u_spi_tpm.u_tpm_rd_buffer

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
89.74	100.00	69.23			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
89.74	100.00	69.23			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.66	99.29	91.20		91.67	96.13	100.00	u_spi_tpm

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_upload.u_payload_buffer

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.15	100.00	84.62			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.15	100.00	84.62			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.37	100.00	86.11		100.00	95.74	100.00	u_upload

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_spi_tpm.u_tpm_wr_buffer

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.15	100.00	84.62			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.15	100.00	84.62			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.66	99.29	91.20		91.67	96.13	100.00	u_spi_tpm

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : spid_fifo2sram_adapter ( parameter FifoWidth=8,FifoDepth=256,SramAw=10,SramDw=32,SramBaseAddr=896,EnPack=1,FifoPtrW=8,NumEntryPerWord=4,g_multiple_entry_per_word.SubWordW=2 )
Line Coverage for Module self-instances :

SCORE	LINE
96.15	100.00

tb.dut.u_upload.u_payload_buffer

	Line No.	Total	Covered	Percent
TOTAL		18	18	100.00
CONT_ASSIGN	52	1	1	100.00
CONT_ASSIGN	56	1	1	100.00
CONT_ASSIGN	57	1	1	100.00
CONT_ASSIGN	62	1	1	100.00
CONT_ASSIGN	73	1	1	100.00
ALWAYS	76	6	6	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	97	5	5	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_spi_device_0.1/rtl/spid_fifo2sram_adapter.sv' or '../src/lowrisc_ip_spi_device_0.1/rtl/spid_fifo2sram_adapter.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
52	1	1
56	1	1
57	1	1
62	1	1
73	1	1
76	1	1
77	1	1
78	1	1
79	1	1
80	1	1
81	1	1
			MISSING_ELSE
92	1	1
94	1	1
97	1	1
98	1	1
99	1	1
100		unreachable
101	1	1
102	1	1
			MISSING_ELSE

---

Line Coverage for Module : spid_fifo2sram_adapter ( parameter FifoWidth=8,FifoDepth=64,SramAw=10,SramDw=32,SramBaseAddr=992,EnPack=1,FifoPtrW=6,NumEntryPerWord=4,g_multiple_entry_per_word.SubWordW=2 )
Line Coverage for Module self-instances :

SCORE	LINE
96.15	100.00

tb.dut.u_spi_tpm.u_tpm_wr_buffer

	Line No.	Total	Covered	Percent
TOTAL		18	18	100.00
CONT_ASSIGN	52	1	1	100.00
CONT_ASSIGN	56	1	1	100.00
CONT_ASSIGN	57	1	1	100.00
CONT_ASSIGN	62	1	1	100.00
CONT_ASSIGN	73	1	1	100.00
ALWAYS	76	6	6	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	97	5	5	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_spi_device_0.1/rtl/spid_fifo2sram_adapter.sv' or '../src/lowrisc_ip_spi_device_0.1/rtl/spid_fifo2sram_adapter.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
52	1	1
56	1	1
57	1	1
62	1	1
73	1	1
76	1	1
77	1	1
78	1	1
79	1	1
80	1	1
81	1	1
			MISSING_ELSE
92	1	1
94	1	1
97	1	1
98	1	1
99	1	1
100		unreachable
101	1	1
102	1	1
			MISSING_ELSE

---

Line Coverage for Module : spid_fifo2sram_adapter ( parameter FifoWidth=32,FifoDepth=16,SramAw=10,SramDw=32,SramBaseAddr=832,EnPack=1,FifoPtrW=4,NumEntryPerWord=1 )
Line Coverage for Module self-instances :

SCORE	LINE
89.74	100.00

tb.dut.u_spi_tpm.u_tpm_rd_buffer

	Line No.	Total	Covered	Percent
TOTAL		14	14	100.00
CONT_ASSIGN	52	1	1	100.00
CONT_ASSIGN	56	1	1	100.00
CONT_ASSIGN	57	1	1	100.00
CONT_ASSIGN	62	1	1	100.00
CONT_ASSIGN	87	1	1	100.00
CONT_ASSIGN	88	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	97	6	6	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_spi_device_0.1/rtl/spid_fifo2sram_adapter.sv' or '../src/lowrisc_ip_spi_device_0.1/rtl/spid_fifo2sram_adapter.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
52	1	1
56	1	1
57	1	1
62	1	1
87	1	1
88	1	1
92	1	1
94	1	1
97	1	1
98	1	1
99	1	1
100	1	1
101	1	1
102	1	1
			MISSING_ELSE

---

Cond Coverage for Module : spid_fifo2sram_adapter ( parameter FifoWidth=8,FifoDepth=256,SramAw=10,SramDw=32,SramBaseAddr=896,EnPack=1,FifoPtrW=8,NumEntryPerWord=4,g_multiple_entry_per_word.SubWordW=2 )
Cond Coverage for Module self-instances :

SCORE	COND
96.15	84.62

tb.dut.u_upload.u_payload_buffer

	Total	Covered	Percent
Conditions	13	11	84.62
Logical	13	11	84.62
Non-Logical	0	0
Event	0	0

 LINE       56
 EXPRESSION (wvalid_i & ((!clr_i)))
             ----1---   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Covered	T5,T7,T9

 LINE       57
 EXPRESSION (sram_gnt_i & ((!clr_i)))
             -----1----   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Covered	T5,T7,T9

 LINE       79
 EXPRESSION (fifoptr[0+:g_multiple_entry_per_word.SubWordW] == i)
            --------------------------1--------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       92
 EXPRESSION (sram_req_o && sram_gnt_i)
             -----1----    -----2----

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Covered	T5,T7,T9

 LINE       102
 EXPRESSION ((fifoptr == 8'((FifoDepth - 1))) ? '0 : ((fifoptr + 1'b1)))
             ----------------1---------------

-1-	Status	Tests
0	Covered	T5,T7,T9
1	Covered	T5,T7,T11

 LINE       102
 SUB-EXPRESSION (fifoptr == 8'((FifoDepth - 1)))
                ----------------1---------------

-1-	Status	Tests
0	Covered	T5,T7,T9
1	Covered	T5,T7,T11

---

Cond Coverage for Module : spid_fifo2sram_adapter ( parameter FifoWidth=8,FifoDepth=64,SramAw=10,SramDw=32,SramBaseAddr=992,EnPack=1,FifoPtrW=6,NumEntryPerWord=4,g_multiple_entry_per_word.SubWordW=2 )
Cond Coverage for Module self-instances :

SCORE	COND
96.15	84.62

tb.dut.u_spi_tpm.u_tpm_wr_buffer

	Total	Covered	Percent
Conditions	13	11	84.62
Logical	13	11	84.62
Non-Logical	0	0
Event	0	0

 LINE       56
 EXPRESSION (wvalid_i & ((!clr_i)))
             ----1---   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Covered	T5,T7,T9

 LINE       57
 EXPRESSION (sram_gnt_i & ((!clr_i)))
             -----1----   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Covered	T5,T7,T9

 LINE       79
 EXPRESSION (fifoptr[0+:g_multiple_entry_per_word.SubWordW] == i)
            --------------------------1--------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       92
 EXPRESSION (sram_req_o && sram_gnt_i)
             -----1----    -----2----

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Covered	T5,T7,T9

 LINE       102
 EXPRESSION ((fifoptr == 6'((FifoDepth - 1))) ? '0 : ((fifoptr + 1'b1)))
             ----------------1---------------

-1-	Status	Tests
0	Covered	T5,T7,T9
1	Covered	T5,T7,T9

 LINE       102
 SUB-EXPRESSION (fifoptr == 6'((FifoDepth - 1)))
                ----------------1---------------

-1-	Status	Tests
0	Covered	T5,T7,T9
1	Covered	T5,T7,T9

---

Cond Coverage for Module : spid_fifo2sram_adapter ( parameter FifoWidth=32,FifoDepth=16,SramAw=10,SramDw=32,SramBaseAddr=832,EnPack=1,FifoPtrW=4,NumEntryPerWord=1 )
Cond Coverage for Module self-instances :

SCORE	COND
89.74	69.23

tb.dut.u_spi_tpm.u_tpm_rd_buffer

	Total	Covered	Percent
Conditions	13	9	69.23
Logical	13	9	69.23
Non-Logical	0	0
Event	0	0

 LINE       56
 EXPRESSION (wvalid_i & ((!clr_i)))
             ----1---   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T5,T7,T9
1	0	Not Covered
1	1	Covered	T5,T7,T9

 LINE       57
 EXPRESSION (sram_gnt_i & ((!clr_i)))
             -----1----   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T5,T7,T9
1	0	Not Covered
1	1	Covered	T5,T7,T9

 LINE       92
 EXPRESSION (sram_req_o && sram_gnt_i)
             -----1----    -----2----

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Covered	T5,T7,T9

 LINE       102
 EXPRESSION ((fifoptr == 4'((FifoDepth - 1))) ? '0 : ((fifoptr + 1'b1)))
             ----------------1---------------

-1-	Status	Tests
0	Covered	T5,T7,T9
1	Covered	T5,T7,T9

 LINE       102
 SUB-EXPRESSION (fifoptr == 4'((FifoDepth - 1)))
                ----------------1---------------

-1-	Status	Tests
0	Covered	T5,T7,T9
1	Covered	T5,T7,T9

---

Branch Coverage for Module : spid_fifo2sram_adapter ( parameter FifoWidth=8,FifoDepth=256,SramAw=10,SramDw=32,SramBaseAddr=896,EnPack=1,FifoPtrW=8,NumEntryPerWord=4,g_multiple_entry_per_word.SubWordW=2 )
Branch Coverage for Module self-instances :

SCORE	BRANCH
96.15	100.00

tb.dut.u_upload.u_payload_buffer

	Line No.	Total	Covered	Percent
Branches		6	6	100.00
IF	97	4	4	100.00
IF	79	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_spi_device_0.1/rtl/spid_fifo2sram_adapter.sv' or '../src/lowrisc_ip_spi_device_0.1/rtl/spid_fifo2sram_adapter.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	97	if ((!rst_ni))
-2-:	99	if (clr_i)
-3-:	101	if (fifoptr_inc)
-4-:	102	((fifoptr == 8'((FifoDepth - 1)))) ? 

Branches:

-1-	-2-	-3-	-4-	Status	Tests
1	-	-	-	Covered	T1,T2,T3
0	1	-	-	Unreachable
0	0	1	1	Covered	T5,T7,T11
0	0	1	0	Covered	T5,T7,T9
0	0	0	-	Covered	T1,T2,T5

	LineNo.	Expression
-1-:	79	if ((fifoptr[0+:g_multiple_entry_per_word.SubWordW] == i))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Branch Coverage for Module : spid_fifo2sram_adapter ( parameter FifoWidth=8,FifoDepth=64,SramAw=10,SramDw=32,SramBaseAddr=992,EnPack=1,FifoPtrW=6,NumEntryPerWord=4,g_multiple_entry_per_word.SubWordW=2 )
Branch Coverage for Module self-instances :

SCORE	BRANCH
96.15	100.00

tb.dut.u_spi_tpm.u_tpm_wr_buffer

	Line No.	Total	Covered	Percent
Branches		6	6	100.00
IF	97	4	4	100.00
IF	79	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_spi_device_0.1/rtl/spid_fifo2sram_adapter.sv' or '../src/lowrisc_ip_spi_device_0.1/rtl/spid_fifo2sram_adapter.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	97	if ((!rst_ni))
-2-:	99	if (clr_i)
-3-:	101	if (fifoptr_inc)
-4-:	102	((fifoptr == 6'((FifoDepth - 1)))) ? 

Branches:

-1-	-2-	-3-	-4-	Status	Tests
1	-	-	-	Covered	T1,T2,T3
0	1	-	-	Unreachable
0	0	1	1	Covered	T5,T7,T9
0	0	1	0	Covered	T5,T7,T9
0	0	0	-	Covered	T3,T5,T6

	LineNo.	Expression
-1-:	79	if ((fifoptr[0+:g_multiple_entry_per_word.SubWordW] == i))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Branch Coverage for Module : spid_fifo2sram_adapter ( parameter FifoWidth=32,FifoDepth=16,SramAw=10,SramDw=32,SramBaseAddr=832,EnPack=1,FifoPtrW=4,NumEntryPerWord=1 )
Branch Coverage for Module self-instances :

SCORE	BRANCH
89.74	100.00

tb.dut.u_spi_tpm.u_tpm_rd_buffer

	Line No.	Total	Covered	Percent
Branches		5	5	100.00
IF	97	5	5	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_spi_device_0.1/rtl/spid_fifo2sram_adapter.sv' or '../src/lowrisc_ip_spi_device_0.1/rtl/spid_fifo2sram_adapter.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	97	if ((!rst_ni))
-2-:	99	if (clr_i)
-3-:	101	if (fifoptr_inc)
-4-:	102	((fifoptr == 4'((FifoDepth - 1)))) ? 

Branches:

-1-	-2-	-3-	-4-	Status	Tests
1	-	-	-	Covered	T1,T2,T3
0	1	-	-	Covered	T1,T2,T3
0	0	1	1	Covered	T5,T7,T9
0	0	1	0	Covered	T5,T7,T9
0	0	0	-	Covered	T5,T7,T9

---

Assert Coverage for Module : spid_fifo2sram_adapter

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
g_multiple_entry_per_word.NumEntryPerWordPowerOf2_A	3704	3704	0	0
g_multiple_entry_per_word.WidthDivideSramDw_A	3704	3704	0	0

g_multiple_entry_per_word.NumEntryPerWordPowerOf2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	3704	3704	0	0
T1	2	2	0	0
T2	2	2	0	0
T3	2	2	0	0
T4	2	2	0	0
T5	2	2	0	0
T6	2	2	0	0
T7	2	2	0	0
T8	2	2	0	0
T9	2	2	0	0
T10	2	2	0	0

g_multiple_entry_per_word.WidthDivideSramDw_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	3704	3704	0	0
T1	2	2	0	0
T2	2	2	0	0
T3	2	2	0	0
T4	2	2	0	0
T5	2	2	0	0
T6	2	2	0	0
T7	2	2	0	0
T8	2	2	0	0
T9	2	2	0	0
T10	2	2	0	0

Line Coverage for Instance : tb.dut.u_spi_tpm.u_tpm_rd_buffer

	Line No.	Total	Covered	Percent
TOTAL		14	14	100.00
CONT_ASSIGN	52	1	1	100.00
CONT_ASSIGN	56	1	1	100.00
CONT_ASSIGN	57	1	1	100.00
CONT_ASSIGN	62	1	1	100.00
CONT_ASSIGN	87	1	1	100.00
CONT_ASSIGN	88	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	97	6	6	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_spi_device_0.1/rtl/spid_fifo2sram_adapter.sv' or '../src/lowrisc_ip_spi_device_0.1/rtl/spid_fifo2sram_adapter.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
52	1	1
56	1	1
57	1	1
62	1	1
87	1	1
88	1	1
92	1	1
94	1	1
97	1	1
98	1	1
99	1	1
100	1	1
101	1	1
102	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_spi_tpm.u_tpm_rd_buffer

	Total	Covered	Percent
Conditions	13	9	69.23
Logical	13	9	69.23
Non-Logical	0	0
Event	0	0

 LINE       56
 EXPRESSION (wvalid_i & ((!clr_i)))
             ----1---   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T5,T7,T9
1	0	Not Covered
1	1	Covered	T5,T7,T9

 LINE       57
 EXPRESSION (sram_gnt_i & ((!clr_i)))
             -----1----   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T5,T7,T9
1	0	Not Covered
1	1	Covered	T5,T7,T9

 LINE       92
 EXPRESSION (sram_req_o && sram_gnt_i)
             -----1----    -----2----

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Covered	T5,T7,T9

 LINE       102
 EXPRESSION ((fifoptr == 4'((FifoDepth - 1))) ? '0 : ((fifoptr + 1'b1)))
             ----------------1---------------

-1-	Status	Tests
0	Covered	T5,T7,T9
1	Covered	T5,T7,T9

 LINE       102
 SUB-EXPRESSION (fifoptr == 4'((FifoDepth - 1)))
                ----------------1---------------

-1-	Status	Tests
0	Covered	T5,T7,T9
1	Covered	T5,T7,T9

---

Branch Coverage for Instance : tb.dut.u_spi_tpm.u_tpm_rd_buffer

	Line No.	Total	Covered	Percent
Branches		5	5	100.00
IF	97	5	5	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_spi_device_0.1/rtl/spid_fifo2sram_adapter.sv' or '../src/lowrisc_ip_spi_device_0.1/rtl/spid_fifo2sram_adapter.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	97	if ((!rst_ni))
-2-:	99	if (clr_i)
-3-:	101	if (fifoptr_inc)
-4-:	102	((fifoptr == 4'((FifoDepth - 1)))) ? 

Branches:

-1-	-2-	-3-	-4-	Status	Tests
1	-	-	-	Covered	T1,T2,T3
0	1	-	-	Covered	T1,T2,T3
0	0	1	1	Covered	T5,T7,T9
0	0	1	0	Covered	T5,T7,T9
0	0	0	-	Covered	T5,T7,T9

Line Coverage for Instance : tb.dut.u_upload.u_payload_buffer

	Line No.	Total	Covered	Percent
TOTAL		18	18	100.00
CONT_ASSIGN	52	1	1	100.00
CONT_ASSIGN	56	1	1	100.00
CONT_ASSIGN	57	1	1	100.00
CONT_ASSIGN	62	1	1	100.00
CONT_ASSIGN	73	1	1	100.00
ALWAYS	76	6	6	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	97	5	5	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_spi_device_0.1/rtl/spid_fifo2sram_adapter.sv' or '../src/lowrisc_ip_spi_device_0.1/rtl/spid_fifo2sram_adapter.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
52	1	1
56	1	1
57	1	1
62	1	1
73	1	1
76	1	1
77	1	1
78	1	1
79	1	1
80	1	1
81	1	1
			MISSING_ELSE
92	1	1
94	1	1
97	1	1
98	1	1
99	1	1
100		unreachable
101	1	1
102	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_upload.u_payload_buffer

	Total	Covered	Percent
Conditions	13	11	84.62
Logical	13	11	84.62
Non-Logical	0	0
Event	0	0

 LINE       56
 EXPRESSION (wvalid_i & ((!clr_i)))
             ----1---   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Covered	T5,T7,T9

 LINE       57
 EXPRESSION (sram_gnt_i & ((!clr_i)))
             -----1----   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Covered	T5,T7,T9

 LINE       79
 EXPRESSION (fifoptr[0+:g_multiple_entry_per_word.SubWordW] == i)
            --------------------------1--------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       92
 EXPRESSION (sram_req_o && sram_gnt_i)
             -----1----    -----2----

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Covered	T5,T7,T9

 LINE       102
 EXPRESSION ((fifoptr == 8'((FifoDepth - 1))) ? '0 : ((fifoptr + 1'b1)))
             ----------------1---------------

-1-	Status	Tests
0	Covered	T5,T7,T9
1	Covered	T5,T7,T11

 LINE       102
 SUB-EXPRESSION (fifoptr == 8'((FifoDepth - 1)))
                ----------------1---------------

-1-	Status	Tests
0	Covered	T5,T7,T9
1	Covered	T5,T7,T11

---

Branch Coverage for Instance : tb.dut.u_upload.u_payload_buffer

	Line No.	Total	Covered	Percent
Branches		6	6	100.00
IF	97	4	4	100.00
IF	79	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_spi_device_0.1/rtl/spid_fifo2sram_adapter.sv' or '../src/lowrisc_ip_spi_device_0.1/rtl/spid_fifo2sram_adapter.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	97	if ((!rst_ni))
-2-:	99	if (clr_i)
-3-:	101	if (fifoptr_inc)
-4-:	102	((fifoptr == 8'((FifoDepth - 1)))) ? 

Branches:

-1-	-2-	-3-	-4-	Status	Tests
1	-	-	-	Covered	T1,T2,T3
0	1	-	-	Unreachable
0	0	1	1	Covered	T5,T7,T11
0	0	1	0	Covered	T5,T7,T9
0	0	0	-	Covered	T1,T2,T5

	LineNo.	Expression
-1-:	79	if ((fifoptr[0+:g_multiple_entry_per_word.SubWordW] == i))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_upload.u_payload_buffer

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
g_multiple_entry_per_word.NumEntryPerWordPowerOf2_A	1852	1852	0	0
g_multiple_entry_per_word.WidthDivideSramDw_A	1852	1852	0	0

g_multiple_entry_per_word.NumEntryPerWordPowerOf2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1852	1852	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

g_multiple_entry_per_word.WidthDivideSramDw_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1852	1852	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_spi_tpm.u_tpm_wr_buffer

	Line No.	Total	Covered	Percent
TOTAL		18	18	100.00
CONT_ASSIGN	52	1	1	100.00
CONT_ASSIGN	56	1	1	100.00
CONT_ASSIGN	57	1	1	100.00
CONT_ASSIGN	62	1	1	100.00
CONT_ASSIGN	73	1	1	100.00
ALWAYS	76	6	6	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	97	5	5	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_spi_device_0.1/rtl/spid_fifo2sram_adapter.sv' or '../src/lowrisc_ip_spi_device_0.1/rtl/spid_fifo2sram_adapter.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
52	1	1
56	1	1
57	1	1
62	1	1
73	1	1
76	1	1
77	1	1
78	1	1
79	1	1
80	1	1
81	1	1
			MISSING_ELSE
92	1	1
94	1	1
97	1	1
98	1	1
99	1	1
100		unreachable
101	1	1
102	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_spi_tpm.u_tpm_wr_buffer

	Total	Covered	Percent
Conditions	13	11	84.62
Logical	13	11	84.62
Non-Logical	0	0
Event	0	0

 LINE       56
 EXPRESSION (wvalid_i & ((!clr_i)))
             ----1---   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Covered	T5,T7,T9

 LINE       57
 EXPRESSION (sram_gnt_i & ((!clr_i)))
             -----1----   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Covered	T5,T7,T9

 LINE       79
 EXPRESSION (fifoptr[0+:g_multiple_entry_per_word.SubWordW] == i)
            --------------------------1--------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       92
 EXPRESSION (sram_req_o && sram_gnt_i)
             -----1----    -----2----

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Covered	T5,T7,T9

 LINE       102
 EXPRESSION ((fifoptr == 6'((FifoDepth - 1))) ? '0 : ((fifoptr + 1'b1)))
             ----------------1---------------

-1-	Status	Tests
0	Covered	T5,T7,T9
1	Covered	T5,T7,T9

 LINE       102
 SUB-EXPRESSION (fifoptr == 6'((FifoDepth - 1)))
                ----------------1---------------

-1-	Status	Tests
0	Covered	T5,T7,T9
1	Covered	T5,T7,T9

---

Branch Coverage for Instance : tb.dut.u_spi_tpm.u_tpm_wr_buffer

	Line No.	Total	Covered	Percent
Branches		6	6	100.00
IF	97	4	4	100.00
IF	79	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_spi_device_0.1/rtl/spid_fifo2sram_adapter.sv' or '../src/lowrisc_ip_spi_device_0.1/rtl/spid_fifo2sram_adapter.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	97	if ((!rst_ni))
-2-:	99	if (clr_i)
-3-:	101	if (fifoptr_inc)
-4-:	102	((fifoptr == 6'((FifoDepth - 1)))) ? 

Branches:

-1-	-2-	-3-	-4-	Status	Tests
1	-	-	-	Covered	T1,T2,T3
0	1	-	-	Unreachable
0	0	1	1	Covered	T5,T7,T9
0	0	1	0	Covered	T5,T7,T9
0	0	0	-	Covered	T3,T5,T6

	LineNo.	Expression
-1-:	79	if ((fifoptr[0+:g_multiple_entry_per_word.SubWordW] == i))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_spi_tpm.u_tpm_wr_buffer

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
g_multiple_entry_per_word.NumEntryPerWordPowerOf2_A	1852	1852	0	0
g_multiple_entry_per_word.WidthDivideSramDw_A	1852	1852	0	0

g_multiple_entry_per_word.NumEntryPerWordPowerOf2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1852	1852	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

g_multiple_entry_per_word.WidthDivideSramDw_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1852	1852	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0