SPI_DEVICE/1R1W Simulation Results

Tuesday March 26 2024 19:03:00 UTC

GitHub Revision: `b111fbcef3`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 29002153775573720681496722306495080473944791482258036550176866636887326742880

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	spi_device_flash_and_tpm	11.075m	367.051ms	50	50	100.00
V1	csr_hw_reset	spi_device_csr_hw_reset	1.420s	151.839us	5	5	100.00
V1	csr_rw	spi_device_csr_rw	2.740s	590.848us	20	20	100.00
V1	csr_bit_bash	spi_device_csr_bit_bash	40.210s	2.775ms	5	5	100.00
V1	csr_aliasing	spi_device_csr_aliasing	23.960s	3.489ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	spi_device_csr_mem_rw_with_rand_reset	3.870s	139.175us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	spi_device_csr_rw	2.740s	590.848us	20	20	100.00
		spi_device_csr_aliasing	23.960s	3.489ms	5	5	100.00
V1	mem_walk	spi_device_mem_walk	0.680s	11.846us	5	5	100.00
V1	mem_partial_access	spi_device_mem_partial_access	2.330s	61.244us	5	5	100.00
V1		TOTAL			115	115	100.00
V2	csb_read	spi_device_csb_read	0.840s	98.231us	50	50	100.00
V2	mem_parity	spi_device_mem_parity	0.770s	1.776us	0	20	0.00
V2	mem_cfg	spi_device_ram_cfg	0.810s	16.047us	20	20	100.00
V2	tpm_read	spi_device_tpm_rw	9.880s	289.266us	50	50	100.00
V2	tpm_write	spi_device_tpm_rw	9.880s	289.266us	50	50	100.00
V2	tpm_hw_reg	spi_device_tpm_read_hw_reg	27.130s	39.735ms	50	50	100.00
		spi_device_tpm_sts_read	1.260s	461.408us	50	50	100.00
V2	tpm_fully_random_case	spi_device_tpm_all	1.304m	60.269ms	50	50	100.00
V2	pass_cmd_filtering	spi_device_pass_cmd_filtering	32.330s	14.716ms	50	50	100.00
		spi_device_flash_all	6.936m	80.494ms	49	50	98.00
V2	pass_addr_translation	spi_device_pass_addr_payload_swap	47.920s	70.100ms	50	50	100.00
		spi_device_flash_all	6.936m	80.494ms	49	50	98.00
V2	pass_payload_translation	spi_device_pass_addr_payload_swap	47.920s	70.100ms	50	50	100.00
		spi_device_flash_all	6.936m	80.494ms	49	50	98.00
V2	cmd_info_slots	spi_device_flash_all	6.936m	80.494ms	49	50	98.00
V2	cmd_read_status	spi_device_intercept	12.210s	3.742ms	50	50	100.00
		spi_device_flash_all	6.936m	80.494ms	49	50	98.00
V2	cmd_read_jedec	spi_device_intercept	12.210s	3.742ms	50	50	100.00
		spi_device_flash_all	6.936m	80.494ms	49	50	98.00
V2	cmd_read_sfdp	spi_device_intercept	12.210s	3.742ms	50	50	100.00
		spi_device_flash_all	6.936m	80.494ms	49	50	98.00
V2	cmd_fast_read	spi_device_intercept	12.210s	3.742ms	50	50	100.00
		spi_device_flash_all	6.936m	80.494ms	49	50	98.00
V2	cmd_read_pipeline	spi_device_intercept	12.210s	3.742ms	50	50	100.00
		spi_device_flash_all	6.936m	80.494ms	49	50	98.00
V2	flash_cmd_upload	spi_device_upload	49.170s	27.645ms	50	50	100.00
V2	mailbox_command	spi_device_mailbox	49.900s	32.833ms	50	50	100.00
V2	mailbox_cross_outside_command	spi_device_mailbox	49.900s	32.833ms	50	50	100.00
V2	mailbox_cross_inside_command	spi_device_mailbox	49.900s	32.833ms	50	50	100.00
V2	cmd_read_buffer	spi_device_flash_mode	1.359m	15.860ms	49	50	98.00
		spi_device_read_buffer_direct	7.900s	1.744ms	50	50	100.00
V2	cmd_dummy_cycle	spi_device_mailbox	49.900s	32.833ms	50	50	100.00
		spi_device_flash_all	6.936m	80.494ms	49	50	98.00
V2	quad_spi	spi_device_flash_all	6.936m	80.494ms	49	50	98.00
V2	dual_spi	spi_device_flash_all	6.936m	80.494ms	49	50	98.00
V2	4b_3b_feature	spi_device_cfg_cmd	11.580s	3.006ms	50	50	100.00
V2	write_enable_disable	spi_device_cfg_cmd	11.580s	3.006ms	50	50	100.00
V2	TPM_with_flash_or_passthrough_mode	spi_device_flash_and_tpm	11.075m	367.051ms	50	50	100.00
V2	tpm_and_flash_trans_with_min_inactive_time	spi_device_flash_and_tpm_min_idle	10.852m	355.639ms	49	50	98.00
V2	stress_all	spi_device_stress_all	18.155m	132.889ms	50	50	100.00
V2	alert_test	spi_device_alert_test	0.800s	35.614us	50	50	100.00
V2	intr_test	spi_device_intr_test	0.800s	82.277us	50	50	100.00
V2	tl_d_oob_addr_access	spi_device_tl_errors	5.280s	289.948us	20	20	100.00
V2	tl_d_illegal_access	spi_device_tl_errors	5.280s	289.948us	20	20	100.00
V2	tl_d_outstanding_access	spi_device_csr_hw_reset	1.420s	151.839us	5	5	100.00
		spi_device_csr_rw	2.740s	590.848us	20	20	100.00
		spi_device_csr_aliasing	23.960s	3.489ms	5	5	100.00
		spi_device_same_csr_outstanding	4.500s	227.956us	20	20	100.00
V2	tl_d_partial_access	spi_device_csr_hw_reset	1.420s	151.839us	5	5	100.00
		spi_device_csr_rw	2.740s	590.848us	20	20	100.00
		spi_device_csr_aliasing	23.960s	3.489ms	5	5	100.00
		spi_device_same_csr_outstanding	4.500s	227.956us	20	20	100.00
V2		TOTAL			957	980	97.65
V2S	tl_intg_err	spi_device_sec_cm	1.180s	113.701us	5	5	100.00
		spi_device_tl_intg_err	24.140s	2.707ms	20	20	100.00
V2S	sec_cm_bus_integrity	spi_device_tl_intg_err	24.140s	2.707ms	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	spi_device_stress_all_with_rand_reset			0	0	--
V3		TOTAL			0	0	--
		TOTAL			1097	1120	97.95

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	8	100.00
V2	22	22	18	81.82
V2S	2	2	2	100.00
V3	1	0	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
95.92	98.30	94.07	98.61	89.36	97.00	95.84	98.22

Failure Buckets

UVM_ERROR (uvm_hdl_vcs.c:992) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[*]) has 20 failures:

Test spi_device_mem_parity has 20 failures.

0.spi_device_mem_parity.115281856602911459999392019736263984353541172800387156236968888624257420903811
Line 249, in log /container/opentitan-public/scratch/os_regression/spi_device_1r1w-sim-vcs/0.spi_device_mem_parity/latest/run.log

  UVM_ERROR @   1157067 ps: (uvm_hdl_vcs.c:992) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[66])
   Either the name is incorrect, or you may not have PLI/ACC visibility to that name
  UVM_ERROR @   1157067 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))
  UVM_ERROR @   1157067 ps: (uvm_hdl_vcs.c:1142) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[962])
   Either the name is incorrect, or you may not have PLI/ACC visibility to that name

1.spi_device_mem_parity.27686272752165239531600636714503703719887672018607672266877945413860756157646
Line 249, in log /container/opentitan-public/scratch/os_regression/spi_device_1r1w-sim-vcs/1.spi_device_mem_parity/latest/run.log

  UVM_ERROR @   2780386 ps: (uvm_hdl_vcs.c:992) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[111])
   Either the name is incorrect, or you may not have PLI/ACC visibility to that name
  UVM_ERROR @   2780386 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))
  UVM_ERROR @   2780386 ps: (uvm_hdl_vcs.c:1142) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[1007])
   Either the name is incorrect, or you may not have PLI/ACC visibility to that name

... and 18 more failures.

UVM_ERROR (spi_device_scoreboard.sv:1070) [scoreboard] Check failed (item.d_data inside {exp_data_q}) act (*) != exp '{'{other_status:*, wel:*, busy:*}} has 2 failures:

Test spi_device_flash_and_tpm_min_idle has 1 failures.

17.spi_device_flash_and_tpm_min_idle.105482158787723398011758896703907308402068116836677353984411934930819248706145
Line 255, in log /container/opentitan-public/scratch/os_regression/spi_device_1r1w-sim-vcs/17.spi_device_flash_and_tpm_min_idle/latest/run.log

  UVM_ERROR @ 5369658264 ps: (spi_device_scoreboard.sv:1070) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0x2b2c5c) != exp '{'{other_status:'h3a1686, wel:'h0, busy:'h0}}
  UVM_INFO @ 5413417120 ps: (spi_device_flash_all_vseq.sv:46) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_and_tpm_min_idle_vseq.flash_vseq] running iteration 3/7
  UVM_INFO @ 7507294224 ps: (spi_device_tpm_read_hw_reg_vseq.sv:48) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_and_tpm_min_idle_vseq.tpm_vseq] starting sequence 4/18
  UVM_INFO @ 7945695392 ps: (spi_device_flash_all_vseq.sv:46) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_and_tpm_min_idle_vseq.flash_vseq] running iteration 4/7
  UVM_INFO @ 9518634712 ps: (spi_device_flash_all_vseq.sv:46) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_and_tpm_min_idle_vseq.flash_vseq] running iteration 5/7

Test spi_device_flash_all has 1 failures.

44.spi_device_flash_all.27534941962944750155922603293439420086848204604319816520103299454106975472523
Line 252, in log /container/opentitan-public/scratch/os_regression/spi_device_1r1w-sim-vcs/44.spi_device_flash_all/latest/run.log

  UVM_ERROR @ 4806651456 ps: (spi_device_scoreboard.sv:1070) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0x628060) != exp '{'{other_status:'h3e74f2, wel:'h0, busy:'h0}}
  UVM_INFO @ 5868171456 ps: (spi_device_flash_all_vseq.sv:46) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_all_vseq] running iteration 3/11
  UVM_INFO @ 8046721456 ps: (spi_device_flash_all_vseq.sv:46) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_all_vseq] running iteration 4/11
  UVM_INFO @ 9291389456 ps: (spi_device_flash_all_vseq.sv:46) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_all_vseq] running iteration 5/11
  UVM_INFO @ 11383397456 ps: (spi_device_flash_all_vseq.sv:46) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_all_vseq] running iteration 6/11

UVM_FATAL (spi_device_scoreboard.sv:921) [scoreboard] timeout occurred! has 1 failures:
- Test spi_device_flash_mode has 1 failures.
  - 26.spi_device_flash_mode.32468197651155897070804910640035972438886663016860664279796235432026272647205
    Line 249, in log /container/opentitan-public/scratch/os_regression/spi_device_1r1w-sim-vcs/26.spi_device_flash_mode/latest/run.log
```
  UVM_FATAL @ 44240251402 ps: (spi_device_scoreboard.sv:921) [uvm_test_top.env.scoreboard] timeout occurred!
  UVM_INFO @ 44240251402 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```