Unified Coverage Report :: Module :: spid_fifo2sram_adapter

Module : spid_fifo2sram_adapter

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
0.00	0.00	0.00			0.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_spi_device_0.1/rtl/spid_fifo2sram_adapter.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_upload.u_payload_buffer	0.00	0.00	0.00			0.00
tb.dut.u_spi_tpm.u_tpm_wr_buffer	0.00	0.00	0.00			0.00
tb.dut.u_spi_tpm.u_tpm_rd_buffer	0.00	0.00	0.00			0.00

---

Module Instance : tb.dut.u_upload.u_payload_buffer

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
0.00	0.00	0.00			0.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
0.00	0.00	0.00			0.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
0.00	0.00	0.00		0.00	0.00		u_upload

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_spi_tpm.u_tpm_wr_buffer

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
0.00	0.00	0.00			0.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
0.00	0.00	0.00			0.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
0.00	0.00	0.00		0.00	0.00		u_spi_tpm

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_spi_tpm.u_tpm_rd_buffer

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
0.00	0.00	0.00			0.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
0.00	0.00	0.00			0.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
0.00	0.00	0.00		0.00	0.00		u_spi_tpm

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : spid_fifo2sram_adapter ( parameter FifoWidth=8,FifoDepth=256,SramAw=10,SramDw=32,SramBaseAddr=896,EnPack=1,FifoPtrW=8,NumEntryPerWord=4,g_multiple_entry_per_word.SubWordW=2 )
Line Coverage for Module self-instances :

SCORE	LINE
0.00	0.00

tb.dut.u_upload.u_payload_buffer

	Line No.	Total	Covered	Percent
TOTAL		18	0	0.00
CONT_ASSIGN	52	1	0	0.00
CONT_ASSIGN	56	1	0	0.00
CONT_ASSIGN	57	1	0	0.00
CONT_ASSIGN	62	1	0	0.00
CONT_ASSIGN	73	1	0	0.00
ALWAYS	76	6	0	0.00
CONT_ASSIGN	92	1	0	0.00
CONT_ASSIGN	94	1	0	0.00
ALWAYS	97	5	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_spi_device_0.1/rtl/spid_fifo2sram_adapter.sv' or '../src/lowrisc_ip_spi_device_0.1/rtl/spid_fifo2sram_adapter.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
52	0	1
56	0	1
57	0	1
62	0	1
73	0	1
76	0	1
77	0	1
78	0	1
79	0	1
80	0	1
81	0	1
			==> MISSING_ELSE
92	0	1
94	0	1
97	0	1
98	0	1
99	0	1
100		unreachable
101	0	1
102	0	1
			==> MISSING_ELSE

---

Line Coverage for Module : spid_fifo2sram_adapter ( parameter FifoWidth=8,FifoDepth=64,SramAw=10,SramDw=32,SramBaseAddr=992,EnPack=1,FifoPtrW=6,NumEntryPerWord=4,g_multiple_entry_per_word.SubWordW=2 )
Line Coverage for Module self-instances :

SCORE	LINE
0.00	0.00

tb.dut.u_spi_tpm.u_tpm_wr_buffer

	Line No.	Total	Covered	Percent
TOTAL		18	0	0.00
CONT_ASSIGN	52	1	0	0.00
CONT_ASSIGN	56	1	0	0.00
CONT_ASSIGN	57	1	0	0.00
CONT_ASSIGN	62	1	0	0.00
CONT_ASSIGN	73	1	0	0.00
ALWAYS	76	6	0	0.00
CONT_ASSIGN	92	1	0	0.00
CONT_ASSIGN	94	1	0	0.00
ALWAYS	97	5	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_spi_device_0.1/rtl/spid_fifo2sram_adapter.sv' or '../src/lowrisc_ip_spi_device_0.1/rtl/spid_fifo2sram_adapter.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
52	0	1
56	0	1
57	0	1
62	0	1
73	0	1
76	0	1
77	0	1
78	0	1
79	0	1
80	0	1
81	0	1
			==> MISSING_ELSE
92	0	1
94	0	1
97	0	1
98	0	1
99	0	1
100		unreachable
101	0	1
102	0	1
			==> MISSING_ELSE

---

Line Coverage for Module : spid_fifo2sram_adapter ( parameter FifoWidth=32,FifoDepth=16,SramAw=10,SramDw=32,SramBaseAddr=832,EnPack=1,FifoPtrW=4,NumEntryPerWord=1 )
Line Coverage for Module self-instances :

SCORE	LINE
0.00	0.00

tb.dut.u_spi_tpm.u_tpm_rd_buffer

	Line No.	Total	Covered	Percent
TOTAL		14	0	0.00
CONT_ASSIGN	52	1	0	0.00
CONT_ASSIGN	56	1	0	0.00
CONT_ASSIGN	57	1	0	0.00
CONT_ASSIGN	62	1	0	0.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	88	1	0	0.00
CONT_ASSIGN	92	1	0	0.00
CONT_ASSIGN	94	1	0	0.00
ALWAYS	97	6	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_spi_device_0.1/rtl/spid_fifo2sram_adapter.sv' or '../src/lowrisc_ip_spi_device_0.1/rtl/spid_fifo2sram_adapter.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
52	0	1
56	0	1
57	0	1
62	0	1
87	0	1
88	0	1
92	0	1
94	0	1
97	0	1
98	0	1
99	0	1
100	0	1
101	0	1
102	0	1
			==> MISSING_ELSE

---

Cond Coverage for Module : spid_fifo2sram_adapter ( parameter FifoWidth=8,FifoDepth=256,SramAw=10,SramDw=32,SramBaseAddr=896,EnPack=1,FifoPtrW=8,NumEntryPerWord=4,g_multiple_entry_per_word.SubWordW=2 )
Cond Coverage for Module self-instances :

SCORE	COND
0.00	0.00

tb.dut.u_upload.u_payload_buffer

	Total	Covered	Percent
Conditions	13	0	0.00
Logical	13	0	0.00
Non-Logical	0	0
Event	0	0

 LINE       56
 EXPRESSION (wvalid_i & ((!clr_i)))
             ----1---   -----2----

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Unreachable
1	1	Not Covered

 LINE       57
 EXPRESSION (sram_gnt_i & ((!clr_i)))
             -----1----   -----2----

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Unreachable
1	1	Not Covered

 LINE       79
 EXPRESSION (fifoptr[0+:g_multiple_entry_per_word.SubWordW] == i)
            --------------------------1--------------------------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       92
 EXPRESSION (sram_req_o && sram_gnt_i)
             -----1----    -----2----

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       102
 EXPRESSION ((fifoptr == 8'((FifoDepth - 1))) ? '0 : ((fifoptr + 1'b1)))
             ----------------1---------------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       102
 SUB-EXPRESSION (fifoptr == 8'((FifoDepth - 1)))
                ----------------1---------------

-1-	Status	Tests
0	Not Covered
1	Not Covered

---

Cond Coverage for Module : spid_fifo2sram_adapter ( parameter FifoWidth=8,FifoDepth=64,SramAw=10,SramDw=32,SramBaseAddr=992,EnPack=1,FifoPtrW=6,NumEntryPerWord=4,g_multiple_entry_per_word.SubWordW=2 )
Cond Coverage for Module self-instances :

SCORE	COND
0.00	0.00

tb.dut.u_spi_tpm.u_tpm_wr_buffer

	Total	Covered	Percent
Conditions	13	0	0.00
Logical	13	0	0.00
Non-Logical	0	0
Event	0	0

 LINE       56
 EXPRESSION (wvalid_i & ((!clr_i)))
             ----1---   -----2----

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Unreachable
1	1	Not Covered

 LINE       57
 EXPRESSION (sram_gnt_i & ((!clr_i)))
             -----1----   -----2----

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Unreachable
1	1	Not Covered

 LINE       79
 EXPRESSION (fifoptr[0+:g_multiple_entry_per_word.SubWordW] == i)
            --------------------------1--------------------------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       92
 EXPRESSION (sram_req_o && sram_gnt_i)
             -----1----    -----2----

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       102
 EXPRESSION ((fifoptr == 6'((FifoDepth - 1))) ? '0 : ((fifoptr + 1'b1)))
             ----------------1---------------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       102
 SUB-EXPRESSION (fifoptr == 6'((FifoDepth - 1)))
                ----------------1---------------

-1-	Status	Tests
0	Not Covered
1	Not Covered

---

Cond Coverage for Module : spid_fifo2sram_adapter ( parameter FifoWidth=32,FifoDepth=16,SramAw=10,SramDw=32,SramBaseAddr=832,EnPack=1,FifoPtrW=4,NumEntryPerWord=1 )
Cond Coverage for Module self-instances :

SCORE	COND
0.00	0.00

tb.dut.u_spi_tpm.u_tpm_rd_buffer

	Total	Covered	Percent
Conditions	13	0	0.00
Logical	13	0	0.00
Non-Logical	0	0
Event	0	0

 LINE       56
 EXPRESSION (wvalid_i & ((!clr_i)))
             ----1---   -----2----

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       57
 EXPRESSION (sram_gnt_i & ((!clr_i)))
             -----1----   -----2----

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       92
 EXPRESSION (sram_req_o && sram_gnt_i)
             -----1----    -----2----

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       102
 EXPRESSION ((fifoptr == 4'((FifoDepth - 1))) ? '0 : ((fifoptr + 1'b1)))
             ----------------1---------------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       102
 SUB-EXPRESSION (fifoptr == 4'((FifoDepth - 1)))
                ----------------1---------------

-1-	Status	Tests
0	Not Covered
1	Not Covered

---

Branch Coverage for Module : spid_fifo2sram_adapter ( parameter FifoWidth=8,FifoDepth=256,SramAw=10,SramDw=32,SramBaseAddr=896,EnPack=1,FifoPtrW=8,NumEntryPerWord=4,g_multiple_entry_per_word.SubWordW=2 )
Branch Coverage for Module self-instances :

SCORE	BRANCH
0.00	0.00

tb.dut.u_upload.u_payload_buffer

	Line No.	Total	Covered	Percent
Branches		6	0	0.00
IF	97	4	0	0.00
IF	79	2	0	0.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_spi_device_0.1/rtl/spid_fifo2sram_adapter.sv' or '../src/lowrisc_ip_spi_device_0.1/rtl/spid_fifo2sram_adapter.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	97	if ((!rst_ni))
-2-:	99	if (clr_i)
-3-:	101	if (fifoptr_inc)
-4-:	102	((fifoptr == 8'((FifoDepth - 1)))) ? 

Branches:

-1-	-2-	-3-	-4-	Status	Tests
1	-	-	-	Not Covered
0	1	-	-	Unreachable
0	0	1	1	Not Covered
0	0	1	0	Not Covered
0	0	0	-	Not Covered

	LineNo.	Expression
-1-:	79	if ((fifoptr[0+:g_multiple_entry_per_word.SubWordW] == i))

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

---

Branch Coverage for Module : spid_fifo2sram_adapter ( parameter FifoWidth=8,FifoDepth=64,SramAw=10,SramDw=32,SramBaseAddr=992,EnPack=1,FifoPtrW=6,NumEntryPerWord=4,g_multiple_entry_per_word.SubWordW=2 )
Branch Coverage for Module self-instances :

SCORE	BRANCH
0.00	0.00

tb.dut.u_spi_tpm.u_tpm_wr_buffer

	Line No.	Total	Covered	Percent
Branches		6	0	0.00
IF	97	4	0	0.00
IF	79	2	0	0.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_spi_device_0.1/rtl/spid_fifo2sram_adapter.sv' or '../src/lowrisc_ip_spi_device_0.1/rtl/spid_fifo2sram_adapter.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	97	if ((!rst_ni))
-2-:	99	if (clr_i)
-3-:	101	if (fifoptr_inc)
-4-:	102	((fifoptr == 6'((FifoDepth - 1)))) ? 

Branches:

-1-	-2-	-3-	-4-	Status	Tests
1	-	-	-	Not Covered
0	1	-	-	Unreachable
0	0	1	1	Not Covered
0	0	1	0	Not Covered
0	0	0	-	Not Covered

	LineNo.	Expression
-1-:	79	if ((fifoptr[0+:g_multiple_entry_per_word.SubWordW] == i))

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

---

Branch Coverage for Module : spid_fifo2sram_adapter ( parameter FifoWidth=32,FifoDepth=16,SramAw=10,SramDw=32,SramBaseAddr=832,EnPack=1,FifoPtrW=4,NumEntryPerWord=1 )
Branch Coverage for Module self-instances :

SCORE	BRANCH
0.00	0.00

tb.dut.u_spi_tpm.u_tpm_rd_buffer

	Line No.	Total	Covered	Percent
Branches		5	0	0.00
IF	97	5	0	0.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_spi_device_0.1/rtl/spid_fifo2sram_adapter.sv' or '../src/lowrisc_ip_spi_device_0.1/rtl/spid_fifo2sram_adapter.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	97	if ((!rst_ni))
-2-:	99	if (clr_i)
-3-:	101	if (fifoptr_inc)
-4-:	102	((fifoptr == 4'((FifoDepth - 1)))) ? 

Branches:

-1-	-2-	-3-	-4-	Status	Tests
1	-	-	-	Not Covered
0	1	-	-	Not Covered
0	0	1	1	Not Covered
0	0	1	0	Not Covered
0	0	0	-	Not Covered

Line Coverage for Instance : tb.dut.u_upload.u_payload_buffer

	Line No.	Total	Covered	Percent
TOTAL		18	0	0.00
CONT_ASSIGN	52	1	0	0.00
CONT_ASSIGN	56	1	0	0.00
CONT_ASSIGN	57	1	0	0.00
CONT_ASSIGN	62	1	0	0.00
CONT_ASSIGN	73	1	0	0.00
ALWAYS	76	6	0	0.00
CONT_ASSIGN	92	1	0	0.00
CONT_ASSIGN	94	1	0	0.00
ALWAYS	97	5	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_spi_device_0.1/rtl/spid_fifo2sram_adapter.sv' or '../src/lowrisc_ip_spi_device_0.1/rtl/spid_fifo2sram_adapter.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
52	0	1
56	0	1
57	0	1
62	0	1
73	0	1
76	0	1
77	0	1
78	0	1
79	0	1
80	0	1
81	0	1
			==> MISSING_ELSE
92	0	1
94	0	1
97	0	1
98	0	1
99	0	1
100		unreachable
101	0	1
102	0	1
			==> MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_upload.u_payload_buffer

	Total	Covered	Percent
Conditions	13	0	0.00
Logical	13	0	0.00
Non-Logical	0	0
Event	0	0

 LINE       56
 EXPRESSION (wvalid_i & ((!clr_i)))
             ----1---   -----2----

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Unreachable
1	1	Not Covered

 LINE       57
 EXPRESSION (sram_gnt_i & ((!clr_i)))
             -----1----   -----2----

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Unreachable
1	1	Not Covered

 LINE       79
 EXPRESSION (fifoptr[0+:g_multiple_entry_per_word.SubWordW] == i)
            --------------------------1--------------------------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       92
 EXPRESSION (sram_req_o && sram_gnt_i)
             -----1----    -----2----

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       102
 EXPRESSION ((fifoptr == 8'((FifoDepth - 1))) ? '0 : ((fifoptr + 1'b1)))
             ----------------1---------------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       102
 SUB-EXPRESSION (fifoptr == 8'((FifoDepth - 1)))
                ----------------1---------------

-1-	Status	Tests
0	Not Covered
1	Not Covered

---

Branch Coverage for Instance : tb.dut.u_upload.u_payload_buffer

	Line No.	Total	Covered	Percent
Branches		6	0	0.00
IF	97	4	0	0.00
IF	79	2	0	0.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_spi_device_0.1/rtl/spid_fifo2sram_adapter.sv' or '../src/lowrisc_ip_spi_device_0.1/rtl/spid_fifo2sram_adapter.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	97	if ((!rst_ni))
-2-:	99	if (clr_i)
-3-:	101	if (fifoptr_inc)
-4-:	102	((fifoptr == 8'((FifoDepth - 1)))) ? 

Branches:

-1-	-2-	-3-	-4-	Status	Tests
1	-	-	-	Not Covered
0	1	-	-	Unreachable
0	0	1	1	Not Covered
0	0	1	0	Not Covered
0	0	0	-	Not Covered

	LineNo.	Expression
-1-:	79	if ((fifoptr[0+:g_multiple_entry_per_word.SubWordW] == i))

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

Line Coverage for Instance : tb.dut.u_spi_tpm.u_tpm_wr_buffer

	Line No.	Total	Covered	Percent
TOTAL		18	0	0.00
CONT_ASSIGN	52	1	0	0.00
CONT_ASSIGN	56	1	0	0.00
CONT_ASSIGN	57	1	0	0.00
CONT_ASSIGN	62	1	0	0.00
CONT_ASSIGN	73	1	0	0.00
ALWAYS	76	6	0	0.00
CONT_ASSIGN	92	1	0	0.00
CONT_ASSIGN	94	1	0	0.00
ALWAYS	97	5	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_spi_device_0.1/rtl/spid_fifo2sram_adapter.sv' or '../src/lowrisc_ip_spi_device_0.1/rtl/spid_fifo2sram_adapter.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
52	0	1
56	0	1
57	0	1
62	0	1
73	0	1
76	0	1
77	0	1
78	0	1
79	0	1
80	0	1
81	0	1
			==> MISSING_ELSE
92	0	1
94	0	1
97	0	1
98	0	1
99	0	1
100		unreachable
101	0	1
102	0	1
			==> MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_spi_tpm.u_tpm_wr_buffer

	Total	Covered	Percent
Conditions	13	0	0.00
Logical	13	0	0.00
Non-Logical	0	0
Event	0	0

 LINE       56
 EXPRESSION (wvalid_i & ((!clr_i)))
             ----1---   -----2----

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Unreachable
1	1	Not Covered

 LINE       57
 EXPRESSION (sram_gnt_i & ((!clr_i)))
             -----1----   -----2----

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Unreachable
1	1	Not Covered

 LINE       79
 EXPRESSION (fifoptr[0+:g_multiple_entry_per_word.SubWordW] == i)
            --------------------------1--------------------------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       92
 EXPRESSION (sram_req_o && sram_gnt_i)
             -----1----    -----2----

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       102
 EXPRESSION ((fifoptr == 6'((FifoDepth - 1))) ? '0 : ((fifoptr + 1'b1)))
             ----------------1---------------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       102
 SUB-EXPRESSION (fifoptr == 6'((FifoDepth - 1)))
                ----------------1---------------

-1-	Status	Tests
0	Not Covered
1	Not Covered

---

Branch Coverage for Instance : tb.dut.u_spi_tpm.u_tpm_wr_buffer

	Line No.	Total	Covered	Percent
Branches		6	0	0.00
IF	97	4	0	0.00
IF	79	2	0	0.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_spi_device_0.1/rtl/spid_fifo2sram_adapter.sv' or '../src/lowrisc_ip_spi_device_0.1/rtl/spid_fifo2sram_adapter.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	97	if ((!rst_ni))
-2-:	99	if (clr_i)
-3-:	101	if (fifoptr_inc)
-4-:	102	((fifoptr == 6'((FifoDepth - 1)))) ? 

Branches:

-1-	-2-	-3-	-4-	Status	Tests
1	-	-	-	Not Covered
0	1	-	-	Unreachable
0	0	1	1	Not Covered
0	0	1	0	Not Covered
0	0	0	-	Not Covered

	LineNo.	Expression
-1-:	79	if ((fifoptr[0+:g_multiple_entry_per_word.SubWordW] == i))

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

Line Coverage for Instance : tb.dut.u_spi_tpm.u_tpm_rd_buffer

	Line No.	Total	Covered	Percent
TOTAL		14	0	0.00
CONT_ASSIGN	52	1	0	0.00
CONT_ASSIGN	56	1	0	0.00
CONT_ASSIGN	57	1	0	0.00
CONT_ASSIGN	62	1	0	0.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	88	1	0	0.00
CONT_ASSIGN	92	1	0	0.00
CONT_ASSIGN	94	1	0	0.00
ALWAYS	97	6	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_spi_device_0.1/rtl/spid_fifo2sram_adapter.sv' or '../src/lowrisc_ip_spi_device_0.1/rtl/spid_fifo2sram_adapter.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
52	0	1
56	0	1
57	0	1
62	0	1
87	0	1
88	0	1
92	0	1
94	0	1
97	0	1
98	0	1
99	0	1
100	0	1
101	0	1
102	0	1
			==> MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_spi_tpm.u_tpm_rd_buffer

	Total	Covered	Percent
Conditions	13	0	0.00
Logical	13	0	0.00
Non-Logical	0	0
Event	0	0

 LINE       56
 EXPRESSION (wvalid_i & ((!clr_i)))
             ----1---   -----2----

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       57
 EXPRESSION (sram_gnt_i & ((!clr_i)))
             -----1----   -----2----

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       92
 EXPRESSION (sram_req_o && sram_gnt_i)
             -----1----    -----2----

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       102
 EXPRESSION ((fifoptr == 4'((FifoDepth - 1))) ? '0 : ((fifoptr + 1'b1)))
             ----------------1---------------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       102
 SUB-EXPRESSION (fifoptr == 4'((FifoDepth - 1)))
                ----------------1---------------

-1-	Status	Tests
0	Not Covered
1	Not Covered

---

Branch Coverage for Instance : tb.dut.u_spi_tpm.u_tpm_rd_buffer

	Line No.	Total	Covered	Percent
Branches		5	0	0.00
IF	97	5	0	0.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_spi_device_0.1/rtl/spid_fifo2sram_adapter.sv' or '../src/lowrisc_ip_spi_device_0.1/rtl/spid_fifo2sram_adapter.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	97	if ((!rst_ni))
-2-:	99	if (clr_i)
-3-:	101	if (fifoptr_inc)
-4-:	102	((fifoptr == 4'((FifoDepth - 1)))) ? 

Branches:

-1-	-2-	-3-	-4-	Status	Tests
1	-	-	-	Not Covered
0	1	-	-	Not Covered
0	0	1	1	Not Covered
0	0	1	0	Not Covered
0	0	0	-	Not Covered