| | | | | | | | |
| gen_alert_tx[0].u_prim_alert_sender |
100.00 |
|
|
100.00 |
|
|
|
| spi_device_csr_assert |
100.00 |
|
|
|
|
|
100.00 |
| tlul_assert_device |
33.33 |
0.00 |
|
|
|
0.00 |
100.00 |
| u_clk_csb_buf |
0.00 |
0.00 |
|
|
|
|
|
| gen_generic.u_impl_generic |
0.00 |
0.00 |
|
|
|
|
|
| u_clk_csb_mux |
0.00 |
0.00 |
0.00 |
|
|
|
|
| gen_generic.u_impl_generic |
0.00 |
0.00 |
0.00 |
|
|
|
|
| u_clk_spi |
0.00 |
0.00 |
0.00 |
|
|
|
|
| gen_generic.u_impl_generic |
0.00 |
0.00 |
0.00 |
|
|
|
|
| gen_scan.i_dft_tck_mux |
0.00 |
0.00 |
0.00 |
|
|
|
|
| gen_generic.u_impl_generic |
0.00 |
0.00 |
0.00 |
|
|
|
|
| u_clk_spi_in_buf |
0.00 |
0.00 |
|
|
|
|
|
| gen_generic.u_impl_generic |
0.00 |
0.00 |
|
|
|
|
|
| u_clk_spi_in_mux |
0.00 |
0.00 |
0.00 |
|
|
|
|
| gen_generic.u_impl_generic |
0.00 |
0.00 |
0.00 |
|
|
|
|
| u_clk_spi_out_buf |
0.00 |
0.00 |
|
|
|
|
|
| gen_generic.u_impl_generic |
0.00 |
0.00 |
|
|
|
|
|
| u_clk_spi_out_mux |
0.00 |
0.00 |
0.00 |
|
|
|
|
| gen_generic.u_impl_generic |
0.00 |
0.00 |
0.00 |
|
|
|
|
| u_cmdparse |
0.00 |
0.00 |
0.00 |
|
0.00 |
0.00 |
|
| u_csb_buf |
0.00 |
0.00 |
|
|
|
|
|
| gen_generic.u_impl_generic |
0.00 |
0.00 |
|
|
|
|
|
| u_csb_rst_out_scan_mux |
0.00 |
0.00 |
0.00 |
|
|
|
|
| gen_generic.u_impl_generic |
0.00 |
0.00 |
0.00 |
|
|
|
|
| u_csb_rst_scan_mux |
0.00 |
0.00 |
0.00 |
|
|
|
|
| gen_generic.u_impl_generic |
0.00 |
0.00 |
0.00 |
|
|
|
|
| u_flash_readbuf_flip_pulse_sync |
0.00 |
0.00 |
0.00 |
|
|
0.00 |
|
| prim_flop_2sync |
0.00 |
0.00 |
|
|
|
0.00 |
|
| gen_generic.u_impl_generic |
0.00 |
0.00 |
|
|
|
0.00 |
|
| u_sync_1 |
0.00 |
0.00 |
|
|
|
0.00 |
|
| gen_generic.u_impl_generic |
0.00 |
0.00 |
|
|
|
0.00 |
|
| u_sync_2 |
0.00 |
0.00 |
|
|
|
0.00 |
|
| gen_generic.u_impl_generic |
0.00 |
0.00 |
|
|
|
0.00 |
|
| u_flash_readbuf_watermark_pulse_sync |
0.00 |
0.00 |
0.00 |
|
|
0.00 |
|
| prim_flop_2sync |
0.00 |
0.00 |
|
|
|
0.00 |
|
| gen_generic.u_impl_generic |
0.00 |
0.00 |
|
|
|
0.00 |
|
| u_sync_1 |
0.00 |
0.00 |
|
|
|
0.00 |
|
| gen_generic.u_impl_generic |
0.00 |
0.00 |
|
|
|
0.00 |
|
| u_sync_2 |
0.00 |
0.00 |
|
|
|
0.00 |
|
| gen_generic.u_impl_generic |
0.00 |
0.00 |
|
|
|
0.00 |
|
| u_intr_cmdfifo_not_empty |
0.00 |
0.00 |
0.00 |
|
|
0.00 |
|
| u_intr_payload_not_empty |
0.00 |
0.00 |
0.00 |
|
|
0.00 |
|
| u_intr_payload_overflow |
0.00 |
0.00 |
0.00 |
|
|
0.00 |
|
| u_intr_readbuf_flip |
0.00 |
0.00 |
0.00 |
|
|
0.00 |
|
| u_intr_readbuf_watermark |
0.00 |
0.00 |
0.00 |
|
|
0.00 |
|
| u_intr_tpm_cmdaddr_notempty |
0.00 |
0.00 |
0.00 |
|
|
0.00 |
|
| u_intr_tpm_rdfifo_cmd_end |
0.00 |
0.00 |
0.00 |
|
|
0.00 |
|
| u_intr_tpm_rdfifo_drop |
0.00 |
0.00 |
0.00 |
|
|
0.00 |
|
| u_intr_upload_edge |
0.00 |
0.00 |
|
|
|
0.00 |
|
| u_jedec |
0.00 |
0.00 |
0.00 |
|
0.00 |
0.00 |
|
| u_p2s |
0.00 |
0.00 |
0.00 |
|
|
0.00 |
|
| u_passthrough |
0.00 |
0.00 |
0.00 |
|
0.00 |
0.00 |
|
| u_pt_sck_cg |
0.00 |
0.00 |
0.00 |
|
|
0.00 |
|
| gen_generic.u_impl_generic |
0.00 |
0.00 |
0.00 |
|
|
0.00 |
|
| u_read_half_cycle |
0.00 |
0.00 |
|
|
|
0.00 |
|
| gen_generic.u_impl_generic |
0.00 |
0.00 |
|
|
|
0.00 |
|
| u_read_pipe_oe_stg1 |
0.00 |
0.00 |
|
|
|
0.00 |
|
| gen_generic.u_impl_generic |
0.00 |
0.00 |
|
|
|
0.00 |
|
| u_read_pipe_oe_stg2 |
0.00 |
0.00 |
|
|
|
0.00 |
|
| gen_generic.u_impl_generic |
0.00 |
0.00 |
|
|
|
0.00 |
|
| u_read_pipe_stg1 |
0.00 |
0.00 |
|
|
|
0.00 |
|
| gen_generic.u_impl_generic |
0.00 |
0.00 |
|
|
|
0.00 |
|
| u_read_pipe_stg2 |
0.00 |
0.00 |
|
|
|
0.00 |
|
| gen_generic.u_impl_generic |
0.00 |
0.00 |
|
|
|
0.00 |
|
| u_read_en_pipe_stg1 |
0.00 |
0.00 |
|
|
|
0.00 |
|
| gen_generic.u_impl_generic |
0.00 |
0.00 |
|
|
|
0.00 |
|
| u_read_en_pipe_stg2 |
0.00 |
0.00 |
|
|
|
0.00 |
|
| gen_generic.u_impl_generic |
0.00 |
0.00 |
|
|
|
0.00 |
|
| u_read_intercept_pipe_stg1 |
0.00 |
0.00 |
|
|
|
0.00 |
|
| gen_generic.u_impl_generic |
0.00 |
0.00 |
|
|
|
0.00 |
|
| u_read_intercept_pipe_stg2 |
0.00 |
0.00 |
|
|
|
0.00 |
|
| gen_generic.u_impl_generic |
0.00 |
0.00 |
|
|
|
0.00 |
|
| u_read_pipe_stg1 |
0.00 |
0.00 |
|
|
|
0.00 |
|
| gen_generic.u_impl_generic |
0.00 |
0.00 |
|
|
|
0.00 |
|
| u_read_pipe_stg2 |
0.00 |
0.00 |
|
|
|
0.00 |
|
| gen_generic.u_impl_generic |
0.00 |
0.00 |
|
|
|
0.00 |
|
u_readcmd |
0.00 |
0.00 |
0.00 |
|
0.00 |
0.00 |
|
| u_addr_latch_pulse |
0.00 |
0.00 |
0.00 |
|
|
0.00 |
|
| u_readbuffer |
0.00 |
0.00 |
0.00 |
|
|
0.00 |
|
| u_sys2spi_clr |
0.00 |
0.00 |
0.00 |
|
|
0.00 |
|
| gen_nrz_hs_protocol.ack_sync |
0.00 |
0.00 |
|
|
|
0.00 |
|
| gen_generic.u_impl_generic |
0.00 |
0.00 |
|
|
|
0.00 |
|
| u_sync_1 |
0.00 |
0.00 |
|
|
|
0.00 |
|
| gen_generic.u_impl_generic |
0.00 |
0.00 |
|
|
|
0.00 |
|
| u_sync_2 |
0.00 |
0.00 |
|
|
|
0.00 |
|
| gen_generic.u_impl_generic |
0.00 |
0.00 |
|
|
|
0.00 |
|
| gen_nrz_hs_protocol.req_sync |
0.00 |
0.00 |
|
|
|
0.00 |
|
| gen_generic.u_impl_generic |
0.00 |
0.00 |
|
|
|
0.00 |
|
| u_sync_1 |
0.00 |
0.00 |
|
|
|
0.00 |
|
| gen_generic.u_impl_generic |
0.00 |
0.00 |
|
|
|
0.00 |
|
| u_sync_2 |
0.00 |
0.00 |
|
|
|
0.00 |
|
| gen_generic.u_impl_generic |
0.00 |
0.00 |
|
|
|
0.00 |
|
| u_readsram |
0.00 |
0.00 |
0.00 |
|
0.00 |
0.00 |
|
| u_fifo |
0.00 |
0.00 |
0.00 |
|
|
0.00 |
|
| gen_normal_fifo.u_fifo_cnt |
0.00 |
0.00 |
0.00 |
|
|
0.00 |
|
| u_sram_fifo |
0.00 |
0.00 |
0.00 |
|
|
0.00 |
|
| gen_normal_fifo.u_fifo_cnt |
0.00 |
0.00 |
0.00 |
|
|
0.00 |
|
| u_reg |
94.43 |
99.53 |
99.30 |
73.96 |
|
99.35 |
100.00 |
| subtree... |
|
|
|
|
|
|
|
| u_rst_spi_out_sync |
0.00 |
0.00 |
|
|
|
0.00 |
|
| gen_generic.u_impl_generic |
0.00 |
0.00 |
|
|
|
0.00 |
|
| u_s2p |
0.00 |
0.00 |
0.00 |
|
|
0.00 |
|
| u_spi_tpm |
0.00 |
0.00 |
0.00 |
|
0.00 |
0.00 |
|
| u_arbiter |
0.00 |
0.00 |
0.00 |
|
|
0.00 |
|
| gen_arb_ppc.u_reqarb |
0.00 |
0.00 |
0.00 |
|
|
0.00 |
|
| u_req_fifo |
0.00 |
0.00 |
0.00 |
|
|
0.00 |
|
| gen_normal_fifo.u_fifo_cnt |
0.00 |
0.00 |
0.00 |
|
|
0.00 |
|
| u_cmdaddr_buffer |
0.00 |
0.00 |
0.00 |
|
|
0.00 |
|
| sync_rptr |
0.00 |
0.00 |
|
|
|
0.00 |
|
| gen_generic.u_impl_generic |
0.00 |
0.00 |
|
|
|
0.00 |
|
| u_sync_1 |
0.00 |
0.00 |
|
|
|
0.00 |
|
| gen_generic.u_impl_generic |
0.00 |
0.00 |
|
|
|
0.00 |
|
| u_sync_2 |
0.00 |
0.00 |
|
|
|
0.00 |
|
| gen_generic.u_impl_generic |
0.00 |
0.00 |
|
|
|
0.00 |
|
| sync_wptr |
0.00 |
0.00 |
|
|
|
0.00 |
|
| gen_generic.u_impl_generic |
0.00 |
0.00 |
|
|
|
0.00 |
|
| u_sync_1 |
0.00 |
0.00 |
|
|
|
0.00 |
|
| gen_generic.u_impl_generic |
0.00 |
0.00 |
|
|
|
0.00 |
|
| u_sync_2 |
0.00 |
0.00 |
|
|
|
0.00 |
|
| gen_generic.u_impl_generic |
0.00 |
0.00 |
|
|
|
0.00 |
|
| u_csb_sync_rst |
0.00 |
0.00 |
0.00 |
|
|
0.00 |
|
| g_sync.u_sync |
0.00 |
0.00 |
|
|
|
0.00 |
|
| gen_generic.u_impl_generic |
0.00 |
0.00 |
|
|
|
0.00 |
|
| u_sync_1 |
0.00 |
0.00 |
|
|
|
0.00 |
|
| gen_generic.u_impl_generic |
0.00 |
0.00 |
|
|
|
0.00 |
|
| u_sync_2 |
0.00 |
0.00 |
|
|
|
0.00 |
|
| gen_generic.u_impl_generic |
0.00 |
0.00 |
|
|
|
0.00 |
|
| u_hw_reg_slice |
0.00 |
0.00 |
|
|
|
|
|
| u_rdfifo_ready |
0.00 |
0.00 |
|
|
|
0.00 |
|
| gen_generic.u_impl_generic |
0.00 |
0.00 |
|
|
|
0.00 |
|
| u_sync_1 |
0.00 |
0.00 |
|
|
|
0.00 |
|
| gen_generic.u_impl_generic |
0.00 |
0.00 |
|
|
|
0.00 |
|
| u_sync_2 |
0.00 |
0.00 |
|
|
|
0.00 |
|
| gen_generic.u_impl_generic |
0.00 |
0.00 |
|
|
|
0.00 |
|
| u_sram_fifo |
0.00 |
0.00 |
0.00 |
|
|
0.00 |
|
| gen_normal_fifo.u_fifo_cnt |
0.00 |
0.00 |
0.00 |
|
|
0.00 |
|
| u_tpm_rd_buffer |
0.00 |
0.00 |
0.00 |
|
|
0.00 |
|
| u_tpm_wr_buffer |
0.00 |
0.00 |
0.00 |
|
|
0.00 |
|
| u_wrfifo_busy_sync |
0.00 |
0.00 |
|
|
|
0.00 |
|
| gen_generic.u_impl_generic |
0.00 |
0.00 |
|
|
|
0.00 |
|
| u_sync_1 |
0.00 |
0.00 |
|
|
|
0.00 |
|
| gen_generic.u_impl_generic |
0.00 |
0.00 |
|
|
|
0.00 |
|
| u_sync_2 |
0.00 |
0.00 |
|
|
|
0.00 |
|
| gen_generic.u_impl_generic |
0.00 |
0.00 |
|
|
|
0.00 |
|
| u_wrfifo_release_reqack |
0.00 |
0.00 |
0.00 |
|
|
0.00 |
|
| gen_nrz_hs_protocol.ack_sync |
0.00 |
0.00 |
|
|
|
0.00 |
|
| gen_generic.u_impl_generic |
0.00 |
0.00 |
|
|
|
0.00 |
|
| u_sync_1 |
0.00 |
0.00 |
|
|
|
0.00 |
|
| gen_generic.u_impl_generic |
0.00 |
0.00 |
|
|
|
0.00 |
|
| u_sync_2 |
0.00 |
0.00 |
|
|
|
0.00 |
|
| gen_generic.u_impl_generic |
0.00 |
0.00 |
|
|
|
0.00 |
|
| gen_nrz_hs_protocol.req_sync |
0.00 |
0.00 |
|
|
|
0.00 |
|
| gen_generic.u_impl_generic |
0.00 |
0.00 |
|
|
|
0.00 |
|
| u_sync_1 |
0.00 |
0.00 |
|
|
|
0.00 |
|
| gen_generic.u_impl_generic |
0.00 |
0.00 |
|
|
|
0.00 |
|
| u_sync_2 |
0.00 |
0.00 |
|
|
|
0.00 |
|
| gen_generic.u_impl_generic |
0.00 |
0.00 |
|
|
|
0.00 |
|
| u_spid_addr_4b |
0.00 |
0.00 |
0.00 |
|
|
0.00 |
|
| u_spi2sys_sync |
0.00 |
0.00 |
|
|
|
0.00 |
|
| gen_generic.u_impl_generic |
0.00 |
0.00 |
|
|
|
0.00 |
|
| u_sync_1 |
0.00 |
0.00 |
|
|
|
0.00 |
|
| gen_generic.u_impl_generic |
0.00 |
0.00 |
|
|
|
0.00 |
|
| u_sync_2 |
0.00 |
0.00 |
|
|
|
0.00 |
|
| gen_generic.u_impl_generic |
0.00 |
0.00 |
|
|
|
0.00 |
|
| u_sys2spi_sync |
0.00 |
0.00 |
0.00 |
|
|
0.00 |
|
| u_prim_sync_reqack |
0.00 |
0.00 |
0.00 |
|
|
0.00 |
|
| gen_nrz_hs_protocol.ack_sync |
0.00 |
0.00 |
|
|
|
0.00 |
|
| gen_generic.u_impl_generic |
0.00 |
0.00 |
|
|
|
0.00 |
|
| u_sync_1 |
0.00 |
0.00 |
|
|
|
0.00 |
|
| gen_generic.u_impl_generic |
0.00 |
0.00 |
|
|
|
0.00 |
|
| u_sync_2 |
0.00 |
0.00 |
|
|
|
0.00 |
|
| gen_generic.u_impl_generic |
0.00 |
0.00 |
|
|
|
0.00 |
|
| gen_nrz_hs_protocol.req_sync |
0.00 |
0.00 |
|
|
|
0.00 |
|
| gen_generic.u_impl_generic |
0.00 |
0.00 |
|
|
|
0.00 |
|
| u_sync_1 |
0.00 |
0.00 |
|
|
|
0.00 |
|
| gen_generic.u_impl_generic |
0.00 |
0.00 |
|
|
|
0.00 |
|
| u_sync_2 |
0.00 |
0.00 |
|
|
|
0.00 |
|
| gen_generic.u_impl_generic |
0.00 |
0.00 |
|
|
|
0.00 |
|
| u_spid_csb_sync |
0.00 |
0.00 |
0.00 |
|
|
0.00 |
|
| u_count_sync |
0.00 |
0.00 |
|
|
|
0.00 |
|
| gen_generic.u_impl_generic |
0.00 |
0.00 |
|
|
|
0.00 |
|
| u_sync_1 |
0.00 |
0.00 |
|
|
|
0.00 |
|
| gen_generic.u_impl_generic |
0.00 |
0.00 |
|
|
|
0.00 |
|
| u_sync_2 |
0.00 |
0.00 |
|
|
|
0.00 |
|
| gen_generic.u_impl_generic |
0.00 |
0.00 |
|
|
|
0.00 |
|
| u_spid_dpram |
0.00 |
0.00 |
0.00 |
|
|
0.00 |
|
| gen_ram1r1w.u_spi2sys_mem |
0.00 |
0.00 |
|
|
|
0.00 |
|
| u_mem |
0.00 |
0.00 |
|
|
|
0.00 |
|
| gen_generic.u_impl_generic |
0.00 |
0.00 |
|
|
|
0.00 |
|
| gen_ram1r1w.u_sys2spi_mem |
0.00 |
0.00 |
|
|
|
0.00 |
|
| u_mem |
0.00 |
0.00 |
|
|
|
0.00 |
|
| gen_generic.u_impl_generic |
0.00 |
0.00 |
|
|
|
0.00 |
|
| u_spid_status |
0.00 |
0.00 |
0.00 |
|
|
0.00 |
|
| u_csb_rst_scan_mux |
0.00 |
0.00 |
0.00 |
|
|
|
|
| gen_generic.u_impl_generic |
0.00 |
0.00 |
0.00 |
|
|
|
|
| u_sck2csb_status |
0.00 |
0.00 |
|
|
|
0.00 |
|
| gen_generic.u_impl_generic |
0.00 |
0.00 |
|
|
|
0.00 |
|
| u_stage_to_commit |
0.00 |
0.00 |
|
|
|
0.00 |
|
| gen_generic.u_impl_generic |
0.00 |
0.00 |
|
|
|
0.00 |
|
| u_sw_status_update_sync |
0.00 |
0.00 |
0.00 |
|
|
0.00 |
|
| sync_rptr |
0.00 |
0.00 |
|
|
|
0.00 |
|
| gen_generic.u_impl_generic |
0.00 |
0.00 |
|
|
|
0.00 |
|
| u_sync_1 |
0.00 |
0.00 |
|
|
|
0.00 |
|
| gen_generic.u_impl_generic |
0.00 |
0.00 |
|
|
|
0.00 |
|
| u_sync_2 |
0.00 |
0.00 |
|
|
|
0.00 |
|
| gen_generic.u_impl_generic |
0.00 |
0.00 |
|
|
|
0.00 |
|
| sync_wptr |
0.00 |
0.00 |
|
|
|
0.00 |
|
| gen_generic.u_impl_generic |
0.00 |
0.00 |
|
|
|
0.00 |
|
| u_sync_1 |
0.00 |
0.00 |
|
|
|
0.00 |
|
| gen_generic.u_impl_generic |
0.00 |
0.00 |
|
|
|
0.00 |
|
| u_sync_2 |
0.00 |
0.00 |
|
|
|
0.00 |
|
| gen_generic.u_impl_generic |
0.00 |
0.00 |
|
|
|
0.00 |
|
| u_sys_csb_syncd |
0.00 |
0.00 |
|
|
|
0.00 |
|
| gen_generic.u_impl_generic |
0.00 |
0.00 |
|
|
|
0.00 |
|
| u_sync_1 |
0.00 |
0.00 |
|
|
|
0.00 |
|
| gen_generic.u_impl_generic |
0.00 |
0.00 |
|
|
|
0.00 |
|
| u_sync_2 |
0.00 |
0.00 |
|
|
|
0.00 |
|
| gen_generic.u_impl_generic |
0.00 |
0.00 |
|
|
|
0.00 |
|
| u_sys_sram_arbiter |
0.00 |
0.00 |
0.00 |
|
|
0.00 |
|
| gen_arb_ppc.u_reqarb |
0.00 |
0.00 |
0.00 |
|
|
0.00 |
|
| u_req_fifo |
0.00 |
0.00 |
0.00 |
|
|
0.00 |
|
| gen_normal_fifo.u_fifo_cnt |
0.00 |
0.00 |
0.00 |
|
|
0.00 |
|
| u_sys_tpm_csb_sync |
0.00 |
0.00 |
|
|
|
0.00 |
|
| gen_generic.u_impl_generic |
0.00 |
0.00 |
|
|
|
0.00 |
|
| u_sync_1 |
0.00 |
0.00 |
|
|
|
0.00 |
|
| gen_generic.u_impl_generic |
0.00 |
0.00 |
|
|
|
0.00 |
|
| u_sync_2 |
0.00 |
0.00 |
|
|
|
0.00 |
|
| gen_generic.u_impl_generic |
0.00 |
0.00 |
|
|
|
0.00 |
|
| u_tlul2sram_egress |
0.00 |
0.00 |
0.00 |
|
|
0.00 |
|
| u_err |
0.00 |
0.00 |
0.00 |
|
|
0.00 |
|
| u_reqfifo |
0.00 |
0.00 |
0.00 |
|
|
0.00 |
|
| gen_normal_fifo.u_fifo_cnt |
0.00 |
0.00 |
0.00 |
|
|
0.00 |
|
| u_rsp_gen |
0.00 |
0.00 |
|
|
|
|
|
| u_rspfifo |
0.00 |
0.00 |
0.00 |
|
|
0.00 |
|
| gen_normal_fifo.u_fifo_cnt |
0.00 |
0.00 |
0.00 |
|
|
0.00 |
|
| u_sram_byte |
0.00 |
0.00 |
|
|
|
|
|
| u_sramreqfifo |
0.00 |
0.00 |
0.00 |
|
|
0.00 |
|
| gen_normal_fifo.u_fifo_cnt |
0.00 |
0.00 |
0.00 |
|
|
0.00 |
|
| u_tlul_data_integ_enc_data |
0.00 |
0.00 |
|
|
|
|
|
| u_data_gen |
0.00 |
0.00 |
|
|
|
|
|
| u_tlul_data_integ_enc_instr |
0.00 |
0.00 |
|
|
|
|
|
| u_data_gen |
0.00 |
0.00 |
|
|
|
|
|
| u_tlul2sram_ingress |
0.00 |
0.00 |
0.00 |
|
|
0.00 |
|
| u_err |
0.00 |
0.00 |
0.00 |
|
|
0.00 |
|
| u_reqfifo |
0.00 |
0.00 |
0.00 |
|
|
0.00 |
|
| gen_normal_fifo.u_fifo_cnt |
0.00 |
0.00 |
0.00 |
|
|
0.00 |
|
| u_rsp_gen |
0.00 |
0.00 |
|
|
|
|
|
| u_rspfifo |
0.00 |
0.00 |
0.00 |
|
|
0.00 |
|
| gen_normal_fifo.u_fifo_cnt |
0.00 |
0.00 |
0.00 |
|
|
0.00 |
|
| u_sram_byte |
0.00 |
0.00 |
|
|
|
|
|
| u_sramreqfifo |
0.00 |
0.00 |
0.00 |
|
|
0.00 |
|
| gen_normal_fifo.u_fifo_cnt |
0.00 |
0.00 |
0.00 |
|
|
0.00 |
|
| u_tlul_data_integ_enc_data |
0.00 |
0.00 |
|
|
|
|
|
| u_data_gen |
0.00 |
0.00 |
|
|
|
|
|
| u_tlul_data_integ_enc_instr |
0.00 |
0.00 |
|
|
|
|
|
| u_data_gen |
0.00 |
0.00 |
|
|
|
|
|
| u_tpm_csb_buf |
0.00 |
0.00 |
|
|
|
|
|
| gen_generic.u_impl_generic |
0.00 |
0.00 |
|
|
|
|
|
| u_tpm_csb_rst_scan_mux |
0.00 |
0.00 |
0.00 |
|
|
|
|
| gen_generic.u_impl_generic |
0.00 |
0.00 |
0.00 |
|
|
|
|
| u_tpm_csb_rst_sync |
0.00 |
0.00 |
0.00 |
|
|
0.00 |
|
| g_scan_mux.u_scan_mux |
0.00 |
0.00 |
0.00 |
|
|
|
|
| gen_generic.u_impl_generic |
0.00 |
0.00 |
0.00 |
|
|
|
|
| u_sync |
0.00 |
0.00 |
|
|
|
0.00 |
|
| gen_generic.u_impl_generic |
0.00 |
0.00 |
|
|
|
0.00 |
|
| u_sync_1 |
0.00 |
0.00 |
|
|
|
0.00 |
|
| gen_generic.u_impl_generic |
0.00 |
0.00 |
|
|
|
0.00 |
|
| u_sync_2 |
0.00 |
0.00 |
|
|
|
0.00 |
|
| gen_generic.u_impl_generic |
0.00 |
0.00 |
|
|
|
0.00 |
|
| u_tpm_rst_out_scan_mux |
0.00 |
0.00 |
0.00 |
|
|
|
|
| gen_generic.u_impl_generic |
0.00 |
0.00 |
0.00 |
|
|
|
|
| u_tpm_rst_out_sync |
0.00 |
0.00 |
|
|
|
0.00 |
|
| gen_generic.u_impl_generic |
0.00 |
0.00 |
|
|
|
0.00 |
|
| u_upload |
0.00 |
0.00 |
0.00 |
|
0.00 |
0.00 |
|
| u_addrfifo |
0.00 |
0.00 |
0.00 |
|
|
0.00 |
|
| u_sync_rptr_gray |
0.00 |
0.00 |
|
|
|
0.00 |
|
| gen_generic.u_impl_generic |
0.00 |
0.00 |
|
|
|
0.00 |
|
| u_sync_1 |
0.00 |
0.00 |
|
|
|
0.00 |
|
| gen_generic.u_impl_generic |
0.00 |
0.00 |
|
|
|
0.00 |
|
| u_sync_2 |
0.00 |
0.00 |
|
|
|
0.00 |
|
| gen_generic.u_impl_generic |
0.00 |
0.00 |
|
|
|
0.00 |
|
| u_sync_wptr_gray |
0.00 |
0.00 |
|
|
|
0.00 |
|
| gen_generic.u_impl_generic |
0.00 |
0.00 |
|
|
|
0.00 |
|
| u_sync_1 |
0.00 |
0.00 |
|
|
|
0.00 |
|
| gen_generic.u_impl_generic |
0.00 |
0.00 |
|
|
|
0.00 |
|
| u_sync_2 |
0.00 |
0.00 |
|
|
|
0.00 |
|
| gen_generic.u_impl_generic |
0.00 |
0.00 |
|
|
|
0.00 |
|
| u_arbiter |
0.00 |
0.00 |
0.00 |
|
|
0.00 |
|
| gen_arb_ppc.u_reqarb |
0.00 |
0.00 |
0.00 |
|
|
0.00 |
|
| u_req_fifo |
0.00 |
0.00 |
0.00 |
|
|
0.00 |
|
| gen_normal_fifo.u_fifo_cnt |
0.00 |
0.00 |
0.00 |
|
|
0.00 |
|
| u_cmdfifo |
0.00 |
0.00 |
0.00 |
|
|
0.00 |
|
| u_sync_rptr_gray |
0.00 |
0.00 |
|
|
|
0.00 |
|
| gen_generic.u_impl_generic |
0.00 |
0.00 |
|
|
|
0.00 |
|
| u_sync_1 |
0.00 |
0.00 |
|
|
|
0.00 |
|
| gen_generic.u_impl_generic |
0.00 |
0.00 |
|
|
|
0.00 |
|
| u_sync_2 |
0.00 |
0.00 |
|
|
|
0.00 |
|
| gen_generic.u_impl_generic |
0.00 |
0.00 |
|
|
|
0.00 |
|
| u_sync_wptr_gray |
0.00 |
0.00 |
|
|
|
0.00 |
|
| gen_generic.u_impl_generic |
0.00 |
0.00 |
|
|
|
0.00 |
|
| u_sync_1 |
0.00 |
0.00 |
|
|
|
0.00 |
|
| gen_generic.u_impl_generic |
0.00 |
0.00 |
|
|
|
0.00 |
|
| u_sync_2 |
0.00 |
0.00 |
|
|
|
0.00 |
|
| gen_generic.u_impl_generic |
0.00 |
0.00 |
|
|
|
0.00 |
|
| u_payload_buffer |
0.00 |
0.00 |
0.00 |
|
|
0.00 |
|
| u_payloadptr_clr_psync |
0.00 |
0.00 |
0.00 |
|
|
0.00 |
|
| prim_flop_2sync |
0.00 |
0.00 |
|
|
|
0.00 |
|
| gen_generic.u_impl_generic |
0.00 |
0.00 |
|
|
|
0.00 |
|
| u_sync_1 |
0.00 |
0.00 |
|
|
|
0.00 |
|
| gen_generic.u_impl_generic |
0.00 |
0.00 |
|
|
|
0.00 |
|
| u_sync_2 |
0.00 |
0.00 |
|
|
|
0.00 |
|
| gen_generic.u_impl_generic |
0.00 |
0.00 |
|
|
|
0.00 |
|
| u_sys_cmdfifo_set |
0.00 |
0.00 |
0.00 |
|
|
0.00 |
|
| u_count_sync |
0.00 |
0.00 |
|
|
|
0.00 |
|
| gen_generic.u_impl_generic |
0.00 |
0.00 |
|
|
|
0.00 |
|
| u_sync_1 |
0.00 |
0.00 |
|
|
|
0.00 |
|
| gen_generic.u_impl_generic |
0.00 |
0.00 |
|
|
|
0.00 |
|
| u_sync_2 |
0.00 |
0.00 |
|
|
|
0.00 |
|
| gen_generic.u_impl_generic |
0.00 |
0.00 |
|
|
|
0.00 |
|