| T843 |
/workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/41.spi_device_tpm_read_hw_reg.666163627 |
|
|
Aug 25 10:53:12 AM UTC 24 |
Aug 25 10:53:36 AM UTC 24 |
3878462775 ps |
| T844 |
/workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/42.spi_device_cfg_cmd.3177935560 |
|
|
Aug 25 10:53:32 AM UTC 24 |
Aug 25 10:53:36 AM UTC 24 |
29137286 ps |
| T845 |
/workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/42.spi_device_upload.1663673151 |
|
|
Aug 25 10:53:32 AM UTC 24 |
Aug 25 10:53:37 AM UTC 24 |
100139495 ps |
| T846 |
/workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/42.spi_device_pass_cmd_filtering.1761771722 |
|
|
Aug 25 10:53:29 AM UTC 24 |
Aug 25 10:53:38 AM UTC 24 |
3068010452 ps |
| T847 |
/workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/15.spi_device_flash_all.1280203378 |
|
|
Aug 25 10:45:45 AM UTC 24 |
Aug 25 10:53:42 AM UTC 24 |
43796674657 ps |
| T848 |
/workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/42.spi_device_read_buffer_direct.2709419870 |
|
|
Aug 25 10:53:36 AM UTC 24 |
Aug 25 10:53:44 AM UTC 24 |
266991933 ps |
| T849 |
/workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/21.spi_device_stress_all.2331411022 |
|
|
Aug 25 10:47:43 AM UTC 24 |
Aug 25 10:53:47 AM UTC 24 |
23213372199 ps |
| T850 |
/workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/13.spi_device_flash_and_tpm.3762745600 |
|
|
Aug 25 10:45:02 AM UTC 24 |
Aug 25 10:53:54 AM UTC 24 |
38130952539 ps |
| T851 |
/workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/41.spi_device_pass_cmd_filtering.433655976 |
|
|
Aug 25 10:53:15 AM UTC 24 |
Aug 25 10:53:55 AM UTC 24 |
5278132108 ps |
| T852 |
/workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/42.spi_device_alert_test.1363824580 |
|
|
Aug 25 10:53:39 AM UTC 24 |
Aug 25 10:53:55 AM UTC 24 |
10586634 ps |
| T853 |
/workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/43.spi_device_csb_read.1231377753 |
|
|
Aug 25 10:53:51 AM UTC 24 |
Aug 25 10:53:55 AM UTC 24 |
44608863 ps |
| T854 |
/workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/43.spi_device_tpm_sts_read.1737514343 |
|
|
Aug 25 10:53:55 AM UTC 24 |
Aug 25 10:53:57 AM UTC 24 |
23107450 ps |
| T855 |
/workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/40.spi_device_tpm_all.3892607374 |
|
|
Aug 25 10:52:55 AM UTC 24 |
Aug 25 10:53:57 AM UTC 24 |
141832633399 ps |
| T856 |
/workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/43.spi_device_tpm_rw.3424718802 |
|
|
Aug 25 10:53:56 AM UTC 24 |
Aug 25 10:53:59 AM UTC 24 |
217334683 ps |
| T857 |
/workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/42.spi_device_flash_mode.3879927977 |
|
|
Aug 25 10:53:34 AM UTC 24 |
Aug 25 10:54:00 AM UTC 24 |
1250117109 ps |
| T858 |
/workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/37.spi_device_flash_mode_ignore_cmds.2332688350 |
|
|
Aug 25 10:52:22 AM UTC 24 |
Aug 25 10:54:01 AM UTC 24 |
33532359897 ps |
| T859 |
/workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/43.spi_device_tpm_read_hw_reg.2184685261 |
|
|
Aug 25 10:53:52 AM UTC 24 |
Aug 25 10:54:03 AM UTC 24 |
1273628006 ps |
| T860 |
/workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/43.spi_device_cfg_cmd.1136442096 |
|
|
Aug 25 10:54:01 AM UTC 24 |
Aug 25 10:54:06 AM UTC 24 |
42259733 ps |
| T861 |
/workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/40.spi_device_mailbox.1636960587 |
|
|
Aug 25 10:52:59 AM UTC 24 |
Aug 25 10:54:06 AM UTC 24 |
44063807704 ps |
| T862 |
/workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/43.spi_device_pass_cmd_filtering.3097326800 |
|
|
Aug 25 10:53:56 AM UTC 24 |
Aug 25 10:54:08 AM UTC 24 |
7233909560 ps |
| T299 |
/workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/42.spi_device_pass_addr_payload_swap.2015302792 |
|
|
Aug 25 10:53:29 AM UTC 24 |
Aug 25 10:54:09 AM UTC 24 |
6344920557 ps |
| T863 |
/workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/41.spi_device_flash_all.1322726825 |
|
|
Aug 25 10:53:24 AM UTC 24 |
Aug 25 10:54:09 AM UTC 24 |
2124286577 ps |
| T864 |
/workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/43.spi_device_upload.2283321523 |
|
|
Aug 25 10:53:59 AM UTC 24 |
Aug 25 10:54:11 AM UTC 24 |
1247336050 ps |
| T865 |
/workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/41.spi_device_flash_mode_ignore_cmds.2319969987 |
|
|
Aug 25 10:53:22 AM UTC 24 |
Aug 25 10:54:11 AM UTC 24 |
1623321522 ps |
| T318 |
/workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/14.spi_device_flash_all.1193546620 |
|
|
Aug 25 10:45:16 AM UTC 24 |
Aug 25 10:54:13 AM UTC 24 |
47721970094 ps |
| T174 |
/workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/43.spi_device_stress_all.1868574843 |
|
|
Aug 25 10:54:10 AM UTC 24 |
Aug 25 10:54:13 AM UTC 24 |
119107613 ps |
| T866 |
/workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/43.spi_device_alert_test.1905476708 |
|
|
Aug 25 10:54:11 AM UTC 24 |
Aug 25 10:54:14 AM UTC 24 |
17417318 ps |
| T867 |
/workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/44.spi_device_csb_read.833153378 |
|
|
Aug 25 10:54:13 AM UTC 24 |
Aug 25 10:54:15 AM UTC 24 |
38303636 ps |
| T868 |
/workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/44.spi_device_tpm_sts_read.1087709298 |
|
|
Aug 25 10:54:15 AM UTC 24 |
Aug 25 10:54:17 AM UTC 24 |
152266966 ps |
| T303 |
/workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/22.spi_device_flash_all.1126731987 |
|
|
Aug 25 10:48:00 AM UTC 24 |
Aug 25 10:54:17 AM UTC 24 |
35762431032 ps |
| T869 |
/workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/42.spi_device_tpm_all.958363901 |
|
|
Aug 25 10:53:27 AM UTC 24 |
Aug 25 10:54:19 AM UTC 24 |
5214445737 ps |
| T870 |
/workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/43.spi_device_read_buffer_direct.2185555539 |
|
|
Aug 25 10:54:07 AM UTC 24 |
Aug 25 10:54:22 AM UTC 24 |
820756116 ps |
| T871 |
/workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/44.spi_device_tpm_rw.3114207018 |
|
|
Aug 25 10:54:16 AM UTC 24 |
Aug 25 10:54:22 AM UTC 24 |
162789563 ps |
| T872 |
/workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/44.spi_device_tpm_read_hw_reg.3337082037 |
|
|
Aug 25 10:54:14 AM UTC 24 |
Aug 25 10:54:22 AM UTC 24 |
516053122 ps |
| T873 |
/workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/43.spi_device_mailbox.1963261808 |
|
|
Aug 25 10:53:58 AM UTC 24 |
Aug 25 10:54:23 AM UTC 24 |
2529763827 ps |
| T874 |
/workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/37.spi_device_flash_all.2714481341 |
|
|
Aug 25 10:52:23 AM UTC 24 |
Aug 25 10:54:24 AM UTC 24 |
6661735530 ps |
| T320 |
/workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/26.spi_device_flash_and_tpm.598005685 |
|
|
Aug 25 10:49:19 AM UTC 24 |
Aug 25 10:54:25 AM UTC 24 |
46856806425 ps |
| T875 |
/workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/44.spi_device_pass_cmd_filtering.369942417 |
|
|
Aug 25 10:54:18 AM UTC 24 |
Aug 25 10:54:26 AM UTC 24 |
1044857478 ps |
| T300 |
/workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/30.spi_device_stress_all.2598904423 |
|
|
Aug 25 10:50:29 AM UTC 24 |
Aug 25 10:54:26 AM UTC 24 |
23251311687 ps |
| T876 |
/workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/46.spi_device_tpm_all.3379979735 |
|
|
Aug 25 10:54:51 AM UTC 24 |
Aug 25 10:55:43 AM UTC 24 |
34186366649 ps |
| T877 |
/workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/44.spi_device_intercept.6765701 |
|
|
Aug 25 10:54:19 AM UTC 24 |
Aug 25 10:54:27 AM UTC 24 |
291422459 ps |
| T878 |
/workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/44.spi_device_mailbox.1522166582 |
|
|
Aug 25 10:54:22 AM UTC 24 |
Aug 25 10:54:30 AM UTC 24 |
481092408 ps |
| T879 |
/workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/43.spi_device_flash_mode.1957485113 |
|
|
Aug 25 10:54:03 AM UTC 24 |
Aug 25 10:54:31 AM UTC 24 |
9274673023 ps |
| T880 |
/workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/43.spi_device_intercept.3952740397 |
|
|
Aug 25 10:53:58 AM UTC 24 |
Aug 25 10:54:31 AM UTC 24 |
2415898155 ps |
| T881 |
/workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/43.spi_device_pass_addr_payload_swap.4149260427 |
|
|
Aug 25 10:53:56 AM UTC 24 |
Aug 25 10:54:34 AM UTC 24 |
34175971400 ps |
| T882 |
/workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/44.spi_device_alert_test.3334706723 |
|
|
Aug 25 10:54:31 AM UTC 24 |
Aug 25 10:54:34 AM UTC 24 |
14257441 ps |
| T883 |
/workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/44.spi_device_pass_addr_payload_swap.3816686420 |
|
|
Aug 25 10:54:18 AM UTC 24 |
Aug 25 10:54:34 AM UTC 24 |
6384092326 ps |
| T884 |
/workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/44.spi_device_cfg_cmd.3142118935 |
|
|
Aug 25 10:54:24 AM UTC 24 |
Aug 25 10:54:34 AM UTC 24 |
446119914 ps |
| T885 |
/workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/45.spi_device_csb_read.3054909524 |
|
|
Aug 25 10:54:33 AM UTC 24 |
Aug 25 10:54:35 AM UTC 24 |
16191980 ps |
| T886 |
/workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/39.spi_device_mailbox.4050257103 |
|
|
Aug 25 10:52:45 AM UTC 24 |
Aug 25 10:54:36 AM UTC 24 |
85857104728 ps |
| T887 |
/workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/45.spi_device_tpm_read_hw_reg.2965146015 |
|
|
Aug 25 10:54:35 AM UTC 24 |
Aug 25 10:54:37 AM UTC 24 |
10682180 ps |
| T888 |
/workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/45.spi_device_tpm_sts_read.4071029896 |
|
|
Aug 25 10:54:35 AM UTC 24 |
Aug 25 10:54:38 AM UTC 24 |
59172952 ps |
| T889 |
/workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/44.spi_device_tpm_all.239131269 |
|
|
Aug 25 10:54:14 AM UTC 24 |
Aug 25 10:54:38 AM UTC 24 |
2950565498 ps |
| T284 |
/workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/45.spi_device_flash_all.2359481374 |
|
|
Aug 25 10:54:41 AM UTC 24 |
Aug 25 10:55:44 AM UTC 24 |
9777188680 ps |
| T890 |
/workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/43.spi_device_tpm_all.429150909 |
|
|
Aug 25 10:53:55 AM UTC 24 |
Aug 25 10:54:38 AM UTC 24 |
7562700333 ps |
| T891 |
/workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/45.spi_device_tpm_rw.3240771718 |
|
|
Aug 25 10:54:35 AM UTC 24 |
Aug 25 10:54:38 AM UTC 24 |
244422424 ps |
| T892 |
/workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/41.spi_device_mailbox.3457757298 |
|
|
Aug 25 10:53:17 AM UTC 24 |
Aug 25 10:54:39 AM UTC 24 |
11205024825 ps |
| T893 |
/workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/42.spi_device_flash_all.3901822371 |
|
|
Aug 25 10:53:37 AM UTC 24 |
Aug 25 10:54:39 AM UTC 24 |
11679624546 ps |
| T894 |
/workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/44.spi_device_upload.2896217750 |
|
|
Aug 25 10:54:23 AM UTC 24 |
Aug 25 10:54:41 AM UTC 24 |
2690968392 ps |
| T895 |
/workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/45.spi_device_pass_addr_payload_swap.2835762123 |
|
|
Aug 25 10:54:37 AM UTC 24 |
Aug 25 10:54:43 AM UTC 24 |
233430540 ps |
| T896 |
/workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/44.spi_device_read_buffer_direct.2210534085 |
|
|
Aug 25 10:54:26 AM UTC 24 |
Aug 25 10:54:43 AM UTC 24 |
897452142 ps |
| T897 |
/workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/44.spi_device_flash_all.374888740 |
|
|
Aug 25 10:54:27 AM UTC 24 |
Aug 25 10:54:46 AM UTC 24 |
1632506007 ps |
| T898 |
/workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/45.spi_device_read_buffer_direct.2505610469 |
|
|
Aug 25 10:54:40 AM UTC 24 |
Aug 25 10:54:46 AM UTC 24 |
325595516 ps |
| T899 |
/workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/45.spi_device_intercept.27239122 |
|
|
Aug 25 10:54:38 AM UTC 24 |
Aug 25 10:54:47 AM UTC 24 |
1345040556 ps |
| T900 |
/workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/45.spi_device_upload.3078285114 |
|
|
Aug 25 10:54:39 AM UTC 24 |
Aug 25 10:54:47 AM UTC 24 |
585367365 ps |
| T901 |
/workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/45.spi_device_cfg_cmd.1013326169 |
|
|
Aug 25 10:54:40 AM UTC 24 |
Aug 25 10:54:50 AM UTC 24 |
1022991027 ps |
| T902 |
/workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/45.spi_device_alert_test.1629378980 |
|
|
Aug 25 10:54:48 AM UTC 24 |
Aug 25 10:54:50 AM UTC 24 |
26677446 ps |
| T903 |
/workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/46.spi_device_csb_read.897407326 |
|
|
Aug 25 10:54:48 AM UTC 24 |
Aug 25 10:54:50 AM UTC 24 |
184409171 ps |
| T904 |
/workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/46.spi_device_tpm_sts_read.4064634777 |
|
|
Aug 25 10:54:51 AM UTC 24 |
Aug 25 10:54:53 AM UTC 24 |
67829258 ps |
| T905 |
/workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/46.spi_device_tpm_read_hw_reg.1642355013 |
|
|
Aug 25 10:54:48 AM UTC 24 |
Aug 25 10:54:55 AM UTC 24 |
811451704 ps |
| T906 |
/workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/46.spi_device_tpm_rw.3055188438 |
|
|
Aug 25 10:54:51 AM UTC 24 |
Aug 25 10:54:55 AM UTC 24 |
161175743 ps |
| T907 |
/workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/45.spi_device_pass_cmd_filtering.1205524109 |
|
|
Aug 25 10:54:36 AM UTC 24 |
Aug 25 10:54:55 AM UTC 24 |
11915248995 ps |
| T908 |
/workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/42.spi_device_flash_mode_ignore_cmds.2700021428 |
|
|
Aug 25 10:53:36 AM UTC 24 |
Aug 25 10:54:58 AM UTC 24 |
4690635729 ps |
| T909 |
/workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/46.spi_device_pass_cmd_filtering.555785421 |
|
|
Aug 25 10:54:54 AM UTC 24 |
Aug 25 10:54:59 AM UTC 24 |
438252771 ps |
| T910 |
/workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/45.spi_device_tpm_all.442360396 |
|
|
Aug 25 10:54:35 AM UTC 24 |
Aug 25 10:54:59 AM UTC 24 |
6137687791 ps |
| T911 |
/workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/45.spi_device_mailbox.1961931436 |
|
|
Aug 25 10:54:38 AM UTC 24 |
Aug 25 10:54:59 AM UTC 24 |
5200331364 ps |
| T912 |
/workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/32.spi_device_flash_and_tpm.482124854 |
|
|
Aug 25 10:50:59 AM UTC 24 |
Aug 25 10:55:03 AM UTC 24 |
63142544733 ps |
| T913 |
/workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/46.spi_device_intercept.370811697 |
|
|
Aug 25 10:54:56 AM UTC 24 |
Aug 25 10:55:05 AM UTC 24 |
184128786 ps |
| T914 |
/workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/44.spi_device_flash_mode.3304526666 |
|
|
Aug 25 10:54:24 AM UTC 24 |
Aug 25 10:55:06 AM UTC 24 |
6872071807 ps |
| T293 |
/workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/39.spi_device_flash_and_tpm_min_idle.3448821248 |
|
|
Aug 25 10:52:49 AM UTC 24 |
Aug 25 10:55:10 AM UTC 24 |
4883730316 ps |
| T915 |
/workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/46.spi_device_read_buffer_direct.486753404 |
|
|
Aug 25 10:55:04 AM UTC 24 |
Aug 25 10:55:11 AM UTC 24 |
520259444 ps |
| T916 |
/workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/46.spi_device_cfg_cmd.2091490239 |
|
|
Aug 25 10:55:00 AM UTC 24 |
Aug 25 10:55:16 AM UTC 24 |
14920286636 ps |
| T917 |
/workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/46.spi_device_alert_test.2631866041 |
|
|
Aug 25 10:55:17 AM UTC 24 |
Aug 25 10:55:19 AM UTC 24 |
29383238 ps |
| T918 |
/workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/46.spi_device_pass_addr_payload_swap.346020057 |
|
|
Aug 25 10:54:55 AM UTC 24 |
Aug 25 10:55:20 AM UTC 24 |
13882006122 ps |
| T919 |
/workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/47.spi_device_csb_read.3443544576 |
|
|
Aug 25 10:55:20 AM UTC 24 |
Aug 25 10:55:22 AM UTC 24 |
51504153 ps |
| T920 |
/workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/43.spi_device_flash_mode_ignore_cmds.1679870802 |
|
|
Aug 25 10:54:04 AM UTC 24 |
Aug 25 10:55:24 AM UTC 24 |
8630428253 ps |
| T379 |
/workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/45.spi_device_flash_mode.3593294097 |
|
|
Aug 25 10:54:40 AM UTC 24 |
Aug 25 10:55:25 AM UTC 24 |
2024325975 ps |
| T921 |
/workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/47.spi_device_tpm_sts_read.3220456273 |
|
|
Aug 25 10:55:24 AM UTC 24 |
Aug 25 10:55:26 AM UTC 24 |
42209342 ps |
| T922 |
/workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/47.spi_device_tpm_rw.1604989967 |
|
|
Aug 25 10:55:26 AM UTC 24 |
Aug 25 10:55:28 AM UTC 24 |
12682629 ps |
| T923 |
/workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/40.spi_device_flash_mode_ignore_cmds.1305309442 |
|
|
Aug 25 10:53:03 AM UTC 24 |
Aug 25 10:55:29 AM UTC 24 |
11482312419 ps |
| T924 |
/workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/46.spi_device_upload.97772354 |
|
|
Aug 25 10:55:00 AM UTC 24 |
Aug 25 10:55:31 AM UTC 24 |
17803814744 ps |
| T925 |
/workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/47.spi_device_intercept.1532615361 |
|
|
Aug 25 10:55:30 AM UTC 24 |
Aug 25 10:55:37 AM UTC 24 |
272649396 ps |
| T321 |
/workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/28.spi_device_stress_all.857454932 |
|
|
Aug 25 10:49:59 AM UTC 24 |
Aug 25 10:55:39 AM UTC 24 |
49465091684 ps |
| T926 |
/workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/35.spi_device_flash_and_tpm_min_idle.1662622542 |
|
|
Aug 25 10:51:49 AM UTC 24 |
Aug 25 10:55:39 AM UTC 24 |
32807983689 ps |
| T311 |
/workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/45.spi_device_flash_and_tpm.1026574517 |
|
|
Aug 25 10:54:43 AM UTC 24 |
Aug 25 10:55:40 AM UTC 24 |
4196041218 ps |
| T927 |
/workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/47.spi_device_upload.1481961521 |
|
|
Aug 25 10:55:38 AM UTC 24 |
Aug 25 10:55:43 AM UTC 24 |
103066305 ps |
| T286 |
/workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/36.spi_device_flash_all.436917239 |
|
|
Aug 25 10:52:04 AM UTC 24 |
Aug 25 10:55:44 AM UTC 24 |
19620929334 ps |
| T928 |
/workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/46.spi_device_flash_mode.939203002 |
|
|
Aug 25 10:55:00 AM UTC 24 |
Aug 25 10:55:46 AM UTC 24 |
33776973195 ps |
| T929 |
/workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/47.spi_device_flash_mode.436638033 |
|
|
Aug 25 10:55:40 AM UTC 24 |
Aug 25 10:55:47 AM UTC 24 |
316579011 ps |
| T930 |
/workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/47.spi_device_pass_cmd_filtering.3737974847 |
|
|
Aug 25 10:55:27 AM UTC 24 |
Aug 25 10:55:48 AM UTC 24 |
6528576300 ps |
| T931 |
/workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/40.spi_device_flash_and_tpm_min_idle.1128082538 |
|
|
Aug 25 10:53:07 AM UTC 24 |
Aug 25 10:55:48 AM UTC 24 |
16738135413 ps |
| T932 |
/workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/47.spi_device_alert_test.1097686609 |
|
|
Aug 25 10:55:47 AM UTC 24 |
Aug 25 10:55:49 AM UTC 24 |
41442621 ps |
| T933 |
/workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/46.spi_device_mailbox.393757446 |
|
|
Aug 25 10:54:56 AM UTC 24 |
Aug 25 10:55:50 AM UTC 24 |
5378741706 ps |
| T934 |
/workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/42.spi_device_mailbox.1781792588 |
|
|
Aug 25 10:53:32 AM UTC 24 |
Aug 25 10:55:51 AM UTC 24 |
10703816191 ps |
| T935 |
/workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/48.spi_device_csb_read.4239234463 |
|
|
Aug 25 10:55:48 AM UTC 24 |
Aug 25 10:55:51 AM UTC 24 |
41854410 ps |
| T936 |
/workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/41.spi_device_flash_and_tpm_min_idle.672124950 |
|
|
Aug 25 10:53:24 AM UTC 24 |
Aug 25 10:55:52 AM UTC 24 |
12284580062 ps |
| T937 |
/workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/48.spi_device_tpm_rw.3870802075 |
|
|
Aug 25 10:55:50 AM UTC 24 |
Aug 25 10:55:53 AM UTC 24 |
29633590 ps |
| T938 |
/workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/48.spi_device_tpm_sts_read.2649433722 |
|
|
Aug 25 10:55:50 AM UTC 24 |
Aug 25 10:55:53 AM UTC 24 |
73628947 ps |
| T939 |
/workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/48.spi_device_tpm_read_hw_reg.4232025734 |
|
|
Aug 25 10:55:48 AM UTC 24 |
Aug 25 10:55:54 AM UTC 24 |
289901563 ps |
| T940 |
/workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/47.spi_device_stress_all.8134252 |
|
|
Aug 25 10:55:46 AM UTC 24 |
Aug 25 10:55:54 AM UTC 24 |
512665918 ps |
| T941 |
/workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/48.spi_device_pass_addr_payload_swap.1998794560 |
|
|
Aug 25 10:55:52 AM UTC 24 |
Aug 25 10:55:57 AM UTC 24 |
663953000 ps |
| T942 |
/workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/48.spi_device_tpm_all.1391153797 |
|
|
Aug 25 10:55:49 AM UTC 24 |
Aug 25 10:55:58 AM UTC 24 |
876551945 ps |
| T943 |
/workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/47.spi_device_tpm_read_hw_reg.3165460612 |
|
|
Aug 25 10:55:21 AM UTC 24 |
Aug 25 10:56:02 AM UTC 24 |
49228429682 ps |
| T944 |
/workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/48.spi_device_pass_cmd_filtering.2308212226 |
|
|
Aug 25 10:55:52 AM UTC 24 |
Aug 25 10:56:03 AM UTC 24 |
2648384485 ps |
| T945 |
/workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/48.spi_device_cfg_cmd.1841197380 |
|
|
Aug 25 10:55:55 AM UTC 24 |
Aug 25 10:56:03 AM UTC 24 |
432050600 ps |
| T319 |
/workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/34.spi_device_stress_all.110654898 |
|
|
Aug 25 10:51:35 AM UTC 24 |
Aug 25 10:56:04 AM UTC 24 |
79328652844 ps |
| T272 |
/workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/23.spi_device_flash_all.794981821 |
|
|
Aug 25 10:48:19 AM UTC 24 |
Aug 25 10:56:07 AM UTC 24 |
47692915642 ps |
| T946 |
/workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/47.spi_device_tpm_all.812740251 |
|
|
Aug 25 10:55:23 AM UTC 24 |
Aug 25 10:56:08 AM UTC 24 |
5691935602 ps |
| T947 |
/workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/48.spi_device_flash_mode.1246664571 |
|
|
Aug 25 10:55:55 AM UTC 24 |
Aug 25 10:56:08 AM UTC 24 |
272613240 ps |
| T948 |
/workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/47.spi_device_read_buffer_direct.2109800366 |
|
|
Aug 25 10:55:43 AM UTC 24 |
Aug 25 10:56:10 AM UTC 24 |
1606853019 ps |
| T949 |
/workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/48.spi_device_alert_test.3722417771 |
|
|
Aug 25 10:56:08 AM UTC 24 |
Aug 25 10:56:10 AM UTC 24 |
83388149 ps |
| T950 |
/workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/49.spi_device_csb_read.1242315605 |
|
|
Aug 25 10:56:08 AM UTC 24 |
Aug 25 10:56:10 AM UTC 24 |
56116289 ps |
| T951 |
/workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/48.spi_device_read_buffer_direct.1687902241 |
|
|
Aug 25 10:55:59 AM UTC 24 |
Aug 25 10:56:10 AM UTC 24 |
1728775659 ps |
| T952 |
/workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/49.spi_device_tpm_all.3260195951 |
|
|
Aug 25 10:56:10 AM UTC 24 |
Aug 25 10:56:12 AM UTC 24 |
23351018 ps |
| T953 |
/workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/38.spi_device_flash_mode_ignore_cmds.878760784 |
|
|
Aug 25 10:52:33 AM UTC 24 |
Aug 25 10:56:13 AM UTC 24 |
19118197108 ps |
| T954 |
/workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/49.spi_device_tpm_sts_read.2712516631 |
|
|
Aug 25 10:56:11 AM UTC 24 |
Aug 25 10:56:14 AM UTC 24 |
180604323 ps |
| T955 |
/workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/47.spi_device_pass_addr_payload_swap.1492059413 |
|
|
Aug 25 10:55:30 AM UTC 24 |
Aug 25 10:56:16 AM UTC 24 |
32964857781 ps |
| T956 |
/workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/49.spi_device_tpm_rw.4037883348 |
|
|
Aug 25 10:56:12 AM UTC 24 |
Aug 25 10:56:17 AM UTC 24 |
554613258 ps |
| T957 |
/workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/40.spi_device_flash_all.376829923 |
|
|
Aug 25 10:53:05 AM UTC 24 |
Aug 25 10:56:18 AM UTC 24 |
67896453181 ps |
| T958 |
/workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/49.spi_device_pass_addr_payload_swap.29784642 |
|
|
Aug 25 10:56:14 AM UTC 24 |
Aug 25 10:56:18 AM UTC 24 |
30067810 ps |
| T959 |
/workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/49.spi_device_intercept.1695989799 |
|
|
Aug 25 10:56:14 AM UTC 24 |
Aug 25 10:56:18 AM UTC 24 |
35331135 ps |
| T960 |
/workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/49.spi_device_pass_cmd_filtering.1871631917 |
|
|
Aug 25 10:56:12 AM UTC 24 |
Aug 25 10:56:19 AM UTC 24 |
1004139427 ps |
| T961 |
/workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/48.spi_device_intercept.3710131796 |
|
|
Aug 25 10:55:53 AM UTC 24 |
Aug 25 10:56:20 AM UTC 24 |
2195078061 ps |
| T962 |
/workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/33.spi_device_stress_all.3787934158 |
|
|
Aug 25 10:51:17 AM UTC 24 |
Aug 25 10:56:24 AM UTC 24 |
90597596737 ps |
| T963 |
/workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/45.spi_device_flash_mode_ignore_cmds.3843956460 |
|
|
Aug 25 10:54:40 AM UTC 24 |
Aug 25 10:56:24 AM UTC 24 |
30274589760 ps |
| T964 |
/workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/48.spi_device_flash_mode_ignore_cmds.1906741512 |
|
|
Aug 25 10:55:57 AM UTC 24 |
Aug 25 10:56:24 AM UTC 24 |
758553762 ps |
| T965 |
/workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/49.spi_device_cfg_cmd.772772018 |
|
|
Aug 25 10:56:18 AM UTC 24 |
Aug 25 10:56:24 AM UTC 24 |
161647312 ps |
| T966 |
/workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/47.spi_device_flash_and_tpm_min_idle.1620331417 |
|
|
Aug 25 10:55:46 AM UTC 24 |
Aug 25 10:56:26 AM UTC 24 |
4542495680 ps |
| T967 |
/workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/48.spi_device_flash_all.3321643785 |
|
|
Aug 25 10:56:04 AM UTC 24 |
Aug 25 10:56:26 AM UTC 24 |
2393421220 ps |
| T304 |
/workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/27.spi_device_flash_mode_ignore_cmds.2853782357 |
|
|
Aug 25 10:49:30 AM UTC 24 |
Aug 25 10:56:26 AM UTC 24 |
44129888606 ps |
| T968 |
/workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/49.spi_device_flash_mode.838216516 |
|
|
Aug 25 10:56:19 AM UTC 24 |
Aug 25 10:56:26 AM UTC 24 |
189605662 ps |
| T969 |
/workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/49.spi_device_alert_test.155225378 |
|
|
Aug 25 10:56:25 AM UTC 24 |
Aug 25 10:56:27 AM UTC 24 |
12508514 ps |
| T970 |
/workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/37.spi_device_flash_and_tpm_min_idle.2425267263 |
|
|
Aug 25 10:52:25 AM UTC 24 |
Aug 25 10:56:29 AM UTC 24 |
59143829728 ps |
| T971 |
/workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/49.spi_device_upload.2846600481 |
|
|
Aug 25 10:56:17 AM UTC 24 |
Aug 25 10:56:29 AM UTC 24 |
12921170804 ps |
| T972 |
/workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/49.spi_device_tpm_read_hw_reg.1980110940 |
|
|
Aug 25 10:56:09 AM UTC 24 |
Aug 25 10:56:30 AM UTC 24 |
13697959441 ps |
| T973 |
/workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/47.spi_device_flash_and_tpm.694962712 |
|
|
Aug 25 10:55:45 AM UTC 24 |
Aug 25 10:56:32 AM UTC 24 |
4890794893 ps |
| T974 |
/workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/32.spi_device_flash_mode_ignore_cmds.563603721 |
|
|
Aug 25 10:50:57 AM UTC 24 |
Aug 25 10:56:32 AM UTC 24 |
29223064158 ps |
| T975 |
/workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/36.spi_device_stress_all.4078757883 |
|
|
Aug 25 10:52:06 AM UTC 24 |
Aug 25 10:56:38 AM UTC 24 |
100259676569 ps |
| T976 |
/workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/46.spi_device_flash_and_tpm_min_idle.1132383071 |
|
|
Aug 25 10:55:11 AM UTC 24 |
Aug 25 10:56:39 AM UTC 24 |
119200098767 ps |
| T977 |
/workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/49.spi_device_read_buffer_direct.1887456166 |
|
|
Aug 25 10:56:20 AM UTC 24 |
Aug 25 10:56:39 AM UTC 24 |
2268552658 ps |
| T978 |
/workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/49.spi_device_flash_all.719225007 |
|
|
Aug 25 10:56:20 AM UTC 24 |
Aug 25 10:56:44 AM UTC 24 |
979115682 ps |
| T979 |
/workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/43.spi_device_flash_all.3795859997 |
|
|
Aug 25 10:54:07 AM UTC 24 |
Aug 25 10:56:47 AM UTC 24 |
134803472641 ps |
| T980 |
/workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/48.spi_device_upload.670357704 |
|
|
Aug 25 10:55:54 AM UTC 24 |
Aug 25 10:56:51 AM UTC 24 |
18708696615 ps |
| T981 |
/workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/46.spi_device_flash_and_tpm.173462364 |
|
|
Aug 25 10:55:07 AM UTC 24 |
Aug 25 10:56:51 AM UTC 24 |
6286291480 ps |
| T982 |
/workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/44.spi_device_flash_and_tpm_min_idle.3637172397 |
|
|
Aug 25 10:54:27 AM UTC 24 |
Aug 25 10:56:51 AM UTC 24 |
46579539766 ps |
| T275 |
/workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/13.spi_device_flash_mode_ignore_cmds.965721216 |
|
|
Aug 25 10:44:54 AM UTC 24 |
Aug 25 10:56:52 AM UTC 24 |
233162520732 ps |
| T983 |
/workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/39.spi_device_flash_and_tpm.769170674 |
|
|
Aug 25 10:52:48 AM UTC 24 |
Aug 25 10:56:58 AM UTC 24 |
19855759874 ps |
| T291 |
/workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/43.spi_device_flash_and_tpm.236301588 |
|
|
Aug 25 10:54:09 AM UTC 24 |
Aug 25 10:57:16 AM UTC 24 |
51230057616 ps |
| T984 |
/workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/49.spi_device_mailbox.4093998918 |
|
|
Aug 25 10:56:15 AM UTC 24 |
Aug 25 10:57:34 AM UTC 24 |
20883978277 ps |
| T985 |
/workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/47.spi_device_mailbox.4022643713 |
|
|
Aug 25 10:55:32 AM UTC 24 |
Aug 25 10:57:36 AM UTC 24 |
41923059588 ps |
| T305 |
/workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/22.spi_device_flash_and_tpm_min_idle.688594640 |
|
|
Aug 25 10:48:03 AM UTC 24 |
Aug 25 10:57:37 AM UTC 24 |
401032421454 ps |
| T986 |
/workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/48.spi_device_mailbox.1430813971 |
|
|
Aug 25 10:55:54 AM UTC 24 |
Aug 25 10:57:45 AM UTC 24 |
45173540476 ps |
| T270 |
/workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/47.spi_device_flash_mode_ignore_cmds.767822194 |
|
|
Aug 25 10:55:41 AM UTC 24 |
Aug 25 10:57:48 AM UTC 24 |
3430233238 ps |
| T987 |
/workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/42.spi_device_stress_all.2018440582 |
|
|
Aug 25 10:53:38 AM UTC 24 |
Aug 25 10:57:53 AM UTC 24 |
56294017722 ps |
| T988 |
/workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/38.spi_device_flash_all.75997848 |
|
|
Aug 25 10:52:36 AM UTC 24 |
Aug 25 10:57:56 AM UTC 24 |
28845957060 ps |
| T989 |
/workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/49.spi_device_flash_and_tpm_min_idle.626543689 |
|
|
Aug 25 10:56:25 AM UTC 24 |
Aug 25 10:58:00 AM UTC 24 |
6387532047 ps |
| T990 |
/workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/48.spi_device_flash_and_tpm.836010281 |
|
|
Aug 25 10:56:04 AM UTC 24 |
Aug 25 10:58:04 AM UTC 24 |
25389916587 ps |
| T991 |
/workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/34.spi_device_flash_mode_ignore_cmds.206934702 |
|
|
Aug 25 10:51:30 AM UTC 24 |
Aug 25 10:58:19 AM UTC 24 |
30868572064 ps |
| T306 |
/workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/41.spi_device_flash_and_tpm.1296102744 |
|
|
Aug 25 10:53:24 AM UTC 24 |
Aug 25 10:58:24 AM UTC 24 |
82799619276 ps |
| T301 |
/workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/7.spi_device_stress_all.1694683275 |
|
|
Aug 25 10:43:06 AM UTC 24 |
Aug 25 10:58:41 AM UTC 24 |
65954917992 ps |
| T296 |
/workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/36.spi_device_flash_and_tpm_min_idle.4154878350 |
|
|
Aug 25 10:52:05 AM UTC 24 |
Aug 25 10:58:44 AM UTC 24 |
67475298130 ps |
| T317 |
/workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/44.spi_device_flash_and_tpm.1022092478 |
|
|
Aug 25 10:54:27 AM UTC 24 |
Aug 25 10:58:50 AM UTC 24 |
11209736530 ps |
| T992 |
/workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/35.spi_device_flash_all.2940839557 |
|
|
Aug 25 10:51:47 AM UTC 24 |
Aug 25 10:58:59 AM UTC 24 |
210377148022 ps |
| T345 |
/workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/2.spi_device_stress_all.398718359 |
|
|
Aug 25 10:42:07 AM UTC 24 |
Aug 25 10:59:01 AM UTC 24 |
78705072748 ps |
| T993 |
/workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/35.spi_device_stress_all.2367593358 |
|
|
Aug 25 10:51:49 AM UTC 24 |
Aug 25 10:59:08 AM UTC 24 |
34698107738 ps |
| T994 |
/workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/48.spi_device_stress_all.3300449350 |
|
|
Aug 25 10:56:05 AM UTC 24 |
Aug 25 10:59:20 AM UTC 24 |
10499756441 ps |
| T995 |
/workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/47.spi_device_flash_all.1269071089 |
|
|
Aug 25 10:55:43 AM UTC 24 |
Aug 25 10:59:25 AM UTC 24 |
17580299496 ps |
| T996 |
/workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/49.spi_device_flash_mode_ignore_cmds.1008745629 |
|
|
Aug 25 10:56:19 AM UTC 24 |
Aug 25 10:59:33 AM UTC 24 |
16530622963 ps |
| T997 |
/workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/39.spi_device_flash_all.91046112 |
|
|
Aug 25 10:52:48 AM UTC 24 |
Aug 25 10:59:48 AM UTC 24 |
83544839424 ps |
| T287 |
/workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/28.spi_device_flash_and_tpm_min_idle.3809049377 |
|
|
Aug 25 10:49:59 AM UTC 24 |
Aug 25 10:59:58 AM UTC 24 |
92262456518 ps |
| T316 |
/workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/17.spi_device_stress_all.760369962 |
|
|
Aug 25 10:46:22 AM UTC 24 |
Aug 25 11:00:13 AM UTC 24 |
125854038598 ps |
| T322 |
/workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/42.spi_device_flash_and_tpm_min_idle.983844632 |
|
|
Aug 25 10:53:38 AM UTC 24 |
Aug 25 11:01:00 AM UTC 24 |
135497536039 ps |
| T998 |
/workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/46.spi_device_flash_mode_ignore_cmds.508030590 |
|
|
Aug 25 10:55:01 AM UTC 24 |
Aug 25 11:01:19 AM UTC 24 |
34191385062 ps |
| T276 |
/workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/24.spi_device_stress_all.4001548415 |
|
|
Aug 25 10:48:41 AM UTC 24 |
Aug 25 11:01:40 AM UTC 24 |
195723134084 ps |
| T999 |
/workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/43.spi_device_flash_and_tpm_min_idle.3649894940 |
|
|
Aug 25 10:54:10 AM UTC 24 |
Aug 25 11:01:42 AM UTC 24 |
38499099451 ps |
| T273 |
/workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/35.spi_device_flash_and_tpm.1375219695 |
|
|
Aug 25 10:51:49 AM UTC 24 |
Aug 25 11:01:50 AM UTC 24 |
202881732967 ps |
| T1000 |
/workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/44.spi_device_stress_all.3862210245 |
|
|
Aug 25 10:54:31 AM UTC 24 |
Aug 25 11:02:01 AM UTC 24 |
74136146093 ps |
| T294 |
/workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/28.spi_device_flash_and_tpm.1538379138 |
|
|
Aug 25 10:49:58 AM UTC 24 |
Aug 25 11:02:03 AM UTC 24 |
50904919689 ps |
| T1001 |
/workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/49.spi_device_stress_all.2743689317 |
|
|
Aug 25 10:56:25 AM UTC 24 |
Aug 25 11:02:10 AM UTC 24 |
77316722852 ps |
| T288 |
/workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/15.spi_device_flash_mode_ignore_cmds.1236263214 |
|
|
Aug 25 10:45:44 AM UTC 24 |
Aug 25 11:02:11 AM UTC 24 |
83453914246 ps |
| T1002 |
/workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/38.spi_device_stress_all.2789369099 |
|
|
Aug 25 10:52:39 AM UTC 24 |
Aug 25 11:02:35 AM UTC 24 |
148286882001 ps |
| T1003 |
/workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/42.spi_device_flash_and_tpm.1173690557 |
|
|
Aug 25 10:53:38 AM UTC 24 |
Aug 25 11:02:54 AM UTC 24 |
37090054730 ps |
| T1004 |
/workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/27.spi_device_flash_and_tpm_min_idle.3587141188 |
|
|
Aug 25 10:49:38 AM UTC 24 |
Aug 25 11:02:54 AM UTC 24 |
59854226822 ps |
| T1005 |
/workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/38.spi_device_flash_and_tpm.3179418622 |
|
|
Aug 25 10:52:38 AM UTC 24 |
Aug 25 11:03:33 AM UTC 24 |
183129478378 ps |
| T307 |
/workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/48.spi_device_flash_and_tpm_min_idle.293933631 |
|
|
Aug 25 10:56:04 AM UTC 24 |
Aug 25 11:03:48 AM UTC 24 |
24361526794 ps |
| T1006 |
/workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/34.spi_device_flash_and_tpm.749055341 |
|
|
Aug 25 10:51:34 AM UTC 24 |
Aug 25 11:03:59 AM UTC 24 |
40927881588 ps |
| T1007 |
/workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/46.spi_device_flash_all.2802657502 |
|
|
Aug 25 10:55:06 AM UTC 24 |
Aug 25 11:04:24 AM UTC 24 |
88777620639 ps |
| T1008 |
/workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/38.spi_device_flash_and_tpm_min_idle.1874403635 |
|
|
Aug 25 10:52:38 AM UTC 24 |
Aug 25 11:06:14 AM UTC 24 |
104591768523 ps |
| T278 |
/workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/25.spi_device_flash_and_tpm_min_idle.448217669 |
|
|
Aug 25 10:49:02 AM UTC 24 |
Aug 25 11:06:39 AM UTC 24 |
416833933842 ps |
| T74 |
/workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/46.spi_device_stress_all.1140190666 |
|
|
Aug 25 10:55:13 AM UTC 24 |
Aug 25 11:08:02 AM UTC 24 |
216199740926 ps |
| T76 |
/workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/40.spi_device_stress_all.347672093 |
|
|
Aug 25 10:53:08 AM UTC 24 |
Aug 25 11:08:17 AM UTC 24 |
145126139646 ps |
| T75 |
/workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/49.spi_device_flash_and_tpm.3870430517 |
|
|
Aug 25 10:56:21 AM UTC 24 |
Aug 25 11:08:22 AM UTC 24 |
45875684988 ps |
| T77 |
/workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/45.spi_device_flash_and_tpm_min_idle.2946416438 |
|
|
Aug 25 10:54:44 AM UTC 24 |
Aug 25 11:09:11 AM UTC 24 |
53262190728 ps |
| T78 |
/workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/44.spi_device_flash_mode_ignore_cmds.4210973095 |
|
|
Aug 25 10:54:25 AM UTC 24 |
Aug 25 11:10:06 AM UTC 24 |
77290015178 ps |
| T79 |
/workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/31.spi_device_flash_and_tpm_min_idle.556520805 |
|
|
Aug 25 10:50:42 AM UTC 24 |
Aug 25 11:11:35 AM UTC 24 |
92270562554 ps |
| T80 |
/workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/45.spi_device_stress_all.3454287913 |
|
|
Aug 25 10:54:46 AM UTC 24 |
Aug 25 11:17:48 AM UTC 24 |
672253648408 ps |
| T101 |
/workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/1.spi_device_csr_hw_reset.3909212168 |
|
|
Aug 25 09:45:16 AM UTC 24 |
Aug 25 09:45:25 AM UTC 24 |
38140362 ps |
| T1009 |
/workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/2.spi_device_intr_test.366549587 |
|
|
Aug 25 09:45:17 AM UTC 24 |
Aug 25 09:45:25 AM UTC 24 |
24316681 ps |
| T102 |
/workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/2.spi_device_csr_hw_reset.1390307095 |
|
|
Aug 25 09:45:17 AM UTC 24 |
Aug 25 09:45:26 AM UTC 24 |
203389113 ps |
| T94 |
/workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/2.spi_device_tl_errors.2591475747 |
|
|
Aug 25 09:45:17 AM UTC 24 |
Aug 25 09:45:26 AM UTC 24 |
26804897 ps |
| T132 |
/workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/2.spi_device_mem_partial_access.818182868 |
|
|
Aug 25 09:45:17 AM UTC 24 |
Aug 25 09:45:26 AM UTC 24 |
199993221 ps |
| T1010 |
/workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/2.spi_device_mem_walk.2970056166 |
|
|
Aug 25 09:45:17 AM UTC 24 |
Aug 25 09:45:26 AM UTC 24 |
13094589 ps |
| T133 |
/workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/2.spi_device_csr_rw.701833667 |
|
|
Aug 25 09:45:17 AM UTC 24 |
Aug 25 09:45:27 AM UTC 24 |
133224545 ps |
| T95 |
/workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/1.spi_device_csr_mem_rw_with_rand_reset.572960377 |
|
|
Aug 25 09:45:17 AM UTC 24 |
Aug 25 09:45:27 AM UTC 24 |
84781991 ps |
| T153 |
/workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/1.spi_device_same_csr_outstanding.1797014283 |
|
|
Aug 25 09:45:17 AM UTC 24 |
Aug 25 09:45:27 AM UTC 24 |
62294032 ps |
| T1011 |
/workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/1.spi_device_intr_test.86565661 |
|
|
Aug 25 09:45:16 AM UTC 24 |
Aug 25 09:45:30 AM UTC 24 |
27609493 ps |
| T96 |
/workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/2.spi_device_tl_intg_err.138644655 |
|
|
Aug 25 09:45:17 AM UTC 24 |
Aug 25 09:45:31 AM UTC 24 |
1402432262 ps |
| T1012 |
/workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/0.spi_device_intr_test.3502705536 |
|
|
Aug 25 09:45:16 AM UTC 24 |
Aug 25 09:45:31 AM UTC 24 |
57647116 ps |
| T1013 |
/workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/1.spi_device_mem_walk.3057648209 |
|
|
Aug 25 09:45:16 AM UTC 24 |
Aug 25 09:45:32 AM UTC 24 |
33974458 ps |
| T1014 |
/workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/0.spi_device_mem_walk.3217577246 |
|
|
Aug 25 09:45:16 AM UTC 24 |
Aug 25 09:45:32 AM UTC 24 |
16974738 ps |
| T103 |
/workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/0.spi_device_csr_hw_reset.3226488544 |
|
|
Aug 25 09:45:16 AM UTC 24 |
Aug 25 09:45:33 AM UTC 24 |
36216035 ps |
| T115 |
/workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/1.spi_device_tl_errors.3082572399 |
|
|
Aug 25 09:45:16 AM UTC 24 |
Aug 25 09:45:33 AM UTC 24 |
143474399 ps |
| T134 |
/workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/0.spi_device_mem_partial_access.1947228115 |
|
|
Aug 25 09:45:16 AM UTC 24 |
Aug 25 09:45:33 AM UTC 24 |
237603985 ps |
| T135 |
/workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/1.spi_device_mem_partial_access.2094230667 |
|
|
Aug 25 09:45:16 AM UTC 24 |
Aug 25 09:45:33 AM UTC 24 |
563436054 ps |
| T154 |
/workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/1.spi_device_csr_rw.3011041343 |
|
|
Aug 25 09:45:17 AM UTC 24 |
Aug 25 09:45:33 AM UTC 24 |
63347385 ps |
| T136 |
/workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/0.spi_device_csr_rw.2514170508 |
|
|
Aug 25 09:45:16 AM UTC 24 |
Aug 25 09:45:34 AM UTC 24 |
140632203 ps |
| T116 |
/workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/0.spi_device_tl_errors.1510398409 |
|
|
Aug 25 09:45:16 AM UTC 24 |
Aug 25 09:45:34 AM UTC 24 |
114241718 ps |
| T128 |
/workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/0.spi_device_csr_mem_rw_with_rand_reset.2755981563 |
|
|
Aug 25 09:45:16 AM UTC 24 |
Aug 25 09:45:35 AM UTC 24 |
104327261 ps |
| T155 |
/workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/2.spi_device_same_csr_outstanding.2589634201 |
|
|
Aug 25 09:45:17 AM UTC 24 |
Aug 25 09:45:35 AM UTC 24 |
44531060 ps |
| T156 |
/workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/0.spi_device_same_csr_outstanding.2380514113 |
|
|
Aug 25 09:45:16 AM UTC 24 |
Aug 25 09:45:35 AM UTC 24 |
63124646 ps |
| T1015 |
/workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/2.spi_device_csr_aliasing.658724226 |
|
|
Aug 25 09:45:17 AM UTC 24 |
Aug 25 09:45:36 AM UTC 24 |
421349558 ps |
| T137 |
/workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/1.spi_device_csr_aliasing.1201070156 |
|
|
Aug 25 09:45:17 AM UTC 24 |
Aug 25 09:45:37 AM UTC 24 |
416937597 ps |
| T138 |
/workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/0.spi_device_csr_aliasing.2772422462 |
|
|
Aug 25 09:45:16 AM UTC 24 |
Aug 25 09:45:38 AM UTC 24 |
417233493 ps |
| T117 |
/workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/1.spi_device_tl_intg_err.2164461158 |
|
|
Aug 25 09:45:16 AM UTC 24 |
Aug 25 09:45:40 AM UTC 24 |
849823293 ps |
| T1016 |
/workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/3.spi_device_intr_test.931183598 |
|
|
Aug 25 09:45:41 AM UTC 24 |
Aug 25 09:45:43 AM UTC 24 |
51314220 ps |
| T1017 |
/workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/3.spi_device_mem_walk.1726091984 |
|
|
Aug 25 09:45:41 AM UTC 24 |
Aug 25 09:45:43 AM UTC 24 |
11395625 ps |
| T122 |
/workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/16.spi_device_tl_errors.765478416 |
|
|
Aug 25 09:45:52 AM UTC 24 |
Aug 25 09:45:57 AM UTC 24 |
104514017 ps |
| T139 |
/workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/2.spi_device_csr_bit_bash.129143654 |
|
|
Aug 25 09:45:17 AM UTC 24 |
Aug 25 09:45:44 AM UTC 24 |
3520198909 ps |
| T1018 |
/workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/4.spi_device_mem_walk.3634344639 |
|
|
Aug 25 09:45:42 AM UTC 24 |
Aug 25 09:45:44 AM UTC 24 |
18927528 ps |
| T1019 |
/workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/3.spi_device_csr_hw_reset.1325776933 |
|
|
Aug 25 09:45:42 AM UTC 24 |
Aug 25 09:45:45 AM UTC 24 |
23553169 ps |
| T1020 |
/workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/4.spi_device_intr_test.3712820003 |
|
|
Aug 25 09:45:42 AM UTC 24 |
Aug 25 09:45:45 AM UTC 24 |
61589746 ps |
| T1021 |
/workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/5.spi_device_intr_test.2419827903 |
|
|
Aug 25 09:45:43 AM UTC 24 |
Aug 25 09:45:45 AM UTC 24 |
161855738 ps |
| T1022 |
/workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/4.spi_device_csr_hw_reset.3147991276 |
|
|
Aug 25 09:45:42 AM UTC 24 |
Aug 25 09:45:45 AM UTC 24 |
67833644 ps |
| T129 |
/workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/3.spi_device_csr_mem_rw_with_rand_reset.3660362369 |
|
|
Aug 25 09:45:42 AM UTC 24 |
Aug 25 09:45:45 AM UTC 24 |
655163672 ps |
| T1023 |
/workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/7.spi_device_intr_test.3802007963 |
|
|
Aug 25 09:45:43 AM UTC 24 |
Aug 25 09:45:45 AM UTC 24 |
15112293 ps |
| T1024 |
/workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/3.spi_device_mem_partial_access.3535169220 |
|
|
Aug 25 09:45:42 AM UTC 24 |
Aug 25 09:45:45 AM UTC 24 |
42033338 ps |
| T1025 |
/workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/6.spi_device_intr_test.4096762336 |
|
|
Aug 25 09:45:43 AM UTC 24 |
Aug 25 09:45:46 AM UTC 24 |
96655244 ps |
| T126 |
/workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/3.spi_device_tl_errors.2845929641 |
|
|
Aug 25 09:45:41 AM UTC 24 |
Aug 25 09:45:46 AM UTC 24 |
103398430 ps |
| T140 |
/workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/3.spi_device_csr_rw.3221068717 |
|
|
Aug 25 09:45:42 AM UTC 24 |
Aug 25 09:45:46 AM UTC 24 |
150200715 ps |
| T1026 |
/workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/4.spi_device_mem_partial_access.3467218540 |
|
|
Aug 25 09:45:42 AM UTC 24 |
Aug 25 09:45:46 AM UTC 24 |
87003058 ps |