Tests
dashboard | hierarchy | modlist | groups | tests | asserts
Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
96.03 98.38 93.99 98.62 89.36 97.19 95.45 99.21


Total test records in report: 1131
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html | tests17.html | tests18.html | tests19.html | tests20.html | tests21.html | tests22.html | tests23.html
T130 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/5.spi_device_tl_errors.1831121543 Aug 25 09:45:43 AM UTC 24 Aug 25 09:45:46 AM UTC 24 50084549 ps
T131 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/2.spi_device_csr_mem_rw_with_rand_reset.1338660144 Aug 25 09:45:41 AM UTC 24 Aug 25 09:45:46 AM UTC 24 805123691 ps
T141 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/5.spi_device_csr_rw.1825334514 Aug 25 09:45:43 AM UTC 24 Aug 25 09:45:46 AM UTC 24 308556326 ps
T1027 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/4.spi_device_csr_rw.1686021156 Aug 25 09:45:42 AM UTC 24 Aug 25 09:45:46 AM UTC 24 105023110 ps
T1028 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/4.spi_device_csr_mem_rw_with_rand_reset.354833125 Aug 25 09:45:43 AM UTC 24 Aug 25 09:45:46 AM UTC 24 47342023 ps
T1029 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/6.spi_device_same_csr_outstanding.1234791362 Aug 25 09:45:43 AM UTC 24 Aug 25 09:45:46 AM UTC 24 89993822 ps
T1030 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/5.spi_device_same_csr_outstanding.840041018 Aug 25 09:45:43 AM UTC 24 Aug 25 09:45:47 AM UTC 24 261440960 ps
T1031 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/5.spi_device_csr_mem_rw_with_rand_reset.2220910886 Aug 25 09:45:43 AM UTC 24 Aug 25 09:45:47 AM UTC 24 93980674 ps
T125 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/7.spi_device_csr_mem_rw_with_rand_reset.216839203 Aug 25 09:45:43 AM UTC 24 Aug 25 09:45:47 AM UTC 24 46655170 ps
T1032 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/6.spi_device_csr_rw.1560291519 Aug 25 09:45:43 AM UTC 24 Aug 25 09:45:47 AM UTC 24 32393451 ps
T1033 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/6.spi_device_csr_mem_rw_with_rand_reset.4222220886 Aug 25 09:45:43 AM UTC 24 Aug 25 09:45:47 AM UTC 24 41754600 ps
T165 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/3.spi_device_same_csr_outstanding.2247621479 Aug 25 09:45:42 AM UTC 24 Aug 25 09:45:47 AM UTC 24 365113342 ps
T166 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/4.spi_device_same_csr_outstanding.192742566 Aug 25 09:45:43 AM UTC 24 Aug 25 09:45:47 AM UTC 24 156554776 ps
T124 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/4.spi_device_tl_errors.2037470645 Aug 25 09:45:42 AM UTC 24 Aug 25 09:45:48 AM UTC 24 291929878 ps
T120 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/6.spi_device_tl_errors.3865990615 Aug 25 09:45:43 AM UTC 24 Aug 25 09:45:48 AM UTC 24 51554268 ps
T167 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/1.spi_device_csr_bit_bash.2175423214 Aug 25 09:45:17 AM UTC 24 Aug 25 09:45:48 AM UTC 24 2549895086 ps
T1034 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/0.spi_device_csr_bit_bash.730232069 Aug 25 09:45:16 AM UTC 24 Aug 25 09:45:48 AM UTC 24 352718667 ps
T123 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/7.spi_device_tl_errors.1287185178 Aug 25 09:45:43 AM UTC 24 Aug 25 09:45:50 AM UTC 24 77538539 ps
T118 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/4.spi_device_tl_intg_err.2905349169 Aug 25 09:45:42 AM UTC 24 Aug 25 09:45:50 AM UTC 24 421939353 ps
T326 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/0.spi_device_tl_intg_err.2871424373 Aug 25 09:45:16 AM UTC 24 Aug 25 09:45:50 AM UTC 24 1611739262 ps
T168 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/3.spi_device_csr_aliasing.592996641 Aug 25 09:45:42 AM UTC 24 Aug 25 09:45:52 AM UTC 24 370863637 ps
T329 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/5.spi_device_tl_intg_err.3166134652 Aug 25 09:45:43 AM UTC 24 Aug 25 09:45:52 AM UTC 24 271905305 ps
T1035 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/15.spi_device_intr_test.4278388986 Aug 25 09:45:50 AM UTC 24 Aug 25 09:45:55 AM UTC 24 13510970 ps
T1036 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/16.spi_device_intr_test.2339622045 Aug 25 09:45:52 AM UTC 24 Aug 25 09:45:55 AM UTC 24 21786538 ps
T333 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/3.spi_device_tl_intg_err.540872453 Aug 25 09:45:41 AM UTC 24 Aug 25 09:45:56 AM UTC 24 10905927318 ps
T1037 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/8.spi_device_intr_test.807476247 Aug 25 09:45:43 AM UTC 24 Aug 25 09:45:56 AM UTC 24 15886664 ps
T1038 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/15.spi_device_same_csr_outstanding.1778580412 Aug 25 09:45:50 AM UTC 24 Aug 25 09:45:56 AM UTC 24 69215025 ps
T1039 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/7.spi_device_csr_rw.3506820547 Aug 25 09:45:43 AM UTC 24 Aug 25 09:45:56 AM UTC 24 37900459 ps
T1040 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/15.spi_device_csr_mem_rw_with_rand_reset.988685374 Aug 25 09:45:52 AM UTC 24 Aug 25 09:45:57 AM UTC 24 166000332 ps
T1041 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/15.spi_device_csr_rw.1106496002 Aug 25 09:45:50 AM UTC 24 Aug 25 09:45:57 AM UTC 24 76038599 ps
T1042 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/8.spi_device_csr_mem_rw_with_rand_reset.923370282 Aug 25 09:45:43 AM UTC 24 Aug 25 09:45:57 AM UTC 24 266604225 ps
T1043 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/16.spi_device_csr_rw.2736647796 Aug 25 09:45:52 AM UTC 24 Aug 25 09:45:57 AM UTC 24 1700257739 ps
T1044 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/8.spi_device_csr_rw.3930920731 Aug 25 09:45:43 AM UTC 24 Aug 25 09:45:57 AM UTC 24 34711222 ps
T1045 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/7.spi_device_same_csr_outstanding.3985927207 Aug 25 09:45:43 AM UTC 24 Aug 25 09:45:58 AM UTC 24 157942285 ps
T1046 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/9.spi_device_same_csr_outstanding.1535741581 Aug 25 09:45:44 AM UTC 24 Aug 25 09:45:58 AM UTC 24 112958816 ps
T127 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/8.spi_device_tl_errors.1809312995 Aug 25 09:45:43 AM UTC 24 Aug 25 09:45:59 AM UTC 24 240867579 ps
T121 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/9.spi_device_tl_errors.67263466 Aug 25 09:45:43 AM UTC 24 Aug 25 09:46:00 AM UTC 24 194938443 ps
T1047 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/4.spi_device_csr_bit_bash.3575693206 Aug 25 09:45:43 AM UTC 24 Aug 25 09:46:13 AM UTC 24 588531244 ps
T330 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/7.spi_device_tl_intg_err.2797639179 Aug 25 09:45:43 AM UTC 24 Aug 25 09:46:01 AM UTC 24 636263586 ps
T334 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/6.spi_device_tl_intg_err.526993666 Aug 25 09:45:43 AM UTC 24 Aug 25 09:46:01 AM UTC 24 1270885643 ps
T331 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/15.spi_device_tl_intg_err.968949342 Aug 25 09:45:50 AM UTC 24 Aug 25 09:46:01 AM UTC 24 1126490224 ps
T332 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/16.spi_device_tl_intg_err.247013379 Aug 25 09:45:52 AM UTC 24 Aug 25 09:46:01 AM UTC 24 321236573 ps
T1048 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/12.spi_device_intr_test.2097313332 Aug 25 09:45:47 AM UTC 24 Aug 25 09:46:01 AM UTC 24 36677514 ps
T1049 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/13.spi_device_intr_test.3123240388 Aug 25 09:45:48 AM UTC 24 Aug 25 09:46:01 AM UTC 24 27064153 ps
T1050 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/12.spi_device_csr_rw.958488433 Aug 25 09:45:47 AM UTC 24 Aug 25 09:46:02 AM UTC 24 641240110 ps
T1051 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/11.spi_device_same_csr_outstanding.232700024 Aug 25 09:45:47 AM UTC 24 Aug 25 09:46:02 AM UTC 24 73939823 ps
T1052 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/12.spi_device_same_csr_outstanding.1451971915 Aug 25 09:45:47 AM UTC 24 Aug 25 09:46:02 AM UTC 24 111350465 ps
T1053 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/11.spi_device_csr_rw.1981017393 Aug 25 09:45:47 AM UTC 24 Aug 25 09:46:02 AM UTC 24 185491251 ps
T1054 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/12.spi_device_csr_mem_rw_with_rand_reset.3539940178 Aug 25 09:45:48 AM UTC 24 Aug 25 09:46:02 AM UTC 24 52945400 ps
T1055 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/11.spi_device_csr_mem_rw_with_rand_reset.799429320 Aug 25 09:45:47 AM UTC 24 Aug 25 09:46:03 AM UTC 24 113018116 ps
T1056 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/3.spi_device_csr_bit_bash.1950432311 Aug 25 09:45:42 AM UTC 24 Aug 25 09:46:04 AM UTC 24 355248759 ps
T1057 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/12.spi_device_tl_errors.2021742004 Aug 25 09:45:47 AM UTC 24 Aug 25 09:46:05 AM UTC 24 168854077 ps
T1058 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/4.spi_device_csr_aliasing.4200800263 Aug 25 09:45:43 AM UTC 24 Aug 25 09:46:05 AM UTC 24 935758789 ps
T327 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/8.spi_device_tl_intg_err.773998476 Aug 25 09:45:43 AM UTC 24 Aug 25 09:46:05 AM UTC 24 2127609703 ps
T1059 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/15.spi_device_tl_errors.1779968037 Aug 25 09:45:50 AM UTC 24 Aug 25 09:46:05 AM UTC 24 66227867 ps
T1060 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/19.spi_device_intr_test.1482971079 Aug 25 09:46:01 AM UTC 24 Aug 25 09:46:05 AM UTC 24 50473901 ps
T1061 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/17.spi_device_intr_test.3682383620 Aug 25 09:45:57 AM UTC 24 Aug 25 09:46:05 AM UTC 24 18985059 ps
T1062 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/22.spi_device_intr_test.1677167607 Aug 25 09:46:03 AM UTC 24 Aug 25 09:46:06 AM UTC 24 50085886 ps
T1063 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/20.spi_device_intr_test.2916645341 Aug 25 09:46:03 AM UTC 24 Aug 25 09:46:06 AM UTC 24 21825973 ps
T1064 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/23.spi_device_intr_test.673977719 Aug 25 09:46:04 AM UTC 24 Aug 25 09:46:06 AM UTC 24 14656053 ps
T1065 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/9.spi_device_intr_test.3486396758 Aug 25 09:45:44 AM UTC 24 Aug 25 09:46:06 AM UTC 24 12890707 ps
T1066 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/21.spi_device_intr_test.1598286500 Aug 25 09:46:03 AM UTC 24 Aug 25 09:46:06 AM UTC 24 13035760 ps
T1067 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/24.spi_device_intr_test.72844937 Aug 25 09:46:04 AM UTC 24 Aug 25 09:46:06 AM UTC 24 12539426 ps
T1068 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/27.spi_device_intr_test.2730821504 Aug 25 09:46:04 AM UTC 24 Aug 25 09:46:06 AM UTC 24 46431533 ps
T1069 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/26.spi_device_intr_test.4157215322 Aug 25 09:46:04 AM UTC 24 Aug 25 09:46:06 AM UTC 24 41672114 ps
T1070 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/10.spi_device_intr_test.3128546211 Aug 25 09:45:44 AM UTC 24 Aug 25 09:46:06 AM UTC 24 43882181 ps
T1071 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/25.spi_device_intr_test.1134264320 Aug 25 09:46:04 AM UTC 24 Aug 25 09:46:06 AM UTC 24 12082365 ps
T1072 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/11.spi_device_intr_test.2712150357 Aug 25 09:45:47 AM UTC 24 Aug 25 09:46:07 AM UTC 24 54843449 ps
T1073 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/9.spi_device_csr_mem_rw_with_rand_reset.1088716043 Aug 25 09:45:44 AM UTC 24 Aug 25 09:46:07 AM UTC 24 54081493 ps
T1074 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/9.spi_device_csr_rw.2342471752 Aug 25 09:45:44 AM UTC 24 Aug 25 09:46:07 AM UTC 24 51285001 ps
T1075 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/19.spi_device_tl_errors.4062822434 Aug 25 09:46:01 AM UTC 24 Aug 25 09:46:07 AM UTC 24 166156722 ps
T1076 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/19.spi_device_csr_rw.4071615886 Aug 25 09:46:01 AM UTC 24 Aug 25 09:46:07 AM UTC 24 69074951 ps
T1077 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/10.spi_device_csr_rw.15895221 Aug 25 09:45:45 AM UTC 24 Aug 25 09:46:08 AM UTC 24 420326067 ps
T1078 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/14.spi_device_tl_intg_err.1716643031 Aug 25 09:45:48 AM UTC 24 Aug 25 09:46:15 AM UTC 24 121234125 ps
T1079 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/16.spi_device_csr_mem_rw_with_rand_reset.2373638066 Aug 25 09:45:57 AM UTC 24 Aug 25 09:46:08 AM UTC 24 597560866 ps
T1080 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/13.spi_device_same_csr_outstanding.718738562 Aug 25 09:45:48 AM UTC 24 Aug 25 09:46:12 AM UTC 24 245178735 ps
T1081 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/8.spi_device_same_csr_outstanding.3281156840 Aug 25 09:45:43 AM UTC 24 Aug 25 09:46:08 AM UTC 24 694716227 ps
T1082 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/10.spi_device_same_csr_outstanding.2172342838 Aug 25 09:45:45 AM UTC 24 Aug 25 09:46:08 AM UTC 24 44717522 ps
T335 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/12.spi_device_tl_intg_err.4021761586 Aug 25 09:45:47 AM UTC 24 Aug 25 09:46:16 AM UTC 24 293313922 ps
T1083 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/30.spi_device_intr_test.2999911435 Aug 25 09:46:06 AM UTC 24 Aug 25 09:46:08 AM UTC 24 56573826 ps
T1084 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/29.spi_device_intr_test.808172032 Aug 25 09:46:06 AM UTC 24 Aug 25 09:46:08 AM UTC 24 11995761 ps
T1085 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/28.spi_device_intr_test.73260779 Aug 25 09:46:06 AM UTC 24 Aug 25 09:46:08 AM UTC 24 42229255 ps
T1086 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/32.spi_device_intr_test.2535450831 Aug 25 09:46:06 AM UTC 24 Aug 25 09:46:08 AM UTC 24 18634130 ps
T1087 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/31.spi_device_intr_test.4123111299 Aug 25 09:46:06 AM UTC 24 Aug 25 09:46:08 AM UTC 24 21693748 ps
T1088 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/13.spi_device_tl_errors.3095335957 Aug 25 09:45:48 AM UTC 24 Aug 25 09:46:11 AM UTC 24 167458038 ps
T1089 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/9.spi_device_tl_intg_err.2955503682 Aug 25 09:45:43 AM UTC 24 Aug 25 09:46:12 AM UTC 24 286441646 ps
T324 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/14.spi_device_tl_errors.967163158 Aug 25 09:45:48 AM UTC 24 Aug 25 09:46:12 AM UTC 24 475862920 ps
T1090 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/19.spi_device_csr_mem_rw_with_rand_reset.1898413662 Aug 25 09:46:03 AM UTC 24 Aug 25 09:46:09 AM UTC 24 62543469 ps
T1091 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/34.spi_device_intr_test.3812454563 Aug 25 09:46:06 AM UTC 24 Aug 25 09:46:09 AM UTC 24 18869776 ps
T1092 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/33.spi_device_intr_test.598292038 Aug 25 09:46:06 AM UTC 24 Aug 25 09:46:09 AM UTC 24 13948929 ps
T1093 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/16.spi_device_same_csr_outstanding.3310247434 Aug 25 09:45:57 AM UTC 24 Aug 25 09:46:09 AM UTC 24 442615588 ps
T1094 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/18.spi_device_intr_test.4248551179 Aug 25 09:45:59 AM UTC 24 Aug 25 09:46:09 AM UTC 24 14678452 ps
T1095 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/19.spi_device_same_csr_outstanding.2702317929 Aug 25 09:46:03 AM UTC 24 Aug 25 09:46:09 AM UTC 24 116535030 ps
T1096 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/14.spi_device_intr_test.2501515408 Aug 25 09:45:50 AM UTC 24 Aug 25 09:46:09 AM UTC 24 122484144 ps
T1097 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/17.spi_device_csr_mem_rw_with_rand_reset.3038287709 Aug 25 09:45:59 AM UTC 24 Aug 25 09:46:10 AM UTC 24 209270687 ps
T1098 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/18.spi_device_csr_rw.3460834447 Aug 25 09:45:59 AM UTC 24 Aug 25 09:46:10 AM UTC 24 376301922 ps
T1099 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/11.spi_device_tl_errors.1931905086 Aug 25 09:45:45 AM UTC 24 Aug 25 09:46:10 AM UTC 24 119669209 ps
T1100 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/14.spi_device_csr_rw.2380995293 Aug 25 09:45:50 AM UTC 24 Aug 25 09:46:10 AM UTC 24 70325149 ps
T1101 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/17.spi_device_csr_rw.2260413157 Aug 25 09:45:59 AM UTC 24 Aug 25 09:46:10 AM UTC 24 79497218 ps
T1102 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/13.spi_device_csr_mem_rw_with_rand_reset.3345969760 Aug 25 09:45:48 AM UTC 24 Aug 25 09:46:10 AM UTC 24 86617766 ps
T1103 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/18.spi_device_same_csr_outstanding.1246996672 Aug 25 09:45:59 AM UTC 24 Aug 25 09:46:10 AM UTC 24 27636609 ps
T1104 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/10.spi_device_csr_mem_rw_with_rand_reset.737476113 Aug 25 09:45:45 AM UTC 24 Aug 25 09:46:11 AM UTC 24 148743997 ps
T1105 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/18.spi_device_csr_mem_rw_with_rand_reset.629555029 Aug 25 09:45:59 AM UTC 24 Aug 25 09:46:11 AM UTC 24 481249203 ps
T1106 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/10.spi_device_tl_errors.1751352919 Aug 25 09:45:44 AM UTC 24 Aug 25 09:46:11 AM UTC 24 500802348 ps
T1107 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/13.spi_device_csr_rw.649792105 Aug 25 09:45:48 AM UTC 24 Aug 25 09:46:11 AM UTC 24 40774580 ps
T1108 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/17.spi_device_same_csr_outstanding.3641173623 Aug 25 09:45:59 AM UTC 24 Aug 25 09:46:11 AM UTC 24 45662464 ps
T325 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/18.spi_device_tl_errors.4004054171 Aug 25 09:45:59 AM UTC 24 Aug 25 09:46:11 AM UTC 24 44749962 ps
T1109 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/17.spi_device_tl_errors.3569461014 Aug 25 09:45:57 AM UTC 24 Aug 25 09:46:11 AM UTC 24 235555379 ps
T1110 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/14.spi_device_same_csr_outstanding.930563005 Aug 25 09:45:50 AM UTC 24 Aug 25 09:46:12 AM UTC 24 44240031 ps
T328 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/11.spi_device_tl_intg_err.3101384181 Aug 25 09:45:47 AM UTC 24 Aug 25 09:46:12 AM UTC 24 420813103 ps
T1111 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/13.spi_device_tl_intg_err.1702068931 Aug 25 09:45:48 AM UTC 24 Aug 25 09:46:19 AM UTC 24 222435922 ps
T1112 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/17.spi_device_tl_intg_err.1640401615 Aug 25 09:45:57 AM UTC 24 Aug 25 09:46:19 AM UTC 24 590315832 ps
T1113 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/40.spi_device_intr_test.771160037 Aug 25 09:46:08 AM UTC 24 Aug 25 09:46:20 AM UTC 24 39257485 ps
T1114 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/38.spi_device_intr_test.1393783332 Aug 25 09:46:08 AM UTC 24 Aug 25 09:46:20 AM UTC 24 10813942 ps
T1115 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/37.spi_device_intr_test.3187284744 Aug 25 09:46:08 AM UTC 24 Aug 25 09:46:20 AM UTC 24 29372688 ps
T1116 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/41.spi_device_intr_test.3126559881 Aug 25 09:46:08 AM UTC 24 Aug 25 09:46:20 AM UTC 24 13062144 ps
T1117 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/39.spi_device_intr_test.3143120784 Aug 25 09:46:08 AM UTC 24 Aug 25 09:46:20 AM UTC 24 14496314 ps
T1118 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/19.spi_device_tl_intg_err.4251376213 Aug 25 09:46:01 AM UTC 24 Aug 25 09:46:21 AM UTC 24 705761014 ps
T1119 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/10.spi_device_tl_intg_err.1763667061 Aug 25 09:45:44 AM UTC 24 Aug 25 09:46:23 AM UTC 24 822457706 ps
T1120 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/18.spi_device_tl_intg_err.2687788603 Aug 25 09:45:59 AM UTC 24 Aug 25 09:46:24 AM UTC 24 2135108297 ps
T1121 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/35.spi_device_intr_test.2676504765 Aug 25 09:46:08 AM UTC 24 Aug 25 09:46:30 AM UTC 24 38176181 ps
T1122 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/36.spi_device_intr_test.635452798 Aug 25 09:46:08 AM UTC 24 Aug 25 09:46:30 AM UTC 24 12715592 ps
T1123 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/46.spi_device_intr_test.816851672 Aug 25 09:46:08 AM UTC 24 Aug 25 09:46:31 AM UTC 24 26994023 ps
T1124 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/47.spi_device_intr_test.4090038140 Aug 25 09:46:08 AM UTC 24 Aug 25 09:46:31 AM UTC 24 94596214 ps
T1125 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/48.spi_device_intr_test.3729509821 Aug 25 09:46:09 AM UTC 24 Aug 25 09:46:31 AM UTC 24 34964778 ps
T1126 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/49.spi_device_intr_test.2253740660 Aug 25 09:46:09 AM UTC 24 Aug 25 09:46:31 AM UTC 24 16875233 ps
T1127 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/14.spi_device_csr_mem_rw_with_rand_reset.2400971391 Aug 25 09:45:50 AM UTC 24 Aug 25 09:46:31 AM UTC 24 90768631 ps
T1128 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/43.spi_device_intr_test.3435624365 Aug 25 09:46:08 AM UTC 24 Aug 25 09:46:31 AM UTC 24 42075266 ps
T1129 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/45.spi_device_intr_test.3874051723 Aug 25 09:46:08 AM UTC 24 Aug 25 09:46:31 AM UTC 24 12188689 ps
T1130 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/42.spi_device_intr_test.2556431925 Aug 25 09:46:08 AM UTC 24 Aug 25 09:46:31 AM UTC 24 52323584 ps
T1131 /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/44.spi_device_intr_test.3635343522 Aug 25 09:46:08 AM UTC 24 Aug 25 09:46:38 AM UTC 24 36685786 ps

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/0.spi_device_intercept.1260919688
Short name T8
Test name
Test status
Simulation time 340072726 ps
CPU time 6.57 seconds
Started Aug 25 10:41:43 AM UTC 24
Finished Aug 25 10:41:50 AM UTC 24
Peak memory 234984 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1260919688 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/s
pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_intercept.1260919688
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/0.spi_device_intercept/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/0.spi_device_flash_and_tpm.136986722
Short name T13
Test name
Test status
Simulation time 1666351680 ps
CPU time 35.7 seconds
Started Aug 25 10:41:50 AM UTC 24
Finished Aug 25 10:42:27 AM UTC 24
Peak memory 229536 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=136986722 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_2
4/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_and_tpm.136986722
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/0.spi_device_flash_and_tpm/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/0.spi_device_flash_all.3924908221
Short name T43
Test name
Test status
Simulation time 2348482780 ps
CPU time 33.09 seconds
Started Aug 25 10:41:48 AM UTC 24
Finished Aug 25 10:42:22 AM UTC 24
Peak memory 251472 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3924908221 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/s
pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_all.3924908221
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/0.spi_device_flash_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/5.spi_device_stress_all.2213288240
Short name T33
Test name
Test status
Simulation time 13401779887 ps
CPU time 107.05 seconds
Started Aug 25 10:42:42 AM UTC 24
Finished Aug 25 10:44:33 AM UTC 24
Peak memory 265868 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2213288240 -assert nopostproc +UVM_
TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra
tch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_stress_all.2213288240
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/5.spi_device_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/4.spi_device_flash_and_tpm.1459788156
Short name T66
Test name
Test status
Simulation time 15372033330 ps
CPU time 154.94 seconds
Started Aug 25 10:42:27 AM UTC 24
Finished Aug 25 10:45:05 AM UTC 24
Peak memory 277884 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1459788156 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
24/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_and_tpm.1459788156
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/4.spi_device_flash_and_tpm/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/2.spi_device_tl_intg_err.138644655
Short name T96
Test name
Test status
Simulation time 1402432262 ps
CPU time 6.96 seconds
Started Aug 25 09:45:17 AM UTC 24
Finished Aug 25 09:45:31 AM UTC 24
Peak memory 225068 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=138644655 -assert nopostproc +U
VM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_tl_intg_err.138644655
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/2.spi_device_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/2.spi_device_flash_all.166422023
Short name T59
Test name
Test status
Simulation time 10132667939 ps
CPU time 94.85 seconds
Started Aug 25 10:42:07 AM UTC 24
Finished Aug 25 10:43:44 AM UTC 24
Peak memory 267936 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=166422023 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/sp
i_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_all.166422023
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/2.spi_device_flash_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/5.spi_device_upload.1633536045
Short name T17
Test name
Test status
Simulation time 207349380 ps
CPU time 5.23 seconds
Started Aug 25 10:42:34 AM UTC 24
Finished Aug 25 10:42:41 AM UTC 24
Peak memory 234900 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1633536045 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/spi_
device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_upload.1633536045
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/5.spi_device_upload/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/0.spi_device_ram_cfg.192515123
Short name T3
Test name
Test status
Simulation time 26979431 ps
CPU time 1.05 seconds
Started Aug 25 10:41:38 AM UTC 24
Finished Aug 25 10:41:40 AM UTC 24
Peak memory 225684 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=192515123 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/spi_
device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_ram_cfg.192515123
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/0.spi_device_ram_cfg/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/6.spi_device_stress_all.1483561464
Short name T175
Test name
Test status
Simulation time 8338572247 ps
CPU time 152.56 seconds
Started Aug 25 10:42:52 AM UTC 24
Finished Aug 25 10:45:27 AM UTC 24
Peak memory 278004 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1483561464 -assert nopostproc +UVM_
TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra
tch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_stress_all.1483561464
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/6.spi_device_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/9.spi_device_flash_and_tpm_min_idle.78572219
Short name T223
Test name
Test status
Simulation time 6960374941 ps
CPU time 186.28 seconds
Started Aug 25 10:43:40 AM UTC 24
Finished Aug 25 10:46:50 AM UTC 24
Peak memory 280188 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=78572219 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_24/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_and_tpm_min_idle.78572219
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/9.spi_device_flash_and_tpm_min_idle/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/1.spi_device_tpm_all.4129878499
Short name T45
Test name
Test status
Simulation time 5237479581 ps
CPU time 44.41 seconds
Started Aug 25 10:41:52 AM UTC 24
Finished Aug 25 10:42:39 AM UTC 24
Peak memory 227548 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4129878499 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/spi
_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_all.4129878499
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/1.spi_device_tpm_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/3.spi_device_flash_all.4214921391
Short name T99
Test name
Test status
Simulation time 43005611304 ps
CPU time 198.77 seconds
Started Aug 25 10:42:16 AM UTC 24
Finished Aug 25 10:45:39 AM UTC 24
Peak memory 278088 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4214921391 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/s
pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_all.4214921391
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/3.spi_device_flash_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/13.spi_device_stress_all.1111945834
Short name T142
Test name
Test status
Simulation time 10133189092 ps
CPU time 167.44 seconds
Started Aug 25 10:45:04 AM UTC 24
Finished Aug 25 10:47:55 AM UTC 24
Peak memory 267612 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1111945834 -assert nopostproc +UVM_
TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra
tch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_stress_all.1111945834
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/13.spi_device_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/0.spi_device_read_buffer_direct.3126609265
Short name T24
Test name
Test status
Simulation time 1625053814 ps
CPU time 22.12 seconds
Started Aug 25 10:41:47 AM UTC 24
Finished Aug 25 10:42:10 AM UTC 24
Peak memory 233368 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3126609265 -assert nopostproc +UVM_TESTNAME=spi_device
_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_read_buffer_direct.3126609265
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/0.spi_device_read_buffer_direct/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/1.spi_device_tl_errors.3082572399
Short name T115
Test name
Test status
Simulation time 143474399 ps
CPU time 3.49 seconds
Started Aug 25 09:45:16 AM UTC 24
Finished Aug 25 09:45:33 AM UTC 24
Peak memory 225204 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3082572399 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_08_24/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_tl_errors.3082572399
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/1.spi_device_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/6.spi_device_flash_mode_ignore_cmds.1587942947
Short name T181
Test name
Test status
Simulation time 10766296825 ps
CPU time 222 seconds
Started Aug 25 10:42:50 AM UTC 24
Finished Aug 25 10:46:36 AM UTC 24
Peak memory 284256 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1587942947 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_mode_ignore_cmds.1587942947
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/6.spi_device_flash_mode_ignore_cmds/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/2.spi_device_flash_and_tpm.1761053166
Short name T98
Test name
Test status
Simulation time 28702422634 ps
CPU time 132.88 seconds
Started Aug 25 10:42:07 AM UTC 24
Finished Aug 25 10:44:23 AM UTC 24
Peak memory 261752 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1761053166 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
24/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_and_tpm.1761053166
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/2.spi_device_flash_and_tpm/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/0.spi_device_sec_cm.2085254745
Short name T10
Test name
Test status
Simulation time 60164329 ps
CPU time 1.65 seconds
Started Aug 25 10:41:50 AM UTC 24
Finished Aug 25 10:41:53 AM UTC 24
Peak memory 257976 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2085254745 -assert nopostproc +UVM_TEST
NAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_sec_cm.2085254745
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/0.spi_device_sec_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/10.spi_device_flash_and_tpm_min_idle.3101736815
Short name T205
Test name
Test status
Simulation time 45765355995 ps
CPU time 276.93 seconds
Started Aug 25 10:44:07 AM UTC 24
Finished Aug 25 10:48:49 AM UTC 24
Peak memory 261776 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3101736815 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_and_tpm_min_idle.3101736815
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/10.spi_device_flash_and_tpm_min_idle/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/2.spi_device_flash_and_tpm_min_idle.2169651075
Short name T60
Test name
Test status
Simulation time 4219284713 ps
CPU time 88.62 seconds
Started Aug 25 10:42:07 AM UTC 24
Finished Aug 25 10:43:38 AM UTC 24
Peak memory 245392 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2169651075 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_and_tpm_min_idle.2169651075
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/2.spi_device_flash_and_tpm_min_idle/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/16.spi_device_flash_and_tpm.3602841244
Short name T100
Test name
Test status
Simulation time 18155421700 ps
CPU time 155.18 seconds
Started Aug 25 10:46:08 AM UTC 24
Finished Aug 25 10:48:46 AM UTC 24
Peak memory 294520 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3602841244 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
24/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_and_tpm.3602841244
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/16.spi_device_flash_and_tpm/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/18.spi_device_tpm_all.2762282885
Short name T388
Test name
Test status
Simulation time 2157141285 ps
CPU time 51.6 seconds
Started Aug 25 10:46:27 AM UTC 24
Finished Aug 25 10:47:20 AM UTC 24
Peak memory 227488 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2762282885 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/spi
_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_all.2762282885
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/18.spi_device_tpm_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/0.spi_device_csr_hw_reset.3226488544
Short name T103
Test name
Test status
Simulation time 36216035 ps
CPU time 1.29 seconds
Started Aug 25 09:45:16 AM UTC 24
Finished Aug 25 09:45:33 AM UTC 24
Peak memory 223948 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3226488544 -assert nopostproc +UVM
_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_csr_hw_reset.3226488544
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/0.spi_device_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/16.spi_device_flash_all.600732719
Short name T218
Test name
Test status
Simulation time 19736280305 ps
CPU time 181.74 seconds
Started Aug 25 10:46:02 AM UTC 24
Finished Aug 25 10:49:08 AM UTC 24
Peak memory 284260 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=600732719 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/sp
i_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_all.600732719
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/16.spi_device_flash_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/46.spi_device_stress_all.1140190666
Short name T74
Test name
Test status
Simulation time 216199740926 ps
CPU time 758.05 seconds
Started Aug 25 10:55:13 AM UTC 24
Finished Aug 25 11:08:02 AM UTC 24
Peak memory 317080 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1140190666 -assert nopostproc +UVM_
TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra
tch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_stress_all.1140190666
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/46.spi_device_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/10.spi_device_stress_all.3382848108
Short name T254
Test name
Test status
Simulation time 23468102130 ps
CPU time 249.85 seconds
Started Aug 25 10:44:07 AM UTC 24
Finished Aug 25 10:48:21 AM UTC 24
Peak memory 274056 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3382848108 -assert nopostproc +UVM_
TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra
tch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_stress_all.3382848108
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/10.spi_device_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/1.spi_device_pass_addr_payload_swap.4229598700
Short name T114
Test name
Test status
Simulation time 14899295885 ps
CPU time 33.12 seconds
Started Aug 25 10:41:54 AM UTC 24
Finished Aug 25 10:42:29 AM UTC 24
Peak memory 261704 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4229598700 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_pass_addr_payload_swap.4229598700
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/1.spi_device_pass_addr_payload_swap/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/13.spi_device_flash_mode_ignore_cmds.965721216
Short name T275
Test name
Test status
Simulation time 233162520732 ps
CPU time 708.67 seconds
Started Aug 25 10:44:54 AM UTC 24
Finished Aug 25 10:56:52 AM UTC 24
Peak memory 284248 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=965721216 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_24/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_mode_ignore_cmds.965721216
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/13.spi_device_flash_mode_ignore_cmds/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/5.spi_device_flash_mode_ignore_cmds.1346537868
Short name T48
Test name
Test status
Simulation time 7620959467 ps
CPU time 45.33 seconds
Started Aug 25 10:42:37 AM UTC 24
Finished Aug 25 10:43:24 AM UTC 24
Peak memory 267852 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1346537868 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_mode_ignore_cmds.1346537868
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/5.spi_device_flash_mode_ignore_cmds/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/0.spi_device_tpm_read_hw_reg.3879467636
Short name T27
Test name
Test status
Simulation time 3834420589 ps
CPU time 26.28 seconds
Started Aug 25 10:41:38 AM UTC 24
Finished Aug 25 10:42:05 AM UTC 24
Peak memory 227564 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3879467636 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_24/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_read_hw_reg.3879467636
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/0.spi_device_tpm_read_hw_reg/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/11.spi_device_flash_all.665717418
Short name T253
Test name
Test status
Simulation time 90484363652 ps
CPU time 291.05 seconds
Started Aug 25 10:44:22 AM UTC 24
Finished Aug 25 10:49:18 AM UTC 24
Peak memory 261516 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=665717418 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/sp
i_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_all.665717418
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/11.spi_device_flash_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/8.spi_device_tl_intg_err.773998476
Short name T327
Test name
Test status
Simulation time 2127609703 ps
CPU time 20.1 seconds
Started Aug 25 09:45:43 AM UTC 24
Finished Aug 25 09:46:05 AM UTC 24
Peak memory 227128 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=773998476 -assert nopostproc +U
VM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_tl_intg_err.773998476
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/8.spi_device_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/10.spi_device_flash_all.3202585506
Short name T212
Test name
Test status
Simulation time 3543264488 ps
CPU time 116.74 seconds
Started Aug 25 10:44:02 AM UTC 24
Finished Aug 25 10:46:01 AM UTC 24
Peak memory 261684 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3202585506 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/s
pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_all.3202585506
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/10.spi_device_flash_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/0.spi_device_alert_test.1901438036
Short name T36
Test name
Test status
Simulation time 136470309 ps
CPU time 1.08 seconds
Started Aug 25 10:41:52 AM UTC 24
Finished Aug 25 10:41:55 AM UTC 24
Peak memory 215684 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1901438036 -assert nopostproc +UVM_TES
TNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_
regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_alert_test.1901438036
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/0.spi_device_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/12.spi_device_flash_and_tpm.1366674036
Short name T219
Test name
Test status
Simulation time 124350594693 ps
CPU time 480.04 seconds
Started Aug 25 10:44:39 AM UTC 24
Finished Aug 25 10:52:47 AM UTC 24
Peak memory 280288 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1366674036 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
24/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_and_tpm.1366674036
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/12.spi_device_flash_and_tpm/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/5.spi_device_flash_and_tpm.234415553
Short name T49
Test name
Test status
Simulation time 13781015472 ps
CPU time 110.91 seconds
Started Aug 25 10:42:42 AM UTC 24
Finished Aug 25 10:44:37 AM UTC 24
Peak memory 261776 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=234415553 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_2
4/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_and_tpm.234415553
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/5.spi_device_flash_and_tpm/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/6.spi_device_flash_mode.3742632769
Short name T161
Test name
Test status
Simulation time 2224083414 ps
CPU time 16 seconds
Started Aug 25 10:42:49 AM UTC 24
Finished Aug 25 10:43:07 AM UTC 24
Peak memory 235020 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3742632769 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/
spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_mode.3742632769
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/6.spi_device_flash_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/2.spi_device_cfg_cmd.650749050
Short name T73
Test name
Test status
Simulation time 1937941309 ps
CPU time 8.85 seconds
Started Aug 25 10:42:06 AM UTC 24
Finished Aug 25 10:42:16 AM UTC 24
Peak memory 245164 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=650749050 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/spi_
device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_cfg_cmd.650749050
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/2.spi_device_cfg_cmd/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/26.spi_device_flash_all.1155187597
Short name T281
Test name
Test status
Simulation time 34877305263 ps
CPU time 139.67 seconds
Started Aug 25 10:49:19 AM UTC 24
Finished Aug 25 10:51:41 AM UTC 24
Peak memory 278112 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1155187597 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/s
pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_all.1155187597
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/26.spi_device_flash_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/4.spi_device_flash_and_tpm_min_idle.1910476688
Short name T39
Test name
Test status
Simulation time 36439130016 ps
CPU time 154.79 seconds
Started Aug 25 10:42:27 AM UTC 24
Finished Aug 25 10:45:05 AM UTC 24
Peak memory 267868 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1910476688 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_and_tpm_min_idle.1910476688
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/4.spi_device_flash_and_tpm_min_idle/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/9.spi_device_tl_errors.67263466
Short name T121
Test name
Test status
Simulation time 194938443 ps
CPU time 4.57 seconds
Started Aug 25 09:45:43 AM UTC 24
Finished Aug 25 09:46:00 AM UTC 24
Peak memory 227252 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=67263466 -assert nopostproc +UVM_TESTNAME=s
pi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_08_24/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_tl_errors.67263466
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/9.spi_device_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/12.spi_device_tl_intg_err.4021761586
Short name T335
Test name
Test status
Simulation time 293313922 ps
CPU time 15.91 seconds
Started Aug 25 09:45:47 AM UTC 24
Finished Aug 25 09:46:16 AM UTC 24
Peak memory 225076 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4021761586 -assert nopostproc +
UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra
tch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_tl_intg_err.4021761586
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/12.spi_device_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/15.spi_device_flash_mode_ignore_cmds.1236263214
Short name T288
Test name
Test status
Simulation time 83453914246 ps
CPU time 973.18 seconds
Started Aug 25 10:45:44 AM UTC 24
Finished Aug 25 11:02:11 AM UTC 24
Peak memory 267860 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1236263214 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_mode_ignore_cmds.1236263214
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/15.spi_device_flash_mode_ignore_cmds/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/25.spi_device_flash_and_tpm_min_idle.448217669
Short name T278
Test name
Test status
Simulation time 416833933842 ps
CPU time 1042.65 seconds
Started Aug 25 10:49:02 AM UTC 24
Finished Aug 25 11:06:39 AM UTC 24
Peak memory 278132 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=448217669 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_24/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_and_tpm_min_idle.448217669
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/25.spi_device_flash_and_tpm_min_idle/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/36.spi_device_flash_and_tpm_min_idle.4154878350
Short name T296
Test name
Test status
Simulation time 67475298130 ps
CPU time 392.65 seconds
Started Aug 25 10:52:05 AM UTC 24
Finished Aug 25 10:58:44 AM UTC 24
Peak memory 278284 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4154878350 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_and_tpm_min_idle.4154878350
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/36.spi_device_flash_and_tpm_min_idle/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/4.spi_device_mailbox.1802134829
Short name T111
Test name
Test status
Simulation time 30787684267 ps
CPU time 38.43 seconds
Started Aug 25 10:42:24 AM UTC 24
Finished Aug 25 10:43:04 AM UTC 24
Peak memory 251560 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1802134829 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/spi
_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_mailbox.1802134829
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/4.spi_device_mailbox/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/5.spi_device_tpm_all.3052482652
Short name T105
Test name
Test status
Simulation time 2823178160 ps
CPU time 15.79 seconds
Started Aug 25 10:42:32 AM UTC 24
Finished Aug 25 10:42:49 AM UTC 24
Peak memory 227580 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3052482652 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/spi
_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_all.3052482652
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/5.spi_device_tpm_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/11.spi_device_stress_all.51023075
Short name T383
Test name
Test status
Simulation time 7805798828 ps
CPU time 123.74 seconds
Started Aug 25 10:44:24 AM UTC 24
Finished Aug 25 10:46:30 AM UTC 24
Peak memory 261928 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=51023075 -assert nopostproc +UVM_TE
STNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_stress_all.51023075
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/11.spi_device_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/21.spi_device_flash_mode_ignore_cmds.2103618301
Short name T266
Test name
Test status
Simulation time 4214786324 ps
CPU time 72.6 seconds
Started Aug 25 10:47:39 AM UTC 24
Finished Aug 25 10:48:54 AM UTC 24
Peak memory 261724 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2103618301 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_mode_ignore_cmds.2103618301
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/21.spi_device_flash_mode_ignore_cmds/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/23.spi_device_stress_all.4195530031
Short name T170
Test name
Test status
Simulation time 7991030008 ps
CPU time 157.29 seconds
Started Aug 25 10:48:22 AM UTC 24
Finished Aug 25 10:51:03 AM UTC 24
Peak memory 272092 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4195530031 -assert nopostproc +UVM_
TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra
tch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_stress_all.4195530031
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/23.spi_device_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/24.spi_device_stress_all.4001548415
Short name T276
Test name
Test status
Simulation time 195723134084 ps
CPU time 768.3 seconds
Started Aug 25 10:48:41 AM UTC 24
Finished Aug 25 11:01:40 AM UTC 24
Peak memory 296648 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4001548415 -assert nopostproc +UVM_
TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra
tch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_stress_all.4001548415
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/24.spi_device_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/28.spi_device_flash_and_tpm.1538379138
Short name T294
Test name
Test status
Simulation time 50904919689 ps
CPU time 715.12 seconds
Started Aug 25 10:49:58 AM UTC 24
Finished Aug 25 11:02:03 AM UTC 24
Peak memory 276192 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1538379138 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
24/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_and_tpm.1538379138
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/28.spi_device_flash_and_tpm/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/31.spi_device_flash_and_tpm_min_idle.556520805
Short name T79
Test name
Test status
Simulation time 92270562554 ps
CPU time 1234.85 seconds
Started Aug 25 10:50:42 AM UTC 24
Finished Aug 25 11:11:35 AM UTC 24
Peak memory 284240 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=556520805 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_24/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_and_tpm_min_idle.556520805
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/31.spi_device_flash_and_tpm_min_idle/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/35.spi_device_flash_mode.881974681
Short name T377
Test name
Test status
Simulation time 758413332 ps
CPU time 14.08 seconds
Started Aug 25 10:51:42 AM UTC 24
Finished Aug 25 10:51:58 AM UTC 24
Peak memory 251364 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=881974681 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/s
pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_mode.881974681
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/35.spi_device_flash_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/17.spi_device_pass_addr_payload_swap.1173274018
Short name T230
Test name
Test status
Simulation time 53318021918 ps
CPU time 25.08 seconds
Started Aug 25 10:46:13 AM UTC 24
Finished Aug 25 10:46:40 AM UTC 24
Peak memory 245352 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1173274018 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_pass_addr_payload_swap.1173274018
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/17.spi_device_pass_addr_payload_swap/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/33.spi_device_flash_mode.2115897492
Short name T378
Test name
Test status
Simulation time 319058634 ps
CPU time 9.73 seconds
Started Aug 25 10:51:13 AM UTC 24
Finished Aug 25 10:51:24 AM UTC 24
Peak memory 251360 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2115897492 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/
spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_mode.2115897492
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/33.spi_device_flash_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/36.spi_device_flash_and_tpm.3817410789
Short name T409
Test name
Test status
Simulation time 6513106253 ps
CPU time 70.71 seconds
Started Aug 25 10:52:05 AM UTC 24
Finished Aug 25 10:53:18 AM UTC 24
Peak memory 245308 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3817410789 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
24/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_and_tpm.3817410789
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/36.spi_device_flash_and_tpm/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/0.spi_device_csb_read.3956325807
Short name T2
Test name
Test status
Simulation time 52318371 ps
CPU time 1.2 seconds
Started Aug 25 10:41:36 AM UTC 24
Finished Aug 25 10:41:38 AM UTC 24
Peak memory 215460 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3956325807 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/sp
i_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_csb_read.3956325807
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/0.spi_device_csb_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/0.spi_device_tl_errors.1510398409
Short name T116
Test name
Test status
Simulation time 114241718 ps
CPU time 3.16 seconds
Started Aug 25 09:45:16 AM UTC 24
Finished Aug 25 09:45:34 AM UTC 24
Peak memory 227300 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1510398409 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_08_24/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_tl_errors.1510398409
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/0.spi_device_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/0.spi_device_csr_aliasing.2772422462
Short name T138
Test name
Test status
Simulation time 417233493 ps
CPU time 6.49 seconds
Started Aug 25 09:45:16 AM UTC 24
Finished Aug 25 09:45:38 AM UTC 24
Peak memory 214820 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2772422462 -assert nopostproc +UVM
_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_csr_aliasing.2772422462
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/0.spi_device_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/0.spi_device_csr_bit_bash.730232069
Short name T1034
Test name
Test status
Simulation time 352718667 ps
CPU time 18.79 seconds
Started Aug 25 09:45:16 AM UTC 24
Finished Aug 25 09:45:48 AM UTC 24
Peak memory 225108 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=730232069 -assert nopostproc +UVM_
TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_csr_bit_bash.730232069
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/0.spi_device_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/0.spi_device_csr_mem_rw_with_rand_reset.2755981563
Short name T128
Test name
Test status
Simulation time 104327261 ps
CPU time 3.21 seconds
Started Aug 25 09:45:16 AM UTC 24
Finished Aug 25 09:45:35 AM UTC 24
Peak memory 227456 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000
000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb
_random_seed=2755981563 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_
name 0.spi_device_csr_mem_rw_with_rand_reset.2755981563
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/0.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/0.spi_device_csr_rw.2514170508
Short name T136
Test name
Test status
Simulation time 140632203 ps
CPU time 2.21 seconds
Started Aug 25 09:45:16 AM UTC 24
Finished Aug 25 09:45:34 AM UTC 24
Peak memory 225136 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2514170508 -assert nopostproc +UVM_TESTN
AME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_csr_rw.2514170508
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/0.spi_device_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/0.spi_device_intr_test.3502705536
Short name T1012
Test name
Test status
Simulation time 57647116 ps
CPU time 0.76 seconds
Started Aug 25 09:45:16 AM UTC 24
Finished Aug 25 09:45:31 AM UTC 24
Peak memory 211760 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3502705536 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_08_24/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_intr_test.3502705536
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/0.spi_device_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/0.spi_device_mem_partial_access.1947228115
Short name T134
Test name
Test status
Simulation time 237603985 ps
CPU time 2.02 seconds
Started Aug 25 09:45:16 AM UTC 24
Finished Aug 25 09:45:33 AM UTC 24
Peak memory 225308 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1947228115 -assert nopos
tproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re
po/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_mem_partial_access.1947228115
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/0.spi_device_mem_partial_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/0.spi_device_mem_walk.3217577246
Short name T1014
Test name
Test status
Simulation time 16974738 ps
CPU time 0.88 seconds
Started Aug 25 09:45:16 AM UTC 24
Finished Aug 25 09:45:32 AM UTC 24
Peak memory 211736 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3217577246 -assert nopostproc +UVM
_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_mem_walk.3217577246
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/0.spi_device_mem_walk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/0.spi_device_same_csr_outstanding.2380514113
Short name T156
Test name
Test status
Simulation time 63124646 ps
CPU time 3.82 seconds
Started Aug 25 09:45:16 AM UTC 24
Finished Aug 25 09:45:35 AM UTC 24
Peak memory 224996 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2380514113 -assert nop
ostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_same_csr_outstand
ing.2380514113
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/0.spi_device_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/0.spi_device_tl_intg_err.2871424373
Short name T326
Test name
Test status
Simulation time 1611739262 ps
CPU time 18.71 seconds
Started Aug 25 09:45:16 AM UTC 24
Finished Aug 25 09:45:50 AM UTC 24
Peak memory 228716 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2871424373 -assert nopostproc +
UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra
tch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_tl_intg_err.2871424373
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/0.spi_device_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/1.spi_device_csr_aliasing.1201070156
Short name T137
Test name
Test status
Simulation time 416937597 ps
CPU time 12.9 seconds
Started Aug 25 09:45:17 AM UTC 24
Finished Aug 25 09:45:37 AM UTC 24
Peak memory 225084 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1201070156 -assert nopostproc +UVM
_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_csr_aliasing.1201070156
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/1.spi_device_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/1.spi_device_csr_bit_bash.2175423214
Short name T167
Test name
Test status
Simulation time 2549895086 ps
CPU time 24.02 seconds
Started Aug 25 09:45:17 AM UTC 24
Finished Aug 25 09:45:48 AM UTC 24
Peak memory 214860 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2175423214 -assert nopostproc +UVM
_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_csr_bit_bash.2175423214
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/1.spi_device_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/1.spi_device_csr_hw_reset.3909212168
Short name T101
Test name
Test status
Simulation time 38140362 ps
CPU time 1.16 seconds
Started Aug 25 09:45:16 AM UTC 24
Finished Aug 25 09:45:25 AM UTC 24
Peak memory 214216 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3909212168 -assert nopostproc +UVM
_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_csr_hw_reset.3909212168
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/1.spi_device_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/1.spi_device_csr_mem_rw_with_rand_reset.572960377
Short name T95
Test name
Test status
Simulation time 84781991 ps
CPU time 3.25 seconds
Started Aug 25 09:45:17 AM UTC 24
Finished Aug 25 09:45:27 AM UTC 24
Peak memory 229228 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000
000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb
_random_seed=572960377 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n
ame 1.spi_device_csr_mem_rw_with_rand_reset.572960377
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/1.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/1.spi_device_csr_rw.3011041343
Short name T154
Test name
Test status
Simulation time 63347385 ps
CPU time 2.13 seconds
Started Aug 25 09:45:17 AM UTC 24
Finished Aug 25 09:45:33 AM UTC 24
Peak memory 225348 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3011041343 -assert nopostproc +UVM_TESTN
AME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_csr_rw.3011041343
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/1.spi_device_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/1.spi_device_intr_test.86565661
Short name T1011
Test name
Test status
Simulation time 27609493 ps
CPU time 0.65 seconds
Started Aug 25 09:45:16 AM UTC 24
Finished Aug 25 09:45:30 AM UTC 24
Peak memory 211672 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=86565661 -assert nopostproc +UVM_TESTNAME=s
pi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_08_24/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_intr_test.86565661
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/1.spi_device_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/1.spi_device_mem_partial_access.2094230667
Short name T135
Test name
Test status
Simulation time 563436054 ps
CPU time 2.06 seconds
Started Aug 25 09:45:16 AM UTC 24
Finished Aug 25 09:45:33 AM UTC 24
Peak memory 225068 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2094230667 -assert nopos
tproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re
po/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_mem_partial_access.2094230667
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/1.spi_device_mem_partial_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/1.spi_device_mem_walk.3057648209
Short name T1013
Test name
Test status
Simulation time 33974458 ps
CPU time 0.75 seconds
Started Aug 25 09:45:16 AM UTC 24
Finished Aug 25 09:45:32 AM UTC 24
Peak memory 211756 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3057648209 -assert nopostproc +UVM
_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_mem_walk.3057648209
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/1.spi_device_mem_walk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/1.spi_device_same_csr_outstanding.1797014283
Short name T153
Test name
Test status
Simulation time 62294032 ps
CPU time 3.33 seconds
Started Aug 25 09:45:17 AM UTC 24
Finished Aug 25 09:45:27 AM UTC 24
Peak memory 225140 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1797014283 -assert nop
ostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_same_csr_outstand
ing.1797014283
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/1.spi_device_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/1.spi_device_tl_intg_err.2164461158
Short name T117
Test name
Test status
Simulation time 849823293 ps
CPU time 10.81 seconds
Started Aug 25 09:45:16 AM UTC 24
Finished Aug 25 09:45:40 AM UTC 24
Peak memory 225308 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2164461158 -assert nopostproc +
UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra
tch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_tl_intg_err.2164461158
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/1.spi_device_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/10.spi_device_csr_mem_rw_with_rand_reset.737476113
Short name T1104
Test name
Test status
Simulation time 148743997 ps
CPU time 4.5 seconds
Started Aug 25 09:45:45 AM UTC 24
Finished Aug 25 09:46:11 AM UTC 24
Peak memory 229292 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000
000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb
_random_seed=737476113 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n
ame 10.spi_device_csr_mem_rw_with_rand_reset.737476113
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/10.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/10.spi_device_csr_rw.15895221
Short name T1077
Test name
Test status
Simulation time 420326067 ps
CPU time 1.52 seconds
Started Aug 25 09:45:45 AM UTC 24
Finished Aug 25 09:46:08 AM UTC 24
Peak memory 223912 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=15895221 -assert nopostproc +UVM_TESTNAM
E=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_08_24/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_csr_rw.15895221
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/10.spi_device_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/10.spi_device_intr_test.3128546211
Short name T1070
Test name
Test status
Simulation time 43882181 ps
CPU time 0.88 seconds
Started Aug 25 09:45:44 AM UTC 24
Finished Aug 25 09:46:06 AM UTC 24
Peak memory 211772 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3128546211 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_08_24/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_intr_test.3128546211
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/10.spi_device_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/10.spi_device_same_csr_outstanding.2172342838
Short name T1082
Test name
Test status
Simulation time 44717522 ps
CPU time 2.27 seconds
Started Aug 25 09:45:45 AM UTC 24
Finished Aug 25 09:46:08 AM UTC 24
Peak memory 225004 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2172342838 -assert nop
ostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_same_csr_outstan
ding.2172342838
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/10.spi_device_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/10.spi_device_tl_errors.1751352919
Short name T1106
Test name
Test status
Simulation time 500802348 ps
CPU time 5.9 seconds
Started Aug 25 09:45:44 AM UTC 24
Finished Aug 25 09:46:11 AM UTC 24
Peak memory 227444 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1751352919 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_08_24/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_tl_errors.1751352919
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/10.spi_device_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/10.spi_device_tl_intg_err.1763667061
Short name T1119
Test name
Test status
Simulation time 822457706 ps
CPU time 17.95 seconds
Started Aug 25 09:45:44 AM UTC 24
Finished Aug 25 09:46:23 AM UTC 24
Peak memory 227432 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1763667061 -assert nopostproc +
UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra
tch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_tl_intg_err.1763667061
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/10.spi_device_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/11.spi_device_csr_mem_rw_with_rand_reset.799429320
Short name T1055
Test name
Test status
Simulation time 113018116 ps
CPU time 2.54 seconds
Started Aug 25 09:45:47 AM UTC 24
Finished Aug 25 09:46:03 AM UTC 24
Peak memory 227396 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000
000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb
_random_seed=799429320 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n
ame 11.spi_device_csr_mem_rw_with_rand_reset.799429320
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/11.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/11.spi_device_csr_rw.1981017393
Short name T1053
Test name
Test status
Simulation time 185491251 ps
CPU time 2.38 seconds
Started Aug 25 09:45:47 AM UTC 24
Finished Aug 25 09:46:02 AM UTC 24
Peak memory 225212 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1981017393 -assert nopostproc +UVM_TESTN
AME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_csr_rw.1981017393
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/11.spi_device_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/11.spi_device_intr_test.2712150357
Short name T1072
Test name
Test status
Simulation time 54843449 ps
CPU time 1.15 seconds
Started Aug 25 09:45:47 AM UTC 24
Finished Aug 25 09:46:07 AM UTC 24
Peak memory 211636 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2712150357 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_08_24/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_intr_test.2712150357
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/11.spi_device_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/11.spi_device_same_csr_outstanding.232700024
Short name T1051
Test name
Test status
Simulation time 73939823 ps
CPU time 1.77 seconds
Started Aug 25 09:45:47 AM UTC 24
Finished Aug 25 09:46:02 AM UTC 24
Peak memory 224380 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=232700024 -assert nopo
stproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r
epo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_same_csr_outstand
ing.232700024
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/11.spi_device_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/11.spi_device_tl_errors.1931905086
Short name T1099
Test name
Test status
Simulation time 119669209 ps
CPU time 3.79 seconds
Started Aug 25 09:45:45 AM UTC 24
Finished Aug 25 09:46:10 AM UTC 24
Peak memory 227252 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1931905086 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_08_24/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_tl_errors.1931905086
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/11.spi_device_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/11.spi_device_tl_intg_err.3101384181
Short name T328
Test name
Test status
Simulation time 420813103 ps
CPU time 6.66 seconds
Started Aug 25 09:45:47 AM UTC 24
Finished Aug 25 09:46:12 AM UTC 24
Peak memory 225248 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3101384181 -assert nopostproc +
UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra
tch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_tl_intg_err.3101384181
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/11.spi_device_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/12.spi_device_csr_mem_rw_with_rand_reset.3539940178
Short name T1054
Test name
Test status
Simulation time 52945400 ps
CPU time 1.9 seconds
Started Aug 25 09:45:48 AM UTC 24
Finished Aug 25 09:46:02 AM UTC 24
Peak memory 226068 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000
000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb
_random_seed=3539940178 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_
name 12.spi_device_csr_mem_rw_with_rand_reset.3539940178
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/12.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/12.spi_device_csr_rw.958488433
Short name T1050
Test name
Test status
Simulation time 641240110 ps
CPU time 1.39 seconds
Started Aug 25 09:45:47 AM UTC 24
Finished Aug 25 09:46:02 AM UTC 24
Peak memory 213616 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=958488433 -assert nopostproc +UVM_TESTNA
ME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_csr_rw.958488433
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/12.spi_device_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/12.spi_device_intr_test.2097313332
Short name T1048
Test name
Test status
Simulation time 36677514 ps
CPU time 0.87 seconds
Started Aug 25 09:45:47 AM UTC 24
Finished Aug 25 09:46:01 AM UTC 24
Peak memory 211728 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2097313332 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_08_24/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_intr_test.2097313332
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/12.spi_device_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/12.spi_device_same_csr_outstanding.1451971915
Short name T1052
Test name
Test status
Simulation time 111350465 ps
CPU time 1.86 seconds
Started Aug 25 09:45:47 AM UTC 24
Finished Aug 25 09:46:02 AM UTC 24
Peak memory 224196 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1451971915 -assert nop
ostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_same_csr_outstan
ding.1451971915
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/12.spi_device_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/12.spi_device_tl_errors.2021742004
Short name T1057
Test name
Test status
Simulation time 168854077 ps
CPU time 4.45 seconds
Started Aug 25 09:45:47 AM UTC 24
Finished Aug 25 09:46:05 AM UTC 24
Peak memory 227252 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2021742004 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_08_24/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_tl_errors.2021742004
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/12.spi_device_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/13.spi_device_csr_mem_rw_with_rand_reset.3345969760
Short name T1102
Test name
Test status
Simulation time 86617766 ps
CPU time 2.31 seconds
Started Aug 25 09:45:48 AM UTC 24
Finished Aug 25 09:46:10 AM UTC 24
Peak memory 227120 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000
000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb
_random_seed=3345969760 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_
name 13.spi_device_csr_mem_rw_with_rand_reset.3345969760
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/13.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/13.spi_device_csr_rw.649792105
Short name T1107
Test name
Test status
Simulation time 40774580 ps
CPU time 3.49 seconds
Started Aug 25 09:45:48 AM UTC 24
Finished Aug 25 09:46:11 AM UTC 24
Peak memory 225044 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=649792105 -assert nopostproc +UVM_TESTNA
ME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_csr_rw.649792105
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/13.spi_device_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/13.spi_device_intr_test.3123240388
Short name T1049
Test name
Test status
Simulation time 27064153 ps
CPU time 0.77 seconds
Started Aug 25 09:45:48 AM UTC 24
Finished Aug 25 09:46:01 AM UTC 24
Peak memory 211768 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3123240388 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_08_24/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_intr_test.3123240388
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/13.spi_device_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/13.spi_device_same_csr_outstanding.718738562
Short name T1080
Test name
Test status
Simulation time 245178735 ps
CPU time 4.55 seconds
Started Aug 25 09:45:48 AM UTC 24
Finished Aug 25 09:46:12 AM UTC 24
Peak memory 224992 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=718738562 -assert nopo
stproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r
epo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_same_csr_outstand
ing.718738562
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/13.spi_device_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/13.spi_device_tl_errors.3095335957
Short name T1088
Test name
Test status
Simulation time 167458038 ps
CPU time 3.9 seconds
Started Aug 25 09:45:48 AM UTC 24
Finished Aug 25 09:46:11 AM UTC 24
Peak memory 227456 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3095335957 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_08_24/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_tl_errors.3095335957
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/13.spi_device_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/13.spi_device_tl_intg_err.1702068931
Short name T1111
Test name
Test status
Simulation time 222435922 ps
CPU time 10.95 seconds
Started Aug 25 09:45:48 AM UTC 24
Finished Aug 25 09:46:19 AM UTC 24
Peak memory 225108 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1702068931 -assert nopostproc +
UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra
tch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_tl_intg_err.1702068931
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/13.spi_device_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/14.spi_device_csr_mem_rw_with_rand_reset.2400971391
Short name T1127
Test name
Test status
Simulation time 90768631 ps
CPU time 2.46 seconds
Started Aug 25 09:45:50 AM UTC 24
Finished Aug 25 09:46:31 AM UTC 24
Peak memory 228808 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000
000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb
_random_seed=2400971391 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_
name 14.spi_device_csr_mem_rw_with_rand_reset.2400971391
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/14.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/14.spi_device_csr_rw.2380995293
Short name T1100
Test name
Test status
Simulation time 70325149 ps
CPU time 1.65 seconds
Started Aug 25 09:45:50 AM UTC 24
Finished Aug 25 09:46:10 AM UTC 24
Peak memory 223912 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2380995293 -assert nopostproc +UVM_TESTN
AME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_csr_rw.2380995293
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/14.spi_device_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/14.spi_device_intr_test.2501515408
Short name T1096
Test name
Test status
Simulation time 122484144 ps
CPU time 1 seconds
Started Aug 25 09:45:50 AM UTC 24
Finished Aug 25 09:46:09 AM UTC 24
Peak memory 211768 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2501515408 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_08_24/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_intr_test.2501515408
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/14.spi_device_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/14.spi_device_same_csr_outstanding.930563005
Short name T1110
Test name
Test status
Simulation time 44240031 ps
CPU time 3.11 seconds
Started Aug 25 09:45:50 AM UTC 24
Finished Aug 25 09:46:12 AM UTC 24
Peak memory 225068 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=930563005 -assert nopo
stproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r
epo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_same_csr_outstand
ing.930563005
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/14.spi_device_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/14.spi_device_tl_errors.967163158
Short name T324
Test name
Test status
Simulation time 475862920 ps
CPU time 4.37 seconds
Started Aug 25 09:45:48 AM UTC 24
Finished Aug 25 09:46:12 AM UTC 24
Peak memory 225404 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=967163158 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_08_24/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_tl_errors.967163158
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/14.spi_device_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/14.spi_device_tl_intg_err.1716643031
Short name T1078
Test name
Test status
Simulation time 121234125 ps
CPU time 6.83 seconds
Started Aug 25 09:45:48 AM UTC 24
Finished Aug 25 09:46:15 AM UTC 24
Peak memory 224988 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1716643031 -assert nopostproc +
UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra
tch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_tl_intg_err.1716643031
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/14.spi_device_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/15.spi_device_csr_mem_rw_with_rand_reset.988685374
Short name T1040
Test name
Test status
Simulation time 166000332 ps
CPU time 1.91 seconds
Started Aug 25 09:45:52 AM UTC 24
Finished Aug 25 09:45:57 AM UTC 24
Peak memory 226068 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000
000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb
_random_seed=988685374 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n
ame 15.spi_device_csr_mem_rw_with_rand_reset.988685374
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/15.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/15.spi_device_csr_rw.1106496002
Short name T1041
Test name
Test status
Simulation time 76038599 ps
CPU time 2.35 seconds
Started Aug 25 09:45:50 AM UTC 24
Finished Aug 25 09:45:57 AM UTC 24
Peak memory 225336 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1106496002 -assert nopostproc +UVM_TESTN
AME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_csr_rw.1106496002
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/15.spi_device_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/15.spi_device_intr_test.4278388986
Short name T1035
Test name
Test status
Simulation time 13510970 ps
CPU time 0.88 seconds
Started Aug 25 09:45:50 AM UTC 24
Finished Aug 25 09:45:55 AM UTC 24
Peak memory 211768 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4278388986 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_08_24/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_intr_test.4278388986
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/15.spi_device_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/15.spi_device_same_csr_outstanding.1778580412
Short name T1038
Test name
Test status
Simulation time 69215025 ps
CPU time 1.6 seconds
Started Aug 25 09:45:50 AM UTC 24
Finished Aug 25 09:45:56 AM UTC 24
Peak memory 224168 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1778580412 -assert nop
ostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_same_csr_outstan
ding.1778580412
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/15.spi_device_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/15.spi_device_tl_errors.1779968037
Short name T1059
Test name
Test status
Simulation time 66227867 ps
CPU time 3.94 seconds
Started Aug 25 09:45:50 AM UTC 24
Finished Aug 25 09:46:05 AM UTC 24
Peak memory 225184 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1779968037 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_08_24/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_tl_errors.1779968037
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/15.spi_device_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/15.spi_device_tl_intg_err.968949342
Short name T331
Test name
Test status
Simulation time 1126490224 ps
CPU time 6.62 seconds
Started Aug 25 09:45:50 AM UTC 24
Finished Aug 25 09:46:01 AM UTC 24
Peak memory 233132 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=968949342 -assert nopostproc +U
VM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_tl_intg_err.968949342
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/15.spi_device_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/16.spi_device_csr_mem_rw_with_rand_reset.2373638066
Short name T1079
Test name
Test status
Simulation time 597560866 ps
CPU time 2.6 seconds
Started Aug 25 09:45:57 AM UTC 24
Finished Aug 25 09:46:08 AM UTC 24
Peak memory 229304 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000
000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb
_random_seed=2373638066 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_
name 16.spi_device_csr_mem_rw_with_rand_reset.2373638066
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/16.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/16.spi_device_csr_rw.2736647796
Short name T1043
Test name
Test status
Simulation time 1700257739 ps
CPU time 2.36 seconds
Started Aug 25 09:45:52 AM UTC 24
Finished Aug 25 09:45:57 AM UTC 24
Peak memory 214752 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2736647796 -assert nopostproc +UVM_TESTN
AME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_csr_rw.2736647796
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/16.spi_device_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/16.spi_device_intr_test.2339622045
Short name T1036
Test name
Test status
Simulation time 21786538 ps
CPU time 0.68 seconds
Started Aug 25 09:45:52 AM UTC 24
Finished Aug 25 09:45:55 AM UTC 24
Peak memory 211628 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2339622045 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_08_24/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_intr_test.2339622045
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/16.spi_device_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/16.spi_device_same_csr_outstanding.3310247434
Short name T1093
Test name
Test status
Simulation time 442615588 ps
CPU time 4.38 seconds
Started Aug 25 09:45:57 AM UTC 24
Finished Aug 25 09:46:09 AM UTC 24
Peak memory 225052 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3310247434 -assert nop
ostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_same_csr_outstan
ding.3310247434
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/16.spi_device_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/16.spi_device_tl_errors.765478416
Short name T122
Test name
Test status
Simulation time 104514017 ps
CPU time 2.76 seconds
Started Aug 25 09:45:52 AM UTC 24
Finished Aug 25 09:45:57 AM UTC 24
Peak memory 225204 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=765478416 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_08_24/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_tl_errors.765478416
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/16.spi_device_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/16.spi_device_tl_intg_err.247013379
Short name T332
Test name
Test status
Simulation time 321236573 ps
CPU time 6.37 seconds
Started Aug 25 09:45:52 AM UTC 24
Finished Aug 25 09:46:01 AM UTC 24
Peak memory 225000 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=247013379 -assert nopostproc +U
VM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_tl_intg_err.247013379
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/16.spi_device_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/17.spi_device_csr_mem_rw_with_rand_reset.3038287709
Short name T1097
Test name
Test status
Simulation time 209270687 ps
CPU time 1.87 seconds
Started Aug 25 09:45:59 AM UTC 24
Finished Aug 25 09:46:10 AM UTC 24
Peak memory 226024 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000
000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb
_random_seed=3038287709 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_
name 17.spi_device_csr_mem_rw_with_rand_reset.3038287709
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/17.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/17.spi_device_csr_rw.2260413157
Short name T1101
Test name
Test status
Simulation time 79497218 ps
CPU time 2.22 seconds
Started Aug 25 09:45:59 AM UTC 24
Finished Aug 25 09:46:10 AM UTC 24
Peak memory 225084 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2260413157 -assert nopostproc +UVM_TESTN
AME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_csr_rw.2260413157
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/17.spi_device_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/17.spi_device_intr_test.3682383620
Short name T1061
Test name
Test status
Simulation time 18985059 ps
CPU time 0.76 seconds
Started Aug 25 09:45:57 AM UTC 24
Finished Aug 25 09:46:05 AM UTC 24
Peak memory 211768 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3682383620 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_08_24/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_intr_test.3682383620
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/17.spi_device_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/17.spi_device_same_csr_outstanding.3641173623
Short name T1108
Test name
Test status
Simulation time 45662464 ps
CPU time 3.37 seconds
Started Aug 25 09:45:59 AM UTC 24
Finished Aug 25 09:46:11 AM UTC 24
Peak memory 224984 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3641173623 -assert nop
ostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_same_csr_outstan
ding.3641173623
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/17.spi_device_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/17.spi_device_tl_errors.3569461014
Short name T1109
Test name
Test status
Simulation time 235555379 ps
CPU time 6.22 seconds
Started Aug 25 09:45:57 AM UTC 24
Finished Aug 25 09:46:11 AM UTC 24
Peak memory 225284 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3569461014 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_08_24/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_tl_errors.3569461014
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/17.spi_device_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/17.spi_device_tl_intg_err.1640401615
Short name T1112
Test name
Test status
Simulation time 590315832 ps
CPU time 13.38 seconds
Started Aug 25 09:45:57 AM UTC 24
Finished Aug 25 09:46:19 AM UTC 24
Peak memory 227044 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1640401615 -assert nopostproc +
UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra
tch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_tl_intg_err.1640401615
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/17.spi_device_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/18.spi_device_csr_mem_rw_with_rand_reset.629555029
Short name T1105
Test name
Test status
Simulation time 481249203 ps
CPU time 2.79 seconds
Started Aug 25 09:45:59 AM UTC 24
Finished Aug 25 09:46:11 AM UTC 24
Peak memory 227096 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000
000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb
_random_seed=629555029 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n
ame 18.spi_device_csr_mem_rw_with_rand_reset.629555029
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/18.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/18.spi_device_csr_rw.3460834447
Short name T1098
Test name
Test status
Simulation time 376301922 ps
CPU time 1.8 seconds
Started Aug 25 09:45:59 AM UTC 24
Finished Aug 25 09:46:10 AM UTC 24
Peak memory 223888 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3460834447 -assert nopostproc +UVM_TESTN
AME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_csr_rw.3460834447
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/18.spi_device_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/18.spi_device_intr_test.4248551179
Short name T1094
Test name
Test status
Simulation time 14678452 ps
CPU time 1.08 seconds
Started Aug 25 09:45:59 AM UTC 24
Finished Aug 25 09:46:09 AM UTC 24
Peak memory 211768 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4248551179 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_08_24/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_intr_test.4248551179
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/18.spi_device_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/18.spi_device_same_csr_outstanding.1246996672
Short name T1103
Test name
Test status
Simulation time 27636609 ps
CPU time 2.13 seconds
Started Aug 25 09:45:59 AM UTC 24
Finished Aug 25 09:46:10 AM UTC 24
Peak memory 225024 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1246996672 -assert nop
ostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_same_csr_outstan
ding.1246996672
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/18.spi_device_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/18.spi_device_tl_errors.4004054171
Short name T325
Test name
Test status
Simulation time 44749962 ps
CPU time 3.22 seconds
Started Aug 25 09:45:59 AM UTC 24
Finished Aug 25 09:46:11 AM UTC 24
Peak memory 227024 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4004054171 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_08_24/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_tl_errors.4004054171
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/18.spi_device_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/18.spi_device_tl_intg_err.2687788603
Short name T1120
Test name
Test status
Simulation time 2135108297 ps
CPU time 15.58 seconds
Started Aug 25 09:45:59 AM UTC 24
Finished Aug 25 09:46:24 AM UTC 24
Peak memory 227264 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2687788603 -assert nopostproc +
UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra
tch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_tl_intg_err.2687788603
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/18.spi_device_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/19.spi_device_csr_mem_rw_with_rand_reset.1898413662
Short name T1090
Test name
Test status
Simulation time 62543469 ps
CPU time 3.76 seconds
Started Aug 25 09:46:03 AM UTC 24
Finished Aug 25 09:46:09 AM UTC 24
Peak memory 229244 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000
000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb
_random_seed=1898413662 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_
name 19.spi_device_csr_mem_rw_with_rand_reset.1898413662
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/19.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/19.spi_device_csr_rw.4071615886
Short name T1076
Test name
Test status
Simulation time 69074951 ps
CPU time 1.42 seconds
Started Aug 25 09:46:01 AM UTC 24
Finished Aug 25 09:46:07 AM UTC 24
Peak memory 223888 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4071615886 -assert nopostproc +UVM_TESTN
AME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_csr_rw.4071615886
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/19.spi_device_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/19.spi_device_intr_test.1482971079
Short name T1060
Test name
Test status
Simulation time 50473901 ps
CPU time 0.81 seconds
Started Aug 25 09:46:01 AM UTC 24
Finished Aug 25 09:46:05 AM UTC 24
Peak memory 211768 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1482971079 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_08_24/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_intr_test.1482971079
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/19.spi_device_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/19.spi_device_same_csr_outstanding.2702317929
Short name T1095
Test name
Test status
Simulation time 116535030 ps
CPU time 4.05 seconds
Started Aug 25 09:46:03 AM UTC 24
Finished Aug 25 09:46:09 AM UTC 24
Peak memory 225044 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2702317929 -assert nop
ostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_same_csr_outstan
ding.2702317929
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/19.spi_device_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/19.spi_device_tl_errors.4062822434
Short name T1075
Test name
Test status
Simulation time 166156722 ps
CPU time 1.42 seconds
Started Aug 25 09:46:01 AM UTC 24
Finished Aug 25 09:46:07 AM UTC 24
Peak memory 224272 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4062822434 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_08_24/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_tl_errors.4062822434
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/19.spi_device_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/19.spi_device_tl_intg_err.4251376213
Short name T1118
Test name
Test status
Simulation time 705761014 ps
CPU time 15.11 seconds
Started Aug 25 09:46:01 AM UTC 24
Finished Aug 25 09:46:21 AM UTC 24
Peak memory 227168 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4251376213 -assert nopostproc +
UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra
tch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_tl_intg_err.4251376213
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/19.spi_device_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/2.spi_device_csr_aliasing.658724226
Short name T1015
Test name
Test status
Simulation time 421349558 ps
CPU time 6.55 seconds
Started Aug 25 09:45:17 AM UTC 24
Finished Aug 25 09:45:36 AM UTC 24
Peak memory 214764 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=658724226 -assert nopostproc +UVM_
TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_csr_aliasing.658724226
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/2.spi_device_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/2.spi_device_csr_bit_bash.129143654
Short name T139
Test name
Test status
Simulation time 3520198909 ps
CPU time 19 seconds
Started Aug 25 09:45:17 AM UTC 24
Finished Aug 25 09:45:44 AM UTC 24
Peak memory 214960 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=129143654 -assert nopostproc +UVM_
TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_csr_bit_bash.129143654
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/2.spi_device_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/2.spi_device_csr_hw_reset.1390307095
Short name T102
Test name
Test status
Simulation time 203389113 ps
CPU time 1.33 seconds
Started Aug 25 09:45:17 AM UTC 24
Finished Aug 25 09:45:26 AM UTC 24
Peak memory 226236 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1390307095 -assert nopostproc +UVM
_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_csr_hw_reset.1390307095
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/2.spi_device_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/2.spi_device_csr_mem_rw_with_rand_reset.1338660144
Short name T131
Test name
Test status
Simulation time 805123691 ps
CPU time 3.95 seconds
Started Aug 25 09:45:41 AM UTC 24
Finished Aug 25 09:45:46 AM UTC 24
Peak memory 229496 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000
000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb
_random_seed=1338660144 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_
name 2.spi_device_csr_mem_rw_with_rand_reset.1338660144
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/2.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/2.spi_device_csr_rw.701833667
Short name T133
Test name
Test status
Simulation time 133224545 ps
CPU time 2.64 seconds
Started Aug 25 09:45:17 AM UTC 24
Finished Aug 25 09:45:27 AM UTC 24
Peak memory 224996 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=701833667 -assert nopostproc +UVM_TESTNA
ME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_csr_rw.701833667
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/2.spi_device_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/2.spi_device_intr_test.366549587
Short name T1009
Test name
Test status
Simulation time 24316681 ps
CPU time 0.94 seconds
Started Aug 25 09:45:17 AM UTC 24
Finished Aug 25 09:45:25 AM UTC 24
Peak memory 211760 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=366549587 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_08_24/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_intr_test.366549587
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/2.spi_device_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/2.spi_device_mem_partial_access.818182868
Short name T132
Test name
Test status
Simulation time 199993221 ps
CPU time 1.51 seconds
Started Aug 25 09:45:17 AM UTC 24
Finished Aug 25 09:45:26 AM UTC 24
Peak memory 223944 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=818182868 -assert nopost
proc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep
o/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_mem_partial_access.818182868
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/2.spi_device_mem_partial_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/2.spi_device_mem_walk.2970056166
Short name T1010
Test name
Test status
Simulation time 13094589 ps
CPU time 0.68 seconds
Started Aug 25 09:45:17 AM UTC 24
Finished Aug 25 09:45:26 AM UTC 24
Peak memory 211756 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2970056166 -assert nopostproc +UVM
_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_mem_walk.2970056166
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/2.spi_device_mem_walk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/2.spi_device_same_csr_outstanding.2589634201
Short name T155
Test name
Test status
Simulation time 44531060 ps
CPU time 3 seconds
Started Aug 25 09:45:17 AM UTC 24
Finished Aug 25 09:45:35 AM UTC 24
Peak memory 225024 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2589634201 -assert nop
ostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_same_csr_outstand
ing.2589634201
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/2.spi_device_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/2.spi_device_tl_errors.2591475747
Short name T94
Test name
Test status
Simulation time 26804897 ps
CPU time 1.56 seconds
Started Aug 25 09:45:17 AM UTC 24
Finished Aug 25 09:45:26 AM UTC 24
Peak memory 224016 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2591475747 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_08_24/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_tl_errors.2591475747
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/2.spi_device_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/20.spi_device_intr_test.2916645341
Short name T1063
Test name
Test status
Simulation time 21825973 ps
CPU time 0.7 seconds
Started Aug 25 09:46:03 AM UTC 24
Finished Aug 25 09:46:06 AM UTC 24
Peak memory 211768 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2916645341 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_08_24/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.spi_device_intr_test.2916645341
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/20.spi_device_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/21.spi_device_intr_test.1598286500
Short name T1066
Test name
Test status
Simulation time 13035760 ps
CPU time 0.86 seconds
Started Aug 25 09:46:03 AM UTC 24
Finished Aug 25 09:46:06 AM UTC 24
Peak memory 211768 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1598286500 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_08_24/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.spi_device_intr_test.1598286500
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/21.spi_device_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/22.spi_device_intr_test.1677167607
Short name T1062
Test name
Test status
Simulation time 50085886 ps
CPU time 0.66 seconds
Started Aug 25 09:46:03 AM UTC 24
Finished Aug 25 09:46:06 AM UTC 24
Peak memory 211768 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1677167607 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_08_24/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.spi_device_intr_test.1677167607
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/22.spi_device_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/23.spi_device_intr_test.673977719
Short name T1064
Test name
Test status
Simulation time 14656053 ps
CPU time 0.76 seconds
Started Aug 25 09:46:04 AM UTC 24
Finished Aug 25 09:46:06 AM UTC 24
Peak memory 211772 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=673977719 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_08_24/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.spi_device_intr_test.673977719
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/23.spi_device_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/24.spi_device_intr_test.72844937
Short name T1067
Test name
Test status
Simulation time 12539426 ps
CPU time 0.86 seconds
Started Aug 25 09:46:04 AM UTC 24
Finished Aug 25 09:46:06 AM UTC 24
Peak memory 211768 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=72844937 -assert nopostproc +UVM_TESTNAME=s
pi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_08_24/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.spi_device_intr_test.72844937
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/24.spi_device_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/25.spi_device_intr_test.1134264320
Short name T1071
Test name
Test status
Simulation time 12082365 ps
CPU time 0.88 seconds
Started Aug 25 09:46:04 AM UTC 24
Finished Aug 25 09:46:06 AM UTC 24
Peak memory 211768 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1134264320 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_08_24/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.spi_device_intr_test.1134264320
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/25.spi_device_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/26.spi_device_intr_test.4157215322
Short name T1069
Test name
Test status
Simulation time 41672114 ps
CPU time 0.76 seconds
Started Aug 25 09:46:04 AM UTC 24
Finished Aug 25 09:46:06 AM UTC 24
Peak memory 211768 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4157215322 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_08_24/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.spi_device_intr_test.4157215322
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/26.spi_device_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/27.spi_device_intr_test.2730821504
Short name T1068
Test name
Test status
Simulation time 46431533 ps
CPU time 0.67 seconds
Started Aug 25 09:46:04 AM UTC 24
Finished Aug 25 09:46:06 AM UTC 24
Peak memory 211768 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2730821504 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_08_24/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.spi_device_intr_test.2730821504
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/27.spi_device_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/28.spi_device_intr_test.73260779
Short name T1085
Test name
Test status
Simulation time 42229255 ps
CPU time 1.04 seconds
Started Aug 25 09:46:06 AM UTC 24
Finished Aug 25 09:46:08 AM UTC 24
Peak memory 211768 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=73260779 -assert nopostproc +UVM_TESTNAME=s
pi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_08_24/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.spi_device_intr_test.73260779
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/28.spi_device_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/29.spi_device_intr_test.808172032
Short name T1084
Test name
Test status
Simulation time 11995761 ps
CPU time 1 seconds
Started Aug 25 09:46:06 AM UTC 24
Finished Aug 25 09:46:08 AM UTC 24
Peak memory 211772 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=808172032 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_08_24/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.spi_device_intr_test.808172032
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/29.spi_device_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/3.spi_device_csr_aliasing.592996641
Short name T168
Test name
Test status
Simulation time 370863637 ps
CPU time 7.93 seconds
Started Aug 25 09:45:42 AM UTC 24
Finished Aug 25 09:45:52 AM UTC 24
Peak memory 225076 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=592996641 -assert nopostproc +UVM_
TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_csr_aliasing.592996641
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/3.spi_device_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/3.spi_device_csr_bit_bash.1950432311
Short name T1056
Test name
Test status
Simulation time 355248759 ps
CPU time 20.42 seconds
Started Aug 25 09:45:42 AM UTC 24
Finished Aug 25 09:46:04 AM UTC 24
Peak memory 214764 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1950432311 -assert nopostproc +UVM
_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_csr_bit_bash.1950432311
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/3.spi_device_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/3.spi_device_csr_hw_reset.1325776933
Short name T1019
Test name
Test status
Simulation time 23553169 ps
CPU time 1.11 seconds
Started Aug 25 09:45:42 AM UTC 24
Finished Aug 25 09:45:45 AM UTC 24
Peak memory 213668 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1325776933 -assert nopostproc +UVM
_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_csr_hw_reset.1325776933
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/3.spi_device_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/3.spi_device_csr_mem_rw_with_rand_reset.3660362369
Short name T129
Test name
Test status
Simulation time 655163672 ps
CPU time 1.55 seconds
Started Aug 25 09:45:42 AM UTC 24
Finished Aug 25 09:45:45 AM UTC 24
Peak memory 226068 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000
000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb
_random_seed=3660362369 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_
name 3.spi_device_csr_mem_rw_with_rand_reset.3660362369
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/3.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/3.spi_device_csr_rw.3221068717
Short name T140
Test name
Test status
Simulation time 150200715 ps
CPU time 2.02 seconds
Started Aug 25 09:45:42 AM UTC 24
Finished Aug 25 09:45:46 AM UTC 24
Peak memory 225016 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3221068717 -assert nopostproc +UVM_TESTN
AME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_csr_rw.3221068717
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/3.spi_device_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/3.spi_device_intr_test.931183598
Short name T1016
Test name
Test status
Simulation time 51314220 ps
CPU time 0.73 seconds
Started Aug 25 09:45:41 AM UTC 24
Finished Aug 25 09:45:43 AM UTC 24
Peak memory 211768 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=931183598 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_08_24/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_intr_test.931183598
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/3.spi_device_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/3.spi_device_mem_partial_access.3535169220
Short name T1024
Test name
Test status
Simulation time 42033338 ps
CPU time 2.02 seconds
Started Aug 25 09:45:42 AM UTC 24
Finished Aug 25 09:45:45 AM UTC 24
Peak memory 225116 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3535169220 -assert nopos
tproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re
po/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_mem_partial_access.3535169220
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/3.spi_device_mem_partial_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/3.spi_device_mem_walk.1726091984
Short name T1017
Test name
Test status
Simulation time 11395625 ps
CPU time 0.75 seconds
Started Aug 25 09:45:41 AM UTC 24
Finished Aug 25 09:45:43 AM UTC 24
Peak memory 211756 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1726091984 -assert nopostproc +UVM
_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_mem_walk.1726091984
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/3.spi_device_mem_walk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/3.spi_device_same_csr_outstanding.2247621479
Short name T165
Test name
Test status
Simulation time 365113342 ps
CPU time 3.62 seconds
Started Aug 25 09:45:42 AM UTC 24
Finished Aug 25 09:45:47 AM UTC 24
Peak memory 225032 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2247621479 -assert nop
ostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_same_csr_outstand
ing.2247621479
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/3.spi_device_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/3.spi_device_tl_errors.2845929641
Short name T126
Test name
Test status
Simulation time 103398430 ps
CPU time 3.3 seconds
Started Aug 25 09:45:41 AM UTC 24
Finished Aug 25 09:45:46 AM UTC 24
Peak memory 225284 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2845929641 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_08_24/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_tl_errors.2845929641
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/3.spi_device_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/3.spi_device_tl_intg_err.540872453
Short name T333
Test name
Test status
Simulation time 10905927318 ps
CPU time 13.31 seconds
Started Aug 25 09:45:41 AM UTC 24
Finished Aug 25 09:45:56 AM UTC 24
Peak memory 225372 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=540872453 -assert nopostproc +U
VM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_tl_intg_err.540872453
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/3.spi_device_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/30.spi_device_intr_test.2999911435
Short name T1083
Test name
Test status
Simulation time 56573826 ps
CPU time 0.92 seconds
Started Aug 25 09:46:06 AM UTC 24
Finished Aug 25 09:46:08 AM UTC 24
Peak memory 211768 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2999911435 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_08_24/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.spi_device_intr_test.2999911435
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/30.spi_device_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/31.spi_device_intr_test.4123111299
Short name T1087
Test name
Test status
Simulation time 21693748 ps
CPU time 1.06 seconds
Started Aug 25 09:46:06 AM UTC 24
Finished Aug 25 09:46:08 AM UTC 24
Peak memory 211768 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4123111299 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_08_24/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.spi_device_intr_test.4123111299
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/31.spi_device_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/32.spi_device_intr_test.2535450831
Short name T1086
Test name
Test status
Simulation time 18634130 ps
CPU time 1.08 seconds
Started Aug 25 09:46:06 AM UTC 24
Finished Aug 25 09:46:08 AM UTC 24
Peak memory 211768 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2535450831 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_08_24/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.spi_device_intr_test.2535450831
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/32.spi_device_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/33.spi_device_intr_test.598292038
Short name T1092
Test name
Test status
Simulation time 13948929 ps
CPU time 1.03 seconds
Started Aug 25 09:46:06 AM UTC 24
Finished Aug 25 09:46:09 AM UTC 24
Peak memory 211768 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=598292038 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_08_24/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.spi_device_intr_test.598292038
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/33.spi_device_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/34.spi_device_intr_test.3812454563
Short name T1091
Test name
Test status
Simulation time 18869776 ps
CPU time 1.01 seconds
Started Aug 25 09:46:06 AM UTC 24
Finished Aug 25 09:46:09 AM UTC 24
Peak memory 211680 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3812454563 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_08_24/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.spi_device_intr_test.3812454563
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/34.spi_device_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/35.spi_device_intr_test.2676504765
Short name T1121
Test name
Test status
Simulation time 38176181 ps
CPU time 0.77 seconds
Started Aug 25 09:46:08 AM UTC 24
Finished Aug 25 09:46:30 AM UTC 24
Peak memory 211772 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2676504765 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_08_24/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.spi_device_intr_test.2676504765
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/35.spi_device_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/36.spi_device_intr_test.635452798
Short name T1122
Test name
Test status
Simulation time 12715592 ps
CPU time 0.87 seconds
Started Aug 25 09:46:08 AM UTC 24
Finished Aug 25 09:46:30 AM UTC 24
Peak memory 211768 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=635452798 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_08_24/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.spi_device_intr_test.635452798
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/36.spi_device_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/37.spi_device_intr_test.3187284744
Short name T1115
Test name
Test status
Simulation time 29372688 ps
CPU time 0.87 seconds
Started Aug 25 09:46:08 AM UTC 24
Finished Aug 25 09:46:20 AM UTC 24
Peak memory 211768 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3187284744 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_08_24/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.spi_device_intr_test.3187284744
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/37.spi_device_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/38.spi_device_intr_test.1393783332
Short name T1114
Test name
Test status
Simulation time 10813942 ps
CPU time 0.82 seconds
Started Aug 25 09:46:08 AM UTC 24
Finished Aug 25 09:46:20 AM UTC 24
Peak memory 211768 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1393783332 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_08_24/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.spi_device_intr_test.1393783332
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/38.spi_device_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/39.spi_device_intr_test.3143120784
Short name T1117
Test name
Test status
Simulation time 14496314 ps
CPU time 0.89 seconds
Started Aug 25 09:46:08 AM UTC 24
Finished Aug 25 09:46:20 AM UTC 24
Peak memory 211768 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3143120784 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_08_24/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.spi_device_intr_test.3143120784
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/39.spi_device_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/4.spi_device_csr_aliasing.4200800263
Short name T1058
Test name
Test status
Simulation time 935758789 ps
CPU time 20.39 seconds
Started Aug 25 09:45:43 AM UTC 24
Finished Aug 25 09:46:05 AM UTC 24
Peak memory 225236 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4200800263 -assert nopostproc +UVM
_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_csr_aliasing.4200800263
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/4.spi_device_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/4.spi_device_csr_bit_bash.3575693206
Short name T1047
Test name
Test status
Simulation time 588531244 ps
CPU time 29.1 seconds
Started Aug 25 09:45:43 AM UTC 24
Finished Aug 25 09:46:13 AM UTC 24
Peak memory 225196 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3575693206 -assert nopostproc +UVM
_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_csr_bit_bash.3575693206
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/4.spi_device_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/4.spi_device_csr_hw_reset.3147991276
Short name T1022
Test name
Test status
Simulation time 67833644 ps
CPU time 1.39 seconds
Started Aug 25 09:45:42 AM UTC 24
Finished Aug 25 09:45:45 AM UTC 24
Peak memory 226292 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3147991276 -assert nopostproc +UVM
_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_csr_hw_reset.3147991276
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/4.spi_device_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/4.spi_device_csr_mem_rw_with_rand_reset.354833125
Short name T1028
Test name
Test status
Simulation time 47342023 ps
CPU time 2.12 seconds
Started Aug 25 09:45:43 AM UTC 24
Finished Aug 25 09:45:46 AM UTC 24
Peak memory 227108 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000
000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb
_random_seed=354833125 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n
ame 4.spi_device_csr_mem_rw_with_rand_reset.354833125
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/4.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/4.spi_device_csr_rw.1686021156
Short name T1027
Test name
Test status
Simulation time 105023110 ps
CPU time 2.14 seconds
Started Aug 25 09:45:42 AM UTC 24
Finished Aug 25 09:45:46 AM UTC 24
Peak memory 225144 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1686021156 -assert nopostproc +UVM_TESTN
AME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_csr_rw.1686021156
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/4.spi_device_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/4.spi_device_intr_test.3712820003
Short name T1020
Test name
Test status
Simulation time 61589746 ps
CPU time 0.96 seconds
Started Aug 25 09:45:42 AM UTC 24
Finished Aug 25 09:45:45 AM UTC 24
Peak memory 211020 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3712820003 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_08_24/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_intr_test.3712820003
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/4.spi_device_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/4.spi_device_mem_partial_access.3467218540
Short name T1026
Test name
Test status
Simulation time 87003058 ps
CPU time 1.76 seconds
Started Aug 25 09:45:42 AM UTC 24
Finished Aug 25 09:45:46 AM UTC 24
Peak memory 223948 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3467218540 -assert nopos
tproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re
po/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_mem_partial_access.3467218540
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/4.spi_device_mem_partial_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/4.spi_device_mem_walk.3634344639
Short name T1018
Test name
Test status
Simulation time 18927528 ps
CPU time 0.78 seconds
Started Aug 25 09:45:42 AM UTC 24
Finished Aug 25 09:45:44 AM UTC 24
Peak memory 211756 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3634344639 -assert nopostproc +UVM
_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_mem_walk.3634344639
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/4.spi_device_mem_walk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/4.spi_device_same_csr_outstanding.192742566
Short name T166
Test name
Test status
Simulation time 156554776 ps
CPU time 3.25 seconds
Started Aug 25 09:45:43 AM UTC 24
Finished Aug 25 09:45:47 AM UTC 24
Peak memory 224972 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=192742566 -assert nopo
stproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r
epo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_same_csr_outstanding.192742566
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/4.spi_device_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/4.spi_device_tl_errors.2037470645
Short name T124
Test name
Test status
Simulation time 291929878 ps
CPU time 4.2 seconds
Started Aug 25 09:45:42 AM UTC 24
Finished Aug 25 09:45:48 AM UTC 24
Peak memory 225196 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2037470645 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_08_24/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_tl_errors.2037470645
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/4.spi_device_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/4.spi_device_tl_intg_err.2905349169
Short name T118
Test name
Test status
Simulation time 421939353 ps
CPU time 6.09 seconds
Started Aug 25 09:45:42 AM UTC 24
Finished Aug 25 09:45:50 AM UTC 24
Peak memory 227032 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2905349169 -assert nopostproc +
UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra
tch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_tl_intg_err.2905349169
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/4.spi_device_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/40.spi_device_intr_test.771160037
Short name T1113
Test name
Test status
Simulation time 39257485 ps
CPU time 0.78 seconds
Started Aug 25 09:46:08 AM UTC 24
Finished Aug 25 09:46:20 AM UTC 24
Peak memory 211772 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=771160037 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_08_24/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.spi_device_intr_test.771160037
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/40.spi_device_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/41.spi_device_intr_test.3126559881
Short name T1116
Test name
Test status
Simulation time 13062144 ps
CPU time 0.79 seconds
Started Aug 25 09:46:08 AM UTC 24
Finished Aug 25 09:46:20 AM UTC 24
Peak memory 211768 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3126559881 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_08_24/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.spi_device_intr_test.3126559881
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/41.spi_device_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/42.spi_device_intr_test.2556431925
Short name T1130
Test name
Test status
Simulation time 52323584 ps
CPU time 1.08 seconds
Started Aug 25 09:46:08 AM UTC 24
Finished Aug 25 09:46:31 AM UTC 24
Peak memory 211772 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2556431925 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_08_24/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.spi_device_intr_test.2556431925
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/42.spi_device_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/43.spi_device_intr_test.3435624365
Short name T1128
Test name
Test status
Simulation time 42075266 ps
CPU time 0.82 seconds
Started Aug 25 09:46:08 AM UTC 24
Finished Aug 25 09:46:31 AM UTC 24
Peak memory 211772 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3435624365 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_08_24/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.spi_device_intr_test.3435624365
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/43.spi_device_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/44.spi_device_intr_test.3635343522
Short name T1131
Test name
Test status
Simulation time 36685786 ps
CPU time 1.03 seconds
Started Aug 25 09:46:08 AM UTC 24
Finished Aug 25 09:46:38 AM UTC 24
Peak memory 213412 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3635343522 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_08_24/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.spi_device_intr_test.3635343522
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/44.spi_device_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/45.spi_device_intr_test.3874051723
Short name T1129
Test name
Test status
Simulation time 12188689 ps
CPU time 1 seconds
Started Aug 25 09:46:08 AM UTC 24
Finished Aug 25 09:46:31 AM UTC 24
Peak memory 211772 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3874051723 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_08_24/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.spi_device_intr_test.3874051723
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/45.spi_device_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/46.spi_device_intr_test.816851672
Short name T1123
Test name
Test status
Simulation time 26994023 ps
CPU time 0.89 seconds
Started Aug 25 09:46:08 AM UTC 24
Finished Aug 25 09:46:31 AM UTC 24
Peak memory 211768 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=816851672 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_08_24/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.spi_device_intr_test.816851672
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/46.spi_device_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/47.spi_device_intr_test.4090038140
Short name T1124
Test name
Test status
Simulation time 94596214 ps
CPU time 1.11 seconds
Started Aug 25 09:46:08 AM UTC 24
Finished Aug 25 09:46:31 AM UTC 24
Peak memory 211768 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4090038140 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_08_24/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.spi_device_intr_test.4090038140
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/47.spi_device_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/48.spi_device_intr_test.3729509821
Short name T1125
Test name
Test status
Simulation time 34964778 ps
CPU time 1.03 seconds
Started Aug 25 09:46:09 AM UTC 24
Finished Aug 25 09:46:31 AM UTC 24
Peak memory 210772 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3729509821 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_08_24/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.spi_device_intr_test.3729509821
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/48.spi_device_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/49.spi_device_intr_test.2253740660
Short name T1126
Test name
Test status
Simulation time 16875233 ps
CPU time 1.16 seconds
Started Aug 25 09:46:09 AM UTC 24
Finished Aug 25 09:46:31 AM UTC 24
Peak memory 210596 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2253740660 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_08_24/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.spi_device_intr_test.2253740660
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/49.spi_device_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/5.spi_device_csr_mem_rw_with_rand_reset.2220910886
Short name T1031
Test name
Test status
Simulation time 93980674 ps
CPU time 2.13 seconds
Started Aug 25 09:45:43 AM UTC 24
Finished Aug 25 09:45:47 AM UTC 24
Peak memory 225192 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000
000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb
_random_seed=2220910886 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_
name 5.spi_device_csr_mem_rw_with_rand_reset.2220910886
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/5.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/5.spi_device_csr_rw.1825334514
Short name T141
Test name
Test status
Simulation time 308556326 ps
CPU time 1.86 seconds
Started Aug 25 09:45:43 AM UTC 24
Finished Aug 25 09:45:46 AM UTC 24
Peak memory 213672 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1825334514 -assert nopostproc +UVM_TESTN
AME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_csr_rw.1825334514
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/5.spi_device_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/5.spi_device_intr_test.2419827903
Short name T1021
Test name
Test status
Simulation time 161855738 ps
CPU time 0.83 seconds
Started Aug 25 09:45:43 AM UTC 24
Finished Aug 25 09:45:45 AM UTC 24
Peak memory 211760 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2419827903 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_08_24/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_intr_test.2419827903
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/5.spi_device_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/5.spi_device_same_csr_outstanding.840041018
Short name T1030
Test name
Test status
Simulation time 261440960 ps
CPU time 2.17 seconds
Started Aug 25 09:45:43 AM UTC 24
Finished Aug 25 09:45:47 AM UTC 24
Peak memory 225144 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=840041018 -assert nopo
stproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r
epo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_same_csr_outstanding.840041018
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/5.spi_device_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/5.spi_device_tl_errors.1831121543
Short name T130
Test name
Test status
Simulation time 50084549 ps
CPU time 2.16 seconds
Started Aug 25 09:45:43 AM UTC 24
Finished Aug 25 09:45:46 AM UTC 24
Peak memory 225192 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1831121543 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_08_24/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_tl_errors.1831121543
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/5.spi_device_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/5.spi_device_tl_intg_err.3166134652
Short name T329
Test name
Test status
Simulation time 271905305 ps
CPU time 7.31 seconds
Started Aug 25 09:45:43 AM UTC 24
Finished Aug 25 09:45:52 AM UTC 24
Peak memory 227108 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3166134652 -assert nopostproc +
UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra
tch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_tl_intg_err.3166134652
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/5.spi_device_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/6.spi_device_csr_mem_rw_with_rand_reset.4222220886
Short name T1033
Test name
Test status
Simulation time 41754600 ps
CPU time 2.77 seconds
Started Aug 25 09:45:43 AM UTC 24
Finished Aug 25 09:45:47 AM UTC 24
Peak memory 229140 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000
000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb
_random_seed=4222220886 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_
name 6.spi_device_csr_mem_rw_with_rand_reset.4222220886
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/6.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/6.spi_device_csr_rw.1560291519
Short name T1032
Test name
Test status
Simulation time 32393451 ps
CPU time 2.38 seconds
Started Aug 25 09:45:43 AM UTC 24
Finished Aug 25 09:45:47 AM UTC 24
Peak memory 225200 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1560291519 -assert nopostproc +UVM_TESTN
AME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_csr_rw.1560291519
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/6.spi_device_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/6.spi_device_intr_test.4096762336
Short name T1025
Test name
Test status
Simulation time 96655244 ps
CPU time 1.09 seconds
Started Aug 25 09:45:43 AM UTC 24
Finished Aug 25 09:45:46 AM UTC 24
Peak memory 211760 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4096762336 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_08_24/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_intr_test.4096762336
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/6.spi_device_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/6.spi_device_same_csr_outstanding.1234791362
Short name T1029
Test name
Test status
Simulation time 89993822 ps
CPU time 1.96 seconds
Started Aug 25 09:45:43 AM UTC 24
Finished Aug 25 09:45:46 AM UTC 24
Peak memory 224168 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1234791362 -assert nop
ostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_same_csr_outstand
ing.1234791362
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/6.spi_device_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/6.spi_device_tl_errors.3865990615
Short name T120
Test name
Test status
Simulation time 51554268 ps
CPU time 3.65 seconds
Started Aug 25 09:45:43 AM UTC 24
Finished Aug 25 09:45:48 AM UTC 24
Peak memory 225192 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3865990615 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_08_24/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_tl_errors.3865990615
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/6.spi_device_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/6.spi_device_tl_intg_err.526993666
Short name T334
Test name
Test status
Simulation time 1270885643 ps
CPU time 16.03 seconds
Started Aug 25 09:45:43 AM UTC 24
Finished Aug 25 09:46:01 AM UTC 24
Peak memory 227304 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=526993666 -assert nopostproc +U
VM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_tl_intg_err.526993666
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/6.spi_device_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/7.spi_device_csr_mem_rw_with_rand_reset.216839203
Short name T125
Test name
Test status
Simulation time 46655170 ps
CPU time 2.03 seconds
Started Aug 25 09:45:43 AM UTC 24
Finished Aug 25 09:45:47 AM UTC 24
Peak memory 227304 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000
000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb
_random_seed=216839203 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n
ame 7.spi_device_csr_mem_rw_with_rand_reset.216839203
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/7.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/7.spi_device_csr_rw.3506820547
Short name T1039
Test name
Test status
Simulation time 37900459 ps
CPU time 1.62 seconds
Started Aug 25 09:45:43 AM UTC 24
Finished Aug 25 09:45:56 AM UTC 24
Peak memory 223892 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3506820547 -assert nopostproc +UVM_TESTN
AME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_csr_rw.3506820547
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/7.spi_device_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/7.spi_device_intr_test.3802007963
Short name T1023
Test name
Test status
Simulation time 15112293 ps
CPU time 0.85 seconds
Started Aug 25 09:45:43 AM UTC 24
Finished Aug 25 09:45:45 AM UTC 24
Peak memory 211760 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3802007963 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_08_24/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_intr_test.3802007963
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/7.spi_device_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/7.spi_device_same_csr_outstanding.3985927207
Short name T1045
Test name
Test status
Simulation time 157942285 ps
CPU time 3.56 seconds
Started Aug 25 09:45:43 AM UTC 24
Finished Aug 25 09:45:58 AM UTC 24
Peak memory 225048 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3985927207 -assert nop
ostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_same_csr_outstand
ing.3985927207
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/7.spi_device_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/7.spi_device_tl_errors.1287185178
Short name T123
Test name
Test status
Simulation time 77538539 ps
CPU time 5.13 seconds
Started Aug 25 09:45:43 AM UTC 24
Finished Aug 25 09:45:50 AM UTC 24
Peak memory 225520 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1287185178 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_08_24/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_tl_errors.1287185178
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/7.spi_device_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/7.spi_device_tl_intg_err.2797639179
Short name T330
Test name
Test status
Simulation time 636263586 ps
CPU time 15.83 seconds
Started Aug 25 09:45:43 AM UTC 24
Finished Aug 25 09:46:01 AM UTC 24
Peak memory 227136 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2797639179 -assert nopostproc +
UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra
tch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_tl_intg_err.2797639179
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/7.spi_device_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/8.spi_device_csr_mem_rw_with_rand_reset.923370282
Short name T1042
Test name
Test status
Simulation time 266604225 ps
CPU time 1.9 seconds
Started Aug 25 09:45:43 AM UTC 24
Finished Aug 25 09:45:57 AM UTC 24
Peak memory 226072 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000
000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb
_random_seed=923370282 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n
ame 8.spi_device_csr_mem_rw_with_rand_reset.923370282
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/8.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/8.spi_device_csr_rw.3930920731
Short name T1044
Test name
Test status
Simulation time 34711222 ps
CPU time 2.27 seconds
Started Aug 25 09:45:43 AM UTC 24
Finished Aug 25 09:45:57 AM UTC 24
Peak memory 225092 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3930920731 -assert nopostproc +UVM_TESTN
AME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_csr_rw.3930920731
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/8.spi_device_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/8.spi_device_intr_test.807476247
Short name T1037
Test name
Test status
Simulation time 15886664 ps
CPU time 1.01 seconds
Started Aug 25 09:45:43 AM UTC 24
Finished Aug 25 09:45:56 AM UTC 24
Peak memory 211768 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=807476247 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_08_24/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_intr_test.807476247
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/8.spi_device_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/8.spi_device_same_csr_outstanding.3281156840
Short name T1081
Test name
Test status
Simulation time 694716227 ps
CPU time 3.39 seconds
Started Aug 25 09:45:43 AM UTC 24
Finished Aug 25 09:46:08 AM UTC 24
Peak memory 227120 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3281156840 -assert nop
ostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_same_csr_outstand
ing.3281156840
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/8.spi_device_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/8.spi_device_tl_errors.1809312995
Short name T127
Test name
Test status
Simulation time 240867579 ps
CPU time 3.75 seconds
Started Aug 25 09:45:43 AM UTC 24
Finished Aug 25 09:45:59 AM UTC 24
Peak memory 227332 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1809312995 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_08_24/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_tl_errors.1809312995
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/8.spi_device_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/9.spi_device_csr_mem_rw_with_rand_reset.1088716043
Short name T1073
Test name
Test status
Simulation time 54081493 ps
CPU time 1.58 seconds
Started Aug 25 09:45:44 AM UTC 24
Finished Aug 25 09:46:07 AM UTC 24
Peak memory 226072 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000
000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb
_random_seed=1088716043 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_
name 9.spi_device_csr_mem_rw_with_rand_reset.1088716043
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/9.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/9.spi_device_csr_rw.2342471752
Short name T1074
Test name
Test status
Simulation time 51285001 ps
CPU time 1.81 seconds
Started Aug 25 09:45:44 AM UTC 24
Finished Aug 25 09:46:07 AM UTC 24
Peak memory 228008 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2342471752 -assert nopostproc +UVM_TESTN
AME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_csr_rw.2342471752
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/9.spi_device_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/9.spi_device_intr_test.3486396758
Short name T1065
Test name
Test status
Simulation time 12890707 ps
CPU time 0.82 seconds
Started Aug 25 09:45:44 AM UTC 24
Finished Aug 25 09:46:06 AM UTC 24
Peak memory 211764 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3486396758 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_08_24/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_intr_test.3486396758
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/9.spi_device_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/9.spi_device_same_csr_outstanding.1535741581
Short name T1046
Test name
Test status
Simulation time 112958816 ps
CPU time 3.37 seconds
Started Aug 25 09:45:44 AM UTC 24
Finished Aug 25 09:45:58 AM UTC 24
Peak memory 225056 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1535741581 -assert nop
ostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_same_csr_outstand
ing.1535741581
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/9.spi_device_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/9.spi_device_tl_intg_err.2955503682
Short name T1089
Test name
Test status
Simulation time 286441646 ps
CPU time 16.91 seconds
Started Aug 25 09:45:43 AM UTC 24
Finished Aug 25 09:46:12 AM UTC 24
Peak memory 227196 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2955503682 -assert nopostproc +
UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra
tch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_tl_intg_err.2955503682
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/9.spi_device_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/0.spi_device_cfg_cmd.2394037765
Short name T16
Test name
Test status
Simulation time 752228911 ps
CPU time 14.51 seconds
Started Aug 25 10:41:44 AM UTC 24
Finished Aug 25 10:42:00 AM UTC 24
Peak memory 245216 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2394037765 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/spi
_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_cfg_cmd.2394037765
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/0.spi_device_cfg_cmd/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/0.spi_device_flash_and_tpm_min_idle.2733352014
Short name T397
Test name
Test status
Simulation time 24612423214 ps
CPU time 336.47 seconds
Started Aug 25 10:41:50 AM UTC 24
Finished Aug 25 10:47:32 AM UTC 24
Peak memory 263880 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2733352014 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_and_tpm_min_idle.2733352014
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/0.spi_device_flash_and_tpm_min_idle/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/0.spi_device_flash_mode.572772625
Short name T7
Test name
Test status
Simulation time 332245037 ps
CPU time 4.3 seconds
Started Aug 25 10:41:44 AM UTC 24
Finished Aug 25 10:41:50 AM UTC 24
Peak memory 234968 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=572772625 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/s
pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_mode.572772625
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/0.spi_device_flash_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/0.spi_device_flash_mode_ignore_cmds.2174621427
Short name T252
Test name
Test status
Simulation time 131753692238 ps
CPU time 345.49 seconds
Started Aug 25 10:41:44 AM UTC 24
Finished Aug 25 10:47:36 AM UTC 24
Peak memory 265888 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2174621427 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_mode_ignore_cmds.2174621427
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/0.spi_device_flash_mode_ignore_cmds/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/0.spi_device_mailbox.3534391458
Short name T112
Test name
Test status
Simulation time 2125805987 ps
CPU time 28.02 seconds
Started Aug 25 10:41:43 AM UTC 24
Finished Aug 25 10:42:12 AM UTC 24
Peak memory 261724 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3534391458 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/spi
_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_mailbox.3534391458
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/0.spi_device_mailbox/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/0.spi_device_pass_addr_payload_swap.651807047
Short name T6
Test name
Test status
Simulation time 301072607 ps
CPU time 7.87 seconds
Started Aug 25 10:41:40 AM UTC 24
Finished Aug 25 10:41:49 AM UTC 24
Peak memory 234940 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=651807047 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_24/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_pass_addr_payload_swap.651807047
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/0.spi_device_pass_addr_payload_swap/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/0.spi_device_pass_cmd_filtering.3117347291
Short name T21
Test name
Test status
Simulation time 10388372526 ps
CPU time 23.77 seconds
Started Aug 25 10:41:39 AM UTC 24
Finished Aug 25 10:42:04 AM UTC 24
Peak memory 235096 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3117347291 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_08_24/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_pass_cmd_filtering.3117347291
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/0.spi_device_pass_cmd_filtering/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/0.spi_device_stress_all.1756428015
Short name T9
Test name
Test status
Simulation time 61842359 ps
CPU time 1.32 seconds
Started Aug 25 10:41:50 AM UTC 24
Finished Aug 25 10:41:52 AM UTC 24
Peak memory 215744 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1756428015 -assert nopostproc +UVM_
TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra
tch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_stress_all.1756428015
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/0.spi_device_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/0.spi_device_tpm_all.1538309341
Short name T11
Test name
Test status
Simulation time 924727619 ps
CPU time 14.57 seconds
Started Aug 25 10:41:38 AM UTC 24
Finished Aug 25 10:41:54 AM UTC 24
Peak memory 227500 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1538309341 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/spi
_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_all.1538309341
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/0.spi_device_tpm_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/0.spi_device_tpm_rw.2418515073
Short name T5
Test name
Test status
Simulation time 165626321 ps
CPU time 2.16 seconds
Started Aug 25 10:41:39 AM UTC 24
Finished Aug 25 10:41:42 AM UTC 24
Peak memory 227456 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2418515073 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/spi_
device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_rw.2418515073
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/0.spi_device_tpm_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/0.spi_device_tpm_sts_read.2689021675
Short name T4
Test name
Test status
Simulation time 756851763 ps
CPU time 1.49 seconds
Started Aug 25 10:41:39 AM UTC 24
Finished Aug 25 10:41:41 AM UTC 24
Peak memory 215612 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2689021675 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_2
4/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_sts_read.2689021675
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/0.spi_device_tpm_sts_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/0.spi_device_upload.2770788258
Short name T42
Test name
Test status
Simulation time 21016328990 ps
CPU time 26.54 seconds
Started Aug 25 10:41:44 AM UTC 24
Finished Aug 25 10:42:12 AM UTC 24
Peak memory 235084 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2770788258 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/spi_
device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_upload.2770788258
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/0.spi_device_upload/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/1.spi_device_alert_test.2845150751
Short name T92
Test name
Test status
Simulation time 36404647 ps
CPU time 1.07 seconds
Started Aug 25 10:42:00 AM UTC 24
Finished Aug 25 10:42:03 AM UTC 24
Peak memory 215684 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2845150751 -assert nopostproc +UVM_TES
TNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_
regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_alert_test.2845150751
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/1.spi_device_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/1.spi_device_cfg_cmd.2740667906
Short name T104
Test name
Test status
Simulation time 3409387789 ps
CPU time 21.76 seconds
Started Aug 25 10:41:55 AM UTC 24
Finished Aug 25 10:42:19 AM UTC 24
Peak memory 235100 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2740667906 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/spi
_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_cfg_cmd.2740667906
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/1.spi_device_cfg_cmd/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/1.spi_device_csb_read.2617022515
Short name T12
Test name
Test status
Simulation time 20602094 ps
CPU time 1.26 seconds
Started Aug 25 10:41:52 AM UTC 24
Finished Aug 25 10:41:55 AM UTC 24
Peak memory 215580 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2617022515 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/sp
i_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_csb_read.2617022515
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/1.spi_device_csb_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/1.spi_device_flash_all.961076715
Short name T295
Test name
Test status
Simulation time 511765829603 ps
CPU time 497.74 seconds
Started Aug 25 10:41:58 AM UTC 24
Finished Aug 25 10:50:23 AM UTC 24
Peak memory 265832 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=961076715 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/sp
i_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_all.961076715
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/1.spi_device_flash_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/1.spi_device_flash_and_tpm.2545769864
Short name T556
Test name
Test status
Simulation time 137228995476 ps
CPU time 380.68 seconds
Started Aug 25 10:41:58 AM UTC 24
Finished Aug 25 10:48:24 AM UTC 24
Peak memory 267876 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2545769864 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
24/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_and_tpm.2545769864
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/1.spi_device_flash_and_tpm/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/1.spi_device_flash_and_tpm_min_idle.3009389950
Short name T51
Test name
Test status
Simulation time 5671030634 ps
CPU time 52.19 seconds
Started Aug 25 10:42:00 AM UTC 24
Finished Aug 25 10:42:54 AM UTC 24
Peak memory 251472 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3009389950 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_and_tpm_min_idle.3009389950
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/1.spi_device_flash_and_tpm_min_idle/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/1.spi_device_flash_mode.2520518666
Short name T19
Test name
Test status
Simulation time 702959881 ps
CPU time 6.1 seconds
Started Aug 25 10:41:56 AM UTC 24
Finished Aug 25 10:42:03 AM UTC 24
Peak memory 245200 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2520518666 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/
spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_mode.2520518666
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/1.spi_device_flash_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/1.spi_device_flash_mode_ignore_cmds.419279221
Short name T81
Test name
Test status
Simulation time 21890152916 ps
CPU time 107.33 seconds
Started Aug 25 10:41:56 AM UTC 24
Finished Aug 25 10:43:46 AM UTC 24
Peak memory 265816 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=419279221 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_24/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_mode_ignore_cmds.419279221
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/1.spi_device_flash_mode_ignore_cmds/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/1.spi_device_intercept.3649963241
Short name T70
Test name
Test status
Simulation time 1114530345 ps
CPU time 18.36 seconds
Started Aug 25 10:41:54 AM UTC 24
Finished Aug 25 10:42:14 AM UTC 24
Peak memory 235028 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3649963241 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/s
pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_intercept.3649963241
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/1.spi_device_intercept/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/1.spi_device_mailbox.764242307
Short name T85
Test name
Test status
Simulation time 549231916 ps
CPU time 25.21 seconds
Started Aug 25 10:41:54 AM UTC 24
Finished Aug 25 10:42:21 AM UTC 24
Peak memory 251368 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=764242307 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/spi_
device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_mailbox.764242307
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/1.spi_device_mailbox/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/1.spi_device_pass_cmd_filtering.530799807
Short name T55
Test name
Test status
Simulation time 11997037869 ps
CPU time 20.03 seconds
Started Aug 25 10:41:54 AM UTC 24
Finished Aug 25 10:42:16 AM UTC 24
Peak memory 245308 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=530799807 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_08_24/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_pass_cmd_filtering.530799807
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/1.spi_device_pass_cmd_filtering/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/1.spi_device_read_buffer_direct.1539245871
Short name T22
Test name
Test status
Simulation time 275578732 ps
CPU time 6.63 seconds
Started Aug 25 10:41:58 AM UTC 24
Finished Aug 25 10:42:05 AM UTC 24
Peak memory 231328 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1539245871 -assert nopostproc +UVM_TESTNAME=spi_device
_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_read_buffer_direct.1539245871
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/1.spi_device_read_buffer_direct/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/1.spi_device_sec_cm.1489765467
Short name T28
Test name
Test status
Simulation time 643839221 ps
CPU time 1.95 seconds
Started Aug 25 10:42:00 AM UTC 24
Finished Aug 25 10:42:04 AM UTC 24
Peak memory 257980 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1489765467 -assert nopostproc +UVM_TEST
NAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_sec_cm.1489765467
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/1.spi_device_sec_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/1.spi_device_stress_all.3887038699
Short name T20
Test name
Test status
Simulation time 237490691 ps
CPU time 1.6 seconds
Started Aug 25 10:42:00 AM UTC 24
Finished Aug 25 10:42:03 AM UTC 24
Peak memory 215708 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3887038699 -assert nopostproc +UVM_
TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra
tch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_stress_all.3887038699
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/1.spi_device_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/1.spi_device_tpm_read_hw_reg.1194467799
Short name T25
Test name
Test status
Simulation time 2584930605 ps
CPU time 9.59 seconds
Started Aug 25 10:41:52 AM UTC 24
Finished Aug 25 10:42:03 AM UTC 24
Peak memory 227560 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1194467799 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_24/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_read_hw_reg.1194467799
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/1.spi_device_tpm_read_hw_reg/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/1.spi_device_tpm_rw.3088063188
Short name T15
Test name
Test status
Simulation time 92888450 ps
CPU time 4.52 seconds
Started Aug 25 10:41:54 AM UTC 24
Finished Aug 25 10:42:00 AM UTC 24
Peak memory 227484 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3088063188 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/spi_
device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_rw.3088063188
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/1.spi_device_tpm_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/1.spi_device_tpm_sts_read.3868396747
Short name T14
Test name
Test status
Simulation time 92608997 ps
CPU time 1.18 seconds
Started Aug 25 10:41:52 AM UTC 24
Finished Aug 25 10:41:55 AM UTC 24
Peak memory 215868 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3868396747 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_2
4/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_sts_read.3868396747
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/1.spi_device_tpm_sts_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/1.spi_device_upload.1226496135
Short name T37
Test name
Test status
Simulation time 554048988 ps
CPU time 3.16 seconds
Started Aug 25 10:41:55 AM UTC 24
Finished Aug 25 10:42:00 AM UTC 24
Peak memory 234636 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1226496135 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/spi_
device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_upload.1226496135
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/1.spi_device_upload/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/10.spi_device_alert_test.4158667134
Short name T453
Test name
Test status
Simulation time 11297933 ps
CPU time 1.07 seconds
Started Aug 25 10:44:08 AM UTC 24
Finished Aug 25 10:44:11 AM UTC 24
Peak memory 215744 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4158667134 -assert nopostproc +UVM_TES
TNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_
regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_alert_test.4158667134
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/10.spi_device_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/10.spi_device_cfg_cmd.1964808660
Short name T458
Test name
Test status
Simulation time 2065415006 ps
CPU time 15.46 seconds
Started Aug 25 10:43:59 AM UTC 24
Finished Aug 25 10:44:16 AM UTC 24
Peak memory 244880 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1964808660 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/spi
_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_cfg_cmd.1964808660
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/10.spi_device_cfg_cmd/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/10.spi_device_csb_read.2622275735
Short name T432
Test name
Test status
Simulation time 58111678 ps
CPU time 1.12 seconds
Started Aug 25 10:43:47 AM UTC 24
Finished Aug 25 10:43:49 AM UTC 24
Peak memory 215812 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2622275735 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/sp
i_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_csb_read.2622275735
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/10.spi_device_csb_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/10.spi_device_flash_and_tpm.3150969897
Short name T186
Test name
Test status
Simulation time 154055372 ps
CPU time 6.83 seconds
Started Aug 25 10:44:03 AM UTC 24
Finished Aug 25 10:44:11 AM UTC 24
Peak memory 245212 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3150969897 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
24/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_and_tpm.3150969897
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/10.spi_device_flash_and_tpm/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/10.spi_device_flash_mode.1362856766
Short name T470
Test name
Test status
Simulation time 2337164463 ps
CPU time 48.79 seconds
Started Aug 25 10:43:59 AM UTC 24
Finished Aug 25 10:44:50 AM UTC 24
Peak memory 247040 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1362856766 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/
spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_mode.1362856766
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/10.spi_device_flash_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/10.spi_device_flash_mode_ignore_cmds.1647051679
Short name T184
Test name
Test status
Simulation time 6555649637 ps
CPU time 23.27 seconds
Started Aug 25 10:44:01 AM UTC 24
Finished Aug 25 10:44:25 AM UTC 24
Peak memory 249428 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1647051679 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_mode_ignore_cmds.1647051679
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/10.spi_device_flash_mode_ignore_cmds/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/10.spi_device_intercept.865596060
Short name T110
Test name
Test status
Simulation time 213312442 ps
CPU time 7.76 seconds
Started Aug 25 10:43:58 AM UTC 24
Finished Aug 25 10:44:07 AM UTC 24
Peak memory 245224 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=865596060 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/sp
i_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_intercept.865596060
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/10.spi_device_intercept/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/10.spi_device_mailbox.1554562248
Short name T108
Test name
Test status
Simulation time 4592295792 ps
CPU time 73.24 seconds
Started Aug 25 10:43:58 AM UTC 24
Finished Aug 25 10:45:13 AM UTC 24
Peak memory 261788 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1554562248 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/spi
_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_mailbox.1554562248
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/10.spi_device_mailbox/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/10.spi_device_pass_addr_payload_swap.900518073
Short name T65
Test name
Test status
Simulation time 315809909 ps
CPU time 12.78 seconds
Started Aug 25 10:43:55 AM UTC 24
Finished Aug 25 10:44:09 AM UTC 24
Peak memory 261648 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=900518073 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_24/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_pass_addr_payload_swap.900518073
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/10.spi_device_pass_addr_payload_swap/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/10.spi_device_pass_cmd_filtering.1702136423
Short name T196
Test name
Test status
Simulation time 418501603 ps
CPU time 4.64 seconds
Started Aug 25 10:43:54 AM UTC 24
Finished Aug 25 10:44:00 AM UTC 24
Peak memory 245260 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1702136423 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_08_24/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_pass_cmd_filtering.1702136423
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/10.spi_device_pass_cmd_filtering/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/10.spi_device_read_buffer_direct.1794254399
Short name T455
Test name
Test status
Simulation time 404938157 ps
CPU time 10.19 seconds
Started Aug 25 10:44:01 AM UTC 24
Finished Aug 25 10:44:12 AM UTC 24
Peak memory 231260 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1794254399 -assert nopostproc +UVM_TESTNAME=spi_device
_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_read_buffer_direct.1794254399
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/10.spi_device_read_buffer_direct/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/10.spi_device_tpm_all.1165698728
Short name T385
Test name
Test status
Simulation time 3829492554 ps
CPU time 24.94 seconds
Started Aug 25 10:43:50 AM UTC 24
Finished Aug 25 10:44:16 AM UTC 24
Peak memory 231724 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1165698728 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/spi
_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_all.1165698728
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/10.spi_device_tpm_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/10.spi_device_tpm_read_hw_reg.2834173104
Short name T452
Test name
Test status
Simulation time 18221971465 ps
CPU time 15.85 seconds
Started Aug 25 10:43:50 AM UTC 24
Finished Aug 25 10:44:07 AM UTC 24
Peak memory 227560 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2834173104 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_24/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_read_hw_reg.2834173104
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/10.spi_device_tpm_read_hw_reg/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/10.spi_device_tpm_rw.1534806402
Short name T394
Test name
Test status
Simulation time 185690277 ps
CPU time 3.05 seconds
Started Aug 25 10:43:52 AM UTC 24
Finished Aug 25 10:43:56 AM UTC 24
Peak memory 227420 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1534806402 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/spi_
device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_rw.1534806402
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/10.spi_device_tpm_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/10.spi_device_tpm_sts_read.3709434985
Short name T449
Test name
Test status
Simulation time 317954086 ps
CPU time 1.31 seconds
Started Aug 25 10:43:52 AM UTC 24
Finished Aug 25 10:43:54 AM UTC 24
Peak memory 215872 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3709434985 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_2
4/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_sts_read.3709434985
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/10.spi_device_tpm_sts_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/10.spi_device_upload.3874561821
Short name T451
Test name
Test status
Simulation time 71532679 ps
CPU time 3.29 seconds
Started Aug 25 10:43:58 AM UTC 24
Finished Aug 25 10:44:02 AM UTC 24
Peak memory 234724 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3874561821 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/spi_
device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_upload.3874561821
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/10.spi_device_upload/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/11.spi_device_alert_test.3093671260
Short name T461
Test name
Test status
Simulation time 15464654 ps
CPU time 1.09 seconds
Started Aug 25 10:44:24 AM UTC 24
Finished Aug 25 10:44:26 AM UTC 24
Peak memory 215744 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3093671260 -assert nopostproc +UVM_TES
TNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_
regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_alert_test.3093671260
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/11.spi_device_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/11.spi_device_cfg_cmd.2450651302
Short name T229
Test name
Test status
Simulation time 336969392 ps
CPU time 6.48 seconds
Started Aug 25 10:44:17 AM UTC 24
Finished Aug 25 10:44:25 AM UTC 24
Peak memory 245148 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2450651302 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/spi
_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_cfg_cmd.2450651302
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/11.spi_device_cfg_cmd/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/11.spi_device_csb_read.3300086172
Short name T454
Test name
Test status
Simulation time 34781324 ps
CPU time 1.18 seconds
Started Aug 25 10:44:09 AM UTC 24
Finished Aug 25 10:44:12 AM UTC 24
Peak memory 215808 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3300086172 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/sp
i_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_csb_read.3300086172
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/11.spi_device_csb_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/11.spi_device_flash_and_tpm.170859668
Short name T342
Test name
Test status
Simulation time 2728972158 ps
CPU time 38.51 seconds
Started Aug 25 10:44:22 AM UTC 24
Finished Aug 25 10:45:02 AM UTC 24
Peak memory 261776 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=170859668 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_2
4/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_and_tpm.170859668
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/11.spi_device_flash_and_tpm/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/11.spi_device_flash_and_tpm_min_idle.28348594
Short name T178
Test name
Test status
Simulation time 66024923552 ps
CPU time 78.26 seconds
Started Aug 25 10:44:23 AM UTC 24
Finished Aug 25 10:45:43 AM UTC 24
Peak memory 261776 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=28348594 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_24/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_and_tpm_min_idle.28348594
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/11.spi_device_flash_and_tpm_min_idle/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/11.spi_device_flash_mode.2642814684
Short name T465
Test name
Test status
Simulation time 1633996481 ps
CPU time 12.28 seconds
Started Aug 25 10:44:17 AM UTC 24
Finished Aug 25 10:44:31 AM UTC 24
Peak memory 249308 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2642814684 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/
spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_mode.2642814684
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/11.spi_device_flash_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/11.spi_device_flash_mode_ignore_cmds.2317749883
Short name T283
Test name
Test status
Simulation time 125253957072 ps
CPU time 371.66 seconds
Started Aug 25 10:44:21 AM UTC 24
Finished Aug 25 10:50:38 AM UTC 24
Peak memory 263764 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2317749883 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_mode_ignore_cmds.2317749883
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/11.spi_device_flash_mode_ignore_cmds/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/11.spi_device_intercept.3575369539
Short name T225
Test name
Test status
Simulation time 387237821 ps
CPU time 6.05 seconds
Started Aug 25 10:44:14 AM UTC 24
Finished Aug 25 10:44:21 AM UTC 24
Peak memory 235040 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3575369539 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/s
pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_intercept.3575369539
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/11.spi_device_intercept/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/11.spi_device_mailbox.1109375306
Short name T242
Test name
Test status
Simulation time 324774905 ps
CPU time 4.95 seconds
Started Aug 25 10:44:15 AM UTC 24
Finished Aug 25 10:44:22 AM UTC 24
Peak memory 245212 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1109375306 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/spi
_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_mailbox.1109375306
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/11.spi_device_mailbox/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/11.spi_device_pass_addr_payload_swap.219210324
Short name T201
Test name
Test status
Simulation time 396483407 ps
CPU time 8.84 seconds
Started Aug 25 10:44:13 AM UTC 24
Finished Aug 25 10:44:23 AM UTC 24
Peak memory 251360 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=219210324 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_24/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_pass_addr_payload_swap.219210324
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/11.spi_device_pass_addr_payload_swap/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/11.spi_device_pass_cmd_filtering.1846144408
Short name T460
Test name
Test status
Simulation time 337054823 ps
CPU time 6.24 seconds
Started Aug 25 10:44:13 AM UTC 24
Finished Aug 25 10:44:20 AM UTC 24
Peak memory 249340 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1846144408 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_08_24/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_pass_cmd_filtering.1846144408
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/11.spi_device_pass_cmd_filtering/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/11.spi_device_read_buffer_direct.1304057405
Short name T466
Test name
Test status
Simulation time 18340411288 ps
CPU time 21.07 seconds
Started Aug 25 10:44:21 AM UTC 24
Finished Aug 25 10:44:43 AM UTC 24
Peak memory 231512 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1304057405 -assert nopostproc +UVM_TESTNAME=spi_device
_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_read_buffer_direct.1304057405
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/11.spi_device_read_buffer_direct/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/11.spi_device_tpm_all.3380718839
Short name T381
Test name
Test status
Simulation time 20554707560 ps
CPU time 22 seconds
Started Aug 25 10:44:12 AM UTC 24
Finished Aug 25 10:44:35 AM UTC 24
Peak memory 227616 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3380718839 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/spi
_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_all.3380718839
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/11.spi_device_tpm_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/11.spi_device_tpm_read_hw_reg.3912742384
Short name T459
Test name
Test status
Simulation time 1310902153 ps
CPU time 7.04 seconds
Started Aug 25 10:44:12 AM UTC 24
Finished Aug 25 10:44:20 AM UTC 24
Peak memory 227492 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3912742384 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_24/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_read_hw_reg.3912742384
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/11.spi_device_tpm_read_hw_reg/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/11.spi_device_tpm_rw.963600337
Short name T457
Test name
Test status
Simulation time 14883655 ps
CPU time 1.04 seconds
Started Aug 25 10:44:13 AM UTC 24
Finished Aug 25 10:44:15 AM UTC 24
Peak memory 215740 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=963600337 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/spi_d
evice_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_rw.963600337
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/11.spi_device_tpm_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/11.spi_device_tpm_sts_read.308584350
Short name T456
Test name
Test status
Simulation time 129243929 ps
CPU time 1.08 seconds
Started Aug 25 10:44:12 AM UTC 24
Finished Aug 25 10:44:14 AM UTC 24
Peak memory 215808 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=308584350 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24
/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_sts_read.308584350
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/11.spi_device_tpm_sts_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/11.spi_device_upload.1895817863
Short name T179
Test name
Test status
Simulation time 2672711350 ps
CPU time 11.34 seconds
Started Aug 25 10:44:16 AM UTC 24
Finished Aug 25 10:44:29 AM UTC 24
Peak memory 235024 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1895817863 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/spi_
device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_upload.1895817863
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/11.spi_device_upload/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/12.spi_device_alert_test.1689073158
Short name T467
Test name
Test status
Simulation time 12013480 ps
CPU time 1.02 seconds
Started Aug 25 10:44:43 AM UTC 24
Finished Aug 25 10:44:45 AM UTC 24
Peak memory 215684 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1689073158 -assert nopostproc +UVM_TES
TNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_
regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_alert_test.1689073158
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/12.spi_device_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/12.spi_device_cfg_cmd.1931333340
Short name T250
Test name
Test status
Simulation time 320357109 ps
CPU time 5.44 seconds
Started Aug 25 10:44:32 AM UTC 24
Finished Aug 25 10:44:38 AM UTC 24
Peak memory 234880 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1931333340 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/spi
_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_cfg_cmd.1931333340
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/12.spi_device_cfg_cmd/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/12.spi_device_csb_read.4041194968
Short name T462
Test name
Test status
Simulation time 30002908 ps
CPU time 1.12 seconds
Started Aug 25 10:44:24 AM UTC 24
Finished Aug 25 10:44:26 AM UTC 24
Peak memory 215812 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4041194968 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/sp
i_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_csb_read.4041194968
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/12.spi_device_csb_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/12.spi_device_flash_all.616048611
Short name T360
Test name
Test status
Simulation time 11783801013 ps
CPU time 98.39 seconds
Started Aug 25 10:44:38 AM UTC 24
Finished Aug 25 10:46:19 AM UTC 24
Peak memory 261780 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=616048611 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/sp
i_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_all.616048611
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/12.spi_device_flash_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/12.spi_device_flash_and_tpm_min_idle.3330974868
Short name T277
Test name
Test status
Simulation time 66242272736 ps
CPU time 275.7 seconds
Started Aug 25 10:44:39 AM UTC 24
Finished Aug 25 10:49:20 AM UTC 24
Peak memory 265872 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3330974868 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_and_tpm_min_idle.3330974868
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/12.spi_device_flash_and_tpm_min_idle/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/12.spi_device_flash_mode.1140811254
Short name T359
Test name
Test status
Simulation time 412985502 ps
CPU time 9.39 seconds
Started Aug 25 10:44:33 AM UTC 24
Finished Aug 25 10:44:43 AM UTC 24
Peak memory 234972 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1140811254 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/
spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_mode.1140811254
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/12.spi_device_flash_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/12.spi_device_flash_mode_ignore_cmds.180872696
Short name T355
Test name
Test status
Simulation time 14940465951 ps
CPU time 100.38 seconds
Started Aug 25 10:44:34 AM UTC 24
Finished Aug 25 10:46:17 AM UTC 24
Peak memory 261716 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=180872696 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_24/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_mode_ignore_cmds.180872696
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/12.spi_device_flash_mode_ignore_cmds/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/12.spi_device_intercept.602925947
Short name T259
Test name
Test status
Simulation time 7887081399 ps
CPU time 22.67 seconds
Started Aug 25 10:44:30 AM UTC 24
Finished Aug 25 10:44:53 AM UTC 24
Peak memory 245288 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=602925947 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/sp
i_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_intercept.602925947
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/12.spi_device_intercept/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/12.spi_device_mailbox.732331766
Short name T202
Test name
Test status
Simulation time 374665633 ps
CPU time 13.01 seconds
Started Aug 25 10:44:31 AM UTC 24
Finished Aug 25 10:44:45 AM UTC 24
Peak memory 245204 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=732331766 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/spi_
device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_mailbox.732331766
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/12.spi_device_mailbox/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/12.spi_device_pass_addr_payload_swap.3958335471
Short name T247
Test name
Test status
Simulation time 2840029479 ps
CPU time 15.39 seconds
Started Aug 25 10:44:29 AM UTC 24
Finished Aug 25 10:44:46 AM UTC 24
Peak memory 251428 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3958335471 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_pass_addr_payload_swap.3958335471
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/12.spi_device_pass_addr_payload_swap/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/12.spi_device_pass_cmd_filtering.1482186150
Short name T362
Test name
Test status
Simulation time 8717173440 ps
CPU time 30.25 seconds
Started Aug 25 10:44:29 AM UTC 24
Finished Aug 25 10:45:01 AM UTC 24
Peak memory 245480 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1482186150 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_08_24/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_pass_cmd_filtering.1482186150
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/12.spi_device_pass_cmd_filtering/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/12.spi_device_read_buffer_direct.280562203
Short name T471
Test name
Test status
Simulation time 766351814 ps
CPU time 13.45 seconds
Started Aug 25 10:44:36 AM UTC 24
Finished Aug 25 10:44:51 AM UTC 24
Peak memory 231268 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=280562203 -assert nopostproc +UVM_TESTNAME=spi_device_
base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_read_buffer_direct.280562203
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/12.spi_device_read_buffer_direct/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/12.spi_device_stress_all.120221836
Short name T34
Test name
Test status
Simulation time 197848351 ps
CPU time 1.61 seconds
Started Aug 25 10:44:41 AM UTC 24
Finished Aug 25 10:44:44 AM UTC 24
Peak memory 216288 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=120221836 -assert nopostproc +UVM_T
ESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_stress_all.120221836
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/12.spi_device_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/12.spi_device_tpm_all.3608058432
Short name T463
Test name
Test status
Simulation time 34568192 ps
CPU time 1.11 seconds
Started Aug 25 10:44:26 AM UTC 24
Finished Aug 25 10:44:29 AM UTC 24
Peak memory 215744 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3608058432 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/spi
_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_all.3608058432
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/12.spi_device_tpm_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/12.spi_device_tpm_read_hw_reg.293311888
Short name T472
Test name
Test status
Simulation time 14782684329 ps
CPU time 25.16 seconds
Started Aug 25 10:44:26 AM UTC 24
Finished Aug 25 10:44:53 AM UTC 24
Peak memory 227628 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=293311888 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08
_24/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_read_hw_reg.293311888
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/12.spi_device_tpm_read_hw_reg/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/12.spi_device_tpm_rw.1423984576
Short name T400
Test name
Test status
Simulation time 42218208 ps
CPU time 2.96 seconds
Started Aug 25 10:44:28 AM UTC 24
Finished Aug 25 10:44:32 AM UTC 24
Peak memory 227412 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1423984576 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/spi_
device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_rw.1423984576
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/12.spi_device_tpm_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/12.spi_device_tpm_sts_read.4219521578
Short name T464
Test name
Test status
Simulation time 149439595 ps
CPU time 1.79 seconds
Started Aug 25 10:44:27 AM UTC 24
Finished Aug 25 10:44:30 AM UTC 24
Peak memory 215872 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4219521578 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_2
4/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_sts_read.4219521578
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/12.spi_device_tpm_sts_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/12.spi_device_upload.2235208692
Short name T207
Test name
Test status
Simulation time 251905027 ps
CPU time 5.49 seconds
Started Aug 25 10:44:32 AM UTC 24
Finished Aug 25 10:44:38 AM UTC 24
Peak memory 234980 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2235208692 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/spi_
device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_upload.2235208692
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/12.spi_device_upload/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/13.spi_device_alert_test.477882767
Short name T474
Test name
Test status
Simulation time 11921423 ps
CPU time 1.05 seconds
Started Aug 25 10:45:04 AM UTC 24
Finished Aug 25 10:45:06 AM UTC 24
Peak memory 215808 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=477882767 -assert nopostproc +UVM_TEST
NAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_alert_test.477882767
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/13.spi_device_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/13.spi_device_cfg_cmd.3124275420
Short name T204
Test name
Test status
Simulation time 1135748780 ps
CPU time 11.86 seconds
Started Aug 25 10:44:50 AM UTC 24
Finished Aug 25 10:45:03 AM UTC 24
Peak memory 234964 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3124275420 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/spi
_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_cfg_cmd.3124275420
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/13.spi_device_cfg_cmd/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/13.spi_device_csb_read.441613276
Short name T468
Test name
Test status
Simulation time 56658957 ps
CPU time 1.12 seconds
Started Aug 25 10:44:46 AM UTC 24
Finished Aug 25 10:44:48 AM UTC 24
Peak memory 215808 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=441613276 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/spi
_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_csb_read.441613276
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/13.spi_device_csb_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/13.spi_device_flash_all.290926702
Short name T67
Test name
Test status
Simulation time 1943940959 ps
CPU time 35.46 seconds
Started Aug 25 10:44:59 AM UTC 24
Finished Aug 25 10:45:36 AM UTC 24
Peak memory 251348 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=290926702 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/sp
i_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_all.290926702
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/13.spi_device_flash_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/13.spi_device_flash_and_tpm.3762745600
Short name T850
Test name
Test status
Simulation time 38130952539 ps
CPU time 523.66 seconds
Started Aug 25 10:45:02 AM UTC 24
Finished Aug 25 10:53:54 AM UTC 24
Peak memory 265868 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3762745600 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
24/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_and_tpm.3762745600
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/13.spi_device_flash_and_tpm/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/13.spi_device_flash_and_tpm_min_idle.1968250756
Short name T361
Test name
Test status
Simulation time 18140469252 ps
CPU time 125.63 seconds
Started Aug 25 10:45:03 AM UTC 24
Finished Aug 25 10:47:11 AM UTC 24
Peak memory 261752 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1968250756 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_and_tpm_min_idle.1968250756
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/13.spi_device_flash_and_tpm_min_idle/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/13.spi_device_flash_mode.3676468100
Short name T375
Test name
Test status
Simulation time 1539553961 ps
CPU time 30.02 seconds
Started Aug 25 10:44:51 AM UTC 24
Finished Aug 25 10:45:23 AM UTC 24
Peak memory 245204 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3676468100 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/
spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_mode.3676468100
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/13.spi_device_flash_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/13.spi_device_intercept.3380490907
Short name T249
Test name
Test status
Simulation time 2260184506 ps
CPU time 24.33 seconds
Started Aug 25 10:44:49 AM UTC 24
Finished Aug 25 10:45:15 AM UTC 24
Peak memory 234972 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3380490907 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/s
pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_intercept.3380490907
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/13.spi_device_intercept/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/13.spi_device_mailbox.4057216164
Short name T198
Test name
Test status
Simulation time 368076536 ps
CPU time 7.59 seconds
Started Aug 25 10:44:49 AM UTC 24
Finished Aug 25 10:44:58 AM UTC 24
Peak memory 245204 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4057216164 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/spi
_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_mailbox.4057216164
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/13.spi_device_mailbox/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/13.spi_device_pass_addr_payload_swap.623276207
Short name T257
Test name
Test status
Simulation time 1906741044 ps
CPU time 12.63 seconds
Started Aug 25 10:44:49 AM UTC 24
Finished Aug 25 10:45:03 AM UTC 24
Peak memory 245284 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=623276207 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_24/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_pass_addr_payload_swap.623276207
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/13.spi_device_pass_addr_payload_swap/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/13.spi_device_pass_cmd_filtering.2542871837
Short name T233
Test name
Test status
Simulation time 16270737788 ps
CPU time 23.96 seconds
Started Aug 25 10:44:47 AM UTC 24
Finished Aug 25 10:45:13 AM UTC 24
Peak memory 245348 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2542871837 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_08_24/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_pass_cmd_filtering.2542871837
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/13.spi_device_pass_cmd_filtering/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/13.spi_device_read_buffer_direct.706001303
Short name T473
Test name
Test status
Simulation time 2655866864 ps
CPU time 6.98 seconds
Started Aug 25 10:44:55 AM UTC 24
Finished Aug 25 10:45:03 AM UTC 24
Peak memory 233380 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=706001303 -assert nopostproc +UVM_TESTNAME=spi_device_
base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_read_buffer_direct.706001303
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/13.spi_device_read_buffer_direct/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/13.spi_device_tpm_all.3330185862
Short name T402
Test name
Test status
Simulation time 7417613570 ps
CPU time 57.51 seconds
Started Aug 25 10:44:46 AM UTC 24
Finished Aug 25 10:45:45 AM UTC 24
Peak memory 227628 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3330185862 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/spi
_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_all.3330185862
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/13.spi_device_tpm_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/13.spi_device_tpm_read_hw_reg.3309088912
Short name T476
Test name
Test status
Simulation time 3427563263 ps
CPU time 20.99 seconds
Started Aug 25 10:44:46 AM UTC 24
Finished Aug 25 10:45:08 AM UTC 24
Peak memory 227632 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3309088912 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_24/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_read_hw_reg.3309088912
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/13.spi_device_tpm_read_hw_reg/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/13.spi_device_tpm_rw.4115925073
Short name T403
Test name
Test status
Simulation time 60664887 ps
CPU time 2.13 seconds
Started Aug 25 10:44:46 AM UTC 24
Finished Aug 25 10:44:49 AM UTC 24
Peak memory 227424 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4115925073 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/spi_
device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_rw.4115925073
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/13.spi_device_tpm_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/13.spi_device_tpm_sts_read.2576958229
Short name T469
Test name
Test status
Simulation time 169876533 ps
CPU time 1.25 seconds
Started Aug 25 10:44:46 AM UTC 24
Finished Aug 25 10:44:48 AM UTC 24
Peak memory 215872 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2576958229 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_2
4/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_sts_read.2576958229
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/13.spi_device_tpm_sts_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/13.spi_device_upload.4251464835
Short name T244
Test name
Test status
Simulation time 34834623709 ps
CPU time 44.71 seconds
Started Aug 25 10:44:50 AM UTC 24
Finished Aug 25 10:45:37 AM UTC 24
Peak memory 251416 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4251464835 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/spi_
device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_upload.4251464835
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/13.spi_device_upload/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/14.spi_device_alert_test.1477738997
Short name T479
Test name
Test status
Simulation time 42592045 ps
CPU time 1.15 seconds
Started Aug 25 10:45:21 AM UTC 24
Finished Aug 25 10:45:23 AM UTC 24
Peak memory 215744 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1477738997 -assert nopostproc +UVM_TES
TNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_
regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_alert_test.1477738997
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/14.spi_device_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/14.spi_device_cfg_cmd.2396440598
Short name T226
Test name
Test status
Simulation time 699715900 ps
CPU time 3.68 seconds
Started Aug 25 10:45:14 AM UTC 24
Finished Aug 25 10:45:19 AM UTC 24
Peak memory 234960 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2396440598 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/spi
_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_cfg_cmd.2396440598
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/14.spi_device_cfg_cmd/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/14.spi_device_csb_read.4061880033
Short name T475
Test name
Test status
Simulation time 18269383 ps
CPU time 1.18 seconds
Started Aug 25 10:45:04 AM UTC 24
Finished Aug 25 10:45:07 AM UTC 24
Peak memory 215808 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4061880033 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/sp
i_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_csb_read.4061880033
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/14.spi_device_csb_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/14.spi_device_flash_all.1193546620
Short name T318
Test name
Test status
Simulation time 47721970094 ps
CPU time 528.18 seconds
Started Aug 25 10:45:16 AM UTC 24
Finished Aug 25 10:54:13 AM UTC 24
Peak memory 267884 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1193546620 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/s
pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_all.1193546620
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/14.spi_device_flash_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/14.spi_device_flash_and_tpm.2179028432
Short name T401
Test name
Test status
Simulation time 6063538839 ps
CPU time 26.79 seconds
Started Aug 25 10:45:16 AM UTC 24
Finished Aug 25 10:45:45 AM UTC 24
Peak memory 229660 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2179028432 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
24/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_and_tpm.2179028432
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/14.spi_device_flash_and_tpm/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/14.spi_device_flash_and_tpm_min_idle.3304048486
Short name T143
Test name
Test status
Simulation time 39221437777 ps
CPU time 152.24 seconds
Started Aug 25 10:45:20 AM UTC 24
Finished Aug 25 10:47:56 AM UTC 24
Peak memory 263800 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3304048486 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_and_tpm_min_idle.3304048486
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/14.spi_device_flash_and_tpm_min_idle/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/14.spi_device_flash_mode.1280593907
Short name T374
Test name
Test status
Simulation time 3047360822 ps
CPU time 49.89 seconds
Started Aug 25 10:45:14 AM UTC 24
Finished Aug 25 10:46:06 AM UTC 24
Peak memory 245340 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1280593907 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/
spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_mode.1280593907
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/14.spi_device_flash_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/14.spi_device_flash_mode_ignore_cmds.628262628
Short name T210
Test name
Test status
Simulation time 2281696296 ps
CPU time 88.62 seconds
Started Aug 25 10:45:14 AM UTC 24
Finished Aug 25 10:46:45 AM UTC 24
Peak memory 267796 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=628262628 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_24/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_mode_ignore_cmds.628262628
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/14.spi_device_flash_mode_ignore_cmds/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/14.spi_device_intercept.23543333
Short name T197
Test name
Test status
Simulation time 92148852 ps
CPU time 4.25 seconds
Started Aug 25 10:45:10 AM UTC 24
Finished Aug 25 10:45:15 AM UTC 24
Peak memory 245200 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=23543333 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/spi
_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_intercept.23543333
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/14.spi_device_intercept/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/14.spi_device_mailbox.3169862771
Short name T371
Test name
Test status
Simulation time 6266157323 ps
CPU time 48.87 seconds
Started Aug 25 10:45:10 AM UTC 24
Finished Aug 25 10:46:01 AM UTC 24
Peak memory 235096 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3169862771 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/spi
_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_mailbox.3169862771
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/14.spi_device_mailbox/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/14.spi_device_pass_addr_payload_swap.1501182381
Short name T478
Test name
Test status
Simulation time 123059673 ps
CPU time 3.24 seconds
Started Aug 25 10:45:09 AM UTC 24
Finished Aug 25 10:45:13 AM UTC 24
Peak memory 245196 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1501182381 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_pass_addr_payload_swap.1501182381
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/14.spi_device_pass_addr_payload_swap/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/14.spi_device_pass_cmd_filtering.3405268030
Short name T243
Test name
Test status
Simulation time 2436913804 ps
CPU time 4.11 seconds
Started Aug 25 10:45:07 AM UTC 24
Finished Aug 25 10:45:13 AM UTC 24
Peak memory 245420 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3405268030 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_08_24/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_pass_cmd_filtering.3405268030
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/14.spi_device_pass_cmd_filtering/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/14.spi_device_read_buffer_direct.725572113
Short name T484
Test name
Test status
Simulation time 973214702 ps
CPU time 17.39 seconds
Started Aug 25 10:45:16 AM UTC 24
Finished Aug 25 10:45:35 AM UTC 24
Peak memory 231396 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=725572113 -assert nopostproc +UVM_TESTNAME=spi_device_
base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_read_buffer_direct.725572113
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/14.spi_device_read_buffer_direct/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/14.spi_device_stress_all.3807052469
Short name T40
Test name
Test status
Simulation time 21269148172 ps
CPU time 310.24 seconds
Started Aug 25 10:45:20 AM UTC 24
Finished Aug 25 10:50:36 AM UTC 24
Peak memory 261808 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3807052469 -assert nopostproc +UVM_
TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra
tch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_stress_all.3807052469
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/14.spi_device_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/14.spi_device_tpm_all.917746493
Short name T382
Test name
Test status
Simulation time 2040678460 ps
CPU time 47.59 seconds
Started Aug 25 10:45:06 AM UTC 24
Finished Aug 25 10:45:56 AM UTC 24
Peak memory 227548 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=917746493 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/spi_
device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_all.917746493
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/14.spi_device_tpm_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/14.spi_device_tpm_read_hw_reg.2426683438
Short name T482
Test name
Test status
Simulation time 14550928012 ps
CPU time 26.23 seconds
Started Aug 25 10:45:06 AM UTC 24
Finished Aug 25 10:45:34 AM UTC 24
Peak memory 227440 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2426683438 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_24/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_read_hw_reg.2426683438
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/14.spi_device_tpm_read_hw_reg/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/14.spi_device_tpm_rw.611990255
Short name T405
Test name
Test status
Simulation time 976187885 ps
CPU time 11.22 seconds
Started Aug 25 10:45:07 AM UTC 24
Finished Aug 25 10:45:20 AM UTC 24
Peak memory 227488 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=611990255 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/spi_d
evice_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_rw.611990255
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/14.spi_device_tpm_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/14.spi_device_tpm_sts_read.1807846147
Short name T477
Test name
Test status
Simulation time 114425723 ps
CPU time 1.26 seconds
Started Aug 25 10:45:06 AM UTC 24
Finished Aug 25 10:45:09 AM UTC 24
Peak memory 215872 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1807846147 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_2
4/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_sts_read.1807846147
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/14.spi_device_tpm_sts_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/14.spi_device_upload.1936661535
Short name T209
Test name
Test status
Simulation time 284930968 ps
CPU time 4.42 seconds
Started Aug 25 10:45:14 AM UTC 24
Finished Aug 25 10:45:20 AM UTC 24
Peak memory 234980 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1936661535 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/spi_
device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_upload.1936661535
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/14.spi_device_upload/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/15.spi_device_alert_test.3993274462
Short name T486
Test name
Test status
Simulation time 13977240 ps
CPU time 1.11 seconds
Started Aug 25 10:45:47 AM UTC 24
Finished Aug 25 10:45:49 AM UTC 24
Peak memory 215688 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3993274462 -assert nopostproc +UVM_TES
TNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_
regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_alert_test.3993274462
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/15.spi_device_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/15.spi_device_cfg_cmd.628337208
Short name T267
Test name
Test status
Simulation time 193626214 ps
CPU time 6.84 seconds
Started Aug 25 10:45:39 AM UTC 24
Finished Aug 25 10:45:47 AM UTC 24
Peak memory 245284 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=628337208 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/spi_
device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_cfg_cmd.628337208
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/15.spi_device_cfg_cmd/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/15.spi_device_csb_read.2059672125
Short name T480
Test name
Test status
Simulation time 25390811 ps
CPU time 1.14 seconds
Started Aug 25 10:45:24 AM UTC 24
Finished Aug 25 10:45:26 AM UTC 24
Peak memory 215812 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2059672125 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/sp
i_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_csb_read.2059672125
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/15.spi_device_csb_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/15.spi_device_flash_all.1280203378
Short name T847
Test name
Test status
Simulation time 43796674657 ps
CPU time 470.59 seconds
Started Aug 25 10:45:45 AM UTC 24
Finished Aug 25 10:53:42 AM UTC 24
Peak memory 274012 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1280203378 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/s
pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_all.1280203378
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/15.spi_device_flash_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/15.spi_device_flash_and_tpm.1173880886
Short name T778
Test name
Test status
Simulation time 31292410682 ps
CPU time 405.17 seconds
Started Aug 25 10:45:46 AM UTC 24
Finished Aug 25 10:52:37 AM UTC 24
Peak memory 267892 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1173880886 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
24/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_and_tpm.1173880886
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/15.spi_device_flash_and_tpm/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/15.spi_device_flash_and_tpm_min_idle.1520282566
Short name T245
Test name
Test status
Simulation time 4802580265 ps
CPU time 26.72 seconds
Started Aug 25 10:45:46 AM UTC 24
Finished Aug 25 10:46:14 AM UTC 24
Peak memory 251532 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1520282566 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_and_tpm_min_idle.1520282566
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/15.spi_device_flash_and_tpm_min_idle/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/15.spi_device_flash_mode.1751503317
Short name T485
Test name
Test status
Simulation time 212893536 ps
CPU time 4.03 seconds
Started Aug 25 10:45:40 AM UTC 24
Finished Aug 25 10:45:45 AM UTC 24
Peak memory 245288 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1751503317 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/
spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_mode.1751503317
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/15.spi_device_flash_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/15.spi_device_intercept.2057079415
Short name T340
Test name
Test status
Simulation time 3846023099 ps
CPU time 19.89 seconds
Started Aug 25 10:45:36 AM UTC 24
Finished Aug 25 10:45:58 AM UTC 24
Peak memory 235108 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2057079415 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/s
pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_intercept.2057079415
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/15.spi_device_intercept/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/15.spi_device_mailbox.324305590
Short name T213
Test name
Test status
Simulation time 55447507852 ps
CPU time 110.73 seconds
Started Aug 25 10:45:36 AM UTC 24
Finished Aug 25 10:47:30 AM UTC 24
Peak memory 235032 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=324305590 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/spi_
device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_mailbox.324305590
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/15.spi_device_mailbox/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/15.spi_device_pass_addr_payload_swap.311727615
Short name T246
Test name
Test status
Simulation time 8376084529 ps
CPU time 23.73 seconds
Started Aug 25 10:45:35 AM UTC 24
Finished Aug 25 10:46:00 AM UTC 24
Peak memory 245288 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=311727615 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_24/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_pass_addr_payload_swap.311727615
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/15.spi_device_pass_addr_payload_swap/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/15.spi_device_pass_cmd_filtering.2798272226
Short name T217
Test name
Test status
Simulation time 773134394 ps
CPU time 7.49 seconds
Started Aug 25 10:45:35 AM UTC 24
Finished Aug 25 10:45:44 AM UTC 24
Peak memory 229536 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2798272226 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_08_24/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_pass_cmd_filtering.2798272226
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/15.spi_device_pass_cmd_filtering/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/15.spi_device_read_buffer_direct.406937197
Short name T490
Test name
Test status
Simulation time 1345778976 ps
CPU time 12.12 seconds
Started Aug 25 10:45:44 AM UTC 24
Finished Aug 25 10:45:57 AM UTC 24
Peak memory 233744 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=406937197 -assert nopostproc +UVM_TESTNAME=spi_device_
base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_read_buffer_direct.406937197
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/15.spi_device_read_buffer_direct/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/15.spi_device_stress_all.3295627300
Short name T176
Test name
Test status
Simulation time 235104851 ps
CPU time 1.52 seconds
Started Aug 25 10:45:46 AM UTC 24
Finished Aug 25 10:45:49 AM UTC 24
Peak memory 215736 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3295627300 -assert nopostproc +UVM_
TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra
tch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_stress_all.3295627300
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/15.spi_device_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/15.spi_device_tpm_all.741663444
Short name T384
Test name
Test status
Simulation time 13540338778 ps
CPU time 20.54 seconds
Started Aug 25 10:45:27 AM UTC 24
Finished Aug 25 10:45:49 AM UTC 24
Peak memory 231708 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=741663444 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/spi_
device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_all.741663444
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/15.spi_device_tpm_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/15.spi_device_tpm_read_hw_reg.2513007449
Short name T483
Test name
Test status
Simulation time 1057931002 ps
CPU time 6.22 seconds
Started Aug 25 10:45:27 AM UTC 24
Finished Aug 25 10:45:34 AM UTC 24
Peak memory 227412 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2513007449 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_24/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_read_hw_reg.2513007449
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/15.spi_device_tpm_read_hw_reg/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/15.spi_device_tpm_rw.546210572
Short name T407
Test name
Test status
Simulation time 579241459 ps
CPU time 5.25 seconds
Started Aug 25 10:45:31 AM UTC 24
Finished Aug 25 10:45:37 AM UTC 24
Peak memory 227584 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=546210572 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/spi_d
evice_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_rw.546210572
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/15.spi_device_tpm_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/15.spi_device_tpm_sts_read.653915969
Short name T481
Test name
Test status
Simulation time 37109165 ps
CPU time 1.18 seconds
Started Aug 25 10:45:28 AM UTC 24
Finished Aug 25 10:45:30 AM UTC 24
Peak memory 215868 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=653915969 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24
/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_sts_read.653915969
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/15.spi_device_tpm_sts_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/15.spi_device_upload.49657081
Short name T211
Test name
Test status
Simulation time 168192788 ps
CPU time 3.91 seconds
Started Aug 25 10:45:37 AM UTC 24
Finished Aug 25 10:45:43 AM UTC 24
Peak memory 234964 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=49657081 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/spi_de
vice_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_upload.49657081
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/15.spi_device_upload/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/16.spi_device_alert_test.2130044399
Short name T492
Test name
Test status
Simulation time 12763382 ps
CPU time 1.1 seconds
Started Aug 25 10:46:10 AM UTC 24
Finished Aug 25 10:46:12 AM UTC 24
Peak memory 215744 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2130044399 -assert nopostproc +UVM_TES
TNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_
regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_alert_test.2130044399
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/16.spi_device_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/16.spi_device_cfg_cmd.3653318126
Short name T237
Test name
Test status
Simulation time 5840695157 ps
CPU time 17.93 seconds
Started Aug 25 10:45:58 AM UTC 24
Finished Aug 25 10:46:17 AM UTC 24
Peak memory 245332 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3653318126 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/spi
_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_cfg_cmd.3653318126
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/16.spi_device_cfg_cmd/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/16.spi_device_csb_read.3997271743
Short name T487
Test name
Test status
Simulation time 12842966 ps
CPU time 1.13 seconds
Started Aug 25 10:45:48 AM UTC 24
Finished Aug 25 10:45:50 AM UTC 24
Peak memory 215808 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3997271743 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/sp
i_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_csb_read.3997271743
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/16.spi_device_csb_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/16.spi_device_flash_and_tpm_min_idle.1678912410
Short name T513
Test name
Test status
Simulation time 5091281975 ps
CPU time 35.63 seconds
Started Aug 25 10:46:09 AM UTC 24
Finished Aug 25 10:46:46 AM UTC 24
Peak memory 251540 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1678912410 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_and_tpm_min_idle.1678912410
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/16.spi_device_flash_and_tpm_min_idle/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/16.spi_device_flash_mode.659817418
Short name T350
Test name
Test status
Simulation time 1270308017 ps
CPU time 6.72 seconds
Started Aug 25 10:46:01 AM UTC 24
Finished Aug 25 10:46:09 AM UTC 24
Peak memory 234964 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=659817418 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/s
pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_mode.659817418
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/16.spi_device_flash_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/16.spi_device_flash_mode_ignore_cmds.626195555
Short name T309
Test name
Test status
Simulation time 64994988052 ps
CPU time 190.03 seconds
Started Aug 25 10:46:01 AM UTC 24
Finished Aug 25 10:49:15 AM UTC 24
Peak memory 263760 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=626195555 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_24/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_mode_ignore_cmds.626195555
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/16.spi_device_flash_mode_ignore_cmds/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/16.spi_device_intercept.4126241490
Short name T195
Test name
Test status
Simulation time 692440767 ps
CPU time 12.64 seconds
Started Aug 25 10:45:57 AM UTC 24
Finished Aug 25 10:46:11 AM UTC 24
Peak memory 235036 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4126241490 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/s
pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_intercept.4126241490
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/16.spi_device_intercept/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/16.spi_device_mailbox.2371964429
Short name T347
Test name
Test status
Simulation time 3755358810 ps
CPU time 68.01 seconds
Started Aug 25 10:45:57 AM UTC 24
Finished Aug 25 10:47:07 AM UTC 24
Peak memory 245348 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2371964429 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/spi
_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_mailbox.2371964429
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/16.spi_device_mailbox/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/16.spi_device_pass_addr_payload_swap.1667183553
Short name T199
Test name
Test status
Simulation time 1885053759 ps
CPU time 12.49 seconds
Started Aug 25 10:45:55 AM UTC 24
Finished Aug 25 10:46:09 AM UTC 24
Peak memory 251352 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1667183553 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_pass_addr_payload_swap.1667183553
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/16.spi_device_pass_addr_payload_swap/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/16.spi_device_pass_cmd_filtering.1130360867
Short name T366
Test name
Test status
Simulation time 1236267812 ps
CPU time 12.1 seconds
Started Aug 25 10:45:55 AM UTC 24
Finished Aug 25 10:46:08 AM UTC 24
Peak memory 241848 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1130360867 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_08_24/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_pass_cmd_filtering.1130360867
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/16.spi_device_pass_cmd_filtering/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/16.spi_device_read_buffer_direct.473481025
Short name T500
Test name
Test status
Simulation time 1284967527 ps
CPU time 16.55 seconds
Started Aug 25 10:46:02 AM UTC 24
Finished Aug 25 10:46:20 AM UTC 24
Peak memory 231268 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=473481025 -assert nopostproc +UVM_TESTNAME=spi_device_
base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_read_buffer_direct.473481025
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/16.spi_device_read_buffer_direct/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/16.spi_device_stress_all.2512746786
Short name T495
Test name
Test status
Simulation time 65392983 ps
CPU time 1.42 seconds
Started Aug 25 10:46:10 AM UTC 24
Finished Aug 25 10:46:12 AM UTC 24
Peak memory 215740 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2512746786 -assert nopostproc +UVM_
TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra
tch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_stress_all.2512746786
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/16.spi_device_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/16.spi_device_tpm_all.623943054
Short name T393
Test name
Test status
Simulation time 894136843 ps
CPU time 18.36 seconds
Started Aug 25 10:45:50 AM UTC 24
Finished Aug 25 10:46:10 AM UTC 24
Peak memory 231576 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=623943054 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/spi_
device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_all.623943054
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/16.spi_device_tpm_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/16.spi_device_tpm_read_hw_reg.212214886
Short name T491
Test name
Test status
Simulation time 1621968547 ps
CPU time 10.63 seconds
Started Aug 25 10:45:49 AM UTC 24
Finished Aug 25 10:46:01 AM UTC 24
Peak memory 227408 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=212214886 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08
_24/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_read_hw_reg.212214886
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/16.spi_device_tpm_read_hw_reg/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/16.spi_device_tpm_rw.1172555511
Short name T489
Test name
Test status
Simulation time 347139277 ps
CPU time 1.98 seconds
Started Aug 25 10:45:53 AM UTC 24
Finished Aug 25 10:45:56 AM UTC 24
Peak memory 226756 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1172555511 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/spi_
device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_rw.1172555511
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/16.spi_device_tpm_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/16.spi_device_tpm_sts_read.3758551029
Short name T488
Test name
Test status
Simulation time 21031075 ps
CPU time 1.21 seconds
Started Aug 25 10:45:52 AM UTC 24
Finished Aug 25 10:45:54 AM UTC 24
Peak memory 215872 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3758551029 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_2
4/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_sts_read.3758551029
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/16.spi_device_tpm_sts_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/16.spi_device_upload.286601766
Short name T369
Test name
Test status
Simulation time 69305350620 ps
CPU time 100.4 seconds
Started Aug 25 10:45:58 AM UTC 24
Finished Aug 25 10:47:41 AM UTC 24
Peak memory 245336 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=286601766 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/spi_d
evice_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_upload.286601766
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/16.spi_device_upload/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/17.spi_device_alert_test.1272285096
Short name T504
Test name
Test status
Simulation time 47474984 ps
CPU time 1.06 seconds
Started Aug 25 10:46:23 AM UTC 24
Finished Aug 25 10:46:26 AM UTC 24
Peak memory 215744 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1272285096 -assert nopostproc +UVM_TES
TNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_
regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_alert_test.1272285096
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/17.spi_device_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/17.spi_device_cfg_cmd.660034929
Short name T200
Test name
Test status
Simulation time 154639258 ps
CPU time 7.3 seconds
Started Aug 25 10:46:18 AM UTC 24
Finished Aug 25 10:46:26 AM UTC 24
Peak memory 245160 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=660034929 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/spi_
device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_cfg_cmd.660034929
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/17.spi_device_cfg_cmd/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/17.spi_device_csb_read.3058338079
Short name T494
Test name
Test status
Simulation time 48862185 ps
CPU time 1.16 seconds
Started Aug 25 10:46:10 AM UTC 24
Finished Aug 25 10:46:12 AM UTC 24
Peak memory 215808 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3058338079 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/sp
i_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_csb_read.3058338079
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/17.spi_device_csb_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/17.spi_device_flash_all.2803718707
Short name T501
Test name
Test status
Simulation time 15479867 ps
CPU time 1.19 seconds
Started Aug 25 10:46:19 AM UTC 24
Finished Aug 25 10:46:21 AM UTC 24
Peak memory 225744 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2803718707 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/s
pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_all.2803718707
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/17.spi_device_flash_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/17.spi_device_flash_and_tpm.3135093926
Short name T782
Test name
Test status
Simulation time 73548159538 ps
CPU time 373.23 seconds
Started Aug 25 10:46:21 AM UTC 24
Finished Aug 25 10:52:40 AM UTC 24
Peak memory 278176 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3135093926 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
24/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_and_tpm.3135093926
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/17.spi_device_flash_and_tpm/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/17.spi_device_flash_and_tpm_min_idle.2146580493
Short name T389
Test name
Test status
Simulation time 6066265682 ps
CPU time 66.62 seconds
Started Aug 25 10:46:21 AM UTC 24
Finished Aug 25 10:47:30 AM UTC 24
Peak memory 247436 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2146580493 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_and_tpm_min_idle.2146580493
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/17.spi_device_flash_and_tpm_min_idle/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/17.spi_device_flash_mode.1997055952
Short name T502
Test name
Test status
Simulation time 75543323 ps
CPU time 5.31 seconds
Started Aug 25 10:46:18 AM UTC 24
Finished Aug 25 10:46:24 AM UTC 24
Peak memory 251304 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1997055952 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/
spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_mode.1997055952
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/17.spi_device_flash_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/17.spi_device_flash_mode_ignore_cmds.343483896
Short name T499
Test name
Test status
Simulation time 20942056 ps
CPU time 1.14 seconds
Started Aug 25 10:46:18 AM UTC 24
Finished Aug 25 10:46:20 AM UTC 24
Peak memory 225680 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=343483896 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_24/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_mode_ignore_cmds.343483896
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/17.spi_device_flash_mode_ignore_cmds/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/17.spi_device_intercept.225821411
Short name T338
Test name
Test status
Simulation time 982659643 ps
CPU time 6.37 seconds
Started Aug 25 10:46:16 AM UTC 24
Finished Aug 25 10:46:23 AM UTC 24
Peak memory 229544 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=225821411 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/sp
i_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_intercept.225821411
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/17.spi_device_intercept/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/17.spi_device_mailbox.3176851799
Short name T352
Test name
Test status
Simulation time 20696105509 ps
CPU time 30.75 seconds
Started Aug 25 10:46:17 AM UTC 24
Finished Aug 25 10:46:49 AM UTC 24
Peak memory 245272 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3176851799 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/spi
_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_mailbox.3176851799
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/17.spi_device_mailbox/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/17.spi_device_pass_cmd_filtering.2848937140
Short name T498
Test name
Test status
Simulation time 76267410 ps
CPU time 2.96 seconds
Started Aug 25 10:46:13 AM UTC 24
Finished Aug 25 10:46:17 AM UTC 24
Peak memory 234688 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2848937140 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_08_24/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_pass_cmd_filtering.2848937140
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/17.spi_device_pass_cmd_filtering/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/17.spi_device_read_buffer_direct.647382447
Short name T508
Test name
Test status
Simulation time 343753902 ps
CPU time 9.59 seconds
Started Aug 25 10:46:18 AM UTC 24
Finished Aug 25 10:46:29 AM UTC 24
Peak memory 231332 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=647382447 -assert nopostproc +UVM_TESTNAME=spi_device_
base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_read_buffer_direct.647382447
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/17.spi_device_read_buffer_direct/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/17.spi_device_stress_all.760369962
Short name T316
Test name
Test status
Simulation time 125854038598 ps
CPU time 818.14 seconds
Started Aug 25 10:46:22 AM UTC 24
Finished Aug 25 11:00:13 AM UTC 24
Peak memory 276188 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=760369962 -assert nopostproc +UVM_T
ESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_stress_all.760369962
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/17.spi_device_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/17.spi_device_tpm_all.1036696226
Short name T386
Test name
Test status
Simulation time 37939265521 ps
CPU time 71.6 seconds
Started Aug 25 10:46:12 AM UTC 24
Finished Aug 25 10:47:26 AM UTC 24
Peak memory 227552 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1036696226 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/spi
_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_all.1036696226
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/17.spi_device_tpm_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/17.spi_device_tpm_read_hw_reg.4081721980
Short name T503
Test name
Test status
Simulation time 4176677217 ps
CPU time 12.72 seconds
Started Aug 25 10:46:11 AM UTC 24
Finished Aug 25 10:46:25 AM UTC 24
Peak memory 227572 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4081721980 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_24/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_read_hw_reg.4081721980
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/17.spi_device_tpm_read_hw_reg/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/17.spi_device_tpm_rw.318869695
Short name T496
Test name
Test status
Simulation time 11349283 ps
CPU time 1.08 seconds
Started Aug 25 10:46:13 AM UTC 24
Finished Aug 25 10:46:16 AM UTC 24
Peak memory 215740 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=318869695 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/spi_d
evice_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_rw.318869695
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/17.spi_device_tpm_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/17.spi_device_tpm_sts_read.4117809094
Short name T497
Test name
Test status
Simulation time 30599779 ps
CPU time 1.11 seconds
Started Aug 25 10:46:13 AM UTC 24
Finished Aug 25 10:46:16 AM UTC 24
Peak memory 215812 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4117809094 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_2
4/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_sts_read.4117809094
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/17.spi_device_tpm_sts_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/17.spi_device_upload.2564073163
Short name T251
Test name
Test status
Simulation time 1253283111 ps
CPU time 6.69 seconds
Started Aug 25 10:46:17 AM UTC 24
Finished Aug 25 10:46:25 AM UTC 24
Peak memory 234964 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2564073163 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/spi_
device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_upload.2564073163
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/17.spi_device_upload/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/18.spi_device_alert_test.3735257429
Short name T493
Test name
Test status
Simulation time 96982683 ps
CPU time 1.09 seconds
Started Aug 25 10:46:46 AM UTC 24
Finished Aug 25 10:46:48 AM UTC 24
Peak memory 215684 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3735257429 -assert nopostproc +UVM_TES
TNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_
regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_alert_test.3735257429
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/18.spi_device_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/18.spi_device_cfg_cmd.2829363039
Short name T239
Test name
Test status
Simulation time 67476459 ps
CPU time 3.43 seconds
Started Aug 25 10:46:31 AM UTC 24
Finished Aug 25 10:46:36 AM UTC 24
Peak memory 245132 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2829363039 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/spi
_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_cfg_cmd.2829363039
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/18.spi_device_cfg_cmd/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/18.spi_device_csb_read.972905750
Short name T507
Test name
Test status
Simulation time 64996873 ps
CPU time 1.16 seconds
Started Aug 25 10:46:26 AM UTC 24
Finished Aug 25 10:46:28 AM UTC 24
Peak memory 215580 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=972905750 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/spi
_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_csb_read.972905750
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/18.spi_device_csb_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/18.spi_device_flash_all.3139882525
Short name T351
Test name
Test status
Simulation time 10473489588 ps
CPU time 154.54 seconds
Started Aug 25 10:46:38 AM UTC 24
Finished Aug 25 10:49:16 AM UTC 24
Peak memory 265820 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3139882525 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/s
pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_all.3139882525
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/18.spi_device_flash_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/18.spi_device_flash_and_tpm.2005696665
Short name T370
Test name
Test status
Simulation time 13921745414 ps
CPU time 210.45 seconds
Started Aug 25 10:46:40 AM UTC 24
Finished Aug 25 10:50:14 AM UTC 24
Peak memory 251552 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2005696665 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
24/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_and_tpm.2005696665
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/18.spi_device_flash_and_tpm/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/18.spi_device_flash_and_tpm_min_idle.1008740352
Short name T629
Test name
Test status
Simulation time 30337061939 ps
CPU time 195.97 seconds
Started Aug 25 10:46:41 AM UTC 24
Finished Aug 25 10:50:01 AM UTC 24
Peak memory 261852 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1008740352 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_and_tpm_min_idle.1008740352
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/18.spi_device_flash_and_tpm_min_idle/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/18.spi_device_flash_mode.4068346864
Short name T511
Test name
Test status
Simulation time 190352579 ps
CPU time 3.11 seconds
Started Aug 25 10:46:31 AM UTC 24
Finished Aug 25 10:46:36 AM UTC 24
Peak memory 245148 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4068346864 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/
spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_mode.4068346864
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/18.spi_device_flash_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/18.spi_device_flash_mode_ignore_cmds.455199478
Short name T280
Test name
Test status
Simulation time 8701651012 ps
CPU time 48.38 seconds
Started Aug 25 10:46:37 AM UTC 24
Finished Aug 25 10:47:27 AM UTC 24
Peak memory 245400 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=455199478 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_24/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_mode_ignore_cmds.455199478
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/18.spi_device_flash_mode_ignore_cmds/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/18.spi_device_intercept.3491409628
Short name T220
Test name
Test status
Simulation time 5233718471 ps
CPU time 8.33 seconds
Started Aug 25 10:46:29 AM UTC 24
Finished Aug 25 10:46:39 AM UTC 24
Peak memory 235040 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3491409628 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/s
pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_intercept.3491409628
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/18.spi_device_intercept/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/18.spi_device_mailbox.3266581057
Short name T560
Test name
Test status
Simulation time 8526525534 ps
CPU time 113.88 seconds
Started Aug 25 10:46:30 AM UTC 24
Finished Aug 25 10:48:27 AM UTC 24
Peak memory 245324 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3266581057 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/spi
_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_mailbox.3266581057
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/18.spi_device_mailbox/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/18.spi_device_pass_addr_payload_swap.4268874238
Short name T279
Test name
Test status
Simulation time 12555488581 ps
CPU time 18.01 seconds
Started Aug 25 10:46:29 AM UTC 24
Finished Aug 25 10:46:48 AM UTC 24
Peak memory 235088 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4268874238 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_pass_addr_payload_swap.4268874238
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/18.spi_device_pass_addr_payload_swap/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/18.spi_device_pass_cmd_filtering.1334497091
Short name T358
Test name
Test status
Simulation time 4419818281 ps
CPU time 26.63 seconds
Started Aug 25 10:46:29 AM UTC 24
Finished Aug 25 10:46:57 AM UTC 24
Peak memory 235120 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1334497091 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_08_24/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_pass_cmd_filtering.1334497091
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/18.spi_device_pass_cmd_filtering/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/18.spi_device_read_buffer_direct.1471098809
Short name T512
Test name
Test status
Simulation time 113202920 ps
CPU time 5.16 seconds
Started Aug 25 10:46:38 AM UTC 24
Finished Aug 25 10:46:44 AM UTC 24
Peak memory 233368 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1471098809 -assert nopostproc +UVM_TESTNAME=spi_device
_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_read_buffer_direct.1471098809
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/18.spi_device_read_buffer_direct/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/18.spi_device_stress_all.3185926261
Short name T264
Test name
Test status
Simulation time 3037630256 ps
CPU time 34.78 seconds
Started Aug 25 10:46:45 AM UTC 24
Finished Aug 25 10:47:21 AM UTC 24
Peak memory 261768 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3185926261 -assert nopostproc +UVM_
TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra
tch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_stress_all.3185926261
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/18.spi_device_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/18.spi_device_tpm_read_hw_reg.4059960352
Short name T505
Test name
Test status
Simulation time 41075994 ps
CPU time 1.05 seconds
Started Aug 25 10:46:26 AM UTC 24
Finished Aug 25 10:46:28 AM UTC 24
Peak memory 215808 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4059960352 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_24/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_read_hw_reg.4059960352
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/18.spi_device_tpm_read_hw_reg/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/18.spi_device_tpm_rw.1683089355
Short name T510
Test name
Test status
Simulation time 71112354 ps
CPU time 2.25 seconds
Started Aug 25 10:46:27 AM UTC 24
Finished Aug 25 10:46:31 AM UTC 24
Peak memory 227488 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1683089355 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/spi_
device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_rw.1683089355
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/18.spi_device_tpm_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/18.spi_device_tpm_sts_read.4089864370
Short name T509
Test name
Test status
Simulation time 72336059 ps
CPU time 1.46 seconds
Started Aug 25 10:46:27 AM UTC 24
Finished Aug 25 10:46:30 AM UTC 24
Peak memory 215872 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4089864370 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_2
4/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_sts_read.4089864370
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/18.spi_device_tpm_sts_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/18.spi_device_upload.3004580047
Short name T516
Test name
Test status
Simulation time 4430944530 ps
CPU time 23.28 seconds
Started Aug 25 10:46:30 AM UTC 24
Finished Aug 25 10:46:55 AM UTC 24
Peak memory 235092 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3004580047 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/spi_
device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_upload.3004580047
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/18.spi_device_upload/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/19.spi_device_alert_test.2251058188
Short name T520
Test name
Test status
Simulation time 10868936 ps
CPU time 1.05 seconds
Started Aug 25 10:47:07 AM UTC 24
Finished Aug 25 10:47:09 AM UTC 24
Peak memory 215748 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2251058188 -assert nopostproc +UVM_TES
TNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_
regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_alert_test.2251058188
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/19.spi_device_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/19.spi_device_cfg_cmd.1800236012
Short name T241
Test name
Test status
Simulation time 443495723 ps
CPU time 9.31 seconds
Started Aug 25 10:46:56 AM UTC 24
Finished Aug 25 10:47:07 AM UTC 24
Peak memory 245160 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1800236012 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/spi
_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_cfg_cmd.1800236012
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/19.spi_device_cfg_cmd/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/19.spi_device_csb_read.2804144907
Short name T506
Test name
Test status
Simulation time 40048516 ps
CPU time 1.21 seconds
Started Aug 25 10:46:46 AM UTC 24
Finished Aug 25 10:46:49 AM UTC 24
Peak memory 215808 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2804144907 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/sp
i_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_csb_read.2804144907
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/19.spi_device_csb_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/19.spi_device_flash_all.3359725339
Short name T706
Test name
Test status
Simulation time 99778256302 ps
CPU time 253.77 seconds
Started Aug 25 10:47:03 AM UTC 24
Finished Aug 25 10:51:22 AM UTC 24
Peak memory 261724 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3359725339 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/s
pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_all.3359725339
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/19.spi_device_flash_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/19.spi_device_flash_and_tpm.2087977683
Short name T263
Test name
Test status
Simulation time 3848286344 ps
CPU time 124.21 seconds
Started Aug 25 10:47:04 AM UTC 24
Finished Aug 25 10:49:11 AM UTC 24
Peak memory 265864 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2087977683 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
24/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_and_tpm.2087977683
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/19.spi_device_flash_and_tpm/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/19.spi_device_flash_and_tpm_min_idle.2492559100
Short name T387
Test name
Test status
Simulation time 5109616244 ps
CPU time 71.41 seconds
Started Aug 25 10:47:04 AM UTC 24
Finished Aug 25 10:48:18 AM UTC 24
Peak memory 251604 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2492559100 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_and_tpm_min_idle.2492559100
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/19.spi_device_flash_and_tpm_min_idle/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/19.spi_device_flash_mode.1262346895
Short name T518
Test name
Test status
Simulation time 39412729 ps
CPU time 3.65 seconds
Started Aug 25 10:46:58 AM UTC 24
Finished Aug 25 10:47:03 AM UTC 24
Peak memory 245212 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1262346895 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/
spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_mode.1262346895
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/19.spi_device_flash_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/19.spi_device_flash_mode_ignore_cmds.1467007899
Short name T524
Test name
Test status
Simulation time 481533234 ps
CPU time 15.55 seconds
Started Aug 25 10:46:58 AM UTC 24
Finished Aug 25 10:47:15 AM UTC 24
Peak memory 235036 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1467007899 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_mode_ignore_cmds.1467007899
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/19.spi_device_flash_mode_ignore_cmds/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/19.spi_device_intercept.2315800431
Short name T365
Test name
Test status
Simulation time 1661200546 ps
CPU time 10.77 seconds
Started Aug 25 10:46:51 AM UTC 24
Finished Aug 25 10:47:03 AM UTC 24
Peak memory 245292 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2315800431 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/s
pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_intercept.2315800431
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/19.spi_device_intercept/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/19.spi_device_mailbox.1502064814
Short name T517
Test name
Test status
Simulation time 106657632 ps
CPU time 3.16 seconds
Started Aug 25 10:46:53 AM UTC 24
Finished Aug 25 10:46:57 AM UTC 24
Peak memory 244968 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1502064814 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/spi
_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_mailbox.1502064814
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/19.spi_device_mailbox/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/19.spi_device_pass_addr_payload_swap.1949061663
Short name T323
Test name
Test status
Simulation time 1245758064 ps
CPU time 10.98 seconds
Started Aug 25 10:46:51 AM UTC 24
Finished Aug 25 10:47:03 AM UTC 24
Peak memory 247248 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1949061663 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_pass_addr_payload_swap.1949061663
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/19.spi_device_pass_addr_payload_swap/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/19.spi_device_pass_cmd_filtering.1294109054
Short name T262
Test name
Test status
Simulation time 5207186805 ps
CPU time 11.63 seconds
Started Aug 25 10:46:50 AM UTC 24
Finished Aug 25 10:47:02 AM UTC 24
Peak memory 245368 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1294109054 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_08_24/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_pass_cmd_filtering.1294109054
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/19.spi_device_pass_cmd_filtering/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/19.spi_device_read_buffer_direct.1589160517
Short name T526
Test name
Test status
Simulation time 5225495716 ps
CPU time 23.42 seconds
Started Aug 25 10:47:00 AM UTC 24
Finished Aug 25 10:47:25 AM UTC 24
Peak memory 231448 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1589160517 -assert nopostproc +UVM_TESTNAME=spi_device
_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_read_buffer_direct.1589160517
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/19.spi_device_read_buffer_direct/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/19.spi_device_stress_all.1395686688
Short name T169
Test name
Test status
Simulation time 7499849570 ps
CPU time 72.95 seconds
Started Aug 25 10:47:04 AM UTC 24
Finished Aug 25 10:48:19 AM UTC 24
Peak memory 251532 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1395686688 -assert nopostproc +UVM_
TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra
tch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_stress_all.1395686688
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/19.spi_device_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/19.spi_device_tpm_all.1247471353
Short name T398
Test name
Test status
Simulation time 1407913138 ps
CPU time 35.97 seconds
Started Aug 25 10:46:49 AM UTC 24
Finished Aug 25 10:47:27 AM UTC 24
Peak memory 227484 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1247471353 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/spi
_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_all.1247471353
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/19.spi_device_tpm_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/19.spi_device_tpm_read_hw_reg.4277985949
Short name T525
Test name
Test status
Simulation time 6525956179 ps
CPU time 27.44 seconds
Started Aug 25 10:46:47 AM UTC 24
Finished Aug 25 10:47:16 AM UTC 24
Peak memory 227620 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4277985949 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_24/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_read_hw_reg.4277985949
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/19.spi_device_tpm_read_hw_reg/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/19.spi_device_tpm_rw.1129735979
Short name T515
Test name
Test status
Simulation time 17735103 ps
CPU time 1.54 seconds
Started Aug 25 10:46:50 AM UTC 24
Finished Aug 25 10:46:52 AM UTC 24
Peak memory 226700 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1129735979 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/spi_
device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_rw.1129735979
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/19.spi_device_tpm_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/19.spi_device_tpm_sts_read.647705738
Short name T514
Test name
Test status
Simulation time 61263091 ps
CPU time 1.15 seconds
Started Aug 25 10:46:49 AM UTC 24
Finished Aug 25 10:46:52 AM UTC 24
Peak memory 215868 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=647705738 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24
/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_sts_read.647705738
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/19.spi_device_tpm_sts_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/19.spi_device_upload.2585747029
Short name T519
Test name
Test status
Simulation time 1646135906 ps
CPU time 13.21 seconds
Started Aug 25 10:46:53 AM UTC 24
Finished Aug 25 10:47:07 AM UTC 24
Peak memory 247268 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2585747029 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/spi_
device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_upload.2585747029
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/19.spi_device_upload/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/2.spi_device_alert_test.4093780491
Short name T93
Test name
Test status
Simulation time 40919894 ps
CPU time 1.09 seconds
Started Aug 25 10:42:09 AM UTC 24
Finished Aug 25 10:42:11 AM UTC 24
Peak memory 215680 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4093780491 -assert nopostproc +UVM_TES
TNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_
regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_alert_test.4093780491
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/2.spi_device_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/2.spi_device_csb_read.2281783794
Short name T18
Test name
Test status
Simulation time 15690400 ps
CPU time 1.1 seconds
Started Aug 25 10:42:01 AM UTC 24
Finished Aug 25 10:42:03 AM UTC 24
Peak memory 215444 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2281783794 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/sp
i_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_csb_read.2281783794
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/2.spi_device_csb_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/2.spi_device_flash_mode.3201989952
Short name T157
Test name
Test status
Simulation time 897178773 ps
CPU time 9.33 seconds
Started Aug 25 10:42:06 AM UTC 24
Finished Aug 25 10:42:16 AM UTC 24
Peak memory 245148 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3201989952 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/
spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_mode.3201989952
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/2.spi_device_flash_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/2.spi_device_flash_mode_ignore_cmds.974579603
Short name T82
Test name
Test status
Simulation time 8873468138 ps
CPU time 101.37 seconds
Started Aug 25 10:42:06 AM UTC 24
Finished Aug 25 10:43:49 AM UTC 24
Peak memory 251564 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=974579603 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_24/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_mode_ignore_cmds.974579603
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/2.spi_device_flash_mode_ignore_cmds/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/2.spi_device_intercept.1293787433
Short name T50
Test name
Test status
Simulation time 368784917 ps
CPU time 8.36 seconds
Started Aug 25 10:42:05 AM UTC 24
Finished Aug 25 10:42:15 AM UTC 24
Peak memory 234984 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1293787433 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/s
pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_intercept.1293787433
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/2.spi_device_intercept/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/2.spi_device_mailbox.3341467871
Short name T56
Test name
Test status
Simulation time 1455765764 ps
CPU time 21.41 seconds
Started Aug 25 10:42:05 AM UTC 24
Finished Aug 25 10:42:28 AM UTC 24
Peak memory 249248 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3341467871 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/spi
_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_mailbox.3341467871
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/2.spi_device_mailbox/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/2.spi_device_pass_addr_payload_swap.3577435239
Short name T119
Test name
Test status
Simulation time 239524948 ps
CPU time 3.46 seconds
Started Aug 25 10:42:05 AM UTC 24
Finished Aug 25 10:42:10 AM UTC 24
Peak memory 245324 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3577435239 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_pass_addr_payload_swap.3577435239
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/2.spi_device_pass_addr_payload_swap/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/2.spi_device_pass_cmd_filtering.1948140978
Short name T23
Test name
Test status
Simulation time 150719832 ps
CPU time 3.3 seconds
Started Aug 25 10:42:05 AM UTC 24
Finished Aug 25 10:42:10 AM UTC 24
Peak memory 245332 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1948140978 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_08_24/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_pass_cmd_filtering.1948140978
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/2.spi_device_pass_cmd_filtering/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/2.spi_device_read_buffer_direct.1057887125
Short name T47
Test name
Test status
Simulation time 717520474 ps
CPU time 8.91 seconds
Started Aug 25 10:42:06 AM UTC 24
Finished Aug 25 10:42:16 AM UTC 24
Peak memory 231328 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1057887125 -assert nopostproc +UVM_TESTNAME=spi_device
_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_read_buffer_direct.1057887125
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/2.spi_device_read_buffer_direct/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/2.spi_device_sec_cm.3108931081
Short name T29
Test name
Test status
Simulation time 81837387 ps
CPU time 1.68 seconds
Started Aug 25 10:42:07 AM UTC 24
Finished Aug 25 10:42:10 AM UTC 24
Peak memory 258040 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3108931081 -assert nopostproc +UVM_TEST
NAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_sec_cm.3108931081
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/2.spi_device_sec_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/2.spi_device_stress_all.398718359
Short name T345
Test name
Test status
Simulation time 78705072748 ps
CPU time 999.97 seconds
Started Aug 25 10:42:07 AM UTC 24
Finished Aug 25 10:59:01 AM UTC 24
Peak memory 298652 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=398718359 -assert nopostproc +UVM_T
ESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_stress_all.398718359
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/2.spi_device_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/2.spi_device_tpm_all.3680022049
Short name T68
Test name
Test status
Simulation time 1248465582 ps
CPU time 21.8 seconds
Started Aug 25 10:42:03 AM UTC 24
Finished Aug 25 10:42:26 AM UTC 24
Peak memory 226816 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3680022049 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/spi
_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_all.3680022049
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/2.spi_device_tpm_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/2.spi_device_tpm_read_hw_reg.4064027047
Short name T106
Test name
Test status
Simulation time 806778481 ps
CPU time 4.94 seconds
Started Aug 25 10:42:02 AM UTC 24
Finished Aug 25 10:42:08 AM UTC 24
Peak memory 227428 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4064027047 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_24/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_read_hw_reg.4064027047
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/2.spi_device_tpm_read_hw_reg/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/2.spi_device_tpm_rw.305107261
Short name T38
Test name
Test status
Simulation time 155411637 ps
CPU time 2.6 seconds
Started Aug 25 10:42:03 AM UTC 24
Finished Aug 25 10:42:07 AM UTC 24
Peak memory 226772 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=305107261 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/spi_d
evice_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_rw.305107261
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/2.spi_device_tpm_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/2.spi_device_tpm_sts_read.1040262560
Short name T26
Test name
Test status
Simulation time 79108383 ps
CPU time 1.08 seconds
Started Aug 25 10:42:03 AM UTC 24
Finished Aug 25 10:42:05 AM UTC 24
Peak memory 215868 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1040262560 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_2
4/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_sts_read.1040262560
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/2.spi_device_tpm_sts_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/2.spi_device_upload.3582344406
Short name T72
Test name
Test status
Simulation time 3130398407 ps
CPU time 7.96 seconds
Started Aug 25 10:42:05 AM UTC 24
Finished Aug 25 10:42:15 AM UTC 24
Peak memory 245324 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3582344406 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/spi_
device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_upload.3582344406
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/2.spi_device_upload/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/20.spi_device_alert_test.1959942364
Short name T528
Test name
Test status
Simulation time 12699703 ps
CPU time 1.07 seconds
Started Aug 25 10:47:28 AM UTC 24
Finished Aug 25 10:47:30 AM UTC 24
Peak memory 215744 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1959942364 -assert nopostproc +UVM_TES
TNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_
regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_alert_test.1959942364
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/20.spi_device_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/20.spi_device_cfg_cmd.1960631272
Short name T527
Test name
Test status
Simulation time 396881817 ps
CPU time 3.21 seconds
Started Aug 25 10:47:21 AM UTC 24
Finished Aug 25 10:47:25 AM UTC 24
Peak memory 234580 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1960631272 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/spi
_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_cfg_cmd.1960631272
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/20.spi_device_cfg_cmd/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/20.spi_device_csb_read.4288481724
Short name T521
Test name
Test status
Simulation time 22509944 ps
CPU time 1.11 seconds
Started Aug 25 10:47:08 AM UTC 24
Finished Aug 25 10:47:11 AM UTC 24
Peak memory 215812 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4288481724 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/sp
i_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_csb_read.4288481724
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/20.spi_device_csb_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/20.spi_device_flash_all.663306514
Short name T313
Test name
Test status
Simulation time 41690013068 ps
CPU time 152.29 seconds
Started Aug 25 10:47:26 AM UTC 24
Finished Aug 25 10:50:01 AM UTC 24
Peak memory 263764 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=663306514 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/sp
i_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_all.663306514
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/20.spi_device_flash_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/20.spi_device_flash_and_tpm.2256040900
Short name T833
Test name
Test status
Simulation time 32559137152 ps
CPU time 355.53 seconds
Started Aug 25 10:47:27 AM UTC 24
Finished Aug 25 10:53:28 AM UTC 24
Peak memory 265808 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2256040900 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
24/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_and_tpm.2256040900
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/20.spi_device_flash_and_tpm/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/20.spi_device_flash_and_tpm_min_idle.2702913211
Short name T147
Test name
Test status
Simulation time 4542304040 ps
CPU time 33.27 seconds
Started Aug 25 10:47:27 AM UTC 24
Finished Aug 25 10:48:01 AM UTC 24
Peak memory 247508 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2702913211 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_and_tpm_min_idle.2702913211
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/20.spi_device_flash_and_tpm_min_idle/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/20.spi_device_flash_mode.2717389917
Short name T558
Test name
Test status
Simulation time 3674174418 ps
CPU time 63.8 seconds
Started Aug 25 10:47:21 AM UTC 24
Finished Aug 25 10:48:27 AM UTC 24
Peak memory 263724 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2717389917 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/
spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_mode.2717389917
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/20.spi_device_flash_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/20.spi_device_flash_mode_ignore_cmds.4167858251
Short name T297
Test name
Test status
Simulation time 2118502061 ps
CPU time 42.97 seconds
Started Aug 25 10:47:22 AM UTC 24
Finished Aug 25 10:48:07 AM UTC 24
Peak memory 261668 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4167858251 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_mode_ignore_cmds.4167858251
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/20.spi_device_flash_mode_ignore_cmds/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/20.spi_device_intercept.1440559868
Short name T535
Test name
Test status
Simulation time 1481092845 ps
CPU time 22.82 seconds
Started Aug 25 10:47:16 AM UTC 24
Finished Aug 25 10:47:40 AM UTC 24
Peak memory 229552 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1440559868 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/s
pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_intercept.1440559868
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/20.spi_device_intercept/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/20.spi_device_mailbox.165344276
Short name T349
Test name
Test status
Simulation time 15515137162 ps
CPU time 27.43 seconds
Started Aug 25 10:47:17 AM UTC 24
Finished Aug 25 10:47:46 AM UTC 24
Peak memory 229684 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=165344276 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/spi_
device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_mailbox.165344276
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/20.spi_device_mailbox/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/20.spi_device_pass_addr_payload_swap.2211272640
Short name T268
Test name
Test status
Simulation time 4909226378 ps
CPU time 16.95 seconds
Started Aug 25 10:47:16 AM UTC 24
Finished Aug 25 10:47:34 AM UTC 24
Peak memory 234928 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2211272640 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_pass_addr_payload_swap.2211272640
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/20.spi_device_pass_addr_payload_swap/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/20.spi_device_pass_cmd_filtering.1899596766
Short name T231
Test name
Test status
Simulation time 94589838 ps
CPU time 3.62 seconds
Started Aug 25 10:47:16 AM UTC 24
Finished Aug 25 10:47:21 AM UTC 24
Peak memory 245240 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1899596766 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_08_24/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_pass_cmd_filtering.1899596766
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/20.spi_device_pass_cmd_filtering/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/20.spi_device_read_buffer_direct.3225982615
Short name T534
Test name
Test status
Simulation time 3399580635 ps
CPU time 13.81 seconds
Started Aug 25 10:47:24 AM UTC 24
Finished Aug 25 10:47:39 AM UTC 24
Peak memory 233780 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3225982615 -assert nopostproc +UVM_TESTNAME=spi_device
_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_read_buffer_direct.3225982615
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/20.spi_device_read_buffer_direct/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/20.spi_device_stress_all.3633898254
Short name T152
Test name
Test status
Simulation time 18123311670 ps
CPU time 169.32 seconds
Started Aug 25 10:47:28 AM UTC 24
Finished Aug 25 10:50:21 AM UTC 24
Peak memory 278156 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3633898254 -assert nopostproc +UVM_
TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra
tch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_stress_all.3633898254
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/20.spi_device_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/20.spi_device_tpm_all.3301016575
Short name T390
Test name
Test status
Simulation time 6098398454 ps
CPU time 29.31 seconds
Started Aug 25 10:47:11 AM UTC 24
Finished Aug 25 10:47:41 AM UTC 24
Peak memory 227608 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3301016575 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/spi
_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_all.3301016575
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/20.spi_device_tpm_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/20.spi_device_tpm_read_hw_reg.3191328900
Short name T529
Test name
Test status
Simulation time 4430136153 ps
CPU time 21.85 seconds
Started Aug 25 10:47:08 AM UTC 24
Finished Aug 25 10:47:32 AM UTC 24
Peak memory 227680 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3191328900 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_24/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_read_hw_reg.3191328900
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/20.spi_device_tpm_read_hw_reg/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/20.spi_device_tpm_rw.3276392382
Short name T523
Test name
Test status
Simulation time 186852544 ps
CPU time 1.76 seconds
Started Aug 25 10:47:12 AM UTC 24
Finished Aug 25 10:47:15 AM UTC 24
Peak memory 226384 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3276392382 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/spi_
device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_rw.3276392382
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/20.spi_device_tpm_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/20.spi_device_tpm_sts_read.601332214
Short name T522
Test name
Test status
Simulation time 138575684 ps
CPU time 1.8 seconds
Started Aug 25 10:47:12 AM UTC 24
Finished Aug 25 10:47:15 AM UTC 24
Peak memory 215868 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=601332214 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24
/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_sts_read.601332214
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/20.spi_device_tpm_sts_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/20.spi_device_upload.3621476242
Short name T221
Test name
Test status
Simulation time 1635750720 ps
CPU time 10.92 seconds
Started Aug 25 10:47:20 AM UTC 24
Finished Aug 25 10:47:32 AM UTC 24
Peak memory 245144 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3621476242 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/spi_
device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_upload.3621476242
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/20.spi_device_upload/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/21.spi_device_alert_test.1938477766
Short name T537
Test name
Test status
Simulation time 45579892 ps
CPU time 1.02 seconds
Started Aug 25 10:47:43 AM UTC 24
Finished Aug 25 10:47:45 AM UTC 24
Peak memory 215684 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1938477766 -assert nopostproc +UVM_TES
TNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_
regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_alert_test.1938477766
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/21.spi_device_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/21.spi_device_cfg_cmd.2085397842
Short name T265
Test name
Test status
Simulation time 207272753 ps
CPU time 6.65 seconds
Started Aug 25 10:47:37 AM UTC 24
Finished Aug 25 10:47:45 AM UTC 24
Peak memory 235024 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2085397842 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/spi
_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_cfg_cmd.2085397842
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/21.spi_device_cfg_cmd/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/21.spi_device_csb_read.2596824773
Short name T530
Test name
Test status
Simulation time 146422825 ps
CPU time 1.19 seconds
Started Aug 25 10:47:31 AM UTC 24
Finished Aug 25 10:47:33 AM UTC 24
Peak memory 215808 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2596824773 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/sp
i_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_csb_read.2596824773
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/21.spi_device_csb_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/21.spi_device_flash_all.1862669644
Short name T538
Test name
Test status
Simulation time 562549577 ps
CPU time 6.18 seconds
Started Aug 25 10:47:41 AM UTC 24
Finished Aug 25 10:47:48 AM UTC 24
Peak memory 245212 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1862669644 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/s
pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_all.1862669644
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/21.spi_device_flash_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/21.spi_device_flash_and_tpm.727659045
Short name T41
Test name
Test status
Simulation time 57463552655 ps
CPU time 335.18 seconds
Started Aug 25 10:47:42 AM UTC 24
Finished Aug 25 10:53:22 AM UTC 24
Peak memory 261680 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=727659045 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_2
4/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_and_tpm.727659045
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/21.spi_device_flash_and_tpm/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/21.spi_device_flash_and_tpm_min_idle.1390220140
Short name T623
Test name
Test status
Simulation time 33357531023 ps
CPU time 129.82 seconds
Started Aug 25 10:47:42 AM UTC 24
Finished Aug 25 10:49:54 AM UTC 24
Peak memory 276172 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1390220140 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_and_tpm_min_idle.1390220140
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/21.spi_device_flash_and_tpm_min_idle/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/21.spi_device_flash_mode.2000228448
Short name T548
Test name
Test status
Simulation time 5461731026 ps
CPU time 29.4 seconds
Started Aug 25 10:47:37 AM UTC 24
Finished Aug 25 10:48:08 AM UTC 24
Peak memory 251496 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2000228448 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/
spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_mode.2000228448
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/21.spi_device_flash_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/21.spi_device_intercept.2006470508
Short name T227
Test name
Test status
Simulation time 2148452645 ps
CPU time 6.64 seconds
Started Aug 25 10:47:35 AM UTC 24
Finished Aug 25 10:47:42 AM UTC 24
Peak memory 234976 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2006470508 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/s
pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_intercept.2006470508
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/21.spi_device_intercept/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/21.spi_device_mailbox.4034520321
Short name T339
Test name
Test status
Simulation time 4775242246 ps
CPU time 86.26 seconds
Started Aug 25 10:47:36 AM UTC 24
Finished Aug 25 10:49:05 AM UTC 24
Peak memory 245252 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4034520321 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/spi
_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_mailbox.4034520321
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/21.spi_device_mailbox/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/21.spi_device_pass_addr_payload_swap.2318404441
Short name T222
Test name
Test status
Simulation time 5588213163 ps
CPU time 37.36 seconds
Started Aug 25 10:47:34 AM UTC 24
Finished Aug 25 10:48:13 AM UTC 24
Peak memory 261776 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2318404441 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_pass_addr_payload_swap.2318404441
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/21.spi_device_pass_addr_payload_swap/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/21.spi_device_pass_cmd_filtering.1291777794
Short name T261
Test name
Test status
Simulation time 1764098669 ps
CPU time 12.73 seconds
Started Aug 25 10:47:33 AM UTC 24
Finished Aug 25 10:47:47 AM UTC 24
Peak memory 245180 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1291777794 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_08_24/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_pass_cmd_filtering.1291777794
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/21.spi_device_pass_cmd_filtering/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/21.spi_device_read_buffer_direct.1193019631
Short name T544
Test name
Test status
Simulation time 6734249093 ps
CPU time 10.93 seconds
Started Aug 25 10:47:41 AM UTC 24
Finished Aug 25 10:47:53 AM UTC 24
Peak memory 231388 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1193019631 -assert nopostproc +UVM_TESTNAME=spi_device
_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_read_buffer_direct.1193019631
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/21.spi_device_read_buffer_direct/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/21.spi_device_stress_all.2331411022
Short name T849
Test name
Test status
Simulation time 23213372199 ps
CPU time 358.14 seconds
Started Aug 25 10:47:43 AM UTC 24
Finished Aug 25 10:53:47 AM UTC 24
Peak memory 267996 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2331411022 -assert nopostproc +UVM_
TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra
tch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_stress_all.2331411022
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/21.spi_device_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/21.spi_device_tpm_all.2459384061
Short name T543
Test name
Test status
Simulation time 938518444 ps
CPU time 19.54 seconds
Started Aug 25 10:47:31 AM UTC 24
Finished Aug 25 10:47:52 AM UTC 24
Peak memory 227548 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2459384061 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/spi
_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_all.2459384061
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/21.spi_device_tpm_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/21.spi_device_tpm_read_hw_reg.1069855979
Short name T533
Test name
Test status
Simulation time 794802930 ps
CPU time 6.51 seconds
Started Aug 25 10:47:31 AM UTC 24
Finished Aug 25 10:47:39 AM UTC 24
Peak memory 227432 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1069855979 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_24/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_read_hw_reg.1069855979
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/21.spi_device_tpm_read_hw_reg/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/21.spi_device_tpm_rw.1315794532
Short name T532
Test name
Test status
Simulation time 160261557 ps
CPU time 1.93 seconds
Started Aug 25 10:47:33 AM UTC 24
Finished Aug 25 10:47:36 AM UTC 24
Peak memory 226480 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1315794532 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/spi_
device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_rw.1315794532
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/21.spi_device_tpm_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/21.spi_device_tpm_sts_read.3859363214
Short name T531
Test name
Test status
Simulation time 95031366 ps
CPU time 1.61 seconds
Started Aug 25 10:47:32 AM UTC 24
Finished Aug 25 10:47:35 AM UTC 24
Peak memory 215872 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3859363214 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_2
4/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_sts_read.3859363214
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/21.spi_device_tpm_sts_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/21.spi_device_upload.1571729273
Short name T536
Test name
Test status
Simulation time 568933680 ps
CPU time 4.41 seconds
Started Aug 25 10:47:36 AM UTC 24
Finished Aug 25 10:47:42 AM UTC 24
Peak memory 247208 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1571729273 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/spi_
device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_upload.1571729273
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/21.spi_device_upload/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/22.spi_device_alert_test.1928396271
Short name T545
Test name
Test status
Simulation time 20186967 ps
CPU time 1.09 seconds
Started Aug 25 10:48:04 AM UTC 24
Finished Aug 25 10:48:06 AM UTC 24
Peak memory 215684 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1928396271 -assert nopostproc +UVM_TES
TNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_
regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_alert_test.1928396271
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/22.spi_device_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/22.spi_device_cfg_cmd.3873296960
Short name T144
Test name
Test status
Simulation time 172930451 ps
CPU time 3.23 seconds
Started Aug 25 10:47:54 AM UTC 24
Finished Aug 25 10:47:58 AM UTC 24
Peak memory 234976 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3873296960 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/spi
_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_cfg_cmd.3873296960
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/22.spi_device_cfg_cmd/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/22.spi_device_csb_read.1642317733
Short name T539
Test name
Test status
Simulation time 159065203 ps
CPU time 1.12 seconds
Started Aug 25 10:47:46 AM UTC 24
Finished Aug 25 10:47:48 AM UTC 24
Peak memory 215296 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1642317733 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/sp
i_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_csb_read.1642317733
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/22.spi_device_csb_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/22.spi_device_flash_all.1126731987
Short name T303
Test name
Test status
Simulation time 35762431032 ps
CPU time 371.43 seconds
Started Aug 25 10:48:00 AM UTC 24
Finished Aug 25 10:54:17 AM UTC 24
Peak memory 272044 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1126731987 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/s
pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_all.1126731987
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/22.spi_device_flash_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/22.spi_device_flash_and_tpm.3286015327
Short name T635
Test name
Test status
Simulation time 16720307118 ps
CPU time 121.65 seconds
Started Aug 25 10:48:02 AM UTC 24
Finished Aug 25 10:50:06 AM UTC 24
Peak memory 284296 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3286015327 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
24/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_and_tpm.3286015327
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/22.spi_device_flash_and_tpm/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/22.spi_device_flash_and_tpm_min_idle.688594640
Short name T305
Test name
Test status
Simulation time 401032421454 ps
CPU time 566.34 seconds
Started Aug 25 10:48:03 AM UTC 24
Finished Aug 25 10:57:37 AM UTC 24
Peak memory 278156 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=688594640 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_24/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_and_tpm_min_idle.688594640
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/22.spi_device_flash_and_tpm_min_idle/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/22.spi_device_flash_mode.793751708
Short name T151
Test name
Test status
Simulation time 427388161 ps
CPU time 7.91 seconds
Started Aug 25 10:47:56 AM UTC 24
Finished Aug 25 10:48:05 AM UTC 24
Peak memory 245268 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=793751708 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/s
pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_mode.793751708
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/22.spi_device_flash_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/22.spi_device_flash_mode_ignore_cmds.4238148703
Short name T216
Test name
Test status
Simulation time 126995565210 ps
CPU time 259.04 seconds
Started Aug 25 10:47:57 AM UTC 24
Finished Aug 25 10:52:21 AM UTC 24
Peak memory 265808 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4238148703 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_mode_ignore_cmds.4238148703
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/22.spi_device_flash_mode_ignore_cmds/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/22.spi_device_intercept.4137253386
Short name T109
Test name
Test status
Simulation time 1297729087 ps
CPU time 12.17 seconds
Started Aug 25 10:47:53 AM UTC 24
Finished Aug 25 10:48:06 AM UTC 24
Peak memory 245340 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4137253386 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/s
pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_intercept.4137253386
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/22.spi_device_intercept/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/22.spi_device_mailbox.2228830904
Short name T148
Test name
Test status
Simulation time 208816557 ps
CPU time 8.62 seconds
Started Aug 25 10:47:53 AM UTC 24
Finished Aug 25 10:48:03 AM UTC 24
Peak memory 245136 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2228830904 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/spi
_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_mailbox.2228830904
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/22.spi_device_mailbox/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/22.spi_device_pass_addr_payload_swap.1951200189
Short name T146
Test name
Test status
Simulation time 378224987 ps
CPU time 8.45 seconds
Started Aug 25 10:47:52 AM UTC 24
Finished Aug 25 10:48:01 AM UTC 24
Peak memory 234904 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1951200189 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_pass_addr_payload_swap.1951200189
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/22.spi_device_pass_addr_payload_swap/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/22.spi_device_pass_cmd_filtering.3110788739
Short name T228
Test name
Test status
Simulation time 12388281648 ps
CPU time 39.78 seconds
Started Aug 25 10:47:49 AM UTC 24
Finished Aug 25 10:48:31 AM UTC 24
Peak memory 251500 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3110788739 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_08_24/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_pass_cmd_filtering.3110788739
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/22.spi_device_pass_cmd_filtering/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/22.spi_device_read_buffer_direct.3595581588
Short name T150
Test name
Test status
Simulation time 109211227 ps
CPU time 4.65 seconds
Started Aug 25 10:47:59 AM UTC 24
Finished Aug 25 10:48:05 AM UTC 24
Peak memory 231324 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3595581588 -assert nopostproc +UVM_TESTNAME=spi_device
_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_read_buffer_direct.3595581588
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/22.spi_device_read_buffer_direct/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/22.spi_device_stress_all.3982357830
Short name T310
Test name
Test status
Simulation time 22625264048 ps
CPU time 128.52 seconds
Started Aug 25 10:48:04 AM UTC 24
Finished Aug 25 10:50:15 AM UTC 24
Peak memory 261852 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3982357830 -assert nopostproc +UVM_
TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra
tch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_stress_all.3982357830
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/22.spi_device_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/22.spi_device_tpm_all.735962494
Short name T546
Test name
Test status
Simulation time 2575073338 ps
CPU time 17.61 seconds
Started Aug 25 10:47:47 AM UTC 24
Finished Aug 25 10:48:06 AM UTC 24
Peak memory 231648 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=735962494 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/spi_
device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_all.735962494
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/22.spi_device_tpm_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/22.spi_device_tpm_read_hw_reg.2372177509
Short name T149
Test name
Test status
Simulation time 12499638044 ps
CPU time 15.57 seconds
Started Aug 25 10:47:46 AM UTC 24
Finished Aug 25 10:48:03 AM UTC 24
Peak memory 227552 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2372177509 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_24/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_read_hw_reg.2372177509
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/22.spi_device_tpm_read_hw_reg/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/22.spi_device_tpm_rw.2047185586
Short name T542
Test name
Test status
Simulation time 64471035 ps
CPU time 1.49 seconds
Started Aug 25 10:47:49 AM UTC 24
Finished Aug 25 10:47:52 AM UTC 24
Peak memory 216396 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2047185586 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/spi_
device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_rw.2047185586
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/22.spi_device_tpm_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/22.spi_device_tpm_sts_read.4062248532
Short name T540
Test name
Test status
Simulation time 111696439 ps
CPU time 1.24 seconds
Started Aug 25 10:47:48 AM UTC 24
Finished Aug 25 10:47:51 AM UTC 24
Peak memory 215872 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4062248532 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_2
4/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_sts_read.4062248532
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/22.spi_device_tpm_sts_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/22.spi_device_upload.2343571937
Short name T145
Test name
Test status
Simulation time 1029804830 ps
CPU time 5.08 seconds
Started Aug 25 10:47:53 AM UTC 24
Finished Aug 25 10:47:59 AM UTC 24
Peak memory 234964 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2343571937 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/spi_
device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_upload.2343571937
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/22.spi_device_upload/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/23.spi_device_alert_test.4225185426
Short name T557
Test name
Test status
Simulation time 23020882 ps
CPU time 1.07 seconds
Started Aug 25 10:48:24 AM UTC 24
Finished Aug 25 10:48:27 AM UTC 24
Peak memory 215684 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4225185426 -assert nopostproc +UVM_TES
TNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_
regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_alert_test.4225185426
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/23.spi_device_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/23.spi_device_cfg_cmd.1942343519
Short name T552
Test name
Test status
Simulation time 188347861 ps
CPU time 3.23 seconds
Started Aug 25 10:48:14 AM UTC 24
Finished Aug 25 10:48:18 AM UTC 24
Peak memory 234900 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1942343519 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/spi
_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_cfg_cmd.1942343519
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/23.spi_device_cfg_cmd/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/23.spi_device_csb_read.2284139381
Short name T547
Test name
Test status
Simulation time 55140969 ps
CPU time 1.18 seconds
Started Aug 25 10:48:06 AM UTC 24
Finished Aug 25 10:48:08 AM UTC 24
Peak memory 215812 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2284139381 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/sp
i_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_csb_read.2284139381
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/23.spi_device_csb_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/23.spi_device_flash_all.794981821
Short name T272
Test name
Test status
Simulation time 47692915642 ps
CPU time 461.21 seconds
Started Aug 25 10:48:19 AM UTC 24
Finished Aug 25 10:56:07 AM UTC 24
Peak memory 280160 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=794981821 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/sp
i_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_all.794981821
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/23.spi_device_flash_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/23.spi_device_flash_and_tpm.19183809
Short name T668
Test name
Test status
Simulation time 87575782848 ps
CPU time 135.41 seconds
Started Aug 25 10:48:20 AM UTC 24
Finished Aug 25 10:50:39 AM UTC 24
Peak memory 251524 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=19183809 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24
/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_and_tpm.19183809
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/23.spi_device_flash_and_tpm/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/23.spi_device_flash_and_tpm_min_idle.3153523342
Short name T620
Test name
Test status
Simulation time 10930316902 ps
CPU time 85.76 seconds
Started Aug 25 10:48:20 AM UTC 24
Finished Aug 25 10:49:49 AM UTC 24
Peak memory 263876 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3153523342 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_and_tpm_min_idle.3153523342
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/23.spi_device_flash_and_tpm_min_idle/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/23.spi_device_flash_mode.1620668762
Short name T376
Test name
Test status
Simulation time 371187312 ps
CPU time 8.13 seconds
Started Aug 25 10:48:19 AM UTC 24
Finished Aug 25 10:48:28 AM UTC 24
Peak memory 234988 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1620668762 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/
spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_mode.1620668762
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/23.spi_device_flash_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/23.spi_device_flash_mode_ignore_cmds.1219871051
Short name T312
Test name
Test status
Simulation time 22968149484 ps
CPU time 288.4 seconds
Started Aug 25 10:48:19 AM UTC 24
Finished Aug 25 10:53:12 AM UTC 24
Peak memory 261736 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1219871051 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_mode_ignore_cmds.1219871051
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/23.spi_device_flash_mode_ignore_cmds/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/23.spi_device_intercept.3507388632
Short name T551
Test name
Test status
Simulation time 166778503 ps
CPU time 7.08 seconds
Started Aug 25 10:48:09 AM UTC 24
Finished Aug 25 10:48:18 AM UTC 24
Peak memory 234912 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3507388632 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/s
pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_intercept.3507388632
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/23.spi_device_intercept/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/23.spi_device_mailbox.3791225683
Short name T561
Test name
Test status
Simulation time 395631112 ps
CPU time 16.17 seconds
Started Aug 25 10:48:11 AM UTC 24
Finished Aug 25 10:48:28 AM UTC 24
Peak memory 251364 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3791225683 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/spi
_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_mailbox.3791225683
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/23.spi_device_mailbox/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/23.spi_device_pass_addr_payload_swap.2538867994
Short name T234
Test name
Test status
Simulation time 197626346 ps
CPU time 7.79 seconds
Started Aug 25 10:48:09 AM UTC 24
Finished Aug 25 10:48:18 AM UTC 24
Peak memory 245348 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2538867994 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_pass_addr_payload_swap.2538867994
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/23.spi_device_pass_addr_payload_swap/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/23.spi_device_pass_cmd_filtering.1313977577
Short name T554
Test name
Test status
Simulation time 2438350666 ps
CPU time 13.87 seconds
Started Aug 25 10:48:08 AM UTC 24
Finished Aug 25 10:48:24 AM UTC 24
Peak memory 249512 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1313977577 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_08_24/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_pass_cmd_filtering.1313977577
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/23.spi_device_pass_cmd_filtering/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/23.spi_device_read_buffer_direct.2399095615
Short name T570
Test name
Test status
Simulation time 5491210158 ps
CPU time 19.24 seconds
Started Aug 25 10:48:19 AM UTC 24
Finished Aug 25 10:48:40 AM UTC 24
Peak memory 233496 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2399095615 -assert nopostproc +UVM_TESTNAME=spi_device
_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_read_buffer_direct.2399095615
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/23.spi_device_read_buffer_direct/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/23.spi_device_tpm_all.3098502153
Short name T575
Test name
Test status
Simulation time 28206732757 ps
CPU time 37.99 seconds
Started Aug 25 10:48:07 AM UTC 24
Finished Aug 25 10:48:47 AM UTC 24
Peak memory 231708 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3098502153 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/spi
_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_all.3098502153
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/23.spi_device_tpm_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/23.spi_device_tpm_read_hw_reg.236788771
Short name T562
Test name
Test status
Simulation time 4260517665 ps
CPU time 22.46 seconds
Started Aug 25 10:48:06 AM UTC 24
Finished Aug 25 10:48:30 AM UTC 24
Peak memory 227548 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=236788771 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08
_24/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_read_hw_reg.236788771
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/23.spi_device_tpm_read_hw_reg/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/23.spi_device_tpm_rw.1710041976
Short name T550
Test name
Test status
Simulation time 393291908 ps
CPU time 3.46 seconds
Started Aug 25 10:48:07 AM UTC 24
Finished Aug 25 10:48:12 AM UTC 24
Peak memory 227424 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1710041976 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/spi_
device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_rw.1710041976
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/23.spi_device_tpm_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/23.spi_device_tpm_sts_read.642897952
Short name T549
Test name
Test status
Simulation time 54714434 ps
CPU time 1.14 seconds
Started Aug 25 10:48:07 AM UTC 24
Finished Aug 25 10:48:09 AM UTC 24
Peak memory 215868 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=642897952 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24
/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_sts_read.642897952
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/23.spi_device_tpm_sts_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/23.spi_device_upload.2809849766
Short name T553
Test name
Test status
Simulation time 2258270811 ps
CPU time 9.55 seconds
Started Aug 25 10:48:13 AM UTC 24
Finished Aug 25 10:48:23 AM UTC 24
Peak memory 245224 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2809849766 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/spi_
device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_upload.2809849766
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/23.spi_device_upload/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/24.spi_device_alert_test.1335947811
Short name T573
Test name
Test status
Simulation time 17037422 ps
CPU time 1.08 seconds
Started Aug 25 10:48:41 AM UTC 24
Finished Aug 25 10:48:44 AM UTC 24
Peak memory 215744 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1335947811 -assert nopostproc +UVM_TES
TNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_
regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_alert_test.1335947811
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/24.spi_device_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/24.spi_device_cfg_cmd.182164869
Short name T566
Test name
Test status
Simulation time 115795216 ps
CPU time 3.47 seconds
Started Aug 25 10:48:31 AM UTC 24
Finished Aug 25 10:48:36 AM UTC 24
Peak memory 245140 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=182164869 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/spi_
device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_cfg_cmd.182164869
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/24.spi_device_cfg_cmd/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/24.spi_device_csb_read.845486821
Short name T559
Test name
Test status
Simulation time 16301618 ps
CPU time 1.2 seconds
Started Aug 25 10:48:24 AM UTC 24
Finished Aug 25 10:48:27 AM UTC 24
Peak memory 215640 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=845486821 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/spi
_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_csb_read.845486821
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/24.spi_device_csb_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/24.spi_device_flash_all.3961157030
Short name T581
Test name
Test status
Simulation time 3176690230 ps
CPU time 19.54 seconds
Started Aug 25 10:48:38 AM UTC 24
Finished Aug 25 10:48:59 AM UTC 24
Peak memory 235096 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3961157030 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/s
pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_all.3961157030
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/24.spi_device_flash_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/24.spi_device_flash_and_tpm.1355963849
Short name T639
Test name
Test status
Simulation time 8623293157 ps
CPU time 89.14 seconds
Started Aug 25 10:48:38 AM UTC 24
Finished Aug 25 10:50:09 AM UTC 24
Peak memory 261776 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1355963849 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
24/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_and_tpm.1355963849
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/24.spi_device_flash_and_tpm/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/24.spi_device_flash_and_tpm_min_idle.1533939030
Short name T632
Test name
Test status
Simulation time 2831083470 ps
CPU time 81.6 seconds
Started Aug 25 10:48:40 AM UTC 24
Finished Aug 25 10:50:04 AM UTC 24
Peak memory 261844 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1533939030 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_and_tpm_min_idle.1533939030
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/24.spi_device_flash_and_tpm_min_idle/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/24.spi_device_flash_mode.2304236774
Short name T568
Test name
Test status
Simulation time 275098787 ps
CPU time 4.44 seconds
Started Aug 25 10:48:31 AM UTC 24
Finished Aug 25 10:48:37 AM UTC 24
Peak memory 234944 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2304236774 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/
spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_mode.2304236774
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/24.spi_device_flash_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/24.spi_device_flash_mode_ignore_cmds.1121763683
Short name T569
Test name
Test status
Simulation time 13807972 ps
CPU time 1.2 seconds
Started Aug 25 10:48:37 AM UTC 24
Finished Aug 25 10:48:39 AM UTC 24
Peak memory 225680 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1121763683 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_mode_ignore_cmds.1121763683
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/24.spi_device_flash_mode_ignore_cmds/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/24.spi_device_intercept.3897056668
Short name T565
Test name
Test status
Simulation time 647264869 ps
CPU time 5.19 seconds
Started Aug 25 10:48:29 AM UTC 24
Finished Aug 25 10:48:36 AM UTC 24
Peak memory 245228 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3897056668 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/s
pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_intercept.3897056668
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/24.spi_device_intercept/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/24.spi_device_mailbox.1190215100
Short name T607
Test name
Test status
Simulation time 5594076816 ps
CPU time 62.43 seconds
Started Aug 25 10:48:30 AM UTC 24
Finished Aug 25 10:49:34 AM UTC 24
Peak memory 235024 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1190215100 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/spi
_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_mailbox.1190215100
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/24.spi_device_mailbox/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/24.spi_device_pass_addr_payload_swap.964981460
Short name T567
Test name
Test status
Simulation time 852457717 ps
CPU time 6.09 seconds
Started Aug 25 10:48:29 AM UTC 24
Finished Aug 25 10:48:36 AM UTC 24
Peak memory 234904 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=964981460 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_24/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_pass_addr_payload_swap.964981460
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/24.spi_device_pass_addr_payload_swap/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/24.spi_device_pass_cmd_filtering.1025571807
Short name T572
Test name
Test status
Simulation time 6103941297 ps
CPU time 10.4 seconds
Started Aug 25 10:48:29 AM UTC 24
Finished Aug 25 10:48:41 AM UTC 24
Peak memory 235048 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1025571807 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_08_24/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_pass_cmd_filtering.1025571807
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/24.spi_device_pass_cmd_filtering/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/24.spi_device_read_buffer_direct.4153378486
Short name T576
Test name
Test status
Simulation time 1403526507 ps
CPU time 10.33 seconds
Started Aug 25 10:48:37 AM UTC 24
Finished Aug 25 10:48:48 AM UTC 24
Peak memory 231388 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4153378486 -assert nopostproc +UVM_TESTNAME=spi_device
_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_read_buffer_direct.4153378486
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/24.spi_device_read_buffer_direct/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/24.spi_device_tpm_all.3493289447
Short name T399
Test name
Test status
Simulation time 7592112763 ps
CPU time 53.19 seconds
Started Aug 25 10:48:28 AM UTC 24
Finished Aug 25 10:49:23 AM UTC 24
Peak memory 227552 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3493289447 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/spi
_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_all.3493289447
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/24.spi_device_tpm_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/24.spi_device_tpm_read_hw_reg.709842830
Short name T586
Test name
Test status
Simulation time 15424975383 ps
CPU time 39.37 seconds
Started Aug 25 10:48:26 AM UTC 24
Finished Aug 25 10:49:07 AM UTC 24
Peak memory 227612 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=709842830 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08
_24/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_read_hw_reg.709842830
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/24.spi_device_tpm_read_hw_reg/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/24.spi_device_tpm_rw.1040428766
Short name T564
Test name
Test status
Simulation time 47694113 ps
CPU time 1.59 seconds
Started Aug 25 10:48:28 AM UTC 24
Finished Aug 25 10:48:31 AM UTC 24
Peak memory 216156 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1040428766 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/spi_
device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_rw.1040428766
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/24.spi_device_tpm_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/24.spi_device_tpm_sts_read.2522813940
Short name T563
Test name
Test status
Simulation time 26986197 ps
CPU time 1.21 seconds
Started Aug 25 10:48:28 AM UTC 24
Finished Aug 25 10:48:30 AM UTC 24
Peak memory 215868 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2522813940 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_2
4/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_sts_read.2522813940
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/24.spi_device_tpm_sts_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/24.spi_device_upload.3758494079
Short name T592
Test name
Test status
Simulation time 11117334953 ps
CPU time 38.51 seconds
Started Aug 25 10:48:31 AM UTC 24
Finished Aug 25 10:49:12 AM UTC 24
Peak memory 251496 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3758494079 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/spi_
device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_upload.3758494079
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/24.spi_device_upload/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/25.spi_device_alert_test.1456107104
Short name T589
Test name
Test status
Simulation time 11783422 ps
CPU time 1.08 seconds
Started Aug 25 10:49:07 AM UTC 24
Finished Aug 25 10:49:09 AM UTC 24
Peak memory 215808 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1456107104 -assert nopostproc +UVM_TES
TNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_
regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_alert_test.1456107104
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/25.spi_device_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/25.spi_device_cfg_cmd.1378310137
Short name T585
Test name
Test status
Simulation time 755580306 ps
CPU time 10.07 seconds
Started Aug 25 10:48:55 AM UTC 24
Finished Aug 25 10:49:06 AM UTC 24
Peak memory 245156 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1378310137 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/spi
_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_cfg_cmd.1378310137
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/25.spi_device_cfg_cmd/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/25.spi_device_csb_read.1951184228
Short name T574
Test name
Test status
Simulation time 15447137 ps
CPU time 1.16 seconds
Started Aug 25 10:48:42 AM UTC 24
Finished Aug 25 10:48:45 AM UTC 24
Peak memory 215812 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1951184228 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/sp
i_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_csb_read.1951184228
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/25.spi_device_csb_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/25.spi_device_flash_all.1612609131
Short name T820
Test name
Test status
Simulation time 47016386160 ps
CPU time 249.5 seconds
Started Aug 25 10:49:00 AM UTC 24
Finished Aug 25 10:53:14 AM UTC 24
Peak memory 261848 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1612609131 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/s
pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_all.1612609131
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/25.spi_device_flash_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/25.spi_device_flash_and_tpm.2936344581
Short name T271
Test name
Test status
Simulation time 12295713201 ps
CPU time 131.96 seconds
Started Aug 25 10:49:00 AM UTC 24
Finished Aug 25 10:51:14 AM UTC 24
Peak memory 261784 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2936344581 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
24/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_and_tpm.2936344581
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/25.spi_device_flash_and_tpm/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/25.spi_device_flash_mode.1566743595
Short name T584
Test name
Test status
Simulation time 62752299 ps
CPU time 3.65 seconds
Started Aug 25 10:48:56 AM UTC 24
Finished Aug 25 10:49:01 AM UTC 24
Peak memory 245144 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1566743595 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/
spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_mode.1566743595
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/25.spi_device_flash_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/25.spi_device_flash_mode_ignore_cmds.1039036450
Short name T258
Test name
Test status
Simulation time 46732222059 ps
CPU time 91.56 seconds
Started Aug 25 10:48:57 AM UTC 24
Finished Aug 25 10:50:31 AM UTC 24
Peak memory 249444 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1039036450 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_mode_ignore_cmds.1039036450
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/25.spi_device_flash_mode_ignore_cmds/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/25.spi_device_intercept.757137492
Short name T599
Test name
Test status
Simulation time 2650685333 ps
CPU time 32.33 seconds
Started Aug 25 10:48:50 AM UTC 24
Finished Aug 25 10:49:24 AM UTC 24
Peak memory 235032 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=757137492 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/sp
i_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_intercept.757137492
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/25.spi_device_intercept/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/25.spi_device_mailbox.2900702240
Short name T612
Test name
Test status
Simulation time 8138307320 ps
CPU time 44.65 seconds
Started Aug 25 10:48:53 AM UTC 24
Finished Aug 25 10:49:39 AM UTC 24
Peak memory 251476 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2900702240 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/spi
_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_mailbox.2900702240
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/25.spi_device_mailbox/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/25.spi_device_pass_addr_payload_swap.1803585516
Short name T292
Test name
Test status
Simulation time 6720011984 ps
CPU time 23.78 seconds
Started Aug 25 10:48:50 AM UTC 24
Finished Aug 25 10:49:15 AM UTC 24
Peak memory 261716 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1803585516 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_pass_addr_payload_swap.1803585516
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/25.spi_device_pass_addr_payload_swap/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/25.spi_device_pass_cmd_filtering.2972316760
Short name T580
Test name
Test status
Simulation time 661358388 ps
CPU time 5.99 seconds
Started Aug 25 10:48:50 AM UTC 24
Finished Aug 25 10:48:57 AM UTC 24
Peak memory 234924 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2972316760 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_08_24/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_pass_cmd_filtering.2972316760
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/25.spi_device_pass_cmd_filtering/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/25.spi_device_read_buffer_direct.3317232661
Short name T588
Test name
Test status
Simulation time 258010146 ps
CPU time 7.21 seconds
Started Aug 25 10:49:00 AM UTC 24
Finished Aug 25 10:49:08 AM UTC 24
Peak memory 231256 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3317232661 -assert nopostproc +UVM_TESTNAME=spi_device
_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_read_buffer_direct.3317232661
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/25.spi_device_read_buffer_direct/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/25.spi_device_stress_all.2042408037
Short name T314
Test name
Test status
Simulation time 19902584093 ps
CPU time 76.66 seconds
Started Aug 25 10:49:06 AM UTC 24
Finished Aug 25 10:50:25 AM UTC 24
Peak memory 235156 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2042408037 -assert nopostproc +UVM_
TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra
tch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_stress_all.2042408037
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/25.spi_device_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/25.spi_device_tpm_all.2021686641
Short name T579
Test name
Test status
Simulation time 648733831 ps
CPU time 8.63 seconds
Started Aug 25 10:48:45 AM UTC 24
Finished Aug 25 10:48:55 AM UTC 24
Peak memory 227424 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2021686641 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/spi
_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_all.2021686641
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/25.spi_device_tpm_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/25.spi_device_tpm_read_hw_reg.1646645529
Short name T587
Test name
Test status
Simulation time 3571761036 ps
CPU time 20.3 seconds
Started Aug 25 10:48:45 AM UTC 24
Finished Aug 25 10:49:07 AM UTC 24
Peak memory 227560 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1646645529 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_24/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_read_hw_reg.1646645529
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/25.spi_device_tpm_read_hw_reg/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/25.spi_device_tpm_rw.3908311593
Short name T578
Test name
Test status
Simulation time 188449981 ps
CPU time 2.92 seconds
Started Aug 25 10:48:48 AM UTC 24
Finished Aug 25 10:48:52 AM UTC 24
Peak memory 227424 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3908311593 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/spi_
device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_rw.3908311593
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/25.spi_device_tpm_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/25.spi_device_tpm_sts_read.217272798
Short name T577
Test name
Test status
Simulation time 19109122 ps
CPU time 1.12 seconds
Started Aug 25 10:48:47 AM UTC 24
Finished Aug 25 10:48:49 AM UTC 24
Peak memory 215868 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=217272798 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24
/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_sts_read.217272798
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/25.spi_device_tpm_sts_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/25.spi_device_upload.1880973348
Short name T582
Test name
Test status
Simulation time 602568339 ps
CPU time 3.66 seconds
Started Aug 25 10:48:54 AM UTC 24
Finished Aug 25 10:48:59 AM UTC 24
Peak memory 251348 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1880973348 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/spi_
device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_upload.1880973348
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/25.spi_device_upload/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/26.spi_device_alert_test.2053311150
Short name T597
Test name
Test status
Simulation time 15202077 ps
CPU time 1.12 seconds
Started Aug 25 10:49:21 AM UTC 24
Finished Aug 25 10:49:23 AM UTC 24
Peak memory 215744 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2053311150 -assert nopostproc +UVM_TES
TNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_
regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_alert_test.2053311150
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/26.spi_device_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/26.spi_device_cfg_cmd.717410944
Short name T555
Test name
Test status
Simulation time 8704132696 ps
CPU time 8.14 seconds
Started Aug 25 10:49:15 AM UTC 24
Finished Aug 25 10:49:24 AM UTC 24
Peak memory 235028 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=717410944 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/spi_
device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_cfg_cmd.717410944
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/26.spi_device_cfg_cmd/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/26.spi_device_csb_read.4264375947
Short name T590
Test name
Test status
Simulation time 67198492 ps
CPU time 1.1 seconds
Started Aug 25 10:49:08 AM UTC 24
Finished Aug 25 10:49:10 AM UTC 24
Peak memory 215544 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4264375947 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/sp
i_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_csb_read.4264375947
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/26.spi_device_csb_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/26.spi_device_flash_and_tpm.598005685
Short name T320
Test name
Test status
Simulation time 46856806425 ps
CPU time 300.94 seconds
Started Aug 25 10:49:19 AM UTC 24
Finished Aug 25 10:54:25 AM UTC 24
Peak memory 261844 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=598005685 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_2
4/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_and_tpm.598005685
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/26.spi_device_flash_and_tpm/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/26.spi_device_flash_and_tpm_min_idle.2909380457
Short name T656
Test name
Test status
Simulation time 18808257893 ps
CPU time 66.52 seconds
Started Aug 25 10:49:20 AM UTC 24
Finished Aug 25 10:50:28 AM UTC 24
Peak memory 251556 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2909380457 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_and_tpm_min_idle.2909380457
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/26.spi_device_flash_and_tpm_min_idle/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/26.spi_device_flash_mode.797975198
Short name T618
Test name
Test status
Simulation time 5072437453 ps
CPU time 29.92 seconds
Started Aug 25 10:49:16 AM UTC 24
Finished Aug 25 10:49:48 AM UTC 24
Peak memory 261732 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=797975198 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/s
pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_mode.797975198
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/26.spi_device_flash_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/26.spi_device_flash_mode_ignore_cmds.41414236
Short name T606
Test name
Test status
Simulation time 616526594 ps
CPU time 11.91 seconds
Started Aug 25 10:49:16 AM UTC 24
Finished Aug 25 10:49:29 AM UTC 24
Peak memory 234904 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=41414236 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_24/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_mode_ignore_cmds.41414236
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/26.spi_device_flash_mode_ignore_cmds/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/26.spi_device_intercept.1286351089
Short name T348
Test name
Test status
Simulation time 263694372 ps
CPU time 4.08 seconds
Started Aug 25 10:49:13 AM UTC 24
Finished Aug 25 10:49:18 AM UTC 24
Peak memory 234972 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1286351089 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/s
pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_intercept.1286351089
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/26.spi_device_intercept/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/26.spi_device_mailbox.192737248
Short name T628
Test name
Test status
Simulation time 20600913780 ps
CPU time 44.5 seconds
Started Aug 25 10:49:13 AM UTC 24
Finished Aug 25 10:49:59 AM UTC 24
Peak memory 245348 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=192737248 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/spi_
device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_mailbox.192737248
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/26.spi_device_mailbox/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/26.spi_device_pass_addr_payload_swap.526755568
Short name T232
Test name
Test status
Simulation time 373633557 ps
CPU time 5.37 seconds
Started Aug 25 10:49:12 AM UTC 24
Finished Aug 25 10:49:18 AM UTC 24
Peak memory 234900 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=526755568 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_24/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_pass_addr_payload_swap.526755568
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/26.spi_device_pass_addr_payload_swap/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/26.spi_device_pass_cmd_filtering.2805333676
Short name T596
Test name
Test status
Simulation time 906692773 ps
CPU time 7.55 seconds
Started Aug 25 10:49:12 AM UTC 24
Finished Aug 25 10:49:20 AM UTC 24
Peak memory 245232 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2805333676 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_08_24/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_pass_cmd_filtering.2805333676
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/26.spi_device_pass_cmd_filtering/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/26.spi_device_read_buffer_direct.2038639976
Short name T600
Test name
Test status
Simulation time 245254072 ps
CPU time 5.53 seconds
Started Aug 25 10:49:17 AM UTC 24
Finished Aug 25 10:49:24 AM UTC 24
Peak memory 231260 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2038639976 -assert nopostproc +UVM_TESTNAME=spi_device
_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_read_buffer_direct.2038639976
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/26.spi_device_read_buffer_direct/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/26.spi_device_stress_all.322517876
Short name T770
Test name
Test status
Simulation time 53339811452 ps
CPU time 184.74 seconds
Started Aug 25 10:49:21 AM UTC 24
Finished Aug 25 10:52:29 AM UTC 24
Peak memory 261716 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=322517876 -assert nopostproc +UVM_T
ESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_stress_all.322517876
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/26.spi_device_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/26.spi_device_tpm_all.2949592817
Short name T624
Test name
Test status
Simulation time 6991524156 ps
CPU time 46.22 seconds
Started Aug 25 10:49:08 AM UTC 24
Finished Aug 25 10:49:56 AM UTC 24
Peak memory 227676 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2949592817 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/spi
_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_all.2949592817
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/26.spi_device_tpm_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/26.spi_device_tpm_read_hw_reg.3461733185
Short name T603
Test name
Test status
Simulation time 15171291949 ps
CPU time 18.47 seconds
Started Aug 25 10:49:08 AM UTC 24
Finished Aug 25 10:49:28 AM UTC 24
Peak memory 227248 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3461733185 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_24/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_read_hw_reg.3461733185
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/26.spi_device_tpm_read_hw_reg/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/26.spi_device_tpm_rw.3107679403
Short name T593
Test name
Test status
Simulation time 339267530 ps
CPU time 1.83 seconds
Started Aug 25 10:49:11 AM UTC 24
Finished Aug 25 10:49:13 AM UTC 24
Peak memory 226404 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3107679403 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/spi_
device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_rw.3107679403
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/26.spi_device_tpm_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/26.spi_device_tpm_sts_read.3741183971
Short name T591
Test name
Test status
Simulation time 13803422 ps
CPU time 1.09 seconds
Started Aug 25 10:49:09 AM UTC 24
Finished Aug 25 10:49:12 AM UTC 24
Peak memory 215812 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3741183971 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_2
4/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_sts_read.3741183971
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/26.spi_device_tpm_sts_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/26.spi_device_upload.3748305347
Short name T595
Test name
Test status
Simulation time 722496682 ps
CPU time 4.95 seconds
Started Aug 25 10:49:14 AM UTC 24
Finished Aug 25 10:49:20 AM UTC 24
Peak memory 235092 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3748305347 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/spi_
device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_upload.3748305347
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/26.spi_device_upload/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/27.spi_device_alert_test.1319033282
Short name T613
Test name
Test status
Simulation time 15389902 ps
CPU time 1.11 seconds
Started Aug 25 10:49:39 AM UTC 24
Finished Aug 25 10:49:41 AM UTC 24
Peak memory 215744 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1319033282 -assert nopostproc +UVM_TES
TNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_
regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_alert_test.1319033282
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/27.spi_device_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/27.spi_device_cfg_cmd.1509317107
Short name T337
Test name
Test status
Simulation time 413459419 ps
CPU time 6.03 seconds
Started Aug 25 10:49:30 AM UTC 24
Finished Aug 25 10:49:37 AM UTC 24
Peak memory 234960 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1509317107 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/spi
_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_cfg_cmd.1509317107
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/27.spi_device_cfg_cmd/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/27.spi_device_csb_read.2887846062
Short name T598
Test name
Test status
Simulation time 52142905 ps
CPU time 1.19 seconds
Started Aug 25 10:49:21 AM UTC 24
Finished Aug 25 10:49:23 AM UTC 24
Peak memory 215580 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2887846062 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/sp
i_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_csb_read.2887846062
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/27.spi_device_csb_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/27.spi_device_flash_all.3286833264
Short name T609
Test name
Test status
Simulation time 24135658 ps
CPU time 1.17 seconds
Started Aug 25 10:49:35 AM UTC 24
Finished Aug 25 10:49:37 AM UTC 24
Peak memory 225744 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3286833264 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/s
pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_all.3286833264
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/27.spi_device_flash_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/27.spi_device_flash_and_tpm.373776068
Short name T282
Test name
Test status
Simulation time 6961907170 ps
CPU time 154.34 seconds
Started Aug 25 10:49:36 AM UTC 24
Finished Aug 25 10:52:14 AM UTC 24
Peak memory 276088 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=373776068 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_2
4/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_and_tpm.373776068
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/27.spi_device_flash_and_tpm/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/27.spi_device_flash_and_tpm_min_idle.3587141188
Short name T1004
Test name
Test status
Simulation time 59854226822 ps
CPU time 783.89 seconds
Started Aug 25 10:49:38 AM UTC 24
Finished Aug 25 11:02:54 AM UTC 24
Peak memory 278148 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3587141188 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_and_tpm_min_idle.3587141188
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/27.spi_device_flash_and_tpm_min_idle/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/27.spi_device_flash_mode.2028341825
Short name T617
Test name
Test status
Simulation time 1569014556 ps
CPU time 15.23 seconds
Started Aug 25 10:49:30 AM UTC 24
Finished Aug 25 10:49:46 AM UTC 24
Peak memory 245208 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2028341825 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/
spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_mode.2028341825
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/27.spi_device_flash_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/27.spi_device_flash_mode_ignore_cmds.2853782357
Short name T304
Test name
Test status
Simulation time 44129888606 ps
CPU time 409.91 seconds
Started Aug 25 10:49:30 AM UTC 24
Finished Aug 25 10:56:26 AM UTC 24
Peak memory 261712 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2853782357 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_mode_ignore_cmds.2853782357
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/27.spi_device_flash_mode_ignore_cmds/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/27.spi_device_intercept.939494244
Short name T610
Test name
Test status
Simulation time 3884016746 ps
CPU time 9.01 seconds
Started Aug 25 10:49:28 AM UTC 24
Finished Aug 25 10:49:38 AM UTC 24
Peak memory 234968 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=939494244 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/sp
i_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_intercept.939494244
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/27.spi_device_intercept/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/27.spi_device_mailbox.4233993114
Short name T627
Test name
Test status
Simulation time 1891755467 ps
CPU time 28.17 seconds
Started Aug 25 10:49:29 AM UTC 24
Finished Aug 25 10:49:58 AM UTC 24
Peak memory 245208 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4233993114 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/spi
_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_mailbox.4233993114
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/27.spi_device_mailbox/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/27.spi_device_pass_addr_payload_swap.4123468233
Short name T605
Test name
Test status
Simulation time 33263909 ps
CPU time 2.83 seconds
Started Aug 25 10:49:25 AM UTC 24
Finished Aug 25 10:49:29 AM UTC 24
Peak memory 245008 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4123468233 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_pass_addr_payload_swap.4123468233
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/27.spi_device_pass_addr_payload_swap/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/27.spi_device_pass_cmd_filtering.3347125030
Short name T604
Test name
Test status
Simulation time 49505976 ps
CPU time 2.97 seconds
Started Aug 25 10:49:25 AM UTC 24
Finished Aug 25 10:49:29 AM UTC 24
Peak memory 234632 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3347125030 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_08_24/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_pass_cmd_filtering.3347125030
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/27.spi_device_pass_cmd_filtering/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/27.spi_device_read_buffer_direct.2354395819
Short name T611
Test name
Test status
Simulation time 686218873 ps
CPU time 6.61 seconds
Started Aug 25 10:49:31 AM UTC 24
Finished Aug 25 10:49:39 AM UTC 24
Peak memory 231260 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2354395819 -assert nopostproc +UVM_TESTNAME=spi_device
_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_read_buffer_direct.2354395819
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/27.spi_device_read_buffer_direct/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/27.spi_device_stress_all.4076575486
Short name T172
Test name
Test status
Simulation time 96925939331 ps
CPU time 161.98 seconds
Started Aug 25 10:49:39 AM UTC 24
Finished Aug 25 10:52:24 AM UTC 24
Peak memory 267916 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4076575486 -assert nopostproc +UVM_
TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra
tch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_stress_all.4076575486
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/27.spi_device_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/27.spi_device_tpm_all.519822896
Short name T631
Test name
Test status
Simulation time 8397991732 ps
CPU time 37.65 seconds
Started Aug 25 10:49:24 AM UTC 24
Finished Aug 25 10:50:03 AM UTC 24
Peak memory 231772 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=519822896 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/spi_
device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_all.519822896
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/27.spi_device_tpm_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/27.spi_device_tpm_read_hw_reg.3712217403
Short name T616
Test name
Test status
Simulation time 5886396286 ps
CPU time 19.74 seconds
Started Aug 25 10:49:24 AM UTC 24
Finished Aug 25 10:49:45 AM UTC 24
Peak memory 227556 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3712217403 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_24/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_read_hw_reg.3712217403
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/27.spi_device_tpm_read_hw_reg/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/27.spi_device_tpm_rw.1577218211
Short name T602
Test name
Test status
Simulation time 14228461 ps
CPU time 1.09 seconds
Started Aug 25 10:49:25 AM UTC 24
Finished Aug 25 10:49:28 AM UTC 24
Peak memory 215744 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1577218211 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/spi_
device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_rw.1577218211
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/27.spi_device_tpm_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/27.spi_device_tpm_sts_read.2432420027
Short name T601
Test name
Test status
Simulation time 212458379 ps
CPU time 1.34 seconds
Started Aug 25 10:49:24 AM UTC 24
Finished Aug 25 10:49:27 AM UTC 24
Peak memory 215872 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2432420027 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_2
4/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_sts_read.2432420027
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/27.spi_device_tpm_sts_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/27.spi_device_upload.1678637251
Short name T368
Test name
Test status
Simulation time 1374138786 ps
CPU time 12.73 seconds
Started Aug 25 10:49:29 AM UTC 24
Finished Aug 25 10:49:43 AM UTC 24
Peak memory 234980 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1678637251 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/spi_
device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_upload.1678637251
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/27.spi_device_upload/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/28.spi_device_alert_test.2089349453
Short name T630
Test name
Test status
Simulation time 12346966 ps
CPU time 1.09 seconds
Started Aug 25 10:50:00 AM UTC 24
Finished Aug 25 10:50:02 AM UTC 24
Peak memory 215684 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2089349453 -assert nopostproc +UVM_TES
TNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_
regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_alert_test.2089349453
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/28.spi_device_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/28.spi_device_cfg_cmd.3706295421
Short name T625
Test name
Test status
Simulation time 140154822 ps
CPU time 6.51 seconds
Started Aug 25 10:49:50 AM UTC 24
Finished Aug 25 10:49:57 AM UTC 24
Peak memory 245208 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3706295421 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/spi
_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_cfg_cmd.3706295421
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/28.spi_device_cfg_cmd/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/28.spi_device_csb_read.1167058428
Short name T614
Test name
Test status
Simulation time 28173831 ps
CPU time 1.16 seconds
Started Aug 25 10:49:40 AM UTC 24
Finished Aug 25 10:49:42 AM UTC 24
Peak memory 215812 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1167058428 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/sp
i_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_csb_read.1167058428
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/28.spi_device_csb_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/28.spi_device_flash_all.4234096249
Short name T298
Test name
Test status
Simulation time 2105219268 ps
CPU time 76.83 seconds
Started Aug 25 10:49:57 AM UTC 24
Finished Aug 25 10:51:16 AM UTC 24
Peak memory 267804 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4234096249 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/s
pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_all.4234096249
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/28.spi_device_flash_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/28.spi_device_flash_and_tpm_min_idle.3809049377
Short name T287
Test name
Test status
Simulation time 92262456518 ps
CPU time 590.92 seconds
Started Aug 25 10:49:59 AM UTC 24
Finished Aug 25 10:59:58 AM UTC 24
Peak memory 267980 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3809049377 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_and_tpm_min_idle.3809049377
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/28.spi_device_flash_and_tpm_min_idle/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/28.spi_device_flash_mode.4130938720
Short name T638
Test name
Test status
Simulation time 2875958262 ps
CPU time 16.21 seconds
Started Aug 25 10:49:52 AM UTC 24
Finished Aug 25 10:50:09 AM UTC 24
Peak memory 245348 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4130938720 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/
spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_mode.4130938720
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/28.spi_device_flash_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/28.spi_device_flash_mode_ignore_cmds.2042887614
Short name T687
Test name
Test status
Simulation time 52403152859 ps
CPU time 64.68 seconds
Started Aug 25 10:49:52 AM UTC 24
Finished Aug 25 10:50:58 AM UTC 24
Peak memory 251472 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2042887614 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_mode_ignore_cmds.2042887614
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/28.spi_device_flash_mode_ignore_cmds/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/28.spi_device_intercept.2197012438
Short name T367
Test name
Test status
Simulation time 884421112 ps
CPU time 13.82 seconds
Started Aug 25 10:49:47 AM UTC 24
Finished Aug 25 10:50:02 AM UTC 24
Peak memory 245212 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2197012438 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/s
pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_intercept.2197012438
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/28.spi_device_intercept/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/28.spi_device_mailbox.3737368517
Short name T647
Test name
Test status
Simulation time 3472063759 ps
CPU time 28.26 seconds
Started Aug 25 10:49:48 AM UTC 24
Finished Aug 25 10:50:18 AM UTC 24
Peak memory 245288 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3737368517 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/spi
_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_mailbox.3737368517
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/28.spi_device_mailbox/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/28.spi_device_pass_addr_payload_swap.616352606
Short name T622
Test name
Test status
Simulation time 183838352 ps
CPU time 3.58 seconds
Started Aug 25 10:49:46 AM UTC 24
Finished Aug 25 10:49:51 AM UTC 24
Peak memory 245200 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=616352606 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_24/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_pass_addr_payload_swap.616352606
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/28.spi_device_pass_addr_payload_swap/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/28.spi_device_pass_cmd_filtering.1430781763
Short name T621
Test name
Test status
Simulation time 127700595 ps
CPU time 3.24 seconds
Started Aug 25 10:49:46 AM UTC 24
Finished Aug 25 10:49:50 AM UTC 24
Peak memory 245228 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1430781763 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_08_24/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_pass_cmd_filtering.1430781763
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/28.spi_device_pass_cmd_filtering/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/28.spi_device_read_buffer_direct.867727740
Short name T634
Test name
Test status
Simulation time 440580107 ps
CPU time 8.86 seconds
Started Aug 25 10:49:55 AM UTC 24
Finished Aug 25 10:50:05 AM UTC 24
Peak memory 231268 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=867727740 -assert nopostproc +UVM_TESTNAME=spi_device_
base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_read_buffer_direct.867727740
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/28.spi_device_read_buffer_direct/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/28.spi_device_stress_all.857454932
Short name T321
Test name
Test status
Simulation time 49465091684 ps
CPU time 334.32 seconds
Started Aug 25 10:49:59 AM UTC 24
Finished Aug 25 10:55:39 AM UTC 24
Peak memory 261776 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=857454932 -assert nopostproc +UVM_T
ESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_stress_all.857454932
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/28.spi_device_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/28.spi_device_tpm_all.877178309
Short name T662
Test name
Test status
Simulation time 4478812324 ps
CPU time 48.73 seconds
Started Aug 25 10:49:42 AM UTC 24
Finished Aug 25 10:50:32 AM UTC 24
Peak memory 233756 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=877178309 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/spi_
device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_all.877178309
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/28.spi_device_tpm_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/28.spi_device_tpm_read_hw_reg.4099521822
Short name T626
Test name
Test status
Simulation time 10916724944 ps
CPU time 16.28 seconds
Started Aug 25 10:49:41 AM UTC 24
Finished Aug 25 10:49:58 AM UTC 24
Peak memory 227560 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4099521822 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_24/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_read_hw_reg.4099521822
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/28.spi_device_tpm_read_hw_reg/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/28.spi_device_tpm_rw.3922132485
Short name T619
Test name
Test status
Simulation time 457546969 ps
CPU time 3.39 seconds
Started Aug 25 10:49:44 AM UTC 24
Finished Aug 25 10:49:48 AM UTC 24
Peak memory 227424 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3922132485 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/spi_
device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_rw.3922132485
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/28.spi_device_tpm_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/28.spi_device_tpm_sts_read.2508371951
Short name T615
Test name
Test status
Simulation time 27679852 ps
CPU time 1.18 seconds
Started Aug 25 10:49:43 AM UTC 24
Finished Aug 25 10:49:45 AM UTC 24
Peak memory 215872 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2508371951 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_2
4/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_sts_read.2508371951
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/28.spi_device_tpm_sts_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/28.spi_device_upload.1590235448
Short name T642
Test name
Test status
Simulation time 43579615256 ps
CPU time 22.33 seconds
Started Aug 25 10:49:50 AM UTC 24
Finished Aug 25 10:50:13 AM UTC 24
Peak memory 245332 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1590235448 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/spi_
device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_upload.1590235448
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/28.spi_device_upload/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/29.spi_device_alert_test.4231777693
Short name T644
Test name
Test status
Simulation time 33489072 ps
CPU time 1.1 seconds
Started Aug 25 10:50:15 AM UTC 24
Finished Aug 25 10:50:17 AM UTC 24
Peak memory 215684 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4231777693 -assert nopostproc +UVM_TES
TNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_
regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_alert_test.4231777693
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/29.spi_device_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/29.spi_device_cfg_cmd.1355213705
Short name T641
Test name
Test status
Simulation time 108665658 ps
CPU time 3.16 seconds
Started Aug 25 10:50:07 AM UTC 24
Finished Aug 25 10:50:12 AM UTC 24
Peak memory 245148 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1355213705 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/spi
_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_cfg_cmd.1355213705
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/29.spi_device_cfg_cmd/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/29.spi_device_csb_read.4087372111
Short name T633
Test name
Test status
Simulation time 22562040 ps
CPU time 1.16 seconds
Started Aug 25 10:50:01 AM UTC 24
Finished Aug 25 10:50:04 AM UTC 24
Peak memory 215812 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4087372111 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/sp
i_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_csb_read.4087372111
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/29.spi_device_csb_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/29.spi_device_flash_all.1729358377
Short name T290
Test name
Test status
Simulation time 12283796057 ps
CPU time 144.2 seconds
Started Aug 25 10:50:11 AM UTC 24
Finished Aug 25 10:52:38 AM UTC 24
Peak memory 261708 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1729358377 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/s
pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_all.1729358377
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/29.spi_device_flash_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/29.spi_device_flash_and_tpm.4128746316
Short name T274
Test name
Test status
Simulation time 13183598761 ps
CPU time 106.79 seconds
Started Aug 25 10:50:13 AM UTC 24
Finished Aug 25 10:52:02 AM UTC 24
Peak memory 261840 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4128746316 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
24/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_and_tpm.4128746316
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/29.spi_device_flash_and_tpm/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/29.spi_device_flash_and_tpm_min_idle.2108827210
Short name T752
Test name
Test status
Simulation time 9113389759 ps
CPU time 117.86 seconds
Started Aug 25 10:50:15 AM UTC 24
Finished Aug 25 10:52:15 AM UTC 24
Peak memory 284272 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2108827210 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_and_tpm_min_idle.2108827210
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/29.spi_device_flash_and_tpm_min_idle/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/29.spi_device_flash_mode.3371514880
Short name T705
Test name
Test status
Simulation time 2794832750 ps
CPU time 67.39 seconds
Started Aug 25 10:50:11 AM UTC 24
Finished Aug 25 10:51:20 AM UTC 24
Peak memory 247452 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3371514880 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/
spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_mode.3371514880
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/29.spi_device_flash_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/29.spi_device_flash_mode_ignore_cmds.3152035330
Short name T716
Test name
Test status
Simulation time 26588913882 ps
CPU time 77.57 seconds
Started Aug 25 10:50:11 AM UTC 24
Finished Aug 25 10:51:31 AM UTC 24
Peak memory 261676 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3152035330 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_mode_ignore_cmds.3152035330
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/29.spi_device_flash_mode_ignore_cmds/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/29.spi_device_intercept.2494711209
Short name T650
Test name
Test status
Simulation time 6331203472 ps
CPU time 13.51 seconds
Started Aug 25 10:50:06 AM UTC 24
Finished Aug 25 10:50:21 AM UTC 24
Peak memory 235040 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2494711209 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/s
pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_intercept.2494711209
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/29.spi_device_intercept/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/29.spi_device_mailbox.6458367
Short name T648
Test name
Test status
Simulation time 1852529548 ps
CPU time 10.17 seconds
Started Aug 25 10:50:07 AM UTC 24
Finished Aug 25 10:50:19 AM UTC 24
Peak memory 244648 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=6458367 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/spi_de
vice_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_mailbox.6458367
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/29.spi_device_mailbox/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/29.spi_device_pass_addr_payload_swap.3016447878
Short name T702
Test name
Test status
Simulation time 54237043871 ps
CPU time 69.69 seconds
Started Aug 25 10:50:05 AM UTC 24
Finished Aug 25 10:51:17 AM UTC 24
Peak memory 235112 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3016447878 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_pass_addr_payload_swap.3016447878
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/29.spi_device_pass_addr_payload_swap/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/29.spi_device_pass_cmd_filtering.1411285014
Short name T363
Test name
Test status
Simulation time 62687634 ps
CPU time 3.31 seconds
Started Aug 25 10:50:05 AM UTC 24
Finished Aug 25 10:50:09 AM UTC 24
Peak memory 245224 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1411285014 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_08_24/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_pass_cmd_filtering.1411285014
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/29.spi_device_pass_cmd_filtering/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/29.spi_device_read_buffer_direct.20593759
Short name T646
Test name
Test status
Simulation time 122486172 ps
CPU time 5.86 seconds
Started Aug 25 10:50:11 AM UTC 24
Finished Aug 25 10:50:18 AM UTC 24
Peak memory 233612 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=20593759 -assert nopostproc +UVM_TESTNAME=spi_device_b
ase_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_read_buffer_direct.20593759
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/29.spi_device_read_buffer_direct/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/29.spi_device_stress_all.4178854077
Short name T171
Test name
Test status
Simulation time 7869988123 ps
CPU time 72.96 seconds
Started Aug 25 10:50:15 AM UTC 24
Finished Aug 25 10:51:30 AM UTC 24
Peak memory 245404 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4178854077 -assert nopostproc +UVM_
TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra
tch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_stress_all.4178854077
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/29.spi_device_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/29.spi_device_tpm_all.634631728
Short name T643
Test name
Test status
Simulation time 544594043 ps
CPU time 8.57 seconds
Started Aug 25 10:50:04 AM UTC 24
Finished Aug 25 10:50:14 AM UTC 24
Peak memory 227112 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=634631728 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/spi_
device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_all.634631728
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/29.spi_device_tpm_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/29.spi_device_tpm_read_hw_reg.584416414
Short name T640
Test name
Test status
Simulation time 4203518921 ps
CPU time 7.2 seconds
Started Aug 25 10:50:02 AM UTC 24
Finished Aug 25 10:50:10 AM UTC 24
Peak memory 227648 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=584416414 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08
_24/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_read_hw_reg.584416414
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/29.spi_device_tpm_read_hw_reg/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/29.spi_device_tpm_rw.1032622099
Short name T637
Test name
Test status
Simulation time 39048957 ps
CPU time 1.29 seconds
Started Aug 25 10:50:04 AM UTC 24
Finished Aug 25 10:50:07 AM UTC 24
Peak memory 215900 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1032622099 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/spi_
device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_rw.1032622099
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/29.spi_device_tpm_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/29.spi_device_tpm_sts_read.1097595381
Short name T636
Test name
Test status
Simulation time 106211027 ps
CPU time 1.24 seconds
Started Aug 25 10:50:04 AM UTC 24
Finished Aug 25 10:50:07 AM UTC 24
Peak memory 215600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1097595381 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_2
4/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_sts_read.1097595381
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/29.spi_device_tpm_sts_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/29.spi_device_upload.2816904173
Short name T663
Test name
Test status
Simulation time 912611211 ps
CPU time 23.35 seconds
Started Aug 25 10:50:07 AM UTC 24
Finished Aug 25 10:50:32 AM UTC 24
Peak memory 245332 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2816904173 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/spi_
device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_upload.2816904173
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/29.spi_device_upload/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/3.spi_device_alert_test.131014699
Short name T411
Test name
Test status
Simulation time 15542533 ps
CPU time 1.01 seconds
Started Aug 25 10:42:17 AM UTC 24
Finished Aug 25 10:42:20 AM UTC 24
Peak memory 215804 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=131014699 -assert nopostproc +UVM_TEST
NAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_alert_test.131014699
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/3.spi_device_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/3.spi_device_cfg_cmd.2490951538
Short name T91
Test name
Test status
Simulation time 2455353288 ps
CPU time 4.74 seconds
Started Aug 25 10:42:15 AM UTC 24
Finished Aug 25 10:42:21 AM UTC 24
Peak memory 235080 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2490951538 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/spi
_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_cfg_cmd.2490951538
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/3.spi_device_cfg_cmd/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/3.spi_device_csb_read.250067269
Short name T164
Test name
Test status
Simulation time 74658831 ps
CPU time 1.19 seconds
Started Aug 25 10:42:09 AM UTC 24
Finished Aug 25 10:42:11 AM UTC 24
Peak memory 215804 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=250067269 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/spi
_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_csb_read.250067269
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/3.spi_device_csb_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/3.spi_device_flash_and_tpm.2779929497
Short name T410
Test name
Test status
Simulation time 122957666 ps
CPU time 1.13 seconds
Started Aug 25 10:42:16 AM UTC 24
Finished Aug 25 10:42:18 AM UTC 24
Peak memory 228032 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2779929497 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
24/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_and_tpm.2779929497
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/3.spi_device_flash_and_tpm/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/3.spi_device_flash_and_tpm_min_idle.1699599669
Short name T180
Test name
Test status
Simulation time 26443090583 ps
CPU time 227.2 seconds
Started Aug 25 10:42:17 AM UTC 24
Finished Aug 25 10:46:08 AM UTC 24
Peak memory 278124 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1699599669 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_and_tpm_min_idle.1699599669
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/3.spi_device_flash_and_tpm_min_idle/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/3.spi_device_flash_mode.3607094129
Short name T422
Test name
Test status
Simulation time 4933808993 ps
CPU time 30.12 seconds
Started Aug 25 10:42:15 AM UTC 24
Finished Aug 25 10:42:46 AM UTC 24
Peak memory 245328 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3607094129 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/
spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_mode.3607094129
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/3.spi_device_flash_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/3.spi_device_flash_mode_ignore_cmds.1959481657
Short name T89
Test name
Test status
Simulation time 3323259752 ps
CPU time 29.34 seconds
Started Aug 25 10:42:16 AM UTC 24
Finished Aug 25 10:42:47 AM UTC 24
Peak memory 249356 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1959481657 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_mode_ignore_cmds.1959481657
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/3.spi_device_flash_mode_ignore_cmds/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/3.spi_device_intercept.428383048
Short name T189
Test name
Test status
Simulation time 3260799339 ps
CPU time 30.17 seconds
Started Aug 25 10:42:13 AM UTC 24
Finished Aug 25 10:42:44 AM UTC 24
Peak memory 245348 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=428383048 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/sp
i_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_intercept.428383048
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/3.spi_device_intercept/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/3.spi_device_mailbox.3092726747
Short name T188
Test name
Test status
Simulation time 1776979137 ps
CPU time 17.23 seconds
Started Aug 25 10:42:14 AM UTC 24
Finished Aug 25 10:42:32 AM UTC 24
Peak memory 234908 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3092726747 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/spi
_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_mailbox.3092726747
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/3.spi_device_mailbox/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/3.spi_device_pass_addr_payload_swap.917438488
Short name T53
Test name
Test status
Simulation time 743888059 ps
CPU time 11.32 seconds
Started Aug 25 10:42:13 AM UTC 24
Finished Aug 25 10:42:25 AM UTC 24
Peak memory 234968 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=917438488 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_24/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_pass_addr_payload_swap.917438488
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/3.spi_device_pass_addr_payload_swap/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/3.spi_device_pass_cmd_filtering.1329245368
Short name T54
Test name
Test status
Simulation time 7587989797 ps
CPU time 18.92 seconds
Started Aug 25 10:42:12 AM UTC 24
Finished Aug 25 10:42:33 AM UTC 24
Peak memory 235092 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1329245368 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_08_24/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_pass_cmd_filtering.1329245368
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/3.spi_device_pass_cmd_filtering/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/3.spi_device_read_buffer_direct.400710189
Short name T88
Test name
Test status
Simulation time 428003111 ps
CPU time 5.09 seconds
Started Aug 25 10:42:16 AM UTC 24
Finished Aug 25 10:42:22 AM UTC 24
Peak memory 231292 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=400710189 -assert nopostproc +UVM_TESTNAME=spi_device_
base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_read_buffer_direct.400710189
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/3.spi_device_read_buffer_direct/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/3.spi_device_sec_cm.2721602577
Short name T30
Test name
Test status
Simulation time 116065322 ps
CPU time 1.76 seconds
Started Aug 25 10:42:17 AM UTC 24
Finished Aug 25 10:42:20 AM UTC 24
Peak memory 257976 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2721602577 -assert nopostproc +UVM_TEST
NAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_sec_cm.2721602577
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/3.spi_device_sec_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/3.spi_device_stress_all.2144586834
Short name T97
Test name
Test status
Simulation time 59692799 ps
CPU time 1.51 seconds
Started Aug 25 10:42:17 AM UTC 24
Finished Aug 25 10:42:20 AM UTC 24
Peak memory 215708 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2144586834 -assert nopostproc +UVM_
TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra
tch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_stress_all.2144586834
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/3.spi_device_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/3.spi_device_tpm_all.1575200738
Short name T395
Test name
Test status
Simulation time 16643511386 ps
CPU time 61.56 seconds
Started Aug 25 10:42:12 AM UTC 24
Finished Aug 25 10:43:16 AM UTC 24
Peak memory 231728 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1575200738 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/spi
_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_all.1575200738
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/3.spi_device_tpm_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/3.spi_device_tpm_read_hw_reg.1524460167
Short name T426
Test name
Test status
Simulation time 7134437818 ps
CPU time 37.06 seconds
Started Aug 25 10:42:12 AM UTC 24
Finished Aug 25 10:42:51 AM UTC 24
Peak memory 227580 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1524460167 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_24/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_read_hw_reg.1524460167
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/3.spi_device_tpm_read_hw_reg/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/3.spi_device_tpm_rw.4246225778
Short name T46
Test name
Test status
Simulation time 143646805 ps
CPU time 2.17 seconds
Started Aug 25 10:42:12 AM UTC 24
Finished Aug 25 10:42:16 AM UTC 24
Peak memory 227440 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4246225778 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/spi_
device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_rw.4246225778
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/3.spi_device_tpm_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/3.spi_device_tpm_sts_read.3957651195
Short name T71
Test name
Test status
Simulation time 430098701 ps
CPU time 1.17 seconds
Started Aug 25 10:42:12 AM UTC 24
Finished Aug 25 10:42:15 AM UTC 24
Peak memory 215868 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3957651195 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_2
4/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_sts_read.3957651195
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/3.spi_device_tpm_sts_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/3.spi_device_upload.1940245956
Short name T113
Test name
Test status
Simulation time 2123933681 ps
CPU time 9.77 seconds
Started Aug 25 10:42:14 AM UTC 24
Finished Aug 25 10:42:25 AM UTC 24
Peak memory 245224 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1940245956 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/spi_
device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_upload.1940245956
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/3.spi_device_upload/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/30.spi_device_alert_test.2742008819
Short name T660
Test name
Test status
Simulation time 13764195 ps
CPU time 1.1 seconds
Started Aug 25 10:50:30 AM UTC 24
Finished Aug 25 10:50:32 AM UTC 24
Peak memory 215684 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2742008819 -assert nopostproc +UVM_TES
TNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_
regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_alert_test.2742008819
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/30.spi_device_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/30.spi_device_cfg_cmd.2010066438
Short name T659
Test name
Test status
Simulation time 564011471 ps
CPU time 8.91 seconds
Started Aug 25 10:50:22 AM UTC 24
Finished Aug 25 10:50:32 AM UTC 24
Peak memory 234976 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2010066438 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/spi
_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_cfg_cmd.2010066438
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/30.spi_device_cfg_cmd/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/30.spi_device_csb_read.1136968223
Short name T645
Test name
Test status
Simulation time 46642977 ps
CPU time 1.12 seconds
Started Aug 25 10:50:15 AM UTC 24
Finished Aug 25 10:50:17 AM UTC 24
Peak memory 215812 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1136968223 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/sp
i_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_csb_read.1136968223
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/30.spi_device_csb_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/30.spi_device_flash_all.3212819215
Short name T658
Test name
Test status
Simulation time 12837670 ps
CPU time 1.14 seconds
Started Aug 25 10:50:26 AM UTC 24
Finished Aug 25 10:50:28 AM UTC 24
Peak memory 225744 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3212819215 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/s
pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_all.3212819215
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/30.spi_device_flash_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/30.spi_device_flash_and_tpm.2880829760
Short name T805
Test name
Test status
Simulation time 19784206172 ps
CPU time 145.18 seconds
Started Aug 25 10:50:27 AM UTC 24
Finished Aug 25 10:52:56 AM UTC 24
Peak memory 276100 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2880829760 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
24/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_and_tpm.2880829760
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/30.spi_device_flash_and_tpm/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/30.spi_device_flash_and_tpm_min_idle.840264327
Short name T696
Test name
Test status
Simulation time 4214554973 ps
CPU time 40.49 seconds
Started Aug 25 10:50:27 AM UTC 24
Finished Aug 25 10:51:10 AM UTC 24
Peak memory 261772 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=840264327 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_24/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_and_tpm_min_idle.840264327
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/30.spi_device_flash_and_tpm_min_idle/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/30.spi_device_flash_mode.4259198115
Short name T673
Test name
Test status
Simulation time 2233322193 ps
CPU time 19.77 seconds
Started Aug 25 10:50:22 AM UTC 24
Finished Aug 25 10:50:43 AM UTC 24
Peak memory 234960 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4259198115 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/
spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_mode.4259198115
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/30.spi_device_flash_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/30.spi_device_flash_mode_ignore_cmds.3004307424
Short name T356
Test name
Test status
Simulation time 6336224765 ps
CPU time 30.1 seconds
Started Aug 25 10:50:24 AM UTC 24
Finished Aug 25 10:50:56 AM UTC 24
Peak memory 247396 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3004307424 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_mode_ignore_cmds.3004307424
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/30.spi_device_flash_mode_ignore_cmds/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/30.spi_device_intercept.4240406532
Short name T657
Test name
Test status
Simulation time 313201680 ps
CPU time 7.65 seconds
Started Aug 25 10:50:19 AM UTC 24
Finished Aug 25 10:50:28 AM UTC 24
Peak memory 234856 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4240406532 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/s
pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_intercept.4240406532
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/30.spi_device_intercept/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/30.spi_device_mailbox.1767665959
Short name T655
Test name
Test status
Simulation time 153128867 ps
CPU time 4.08 seconds
Started Aug 25 10:50:22 AM UTC 24
Finished Aug 25 10:50:27 AM UTC 24
Peak memory 229544 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1767665959 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/spi
_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_mailbox.1767665959
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/30.spi_device_mailbox/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/30.spi_device_pass_addr_payload_swap.2402676703
Short name T664
Test name
Test status
Simulation time 1650146256 ps
CPU time 13.68 seconds
Started Aug 25 10:50:19 AM UTC 24
Finished Aug 25 10:50:34 AM UTC 24
Peak memory 251348 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2402676703 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_pass_addr_payload_swap.2402676703
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/30.spi_device_pass_addr_payload_swap/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/30.spi_device_pass_cmd_filtering.1848484823
Short name T652
Test name
Test status
Simulation time 119789216 ps
CPU time 3.62 seconds
Started Aug 25 10:50:19 AM UTC 24
Finished Aug 25 10:50:24 AM UTC 24
Peak memory 245252 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1848484823 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_08_24/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_pass_cmd_filtering.1848484823
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/30.spi_device_pass_cmd_filtering/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/30.spi_device_read_buffer_direct.1888724372
Short name T653
Test name
Test status
Simulation time 479659129 ps
CPU time 8.23 seconds
Started Aug 25 10:50:25 AM UTC 24
Finished Aug 25 10:50:34 AM UTC 24
Peak memory 233624 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1888724372 -assert nopostproc +UVM_TESTNAME=spi_device
_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_read_buffer_direct.1888724372
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/30.spi_device_read_buffer_direct/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/30.spi_device_stress_all.2598904423
Short name T300
Test name
Test status
Simulation time 23251311687 ps
CPU time 232.57 seconds
Started Aug 25 10:50:29 AM UTC 24
Finished Aug 25 10:54:26 AM UTC 24
Peak memory 280324 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2598904423 -assert nopostproc +UVM_
TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra
tch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_stress_all.2598904423
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/30.spi_device_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/30.spi_device_tpm_all.4074244486
Short name T686
Test name
Test status
Simulation time 6328305865 ps
CPU time 39.98 seconds
Started Aug 25 10:50:16 AM UTC 24
Finished Aug 25 10:50:57 AM UTC 24
Peak memory 231724 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4074244486 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/spi
_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_all.4074244486
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/30.spi_device_tpm_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/30.spi_device_tpm_read_hw_reg.4016818166
Short name T654
Test name
Test status
Simulation time 8939079258 ps
CPU time 8.69 seconds
Started Aug 25 10:50:16 AM UTC 24
Finished Aug 25 10:50:26 AM UTC 24
Peak memory 227696 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4016818166 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_24/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_read_hw_reg.4016818166
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/30.spi_device_tpm_read_hw_reg/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/30.spi_device_tpm_rw.1599024362
Short name T651
Test name
Test status
Simulation time 103334598 ps
CPU time 1.65 seconds
Started Aug 25 10:50:18 AM UTC 24
Finished Aug 25 10:50:21 AM UTC 24
Peak memory 215868 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1599024362 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/spi_
device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_rw.1599024362
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/30.spi_device_tpm_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/30.spi_device_tpm_sts_read.1698958695
Short name T649
Test name
Test status
Simulation time 37775149 ps
CPU time 1.26 seconds
Started Aug 25 10:50:18 AM UTC 24
Finished Aug 25 10:50:21 AM UTC 24
Peak memory 215872 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1698958695 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_2
4/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_sts_read.1698958695
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/30.spi_device_tpm_sts_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/30.spi_device_upload.2296067952
Short name T672
Test name
Test status
Simulation time 12317190307 ps
CPU time 19.4 seconds
Started Aug 25 10:50:22 AM UTC 24
Finished Aug 25 10:50:42 AM UTC 24
Peak memory 245348 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2296067952 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/spi_
device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_upload.2296067952
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/30.spi_device_upload/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/31.spi_device_alert_test.3848186296
Short name T676
Test name
Test status
Simulation time 24066936 ps
CPU time 1.09 seconds
Started Aug 25 10:50:44 AM UTC 24
Finished Aug 25 10:50:46 AM UTC 24
Peak memory 215684 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3848186296 -assert nopostproc +UVM_TES
TNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_
regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_alert_test.3848186296
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/31.spi_device_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/31.spi_device_cfg_cmd.229684986
Short name T671
Test name
Test status
Simulation time 65638110 ps
CPU time 4.29 seconds
Started Aug 25 10:50:37 AM UTC 24
Finished Aug 25 10:50:42 AM UTC 24
Peak memory 245156 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=229684986 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/spi_
device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_cfg_cmd.229684986
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/31.spi_device_cfg_cmd/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/31.spi_device_csb_read.1126143469
Short name T661
Test name
Test status
Simulation time 78654709 ps
CPU time 1.18 seconds
Started Aug 25 10:50:30 AM UTC 24
Finished Aug 25 10:50:32 AM UTC 24
Peak memory 215460 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1126143469 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/sp
i_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_csb_read.1126143469
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/31.spi_device_csb_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/31.spi_device_flash_all.376033925
Short name T733
Test name
Test status
Simulation time 9039126539 ps
CPU time 66.05 seconds
Started Aug 25 10:50:40 AM UTC 24
Finished Aug 25 10:51:48 AM UTC 24
Peak memory 261728 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=376033925 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/sp
i_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_all.376033925
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/31.spi_device_flash_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/31.spi_device_flash_and_tpm.825807362
Short name T792
Test name
Test status
Simulation time 28182121521 ps
CPU time 122.48 seconds
Started Aug 25 10:50:41 AM UTC 24
Finished Aug 25 10:52:46 AM UTC 24
Peak memory 267848 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=825807362 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_2
4/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_and_tpm.825807362
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/31.spi_device_flash_and_tpm/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/31.spi_device_flash_mode.3017871797
Short name T670
Test name
Test status
Simulation time 202238896 ps
CPU time 4.08 seconds
Started Aug 25 10:50:37 AM UTC 24
Finished Aug 25 10:50:42 AM UTC 24
Peak memory 235032 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3017871797 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/
spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_mode.3017871797
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/31.spi_device_flash_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/31.spi_device_flash_mode_ignore_cmds.480392656
Short name T690
Test name
Test status
Simulation time 15557625683 ps
CPU time 21.82 seconds
Started Aug 25 10:50:39 AM UTC 24
Finished Aug 25 10:51:02 AM UTC 24
Peak memory 247384 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=480392656 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_24/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_mode_ignore_cmds.480392656
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/31.spi_device_flash_mode_ignore_cmds/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/31.spi_device_intercept.4112784007
Short name T669
Test name
Test status
Simulation time 870968967 ps
CPU time 4.3 seconds
Started Aug 25 10:50:35 AM UTC 24
Finished Aug 25 10:50:41 AM UTC 24
Peak memory 245228 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4112784007 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/s
pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_intercept.4112784007
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/31.spi_device_intercept/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/31.spi_device_mailbox.2627096609
Short name T674
Test name
Test status
Simulation time 449853184 ps
CPU time 6.91 seconds
Started Aug 25 10:50:35 AM UTC 24
Finished Aug 25 10:50:43 AM UTC 24
Peak memory 245284 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2627096609 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/spi
_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_mailbox.2627096609
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/31.spi_device_mailbox/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/31.spi_device_pass_addr_payload_swap.1232852021
Short name T308
Test name
Test status
Simulation time 12267143053 ps
CPU time 36.23 seconds
Started Aug 25 10:50:34 AM UTC 24
Finished Aug 25 10:51:12 AM UTC 24
Peak memory 247332 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1232852021 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_pass_addr_payload_swap.1232852021
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/31.spi_device_pass_addr_payload_swap/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/31.spi_device_pass_cmd_filtering.3926602054
Short name T667
Test name
Test status
Simulation time 144588897 ps
CPU time 3.39 seconds
Started Aug 25 10:50:33 AM UTC 24
Finished Aug 25 10:50:38 AM UTC 24
Peak memory 234924 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3926602054 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_08_24/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_pass_cmd_filtering.3926602054
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/31.spi_device_pass_cmd_filtering/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/31.spi_device_read_buffer_direct.477284368
Short name T675
Test name
Test status
Simulation time 87240426 ps
CPU time 5.02 seconds
Started Aug 25 10:50:39 AM UTC 24
Finished Aug 25 10:50:45 AM UTC 24
Peak memory 231328 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=477284368 -assert nopostproc +UVM_TESTNAME=spi_device_
base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_read_buffer_direct.477284368
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/31.spi_device_read_buffer_direct/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/31.spi_device_stress_all.2230742463
Short name T678
Test name
Test status
Simulation time 44477936 ps
CPU time 1.49 seconds
Started Aug 25 10:50:43 AM UTC 24
Finished Aug 25 10:50:46 AM UTC 24
Peak memory 215760 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2230742463 -assert nopostproc +UVM_
TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra
tch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_stress_all.2230742463
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/31.spi_device_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/31.spi_device_tpm_all.3127232268
Short name T704
Test name
Test status
Simulation time 5167876283 ps
CPU time 45.66 seconds
Started Aug 25 10:50:33 AM UTC 24
Finished Aug 25 10:51:20 AM UTC 24
Peak memory 227612 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3127232268 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/spi
_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_all.3127232268
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/31.spi_device_tpm_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/31.spi_device_tpm_read_hw_reg.700045961
Short name T679
Test name
Test status
Simulation time 1651072550 ps
CPU time 13.06 seconds
Started Aug 25 10:50:33 AM UTC 24
Finished Aug 25 10:50:47 AM UTC 24
Peak memory 227516 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=700045961 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08
_24/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_read_hw_reg.700045961
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/31.spi_device_tpm_read_hw_reg/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/31.spi_device_tpm_rw.1534193065
Short name T665
Test name
Test status
Simulation time 37055946 ps
CPU time 1.12 seconds
Started Aug 25 10:50:33 AM UTC 24
Finished Aug 25 10:50:35 AM UTC 24
Peak memory 215868 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1534193065 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/spi_
device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_rw.1534193065
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/31.spi_device_tpm_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/31.spi_device_tpm_sts_read.2168832416
Short name T666
Test name
Test status
Simulation time 43215631 ps
CPU time 1.36 seconds
Started Aug 25 10:50:33 AM UTC 24
Finished Aug 25 10:50:35 AM UTC 24
Peak memory 215872 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2168832416 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_2
4/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_sts_read.2168832416
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/31.spi_device_tpm_sts_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/31.spi_device_upload.1260373227
Short name T238
Test name
Test status
Simulation time 3285264497 ps
CPU time 11.27 seconds
Started Aug 25 10:50:37 AM UTC 24
Finished Aug 25 10:50:49 AM UTC 24
Peak memory 245412 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1260373227 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/spi_
device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_upload.1260373227
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/31.spi_device_upload/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/32.spi_device_alert_test.2589515667
Short name T693
Test name
Test status
Simulation time 25043046 ps
CPU time 1.15 seconds
Started Aug 25 10:51:04 AM UTC 24
Finished Aug 25 10:51:06 AM UTC 24
Peak memory 215688 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2589515667 -assert nopostproc +UVM_TES
TNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_
regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_alert_test.2589515667
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/32.spi_device_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/32.spi_device_cfg_cmd.1286550269
Short name T691
Test name
Test status
Simulation time 336174004 ps
CPU time 7.45 seconds
Started Aug 25 10:50:54 AM UTC 24
Finished Aug 25 10:51:02 AM UTC 24
Peak memory 234960 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1286550269 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/spi
_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_cfg_cmd.1286550269
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/32.spi_device_cfg_cmd/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/32.spi_device_csb_read.3033168884
Short name T677
Test name
Test status
Simulation time 17370129 ps
CPU time 1.18 seconds
Started Aug 25 10:50:44 AM UTC 24
Finished Aug 25 10:50:46 AM UTC 24
Peak memory 215812 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3033168884 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/sp
i_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_csb_read.3033168884
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/32.spi_device_csb_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/32.spi_device_flash_all.1261784646
Short name T751
Test name
Test status
Simulation time 13101965701 ps
CPU time 73 seconds
Started Aug 25 10:50:58 AM UTC 24
Finished Aug 25 10:52:13 AM UTC 24
Peak memory 249452 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1261784646 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/s
pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_all.1261784646
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/32.spi_device_flash_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/32.spi_device_flash_and_tpm.482124854
Short name T912
Test name
Test status
Simulation time 63142544733 ps
CPU time 239.22 seconds
Started Aug 25 10:50:59 AM UTC 24
Finished Aug 25 10:55:03 AM UTC 24
Peak memory 267920 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=482124854 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_2
4/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_and_tpm.482124854
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/32.spi_device_flash_and_tpm/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/32.spi_device_flash_and_tpm_min_idle.491955159
Short name T315
Test name
Test status
Simulation time 3602750668 ps
CPU time 108.42 seconds
Started Aug 25 10:51:01 AM UTC 24
Finished Aug 25 10:52:52 AM UTC 24
Peak memory 278220 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=491955159 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_24/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_and_tpm_min_idle.491955159
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/32.spi_device_flash_and_tpm_min_idle/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/32.spi_device_flash_mode.1617887787
Short name T723
Test name
Test status
Simulation time 26555937391 ps
CPU time 44.44 seconds
Started Aug 25 10:50:54 AM UTC 24
Finished Aug 25 10:51:40 AM UTC 24
Peak memory 251480 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1617887787 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/
spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_mode.1617887787
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/32.spi_device_flash_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/32.spi_device_flash_mode_ignore_cmds.563603721
Short name T974
Test name
Test status
Simulation time 29223064158 ps
CPU time 330.4 seconds
Started Aug 25 10:50:57 AM UTC 24
Finished Aug 25 10:56:32 AM UTC 24
Peak memory 267864 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=563603721 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_24/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_mode_ignore_cmds.563603721
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/32.spi_device_flash_mode_ignore_cmds/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/32.spi_device_intercept.2288254102
Short name T685
Test name
Test status
Simulation time 774196053 ps
CPU time 4.98 seconds
Started Aug 25 10:50:50 AM UTC 24
Finished Aug 25 10:50:56 AM UTC 24
Peak memory 234908 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2288254102 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/s
pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_intercept.2288254102
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/32.spi_device_intercept/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/32.spi_device_mailbox.303132728
Short name T689
Test name
Test status
Simulation time 1038016923 ps
CPU time 10.53 seconds
Started Aug 25 10:50:50 AM UTC 24
Finished Aug 25 10:51:02 AM UTC 24
Peak memory 234960 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=303132728 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/spi_
device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_mailbox.303132728
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/32.spi_device_mailbox/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/32.spi_device_pass_addr_payload_swap.701785505
Short name T682
Test name
Test status
Simulation time 178436991 ps
CPU time 3.04 seconds
Started Aug 25 10:50:48 AM UTC 24
Finished Aug 25 10:50:52 AM UTC 24
Peak memory 234612 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=701785505 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_24/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_pass_addr_payload_swap.701785505
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/32.spi_device_pass_addr_payload_swap/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/32.spi_device_pass_cmd_filtering.2506395373
Short name T688
Test name
Test status
Simulation time 1518687846 ps
CPU time 11.72 seconds
Started Aug 25 10:50:47 AM UTC 24
Finished Aug 25 10:51:00 AM UTC 24
Peak memory 234988 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2506395373 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_08_24/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_pass_cmd_filtering.2506395373
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/32.spi_device_pass_cmd_filtering/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/32.spi_device_read_buffer_direct.1282490263
Short name T692
Test name
Test status
Simulation time 984316984 ps
CPU time 6.47 seconds
Started Aug 25 10:50:57 AM UTC 24
Finished Aug 25 10:51:05 AM UTC 24
Peak memory 233324 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1282490263 -assert nopostproc +UVM_TESTNAME=spi_device
_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_read_buffer_direct.1282490263
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/32.spi_device_read_buffer_direct/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/32.spi_device_stress_all.10494897
Short name T724
Test name
Test status
Simulation time 1588328581 ps
CPU time 32.54 seconds
Started Aug 25 10:51:04 AM UTC 24
Finished Aug 25 10:51:38 AM UTC 24
Peak memory 249512 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=10494897 -assert nopostproc +UVM_TE
STNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_stress_all.10494897
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/32.spi_device_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/32.spi_device_tpm_all.1728474199
Short name T722
Test name
Test status
Simulation time 25758167869 ps
CPU time 52.07 seconds
Started Aug 25 10:50:46 AM UTC 24
Finished Aug 25 10:51:40 AM UTC 24
Peak memory 227692 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1728474199 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/spi
_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_all.1728474199
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/32.spi_device_tpm_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/32.spi_device_tpm_read_hw_reg.1360573695
Short name T680
Test name
Test status
Simulation time 735262998 ps
CPU time 3.26 seconds
Started Aug 25 10:50:45 AM UTC 24
Finished Aug 25 10:50:49 AM UTC 24
Peak memory 227336 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1360573695 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_24/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_read_hw_reg.1360573695
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/32.spi_device_tpm_read_hw_reg/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/32.spi_device_tpm_rw.782371654
Short name T683
Test name
Test status
Simulation time 272150348 ps
CPU time 4.93 seconds
Started Aug 25 10:50:47 AM UTC 24
Finished Aug 25 10:50:53 AM UTC 24
Peak memory 227484 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=782371654 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/spi_d
evice_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_rw.782371654
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/32.spi_device_tpm_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/32.spi_device_tpm_sts_read.4080735215
Short name T681
Test name
Test status
Simulation time 106402994 ps
CPU time 1.64 seconds
Started Aug 25 10:50:47 AM UTC 24
Finished Aug 25 10:50:50 AM UTC 24
Peak memory 215872 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4080735215 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_2
4/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_sts_read.4080735215
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/32.spi_device_tpm_sts_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/32.spi_device_upload.4227348621
Short name T346
Test name
Test status
Simulation time 1144056548 ps
CPU time 16.59 seconds
Started Aug 25 10:50:51 AM UTC 24
Finished Aug 25 10:51:08 AM UTC 24
Peak memory 247252 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4227348621 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/spi_
device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_upload.4227348621
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/32.spi_device_upload/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/33.spi_device_alert_test.2976336573
Short name T703
Test name
Test status
Simulation time 14587890 ps
CPU time 1.12 seconds
Started Aug 25 10:51:17 AM UTC 24
Finished Aug 25 10:51:20 AM UTC 24
Peak memory 215744 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2976336573 -assert nopostproc +UVM_TES
TNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_
regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_alert_test.2976336573
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/33.spi_device_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/33.spi_device_cfg_cmd.914433681
Short name T709
Test name
Test status
Simulation time 4177006160 ps
CPU time 12.82 seconds
Started Aug 25 10:51:11 AM UTC 24
Finished Aug 25 10:51:25 AM UTC 24
Peak memory 235088 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=914433681 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/spi_
device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_cfg_cmd.914433681
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/33.spi_device_cfg_cmd/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/33.spi_device_csb_read.3283456109
Short name T694
Test name
Test status
Simulation time 19608322 ps
CPU time 1.21 seconds
Started Aug 25 10:51:04 AM UTC 24
Finished Aug 25 10:51:06 AM UTC 24
Peak memory 215812 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3283456109 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/sp
i_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_csb_read.3283456109
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/33.spi_device_csb_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/33.spi_device_flash_all.3959391513
Short name T734
Test name
Test status
Simulation time 4521516088 ps
CPU time 37.11 seconds
Started Aug 25 10:51:15 AM UTC 24
Finished Aug 25 10:51:54 AM UTC 24
Peak memory 261720 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3959391513 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/s
pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_all.3959391513
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/33.spi_device_flash_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/33.spi_device_flash_and_tpm.3462987814
Short name T302
Test name
Test status
Simulation time 11435159377 ps
CPU time 119.03 seconds
Started Aug 25 10:51:16 AM UTC 24
Finished Aug 25 10:53:18 AM UTC 24
Peak memory 261752 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3462987814 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
24/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_and_tpm.3462987814
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/33.spi_device_flash_and_tpm/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/33.spi_device_flash_and_tpm_min_idle.2568000204
Short name T764
Test name
Test status
Simulation time 2034512755 ps
CPU time 67.29 seconds
Started Aug 25 10:51:16 AM UTC 24
Finished Aug 25 10:52:25 AM UTC 24
Peak memory 263708 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2568000204 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_and_tpm_min_idle.2568000204
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/33.spi_device_flash_and_tpm_min_idle/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/33.spi_device_flash_mode_ignore_cmds.965892011
Short name T701
Test name
Test status
Simulation time 15213715 ps
CPU time 1.16 seconds
Started Aug 25 10:51:13 AM UTC 24
Finished Aug 25 10:51:15 AM UTC 24
Peak memory 225740 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=965892011 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_24/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_mode_ignore_cmds.965892011
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/33.spi_device_flash_mode_ignore_cmds/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/33.spi_device_intercept.1575489439
Short name T699
Test name
Test status
Simulation time 163891458 ps
CPU time 3.95 seconds
Started Aug 25 10:51:09 AM UTC 24
Finished Aug 25 10:51:14 AM UTC 24
Peak memory 245216 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1575489439 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/s
pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_intercept.1575489439
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/33.spi_device_intercept/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/33.spi_device_mailbox.2046328796
Short name T700
Test name
Test status
Simulation time 108762296 ps
CPU time 4.65 seconds
Started Aug 25 10:51:09 AM UTC 24
Finished Aug 25 10:51:15 AM UTC 24
Peak memory 245260 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2046328796 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/spi
_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_mailbox.2046328796
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/33.spi_device_mailbox/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/33.spi_device_pass_addr_payload_swap.855539056
Short name T698
Test name
Test status
Simulation time 32020616 ps
CPU time 2.97 seconds
Started Aug 25 10:51:08 AM UTC 24
Finished Aug 25 10:51:12 AM UTC 24
Peak memory 233420 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=855539056 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_24/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_pass_addr_payload_swap.855539056
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/33.spi_device_pass_addr_payload_swap/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/33.spi_device_pass_cmd_filtering.3198730199
Short name T717
Test name
Test status
Simulation time 3847514976 ps
CPU time 23.08 seconds
Started Aug 25 10:51:07 AM UTC 24
Finished Aug 25 10:51:32 AM UTC 24
Peak memory 234992 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3198730199 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_08_24/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_pass_cmd_filtering.3198730199
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/33.spi_device_pass_cmd_filtering/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/33.spi_device_read_buffer_direct.4117081989
Short name T707
Test name
Test status
Simulation time 127816027 ps
CPU time 5.72 seconds
Started Aug 25 10:51:15 AM UTC 24
Finished Aug 25 10:51:22 AM UTC 24
Peak memory 231260 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4117081989 -assert nopostproc +UVM_TESTNAME=spi_device
_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_read_buffer_direct.4117081989
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/33.spi_device_read_buffer_direct/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/33.spi_device_stress_all.3787934158
Short name T962
Test name
Test status
Simulation time 90597596737 ps
CPU time 301.3 seconds
Started Aug 25 10:51:17 AM UTC 24
Finished Aug 25 10:56:24 AM UTC 24
Peak memory 263824 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3787934158 -assert nopostproc +UVM_
TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra
tch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_stress_all.3787934158
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/33.spi_device_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/33.spi_device_tpm_all.2357902731
Short name T684
Test name
Test status
Simulation time 3405560520 ps
CPU time 33.44 seconds
Started Aug 25 10:51:05 AM UTC 24
Finished Aug 25 10:51:40 AM UTC 24
Peak memory 227552 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2357902731 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/spi
_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_all.2357902731
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/33.spi_device_tpm_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/33.spi_device_tpm_read_hw_reg.2781304959
Short name T718
Test name
Test status
Simulation time 13240234922 ps
CPU time 26.81 seconds
Started Aug 25 10:51:05 AM UTC 24
Finished Aug 25 10:51:33 AM UTC 24
Peak memory 227700 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2781304959 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_24/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_read_hw_reg.2781304959
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/33.spi_device_tpm_read_hw_reg/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/33.spi_device_tpm_rw.3126543246
Short name T697
Test name
Test status
Simulation time 82513875 ps
CPU time 1.95 seconds
Started Aug 25 10:51:07 AM UTC 24
Finished Aug 25 10:51:10 AM UTC 24
Peak memory 226700 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3126543246 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/spi_
device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_rw.3126543246
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/33.spi_device_tpm_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/33.spi_device_tpm_sts_read.3567403822
Short name T695
Test name
Test status
Simulation time 83483586 ps
CPU time 1.1 seconds
Started Aug 25 10:51:06 AM UTC 24
Finished Aug 25 10:51:08 AM UTC 24
Peak memory 215872 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3567403822 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_2
4/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_sts_read.3567403822
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/33.spi_device_tpm_sts_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/33.spi_device_upload.2113534421
Short name T364
Test name
Test status
Simulation time 12633086289 ps
CPU time 39.77 seconds
Started Aug 25 10:51:11 AM UTC 24
Finished Aug 25 10:51:52 AM UTC 24
Peak memory 251492 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2113534421 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/spi_
device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_upload.2113534421
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/33.spi_device_upload/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/34.spi_device_alert_test.1342987353
Short name T725
Test name
Test status
Simulation time 13251043 ps
CPU time 1.08 seconds
Started Aug 25 10:51:35 AM UTC 24
Finished Aug 25 10:51:38 AM UTC 24
Peak memory 215668 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1342987353 -assert nopostproc +UVM_TES
TNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_
regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_alert_test.1342987353
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/34.spi_device_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/34.spi_device_cfg_cmd.4066758044
Short name T720
Test name
Test status
Simulation time 156060584 ps
CPU time 4.45 seconds
Started Aug 25 10:51:29 AM UTC 24
Finished Aug 25 10:51:34 AM UTC 24
Peak memory 245140 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4066758044 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/spi
_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_cfg_cmd.4066758044
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/34.spi_device_cfg_cmd/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/34.spi_device_csb_read.2921180263
Short name T708
Test name
Test status
Simulation time 43175019 ps
CPU time 1.18 seconds
Started Aug 25 10:51:21 AM UTC 24
Finished Aug 25 10:51:23 AM UTC 24
Peak memory 215520 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2921180263 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/sp
i_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_csb_read.2921180263
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/34.spi_device_csb_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/34.spi_device_flash_all.2904508451
Short name T721
Test name
Test status
Simulation time 26827385 ps
CPU time 1.33 seconds
Started Aug 25 10:51:31 AM UTC 24
Finished Aug 25 10:51:35 AM UTC 24
Peak memory 225668 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2904508451 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/s
pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_all.2904508451
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/34.spi_device_flash_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/34.spi_device_flash_and_tpm.749055341
Short name T1006
Test name
Test status
Simulation time 40927881588 ps
CPU time 733.55 seconds
Started Aug 25 10:51:34 AM UTC 24
Finished Aug 25 11:03:59 AM UTC 24
Peak memory 284296 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=749055341 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_2
4/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_and_tpm.749055341
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/34.spi_device_flash_and_tpm/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/34.spi_device_flash_and_tpm_min_idle.2635824829
Short name T829
Test name
Test status
Simulation time 11576827559 ps
CPU time 106.92 seconds
Started Aug 25 10:51:34 AM UTC 24
Finished Aug 25 10:53:24 AM UTC 24
Peak memory 251532 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2635824829 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_and_tpm_min_idle.2635824829
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/34.spi_device_flash_and_tpm_min_idle/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/34.spi_device_flash_mode.1617667118
Short name T739
Test name
Test status
Simulation time 6716163977 ps
CPU time 26.65 seconds
Started Aug 25 10:51:30 AM UTC 24
Finished Aug 25 10:51:58 AM UTC 24
Peak memory 261720 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1617667118 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/
spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_mode.1617667118
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/34.spi_device_flash_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/34.spi_device_flash_mode_ignore_cmds.206934702
Short name T991
Test name
Test status
Simulation time 30868572064 ps
CPU time 402.53 seconds
Started Aug 25 10:51:30 AM UTC 24
Finished Aug 25 10:58:19 AM UTC 24
Peak memory 284244 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=206934702 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_24/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_mode_ignore_cmds.206934702
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/34.spi_device_flash_mode_ignore_cmds/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/34.spi_device_intercept.2164500092
Short name T715
Test name
Test status
Simulation time 300676886 ps
CPU time 3.22 seconds
Started Aug 25 10:51:25 AM UTC 24
Finished Aug 25 10:51:30 AM UTC 24
Peak memory 244956 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2164500092 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/s
pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_intercept.2164500092
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/34.spi_device_intercept/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/34.spi_device_mailbox.4064576058
Short name T756
Test name
Test status
Simulation time 7532049434 ps
CPU time 51.1 seconds
Started Aug 25 10:51:26 AM UTC 24
Finished Aug 25 10:52:19 AM UTC 24
Peak memory 245460 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4064576058 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/spi
_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_mailbox.4064576058
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/34.spi_device_mailbox/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/34.spi_device_pass_addr_payload_swap.4213745511
Short name T289
Test name
Test status
Simulation time 2799265509 ps
CPU time 11.85 seconds
Started Aug 25 10:51:25 AM UTC 24
Finished Aug 25 10:51:39 AM UTC 24
Peak memory 235156 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4213745511 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_pass_addr_payload_swap.4213745511
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/34.spi_device_pass_addr_payload_swap/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/34.spi_device_pass_cmd_filtering.4062076995
Short name T719
Test name
Test status
Simulation time 1287500231 ps
CPU time 7.94 seconds
Started Aug 25 10:51:24 AM UTC 24
Finished Aug 25 10:51:33 AM UTC 24
Peak memory 234992 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4062076995 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_08_24/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_pass_cmd_filtering.4062076995
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/34.spi_device_pass_cmd_filtering/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/34.spi_device_read_buffer_direct.3851876624
Short name T738
Test name
Test status
Simulation time 5943062551 ps
CPU time 23.44 seconds
Started Aug 25 10:51:31 AM UTC 24
Finished Aug 25 10:51:57 AM UTC 24
Peak memory 231372 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3851876624 -assert nopostproc +UVM_TESTNAME=spi_device
_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_read_buffer_direct.3851876624
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/34.spi_device_read_buffer_direct/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/34.spi_device_stress_all.110654898
Short name T319
Test name
Test status
Simulation time 79328652844 ps
CPU time 263.35 seconds
Started Aug 25 10:51:35 AM UTC 24
Finished Aug 25 10:56:04 AM UTC 24
Peak memory 263812 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=110654898 -assert nopostproc +UVM_T
ESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_stress_all.110654898
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/34.spi_device_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/34.spi_device_tpm_all.1736419399
Short name T713
Test name
Test status
Simulation time 1046902495 ps
CPU time 5.62 seconds
Started Aug 25 10:51:22 AM UTC 24
Finished Aug 25 10:51:28 AM UTC 24
Peak memory 227484 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1736419399 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/spi
_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_all.1736419399
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/34.spi_device_tpm_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/34.spi_device_tpm_read_hw_reg.1001855453
Short name T714
Test name
Test status
Simulation time 2226118539 ps
CPU time 5.95 seconds
Started Aug 25 10:51:22 AM UTC 24
Finished Aug 25 10:51:29 AM UTC 24
Peak memory 227612 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1001855453 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_24/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_read_hw_reg.1001855453
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/34.spi_device_tpm_read_hw_reg/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/34.spi_device_tpm_rw.1474438785
Short name T711
Test name
Test status
Simulation time 72726717 ps
CPU time 1.55 seconds
Started Aug 25 10:51:23 AM UTC 24
Finished Aug 25 10:51:26 AM UTC 24
Peak memory 215696 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1474438785 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/spi_
device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_rw.1474438785
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/34.spi_device_tpm_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/34.spi_device_tpm_sts_read.518636598
Short name T710
Test name
Test status
Simulation time 214602524 ps
CPU time 1.2 seconds
Started Aug 25 10:51:23 AM UTC 24
Finished Aug 25 10:51:25 AM UTC 24
Peak memory 215868 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=518636598 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24
/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_sts_read.518636598
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/34.spi_device_tpm_sts_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/34.spi_device_upload.75429381
Short name T341
Test name
Test status
Simulation time 6779308807 ps
CPU time 24.69 seconds
Started Aug 25 10:51:26 AM UTC 24
Finished Aug 25 10:51:53 AM UTC 24
Peak memory 251432 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=75429381 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/spi_de
vice_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_upload.75429381
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/34.spi_device_upload/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/35.spi_device_alert_test.3598073809
Short name T736
Test name
Test status
Simulation time 45767779 ps
CPU time 1.12 seconds
Started Aug 25 10:51:53 AM UTC 24
Finished Aug 25 10:51:56 AM UTC 24
Peak memory 215684 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3598073809 -assert nopostproc +UVM_TES
TNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_
regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_alert_test.3598073809
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/35.spi_device_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/35.spi_device_cfg_cmd.994476034
Short name T732
Test name
Test status
Simulation time 1192891065 ps
CPU time 4.49 seconds
Started Aug 25 10:51:42 AM UTC 24
Finished Aug 25 10:51:48 AM UTC 24
Peak memory 234964 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=994476034 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/spi_
device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_cfg_cmd.994476034
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/35.spi_device_cfg_cmd/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/35.spi_device_csb_read.4116676589
Short name T727
Test name
Test status
Simulation time 64641002 ps
CPU time 1.15 seconds
Started Aug 25 10:51:35 AM UTC 24
Finished Aug 25 10:51:38 AM UTC 24
Peak memory 215808 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4116676589 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/sp
i_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_csb_read.4116676589
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/35.spi_device_csb_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/35.spi_device_flash_all.2940839557
Short name T992
Test name
Test status
Simulation time 210377148022 ps
CPU time 424.94 seconds
Started Aug 25 10:51:47 AM UTC 24
Finished Aug 25 10:58:59 AM UTC 24
Peak memory 278172 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2940839557 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/s
pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_all.2940839557
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/35.spi_device_flash_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/35.spi_device_flash_and_tpm.1375219695
Short name T273
Test name
Test status
Simulation time 202881732967 ps
CPU time 592.04 seconds
Started Aug 25 10:51:49 AM UTC 24
Finished Aug 25 11:01:50 AM UTC 24
Peak memory 267892 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1375219695 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
24/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_and_tpm.1375219695
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/35.spi_device_flash_and_tpm/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/35.spi_device_flash_and_tpm_min_idle.1662622542
Short name T926
Test name
Test status
Simulation time 32807983689 ps
CPU time 226.01 seconds
Started Aug 25 10:51:49 AM UTC 24
Finished Aug 25 10:55:39 AM UTC 24
Peak memory 261724 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1662622542 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_and_tpm_min_idle.1662622542
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/35.spi_device_flash_and_tpm_min_idle/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/35.spi_device_flash_mode_ignore_cmds.2063634387
Short name T731
Test name
Test status
Simulation time 24653003 ps
CPU time 1.17 seconds
Started Aug 25 10:51:45 AM UTC 24
Finished Aug 25 10:51:47 AM UTC 24
Peak memory 225680 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2063634387 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_mode_ignore_cmds.2063634387
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/35.spi_device_flash_mode_ignore_cmds/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/35.spi_device_intercept.3762434253
Short name T730
Test name
Test status
Simulation time 69855479 ps
CPU time 4.87 seconds
Started Aug 25 10:51:40 AM UTC 24
Finished Aug 25 10:51:46 AM UTC 24
Peak memory 234912 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3762434253 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/s
pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_intercept.3762434253
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/35.spi_device_intercept/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/35.spi_device_mailbox.3331555616
Short name T735
Test name
Test status
Simulation time 4607562028 ps
CPU time 11.33 seconds
Started Aug 25 10:51:42 AM UTC 24
Finished Aug 25 10:51:55 AM UTC 24
Peak memory 245288 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3331555616 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/spi
_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_mailbox.3331555616
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/35.spi_device_mailbox/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/35.spi_device_pass_addr_payload_swap.2605771559
Short name T344
Test name
Test status
Simulation time 6335205286 ps
CPU time 38.79 seconds
Started Aug 25 10:51:40 AM UTC 24
Finished Aug 25 10:52:21 AM UTC 24
Peak memory 245328 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2605771559 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_pass_addr_payload_swap.2605771559
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/35.spi_device_pass_addr_payload_swap/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/35.spi_device_pass_cmd_filtering.3138531225
Short name T746
Test name
Test status
Simulation time 9713135687 ps
CPU time 22.13 seconds
Started Aug 25 10:51:40 AM UTC 24
Finished Aug 25 10:52:04 AM UTC 24
Peak memory 247404 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3138531225 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_08_24/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_pass_cmd_filtering.3138531225
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/35.spi_device_pass_cmd_filtering/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/35.spi_device_read_buffer_direct.1498395988
Short name T744
Test name
Test status
Simulation time 1221539010 ps
CPU time 16.77 seconds
Started Aug 25 10:51:45 AM UTC 24
Finished Aug 25 10:52:03 AM UTC 24
Peak memory 231448 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1498395988 -assert nopostproc +UVM_TESTNAME=spi_device
_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_read_buffer_direct.1498395988
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/35.spi_device_read_buffer_direct/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/35.spi_device_stress_all.2367593358
Short name T993
Test name
Test status
Simulation time 34698107738 ps
CPU time 431.94 seconds
Started Aug 25 10:51:49 AM UTC 24
Finished Aug 25 10:59:08 AM UTC 24
Peak memory 267948 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2367593358 -assert nopostproc +UVM_
TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra
tch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_stress_all.2367593358
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/35.spi_device_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/35.spi_device_tpm_all.2874859220
Short name T796
Test name
Test status
Simulation time 8620650858 ps
CPU time 66.56 seconds
Started Aug 25 10:51:40 AM UTC 24
Finished Aug 25 10:52:48 AM UTC 24
Peak memory 227584 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2874859220 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/spi
_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_all.2874859220
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/35.spi_device_tpm_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/35.spi_device_tpm_read_hw_reg.3957957416
Short name T726
Test name
Test status
Simulation time 33175159 ps
CPU time 1.05 seconds
Started Aug 25 10:51:35 AM UTC 24
Finished Aug 25 10:51:38 AM UTC 24
Peak memory 215800 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3957957416 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_24/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_read_hw_reg.3957957416
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/35.spi_device_tpm_read_hw_reg/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/35.spi_device_tpm_rw.1874682412
Short name T729
Test name
Test status
Simulation time 90518973 ps
CPU time 1.32 seconds
Started Aug 25 10:51:40 AM UTC 24
Finished Aug 25 10:51:43 AM UTC 24
Peak memory 215868 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1874682412 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/spi_
device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_rw.1874682412
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/35.spi_device_tpm_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/35.spi_device_tpm_sts_read.942686036
Short name T728
Test name
Test status
Simulation time 14168662 ps
CPU time 1.08 seconds
Started Aug 25 10:51:40 AM UTC 24
Finished Aug 25 10:51:42 AM UTC 24
Peak memory 215808 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=942686036 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24
/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_sts_read.942686036
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/35.spi_device_tpm_sts_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/35.spi_device_upload.3338940516
Short name T743
Test name
Test status
Simulation time 814080432 ps
CPU time 16.84 seconds
Started Aug 25 10:51:42 AM UTC 24
Finished Aug 25 10:52:00 AM UTC 24
Peak memory 245144 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3338940516 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/spi_
device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_upload.3338940516
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/35.spi_device_upload/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/36.spi_device_alert_test.3712869711
Short name T748
Test name
Test status
Simulation time 17640206 ps
CPU time 1.08 seconds
Started Aug 25 10:52:07 AM UTC 24
Finished Aug 25 10:52:09 AM UTC 24
Peak memory 215684 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3712869711 -assert nopostproc +UVM_TES
TNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_
regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_alert_test.3712869711
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/36.spi_device_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/36.spi_device_cfg_cmd.2699602666
Short name T776
Test name
Test status
Simulation time 4310293980 ps
CPU time 31.21 seconds
Started Aug 25 10:52:01 AM UTC 24
Finished Aug 25 10:52:34 AM UTC 24
Peak memory 235036 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2699602666 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/spi
_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_cfg_cmd.2699602666
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/36.spi_device_cfg_cmd/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/36.spi_device_csb_read.620705095
Short name T737
Test name
Test status
Simulation time 20708601 ps
CPU time 1.23 seconds
Started Aug 25 10:51:53 AM UTC 24
Finished Aug 25 10:51:56 AM UTC 24
Peak memory 215460 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=620705095 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/spi
_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_csb_read.620705095
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/36.spi_device_csb_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/36.spi_device_flash_all.436917239
Short name T286
Test name
Test status
Simulation time 19620929334 ps
CPU time 217.05 seconds
Started Aug 25 10:52:04 AM UTC 24
Finished Aug 25 10:55:44 AM UTC 24
Peak memory 261716 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=436917239 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/sp
i_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_all.436917239
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/36.spi_device_flash_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/36.spi_device_flash_mode.2681003602
Short name T763
Test name
Test status
Simulation time 4501341255 ps
CPU time 22.15 seconds
Started Aug 25 10:52:01 AM UTC 24
Finished Aug 25 10:52:25 AM UTC 24
Peak memory 261736 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2681003602 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/
spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_mode.2681003602
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/36.spi_device_flash_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/36.spi_device_flash_mode_ignore_cmds.2497236645
Short name T747
Test name
Test status
Simulation time 14797953 ps
CPU time 1.15 seconds
Started Aug 25 10:52:02 AM UTC 24
Finished Aug 25 10:52:05 AM UTC 24
Peak memory 225680 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2497236645 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_mode_ignore_cmds.2497236645
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/36.spi_device_flash_mode_ignore_cmds/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/36.spi_device_intercept.1876975606
Short name T353
Test name
Test status
Simulation time 9269448430 ps
CPU time 36.63 seconds
Started Aug 25 10:52:01 AM UTC 24
Finished Aug 25 10:52:39 AM UTC 24
Peak memory 235100 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1876975606 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/s
pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_intercept.1876975606
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/36.spi_device_intercept/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/36.spi_device_mailbox.4120763608
Short name T766
Test name
Test status
Simulation time 1088420441 ps
CPU time 25.1 seconds
Started Aug 25 10:52:01 AM UTC 24
Finished Aug 25 10:52:28 AM UTC 24
Peak memory 249300 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4120763608 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/spi
_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_mailbox.4120763608
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/36.spi_device_mailbox/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/36.spi_device_pass_addr_payload_swap.938164516
Short name T808
Test name
Test status
Simulation time 129436533111 ps
CPU time 59.62 seconds
Started Aug 25 10:51:59 AM UTC 24
Finished Aug 25 10:53:00 AM UTC 24
Peak memory 245276 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=938164516 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_24/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_pass_addr_payload_swap.938164516
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/36.spi_device_pass_addr_payload_swap/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/36.spi_device_pass_cmd_filtering.2098127503
Short name T745
Test name
Test status
Simulation time 41941718 ps
CPU time 3.4 seconds
Started Aug 25 10:51:59 AM UTC 24
Finished Aug 25 10:52:03 AM UTC 24
Peak memory 245356 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2098127503 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_08_24/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_pass_cmd_filtering.2098127503
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/36.spi_device_pass_cmd_filtering/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/36.spi_device_read_buffer_direct.1146840674
Short name T749
Test name
Test status
Simulation time 250301338 ps
CPU time 6.91 seconds
Started Aug 25 10:52:04 AM UTC 24
Finished Aug 25 10:52:12 AM UTC 24
Peak memory 233576 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1146840674 -assert nopostproc +UVM_TESTNAME=spi_device
_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_read_buffer_direct.1146840674
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/36.spi_device_read_buffer_direct/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/36.spi_device_stress_all.4078757883
Short name T975
Test name
Test status
Simulation time 100259676569 ps
CPU time 267.21 seconds
Started Aug 25 10:52:06 AM UTC 24
Finished Aug 25 10:56:38 AM UTC 24
Peak memory 261772 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4078757883 -assert nopostproc +UVM_
TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra
tch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_stress_all.4078757883
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/36.spi_device_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/36.spi_device_tpm_all.3253332374
Short name T754
Test name
Test status
Simulation time 2681862114 ps
CPU time 18.85 seconds
Started Aug 25 10:51:55 AM UTC 24
Finished Aug 25 10:52:16 AM UTC 24
Peak memory 227616 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3253332374 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/spi
_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_all.3253332374
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/36.spi_device_tpm_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/36.spi_device_tpm_read_hw_reg.2539511061
Short name T740
Test name
Test status
Simulation time 267200160 ps
CPU time 2.85 seconds
Started Aug 25 10:51:55 AM UTC 24
Finished Aug 25 10:51:59 AM UTC 24
Peak memory 227332 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2539511061 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_24/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_read_hw_reg.2539511061
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/36.spi_device_tpm_read_hw_reg/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/36.spi_device_tpm_rw.437829605
Short name T741
Test name
Test status
Simulation time 82222003 ps
CPU time 1.17 seconds
Started Aug 25 10:51:58 AM UTC 24
Finished Aug 25 10:52:00 AM UTC 24
Peak memory 215864 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=437829605 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/spi_d
evice_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_rw.437829605
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/36.spi_device_tpm_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/36.spi_device_tpm_sts_read.4006477448
Short name T742
Test name
Test status
Simulation time 208881795 ps
CPU time 1.45 seconds
Started Aug 25 10:51:58 AM UTC 24
Finished Aug 25 10:52:00 AM UTC 24
Peak memory 215872 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4006477448 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_2
4/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_sts_read.4006477448
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/36.spi_device_tpm_sts_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/36.spi_device_upload.405477271
Short name T235
Test name
Test status
Simulation time 108931435 ps
CPU time 4 seconds
Started Aug 25 10:52:01 AM UTC 24
Finished Aug 25 10:52:06 AM UTC 24
Peak memory 245152 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=405477271 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/spi_d
evice_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_upload.405477271
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/36.spi_device_upload/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/37.spi_device_alert_test.2975291661
Short name T765
Test name
Test status
Simulation time 19468532 ps
CPU time 1.17 seconds
Started Aug 25 10:52:25 AM UTC 24
Finished Aug 25 10:52:27 AM UTC 24
Peak memory 215744 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2975291661 -assert nopostproc +UVM_TES
TNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_
regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_alert_test.2975291661
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/37.spi_device_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/37.spi_device_cfg_cmd.2231359153
Short name T762
Test name
Test status
Simulation time 727885925 ps
CPU time 3.2 seconds
Started Aug 25 10:52:20 AM UTC 24
Finished Aug 25 10:52:25 AM UTC 24
Peak memory 234972 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2231359153 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/spi
_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_cfg_cmd.2231359153
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/37.spi_device_cfg_cmd/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/37.spi_device_csb_read.1141915181
Short name T750
Test name
Test status
Simulation time 26520995 ps
CPU time 1.13 seconds
Started Aug 25 10:52:10 AM UTC 24
Finished Aug 25 10:52:12 AM UTC 24
Peak memory 215812 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1141915181 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/sp
i_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_csb_read.1141915181
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/37.spi_device_csb_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/37.spi_device_flash_all.2714481341
Short name T874
Test name
Test status
Simulation time 6661735530 ps
CPU time 118.56 seconds
Started Aug 25 10:52:23 AM UTC 24
Finished Aug 25 10:54:24 AM UTC 24
Peak memory 267864 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2714481341 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/s
pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_all.2714481341
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/37.spi_device_flash_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/37.spi_device_flash_and_tpm.2889543980
Short name T800
Test name
Test status
Simulation time 1497052620 ps
CPU time 29.74 seconds
Started Aug 25 10:52:23 AM UTC 24
Finished Aug 25 10:52:54 AM UTC 24
Peak memory 261784 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2889543980 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
24/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_and_tpm.2889543980
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/37.spi_device_flash_and_tpm/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/37.spi_device_flash_and_tpm_min_idle.2425267263
Short name T970
Test name
Test status
Simulation time 59143829728 ps
CPU time 240.08 seconds
Started Aug 25 10:52:25 AM UTC 24
Finished Aug 25 10:56:29 AM UTC 24
Peak memory 265868 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2425267263 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_and_tpm_min_idle.2425267263
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/37.spi_device_flash_and_tpm_min_idle/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/37.spi_device_flash_mode.1145274189
Short name T771
Test name
Test status
Simulation time 2046063166 ps
CPU time 8.18 seconds
Started Aug 25 10:52:22 AM UTC 24
Finished Aug 25 10:52:31 AM UTC 24
Peak memory 234956 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1145274189 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/
spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_mode.1145274189
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/37.spi_device_flash_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/37.spi_device_flash_mode_ignore_cmds.2332688350
Short name T858
Test name
Test status
Simulation time 33532359897 ps
CPU time 97.36 seconds
Started Aug 25 10:52:22 AM UTC 24
Finished Aug 25 10:54:01 AM UTC 24
Peak memory 251492 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2332688350 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_mode_ignore_cmds.2332688350
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/37.spi_device_flash_mode_ignore_cmds/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/37.spi_device_intercept.1378004100
Short name T774
Test name
Test status
Simulation time 1336497726 ps
CPU time 14.01 seconds
Started Aug 25 10:52:17 AM UTC 24
Finished Aug 25 10:52:32 AM UTC 24
Peak memory 245276 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1378004100 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/s
pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_intercept.1378004100
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/37.spi_device_intercept/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/37.spi_device_mailbox.1099962346
Short name T760
Test name
Test status
Simulation time 103053861 ps
CPU time 3.3 seconds
Started Aug 25 10:52:17 AM UTC 24
Finished Aug 25 10:52:21 AM UTC 24
Peak memory 234320 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1099962346 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/spi
_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_mailbox.1099962346
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/37.spi_device_mailbox/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/37.spi_device_pass_addr_payload_swap.2383913199
Short name T759
Test name
Test status
Simulation time 53220018 ps
CPU time 3.04 seconds
Started Aug 25 10:52:17 AM UTC 24
Finished Aug 25 10:52:21 AM UTC 24
Peak memory 234908 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2383913199 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_pass_addr_payload_swap.2383913199
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/37.spi_device_pass_addr_payload_swap/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/37.spi_device_pass_cmd_filtering.2057789707
Short name T758
Test name
Test status
Simulation time 57948131 ps
CPU time 3.18 seconds
Started Aug 25 10:52:16 AM UTC 24
Finished Aug 25 10:52:20 AM UTC 24
Peak memory 244932 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2057789707 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_08_24/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_pass_cmd_filtering.2057789707
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/37.spi_device_pass_cmd_filtering/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/37.spi_device_read_buffer_direct.1329767940
Short name T769
Test name
Test status
Simulation time 191078103 ps
CPU time 6.05 seconds
Started Aug 25 10:52:22 AM UTC 24
Finished Aug 25 10:52:29 AM UTC 24
Peak memory 231260 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1329767940 -assert nopostproc +UVM_TESTNAME=spi_device
_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_read_buffer_direct.1329767940
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/37.spi_device_read_buffer_direct/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/37.spi_device_stress_all.1046171672
Short name T767
Test name
Test status
Simulation time 84183638 ps
CPU time 1.7 seconds
Started Aug 25 10:52:25 AM UTC 24
Finished Aug 25 10:52:28 AM UTC 24
Peak memory 215772 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1046171672 -assert nopostproc +UVM_
TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra
tch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_stress_all.1046171672
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/37.spi_device_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/37.spi_device_tpm_all.875719286
Short name T761
Test name
Test status
Simulation time 4971343410 ps
CPU time 8.92 seconds
Started Aug 25 10:52:13 AM UTC 24
Finished Aug 25 10:52:24 AM UTC 24
Peak memory 227612 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=875719286 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/spi_
device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_all.875719286
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/37.spi_device_tpm_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/37.spi_device_tpm_read_hw_reg.3678091944
Short name T753
Test name
Test status
Simulation time 448104667 ps
CPU time 2.28 seconds
Started Aug 25 10:52:12 AM UTC 24
Finished Aug 25 10:52:16 AM UTC 24
Peak memory 216532 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3678091944 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_24/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_read_hw_reg.3678091944
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/37.spi_device_tpm_read_hw_reg/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/37.spi_device_tpm_rw.760628155
Short name T757
Test name
Test status
Simulation time 163557241 ps
CPU time 3.74 seconds
Started Aug 25 10:52:15 AM UTC 24
Finished Aug 25 10:52:20 AM UTC 24
Peak memory 227564 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=760628155 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/spi_d
evice_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_rw.760628155
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/37.spi_device_tpm_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/37.spi_device_tpm_sts_read.1053209069
Short name T755
Test name
Test status
Simulation time 32076748 ps
CPU time 1.18 seconds
Started Aug 25 10:52:14 AM UTC 24
Finished Aug 25 10:52:16 AM UTC 24
Peak memory 215872 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1053209069 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_2
4/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_sts_read.1053209069
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/37.spi_device_tpm_sts_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/37.spi_device_upload.3935385555
Short name T773
Test name
Test status
Simulation time 786549915 ps
CPU time 10.5 seconds
Started Aug 25 10:52:20 AM UTC 24
Finished Aug 25 10:52:32 AM UTC 24
Peak memory 251348 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3935385555 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/spi_
device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_upload.3935385555
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/37.spi_device_upload/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/38.spi_device_alert_test.438315828
Short name T785
Test name
Test status
Simulation time 26812804 ps
CPU time 1.09 seconds
Started Aug 25 10:52:40 AM UTC 24
Finished Aug 25 10:52:42 AM UTC 24
Peak memory 215744 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=438315828 -assert nopostproc +UVM_TEST
NAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_alert_test.438315828
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/38.spi_device_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/38.spi_device_cfg_cmd.2966449921
Short name T779
Test name
Test status
Simulation time 30866752 ps
CPU time 2.85 seconds
Started Aug 25 10:52:33 AM UTC 24
Finished Aug 25 10:52:37 AM UTC 24
Peak memory 234100 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2966449921 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/spi
_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_cfg_cmd.2966449921
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/38.spi_device_cfg_cmd/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/38.spi_device_csb_read.2448897430
Short name T768
Test name
Test status
Simulation time 13969761 ps
CPU time 1.2 seconds
Started Aug 25 10:52:26 AM UTC 24
Finished Aug 25 10:52:29 AM UTC 24
Peak memory 215812 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2448897430 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/sp
i_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_csb_read.2448897430
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/38.spi_device_csb_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/38.spi_device_flash_all.75997848
Short name T988
Test name
Test status
Simulation time 28845957060 ps
CPU time 315.01 seconds
Started Aug 25 10:52:36 AM UTC 24
Finished Aug 25 10:57:56 AM UTC 24
Peak memory 261712 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=75997848 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/spi
_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_all.75997848
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/38.spi_device_flash_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/38.spi_device_flash_and_tpm.3179418622
Short name T1005
Test name
Test status
Simulation time 183129478378 ps
CPU time 645.91 seconds
Started Aug 25 10:52:38 AM UTC 24
Finished Aug 25 11:03:33 AM UTC 24
Peak memory 278148 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3179418622 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
24/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_and_tpm.3179418622
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/38.spi_device_flash_and_tpm/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/38.spi_device_flash_and_tpm_min_idle.1874403635
Short name T1008
Test name
Test status
Simulation time 104591768523 ps
CPU time 804.79 seconds
Started Aug 25 10:52:38 AM UTC 24
Finished Aug 25 11:06:14 AM UTC 24
Peak memory 278156 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1874403635 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_and_tpm_min_idle.1874403635
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/38.spi_device_flash_and_tpm_min_idle/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/38.spi_device_flash_mode.3803048463
Short name T781
Test name
Test status
Simulation time 494936823 ps
CPU time 4.83 seconds
Started Aug 25 10:52:33 AM UTC 24
Finished Aug 25 10:52:39 AM UTC 24
Peak memory 245276 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3803048463 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/
spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_mode.3803048463
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/38.spi_device_flash_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/38.spi_device_flash_mode_ignore_cmds.878760784
Short name T953
Test name
Test status
Simulation time 19118197108 ps
CPU time 215.08 seconds
Started Aug 25 10:52:33 AM UTC 24
Finished Aug 25 10:56:13 AM UTC 24
Peak memory 261716 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=878760784 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_24/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_mode_ignore_cmds.878760784
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/38.spi_device_flash_mode_ignore_cmds/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/38.spi_device_intercept.217953628
Short name T783
Test name
Test status
Simulation time 2716160445 ps
CPU time 9.38 seconds
Started Aug 25 10:52:30 AM UTC 24
Finished Aug 25 10:52:41 AM UTC 24
Peak memory 235032 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=217953628 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/sp
i_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_intercept.217953628
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/38.spi_device_intercept/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/38.spi_device_mailbox.3329552830
Short name T780
Test name
Test status
Simulation time 1383596579 ps
CPU time 5.66 seconds
Started Aug 25 10:52:32 AM UTC 24
Finished Aug 25 10:52:39 AM UTC 24
Peak memory 245216 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3329552830 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/spi
_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_mailbox.3329552830
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/38.spi_device_mailbox/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/38.spi_device_pass_addr_payload_swap.2492783676
Short name T797
Test name
Test status
Simulation time 1132235999 ps
CPU time 18.42 seconds
Started Aug 25 10:52:30 AM UTC 24
Finished Aug 25 10:52:50 AM UTC 24
Peak memory 251348 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2492783676 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_pass_addr_payload_swap.2492783676
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/38.spi_device_pass_addr_payload_swap/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/38.spi_device_pass_cmd_filtering.1866754017
Short name T802
Test name
Test status
Simulation time 9822736301 ps
CPU time 23.14 seconds
Started Aug 25 10:52:30 AM UTC 24
Finished Aug 25 10:52:55 AM UTC 24
Peak memory 235240 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1866754017 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_08_24/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_pass_cmd_filtering.1866754017
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/38.spi_device_pass_cmd_filtering/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/38.spi_device_read_buffer_direct.1577873483
Short name T790
Test name
Test status
Simulation time 1063131847 ps
CPU time 8.47 seconds
Started Aug 25 10:52:35 AM UTC 24
Finished Aug 25 10:52:44 AM UTC 24
Peak memory 233520 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1577873483 -assert nopostproc +UVM_TESTNAME=spi_device
_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_read_buffer_direct.1577873483
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/38.spi_device_read_buffer_direct/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/38.spi_device_stress_all.2789369099
Short name T1002
Test name
Test status
Simulation time 148286882001 ps
CPU time 587.59 seconds
Started Aug 25 10:52:39 AM UTC 24
Finished Aug 25 11:02:35 AM UTC 24
Peak memory 267916 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2789369099 -assert nopostproc +UVM_
TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra
tch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_stress_all.2789369099
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/38.spi_device_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/38.spi_device_tpm_all.4253482876
Short name T784
Test name
Test status
Simulation time 3820757934 ps
CPU time 11.73 seconds
Started Aug 25 10:52:29 AM UTC 24
Finished Aug 25 10:52:42 AM UTC 24
Peak memory 227584 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4253482876 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/spi
_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_all.4253482876
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/38.spi_device_tpm_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/38.spi_device_tpm_read_hw_reg.469159405
Short name T777
Test name
Test status
Simulation time 2458783747 ps
CPU time 6.95 seconds
Started Aug 25 10:52:26 AM UTC 24
Finished Aug 25 10:52:34 AM UTC 24
Peak memory 227688 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=469159405 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08
_24/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_read_hw_reg.469159405
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/38.spi_device_tpm_read_hw_reg/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/38.spi_device_tpm_rw.2929172666
Short name T775
Test name
Test status
Simulation time 136057107 ps
CPU time 2.45 seconds
Started Aug 25 10:52:29 AM UTC 24
Finished Aug 25 10:52:32 AM UTC 24
Peak memory 227456 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2929172666 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/spi_
device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_rw.2929172666
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/38.spi_device_tpm_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/38.spi_device_tpm_sts_read.3228014112
Short name T772
Test name
Test status
Simulation time 35916878 ps
CPU time 1.25 seconds
Started Aug 25 10:52:29 AM UTC 24
Finished Aug 25 10:52:31 AM UTC 24
Peak memory 215872 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3228014112 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_2
4/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_sts_read.3228014112
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/38.spi_device_tpm_sts_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/38.spi_device_upload.2668985991
Short name T793
Test name
Test status
Simulation time 809216233 ps
CPU time 13.17 seconds
Started Aug 25 10:52:32 AM UTC 24
Finished Aug 25 10:52:47 AM UTC 24
Peak memory 245324 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2668985991 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/spi_
device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_upload.2668985991
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/38.spi_device_upload/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/39.spi_device_alert_test.813958861
Short name T801
Test name
Test status
Simulation time 76379256 ps
CPU time 1.08 seconds
Started Aug 25 10:52:52 AM UTC 24
Finished Aug 25 10:52:55 AM UTC 24
Peak memory 215508 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=813958861 -assert nopostproc +UVM_TEST
NAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_alert_test.813958861
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/39.spi_device_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/39.spi_device_cfg_cmd.832656847
Short name T798
Test name
Test status
Simulation time 422642802 ps
CPU time 4.31 seconds
Started Aug 25 10:52:46 AM UTC 24
Finished Aug 25 10:52:51 AM UTC 24
Peak memory 234900 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=832656847 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/spi_
device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_cfg_cmd.832656847
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/39.spi_device_cfg_cmd/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/39.spi_device_csb_read.3205277967
Short name T786
Test name
Test status
Simulation time 14948327 ps
CPU time 1.17 seconds
Started Aug 25 10:52:40 AM UTC 24
Finished Aug 25 10:52:42 AM UTC 24
Peak memory 215808 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3205277967 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/sp
i_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_csb_read.3205277967
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/39.spi_device_csb_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/39.spi_device_flash_all.91046112
Short name T997
Test name
Test status
Simulation time 83544839424 ps
CPU time 413.64 seconds
Started Aug 25 10:52:48 AM UTC 24
Finished Aug 25 10:59:48 AM UTC 24
Peak memory 280140 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=91046112 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/spi
_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_all.91046112
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/39.spi_device_flash_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/39.spi_device_flash_and_tpm.769170674
Short name T983
Test name
Test status
Simulation time 19855759874 ps
CPU time 245.88 seconds
Started Aug 25 10:52:48 AM UTC 24
Finished Aug 25 10:56:58 AM UTC 24
Peak memory 261792 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=769170674 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_2
4/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_and_tpm.769170674
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/39.spi_device_flash_and_tpm/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/39.spi_device_flash_and_tpm_min_idle.3448821248
Short name T293
Test name
Test status
Simulation time 4883730316 ps
CPU time 137.97 seconds
Started Aug 25 10:52:49 AM UTC 24
Finished Aug 25 10:55:10 AM UTC 24
Peak memory 263812 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3448821248 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_and_tpm_min_idle.3448821248
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/39.spi_device_flash_and_tpm_min_idle/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/39.spi_device_flash_mode.1970659904
Short name T804
Test name
Test status
Simulation time 648504183 ps
CPU time 8.67 seconds
Started Aug 25 10:52:46 AM UTC 24
Finished Aug 25 10:52:55 AM UTC 24
Peak memory 245224 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1970659904 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/
spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_mode.1970659904
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/39.spi_device_flash_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/39.spi_device_flash_mode_ignore_cmds.841790949
Short name T821
Test name
Test status
Simulation time 10647610139 ps
CPU time 24.29 seconds
Started Aug 25 10:52:48 AM UTC 24
Finished Aug 25 10:53:14 AM UTC 24
Peak memory 261844 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=841790949 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_24/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_mode_ignore_cmds.841790949
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/39.spi_device_flash_mode_ignore_cmds/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/39.spi_device_intercept.1357149782
Short name T799
Test name
Test status
Simulation time 815826504 ps
CPU time 6.4 seconds
Started Aug 25 10:52:44 AM UTC 24
Finished Aug 25 10:52:51 AM UTC 24
Peak memory 234916 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1357149782 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/s
pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_intercept.1357149782
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/39.spi_device_intercept/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/39.spi_device_mailbox.4050257103
Short name T886
Test name
Test status
Simulation time 85857104728 ps
CPU time 107.96 seconds
Started Aug 25 10:52:45 AM UTC 24
Finished Aug 25 10:54:36 AM UTC 24
Peak memory 245296 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4050257103 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/spi
_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_mailbox.4050257103
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/39.spi_device_mailbox/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/39.spi_device_pass_addr_payload_swap.4292691425
Short name T795
Test name
Test status
Simulation time 78877419 ps
CPU time 2.99 seconds
Started Aug 25 10:52:43 AM UTC 24
Finished Aug 25 10:52:47 AM UTC 24
Peak memory 234668 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4292691425 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_pass_addr_payload_swap.4292691425
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/39.spi_device_pass_addr_payload_swap/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/39.spi_device_pass_cmd_filtering.1935776518
Short name T815
Test name
Test status
Simulation time 1885561389 ps
CPU time 22.76 seconds
Started Aug 25 10:52:43 AM UTC 24
Finished Aug 25 10:53:07 AM UTC 24
Peak memory 245168 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1935776518 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_08_24/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_pass_cmd_filtering.1935776518
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/39.spi_device_pass_cmd_filtering/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/39.spi_device_read_buffer_direct.1039193385
Short name T813
Test name
Test status
Simulation time 1039996029 ps
CPU time 15.98 seconds
Started Aug 25 10:52:48 AM UTC 24
Finished Aug 25 10:53:05 AM UTC 24
Peak memory 231252 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1039193385 -assert nopostproc +UVM_TESTNAME=spi_device
_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_read_buffer_direct.1039193385
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/39.spi_device_read_buffer_direct/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/39.spi_device_stress_all.2194317424
Short name T827
Test name
Test status
Simulation time 2276699606 ps
CPU time 31.07 seconds
Started Aug 25 10:52:50 AM UTC 24
Finished Aug 25 10:53:23 AM UTC 24
Peak memory 235020 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2194317424 -assert nopostproc +UVM_
TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra
tch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_stress_all.2194317424
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/39.spi_device_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/39.spi_device_tpm_all.1167972741
Short name T787
Test name
Test status
Simulation time 24082072 ps
CPU time 1.12 seconds
Started Aug 25 10:52:41 AM UTC 24
Finished Aug 25 10:52:44 AM UTC 24
Peak memory 215744 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1167972741 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/spi
_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_all.1167972741
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/39.spi_device_tpm_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/39.spi_device_tpm_read_hw_reg.630561288
Short name T789
Test name
Test status
Simulation time 200958711 ps
CPU time 2.8 seconds
Started Aug 25 10:52:40 AM UTC 24
Finished Aug 25 10:52:44 AM UTC 24
Peak memory 217088 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=630561288 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08
_24/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_read_hw_reg.630561288
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/39.spi_device_tpm_read_hw_reg/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/39.spi_device_tpm_rw.295702681
Short name T791
Test name
Test status
Simulation time 11443364 ps
CPU time 1.06 seconds
Started Aug 25 10:52:43 AM UTC 24
Finished Aug 25 10:52:45 AM UTC 24
Peak memory 215740 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=295702681 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/spi_d
evice_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_rw.295702681
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/39.spi_device_tpm_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/39.spi_device_tpm_sts_read.3939429280
Short name T788
Test name
Test status
Simulation time 88032754 ps
CPU time 1.47 seconds
Started Aug 25 10:52:42 AM UTC 24
Finished Aug 25 10:52:44 AM UTC 24
Peak memory 215872 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3939429280 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_2
4/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_sts_read.3939429280
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/39.spi_device_tpm_sts_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/39.spi_device_upload.3692660339
Short name T811
Test name
Test status
Simulation time 3652613929 ps
CPU time 15.94 seconds
Started Aug 25 10:52:46 AM UTC 24
Finished Aug 25 10:53:03 AM UTC 24
Peak memory 245396 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3692660339 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/spi_
device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_upload.3692660339
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/39.spi_device_upload/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/4.spi_device_alert_test.3724998064
Short name T417
Test name
Test status
Simulation time 13582838 ps
CPU time 1.12 seconds
Started Aug 25 10:42:27 AM UTC 24
Finished Aug 25 10:42:29 AM UTC 24
Peak memory 215684 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3724998064 -assert nopostproc +UVM_TES
TNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_
regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_alert_test.3724998064
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/4.spi_device_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/4.spi_device_cfg_cmd.3697503072
Short name T107
Test name
Test status
Simulation time 1330650729 ps
CPU time 18.28 seconds
Started Aug 25 10:42:25 AM UTC 24
Finished Aug 25 10:42:44 AM UTC 24
Peak memory 245136 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3697503072 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/spi
_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_cfg_cmd.3697503072
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/4.spi_device_cfg_cmd/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/4.spi_device_csb_read.2892805490
Short name T413
Test name
Test status
Simulation time 15476193 ps
CPU time 1.2 seconds
Started Aug 25 10:42:22 AM UTC 24
Finished Aug 25 10:42:24 AM UTC 24
Peak memory 215868 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2892805490 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/sp
i_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_csb_read.2892805490
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/4.spi_device_csb_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/4.spi_device_flash_all.3570388368
Short name T236
Test name
Test status
Simulation time 55165536457 ps
CPU time 287.19 seconds
Started Aug 25 10:42:27 AM UTC 24
Finished Aug 25 10:47:19 AM UTC 24
Peak memory 251492 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3570388368 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/s
pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_all.3570388368
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/4.spi_device_flash_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/4.spi_device_flash_mode.3036413399
Short name T185
Test name
Test status
Simulation time 3973520012 ps
CPU time 43.05 seconds
Started Aug 25 10:42:25 AM UTC 24
Finished Aug 25 10:43:09 AM UTC 24
Peak memory 251488 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3036413399 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/
spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_mode.3036413399
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/4.spi_device_flash_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/4.spi_device_flash_mode_ignore_cmds.3075203393
Short name T52
Test name
Test status
Simulation time 11503923128 ps
CPU time 52.67 seconds
Started Aug 25 10:42:27 AM UTC 24
Finished Aug 25 10:43:21 AM UTC 24
Peak memory 261684 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3075203393 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_mode_ignore_cmds.3075203393
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/4.spi_device_flash_mode_ignore_cmds/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/4.spi_device_intercept.2266178689
Short name T416
Test name
Test status
Simulation time 426136354 ps
CPU time 3.4 seconds
Started Aug 25 10:42:24 AM UTC 24
Finished Aug 25 10:42:29 AM UTC 24
Peak memory 233612 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2266178689 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/s
pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_intercept.2266178689
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/4.spi_device_intercept/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/4.spi_device_pass_addr_payload_swap.3285657102
Short name T57
Test name
Test status
Simulation time 498286669 ps
CPU time 4.76 seconds
Started Aug 25 10:42:22 AM UTC 24
Finished Aug 25 10:42:28 AM UTC 24
Peak memory 245264 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3285657102 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_pass_addr_payload_swap.3285657102
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/4.spi_device_pass_addr_payload_swap/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/4.spi_device_pass_cmd_filtering.1232931404
Short name T193
Test name
Test status
Simulation time 79856615 ps
CPU time 2.65 seconds
Started Aug 25 10:42:22 AM UTC 24
Finished Aug 25 10:42:26 AM UTC 24
Peak memory 245164 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1232931404 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_08_24/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_pass_cmd_filtering.1232931404
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/4.spi_device_pass_cmd_filtering/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/4.spi_device_read_buffer_direct.4020742601
Short name T158
Test name
Test status
Simulation time 2290610025 ps
CPU time 11.66 seconds
Started Aug 25 10:42:27 AM UTC 24
Finished Aug 25 10:42:40 AM UTC 24
Peak memory 231348 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4020742601 -assert nopostproc +UVM_TESTNAME=spi_device
_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_read_buffer_direct.4020742601
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/4.spi_device_read_buffer_direct/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/4.spi_device_sec_cm.248137100
Short name T31
Test name
Test status
Simulation time 42171445 ps
CPU time 1.48 seconds
Started Aug 25 10:42:27 AM UTC 24
Finished Aug 25 10:42:30 AM UTC 24
Peak memory 257972 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=248137100 -assert nopostproc +UVM_TESTN
AME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_sec_cm.248137100
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/4.spi_device_sec_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/4.spi_device_stress_all.946594627
Short name T32
Test name
Test status
Simulation time 11298323993 ps
CPU time 113.41 seconds
Started Aug 25 10:42:27 AM UTC 24
Finished Aug 25 10:44:23 AM UTC 24
Peak memory 267916 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=946594627 -assert nopostproc +UVM_T
ESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_stress_all.946594627
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/4.spi_device_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/4.spi_device_tpm_all.2076851758
Short name T412
Test name
Test status
Simulation time 102537935 ps
CPU time 0.97 seconds
Started Aug 25 10:42:22 AM UTC 24
Finished Aug 25 10:42:24 AM UTC 24
Peak memory 215748 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2076851758 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/spi
_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_all.2076851758
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/4.spi_device_tpm_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/4.spi_device_tpm_read_hw_reg.378405971
Short name T414
Test name
Test status
Simulation time 27682759 ps
CPU time 1.08 seconds
Started Aug 25 10:42:22 AM UTC 24
Finished Aug 25 10:42:24 AM UTC 24
Peak memory 215748 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=378405971 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08
_24/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_read_hw_reg.378405971
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/4.spi_device_tpm_read_hw_reg/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/4.spi_device_tpm_rw.2278596219
Short name T44
Test name
Test status
Simulation time 57022798 ps
CPU time 1.65 seconds
Started Aug 25 10:42:22 AM UTC 24
Finished Aug 25 10:42:25 AM UTC 24
Peak memory 215868 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2278596219 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/spi_
device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_rw.2278596219
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/4.spi_device_tpm_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/4.spi_device_tpm_sts_read.881292078
Short name T415
Test name
Test status
Simulation time 100286184 ps
CPU time 1.21 seconds
Started Aug 25 10:42:22 AM UTC 24
Finished Aug 25 10:42:24 AM UTC 24
Peak memory 215864 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=881292078 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24
/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_sts_read.881292078
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/4.spi_device_tpm_sts_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/4.spi_device_upload.2952029658
Short name T182
Test name
Test status
Simulation time 2477612945 ps
CPU time 19.65 seconds
Started Aug 25 10:42:25 AM UTC 24
Finished Aug 25 10:42:45 AM UTC 24
Peak memory 251556 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2952029658 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/spi_
device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_upload.2952029658
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/4.spi_device_upload/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/40.spi_device_alert_test.103506719
Short name T818
Test name
Test status
Simulation time 26026779 ps
CPU time 1.09 seconds
Started Aug 25 10:53:09 AM UTC 24
Finished Aug 25 10:53:11 AM UTC 24
Peak memory 215684 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=103506719 -assert nopostproc +UVM_TEST
NAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_alert_test.103506719
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/40.spi_device_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/40.spi_device_cfg_cmd.1354329134
Short name T814
Test name
Test status
Simulation time 113320608 ps
CPU time 3.27 seconds
Started Aug 25 10:53:01 AM UTC 24
Finished Aug 25 10:53:06 AM UTC 24
Peak memory 245132 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1354329134 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/spi
_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_cfg_cmd.1354329134
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/40.spi_device_cfg_cmd/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/40.spi_device_csb_read.4040335402
Short name T803
Test name
Test status
Simulation time 47098646 ps
CPU time 1.14 seconds
Started Aug 25 10:52:52 AM UTC 24
Finished Aug 25 10:52:55 AM UTC 24
Peak memory 215580 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4040335402 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/sp
i_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_csb_read.4040335402
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/40.spi_device_csb_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/40.spi_device_flash_all.376829923
Short name T957
Test name
Test status
Simulation time 67896453181 ps
CPU time 189.63 seconds
Started Aug 25 10:53:05 AM UTC 24
Finished Aug 25 10:56:18 AM UTC 24
Peak memory 261776 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=376829923 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/sp
i_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_all.376829923
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/40.spi_device_flash_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/40.spi_device_flash_and_tpm.3299471597
Short name T839
Test name
Test status
Simulation time 1506493119 ps
CPU time 26.71 seconds
Started Aug 25 10:53:06 AM UTC 24
Finished Aug 25 10:53:34 AM UTC 24
Peak memory 247288 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3299471597 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
24/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_and_tpm.3299471597
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/40.spi_device_flash_and_tpm/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/40.spi_device_flash_and_tpm_min_idle.1128082538
Short name T931
Test name
Test status
Simulation time 16738135413 ps
CPU time 157.67 seconds
Started Aug 25 10:53:07 AM UTC 24
Finished Aug 25 10:55:48 AM UTC 24
Peak memory 280224 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1128082538 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_and_tpm_min_idle.1128082538
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/40.spi_device_flash_and_tpm_min_idle/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/40.spi_device_flash_mode.237561806
Short name T816
Test name
Test status
Simulation time 93585018 ps
CPU time 4.94 seconds
Started Aug 25 10:53:03 AM UTC 24
Finished Aug 25 10:53:09 AM UTC 24
Peak memory 235092 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=237561806 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/s
pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_mode.237561806
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/40.spi_device_flash_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/40.spi_device_flash_mode_ignore_cmds.1305309442
Short name T923
Test name
Test status
Simulation time 11482312419 ps
CPU time 143.29 seconds
Started Aug 25 10:53:03 AM UTC 24
Finished Aug 25 10:55:29 AM UTC 24
Peak memory 249428 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1305309442 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_mode_ignore_cmds.1305309442
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/40.spi_device_flash_mode_ignore_cmds/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/40.spi_device_intercept.2591507970
Short name T809
Test name
Test status
Simulation time 80030150 ps
CPU time 3.25 seconds
Started Aug 25 10:52:57 AM UTC 24
Finished Aug 25 10:53:01 AM UTC 24
Peak memory 245232 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2591507970 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/s
pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_intercept.2591507970
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/40.spi_device_intercept/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/40.spi_device_mailbox.1636960587
Short name T861
Test name
Test status
Simulation time 44063807704 ps
CPU time 65.03 seconds
Started Aug 25 10:52:59 AM UTC 24
Finished Aug 25 10:54:06 AM UTC 24
Peak memory 251476 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1636960587 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/spi
_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_mailbox.1636960587
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/40.spi_device_mailbox/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/40.spi_device_pass_addr_payload_swap.848538133
Short name T824
Test name
Test status
Simulation time 5732852329 ps
CPU time 21.7 seconds
Started Aug 25 10:52:56 AM UTC 24
Finished Aug 25 10:53:19 AM UTC 24
Peak memory 235192 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=848538133 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_24/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_pass_addr_payload_swap.848538133
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/40.spi_device_pass_addr_payload_swap/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/40.spi_device_pass_cmd_filtering.1810141951
Short name T823
Test name
Test status
Simulation time 3799617499 ps
CPU time 19.18 seconds
Started Aug 25 10:52:56 AM UTC 24
Finished Aug 25 10:53:16 AM UTC 24
Peak memory 245368 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1810141951 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_08_24/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_pass_cmd_filtering.1810141951
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/40.spi_device_pass_cmd_filtering/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/40.spi_device_read_buffer_direct.238064399
Short name T817
Test name
Test status
Simulation time 268264250 ps
CPU time 4.6 seconds
Started Aug 25 10:53:04 AM UTC 24
Finished Aug 25 10:53:09 AM UTC 24
Peak memory 231396 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=238064399 -assert nopostproc +UVM_TESTNAME=spi_device_
base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_read_buffer_direct.238064399
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/40.spi_device_read_buffer_direct/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/40.spi_device_stress_all.347672093
Short name T76
Test name
Test status
Simulation time 145126139646 ps
CPU time 896.12 seconds
Started Aug 25 10:53:08 AM UTC 24
Finished Aug 25 11:08:17 AM UTC 24
Peak memory 278160 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=347672093 -assert nopostproc +UVM_T
ESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_stress_all.347672093
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/40.spi_device_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/40.spi_device_tpm_all.3892607374
Short name T855
Test name
Test status
Simulation time 141832633399 ps
CPU time 60.47 seconds
Started Aug 25 10:52:55 AM UTC 24
Finished Aug 25 10:53:57 AM UTC 24
Peak memory 227612 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3892607374 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/spi
_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_all.3892607374
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/40.spi_device_tpm_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/40.spi_device_tpm_read_hw_reg.3417304052
Short name T810
Test name
Test status
Simulation time 1057990158 ps
CPU time 6.73 seconds
Started Aug 25 10:52:54 AM UTC 24
Finished Aug 25 10:53:01 AM UTC 24
Peak memory 227496 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3417304052 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_24/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_read_hw_reg.3417304052
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/40.spi_device_tpm_read_hw_reg/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/40.spi_device_tpm_rw.598120954
Short name T806
Test name
Test status
Simulation time 17693376 ps
CPU time 1.18 seconds
Started Aug 25 10:52:56 AM UTC 24
Finished Aug 25 10:52:58 AM UTC 24
Peak memory 215864 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=598120954 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/spi_d
evice_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_rw.598120954
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/40.spi_device_tpm_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/40.spi_device_tpm_sts_read.1333138830
Short name T807
Test name
Test status
Simulation time 63342062 ps
CPU time 1.26 seconds
Started Aug 25 10:52:56 AM UTC 24
Finished Aug 25 10:52:58 AM UTC 24
Peak memory 215872 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1333138830 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_2
4/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_sts_read.1333138830
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/40.spi_device_tpm_sts_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/40.spi_device_upload.4262602572
Short name T812
Test name
Test status
Simulation time 291813874 ps
CPU time 3.13 seconds
Started Aug 25 10:52:59 AM UTC 24
Finished Aug 25 10:53:03 AM UTC 24
Peak memory 234172 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4262602572 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/spi_
device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_upload.4262602572
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/40.spi_device_upload/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/41.spi_device_alert_test.2809072398
Short name T831
Test name
Test status
Simulation time 65706962 ps
CPU time 1.14 seconds
Started Aug 25 10:53:25 AM UTC 24
Finished Aug 25 10:53:27 AM UTC 24
Peak memory 214132 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2809072398 -assert nopostproc +UVM_TES
TNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_
regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_alert_test.2809072398
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/41.spi_device_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/41.spi_device_cfg_cmd.3462051495
Short name T828
Test name
Test status
Simulation time 279740381 ps
CPU time 3.42 seconds
Started Aug 25 10:53:19 AM UTC 24
Finished Aug 25 10:53:24 AM UTC 24
Peak memory 245208 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3462051495 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/spi
_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_cfg_cmd.3462051495
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/41.spi_device_cfg_cmd/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/41.spi_device_csb_read.536154688
Short name T819
Test name
Test status
Simulation time 17020943 ps
CPU time 1.17 seconds
Started Aug 25 10:53:10 AM UTC 24
Finished Aug 25 10:53:13 AM UTC 24
Peak memory 215512 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=536154688 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/spi
_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_csb_read.536154688
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/41.spi_device_csb_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/41.spi_device_flash_all.1322726825
Short name T863
Test name
Test status
Simulation time 2124286577 ps
CPU time 43.59 seconds
Started Aug 25 10:53:24 AM UTC 24
Finished Aug 25 10:54:09 AM UTC 24
Peak memory 261592 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1322726825 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/s
pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_all.1322726825
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/41.spi_device_flash_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/41.spi_device_flash_and_tpm.1296102744
Short name T306
Test name
Test status
Simulation time 82799619276 ps
CPU time 295.02 seconds
Started Aug 25 10:53:24 AM UTC 24
Finished Aug 25 10:58:24 AM UTC 24
Peak memory 278132 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1296102744 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
24/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_and_tpm.1296102744
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/41.spi_device_flash_and_tpm/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/41.spi_device_flash_and_tpm_min_idle.672124950
Short name T936
Test name
Test status
Simulation time 12284580062 ps
CPU time 145.18 seconds
Started Aug 25 10:53:24 AM UTC 24
Finished Aug 25 10:55:52 AM UTC 24
Peak memory 261844 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=672124950 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_24/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_and_tpm_min_idle.672124950
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/41.spi_device_flash_and_tpm_min_idle/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/41.spi_device_flash_mode.1640533350
Short name T841
Test name
Test status
Simulation time 1296541894 ps
CPU time 14.11 seconds
Started Aug 25 10:53:19 AM UTC 24
Finished Aug 25 10:53:35 AM UTC 24
Peak memory 261608 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1640533350 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/
spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_mode.1640533350
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/41.spi_device_flash_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/41.spi_device_flash_mode_ignore_cmds.2319969987
Short name T865
Test name
Test status
Simulation time 1623321522 ps
CPU time 48.01 seconds
Started Aug 25 10:53:22 AM UTC 24
Finished Aug 25 10:54:11 AM UTC 24
Peak memory 263784 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2319969987 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_mode_ignore_cmds.2319969987
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/41.spi_device_flash_mode_ignore_cmds/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/41.spi_device_intercept.3023642754
Short name T830
Test name
Test status
Simulation time 481474851 ps
CPU time 7.01 seconds
Started Aug 25 10:53:17 AM UTC 24
Finished Aug 25 10:53:25 AM UTC 24
Peak memory 245212 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3023642754 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/s
pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_intercept.3023642754
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/41.spi_device_intercept/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/41.spi_device_mailbox.3457757298
Short name T892
Test name
Test status
Simulation time 11205024825 ps
CPU time 79.36 seconds
Started Aug 25 10:53:17 AM UTC 24
Finished Aug 25 10:54:39 AM UTC 24
Peak memory 245324 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3457757298 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/spi
_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_mailbox.3457757298
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/41.spi_device_mailbox/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/41.spi_device_pass_addr_payload_swap.2217677902
Short name T354
Test name
Test status
Simulation time 981192216 ps
CPU time 7.27 seconds
Started Aug 25 10:53:15 AM UTC 24
Finished Aug 25 10:53:23 AM UTC 24
Peak memory 234932 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2217677902 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_pass_addr_payload_swap.2217677902
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/41.spi_device_pass_addr_payload_swap/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/41.spi_device_pass_cmd_filtering.433655976
Short name T851
Test name
Test status
Simulation time 5278132108 ps
CPU time 38.03 seconds
Started Aug 25 10:53:15 AM UTC 24
Finished Aug 25 10:53:55 AM UTC 24
Peak memory 235092 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=433655976 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_08_24/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_pass_cmd_filtering.433655976
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/41.spi_device_pass_cmd_filtering/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/41.spi_device_read_buffer_direct.3039668967
Short name T836
Test name
Test status
Simulation time 223067227 ps
CPU time 7.07 seconds
Started Aug 25 10:53:23 AM UTC 24
Finished Aug 25 10:53:31 AM UTC 24
Peak memory 233324 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3039668967 -assert nopostproc +UVM_TESTNAME=spi_device
_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_read_buffer_direct.3039668967
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/41.spi_device_read_buffer_direct/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/41.spi_device_stress_all.4094963876
Short name T834
Test name
Test status
Simulation time 242579107 ps
CPU time 1.44 seconds
Started Aug 25 10:53:25 AM UTC 24
Finished Aug 25 10:53:28 AM UTC 24
Peak memory 214868 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4094963876 -assert nopostproc +UVM_
TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra
tch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_stress_all.4094963876
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/41.spi_device_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/41.spi_device_tpm_all.2562561694
Short name T826
Test name
Test status
Simulation time 1298717086 ps
CPU time 7.47 seconds
Started Aug 25 10:53:14 AM UTC 24
Finished Aug 25 10:53:22 AM UTC 24
Peak memory 227484 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2562561694 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/spi
_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_all.2562561694
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/41.spi_device_tpm_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/41.spi_device_tpm_read_hw_reg.666163627
Short name T843
Test name
Test status
Simulation time 3878462775 ps
CPU time 22.08 seconds
Started Aug 25 10:53:12 AM UTC 24
Finished Aug 25 10:53:36 AM UTC 24
Peak memory 227680 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=666163627 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08
_24/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_read_hw_reg.666163627
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/41.spi_device_tpm_read_hw_reg/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/41.spi_device_tpm_rw.3352330326
Short name T825
Test name
Test status
Simulation time 223046478 ps
CPU time 4.72 seconds
Started Aug 25 10:53:15 AM UTC 24
Finished Aug 25 10:53:21 AM UTC 24
Peak memory 227424 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3352330326 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/spi_
device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_rw.3352330326
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/41.spi_device_tpm_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/41.spi_device_tpm_sts_read.3254870843
Short name T822
Test name
Test status
Simulation time 153110515 ps
CPU time 1.23 seconds
Started Aug 25 10:53:14 AM UTC 24
Finished Aug 25 10:53:16 AM UTC 24
Peak memory 215872 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3254870843 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_2
4/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_sts_read.3254870843
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/41.spi_device_tpm_sts_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/41.spi_device_upload.1629537055
Short name T835
Test name
Test status
Simulation time 1264077545 ps
CPU time 10.6 seconds
Started Aug 25 10:53:18 AM UTC 24
Finished Aug 25 10:53:30 AM UTC 24
Peak memory 234968 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1629537055 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/spi_
device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_upload.1629537055
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/41.spi_device_upload/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/42.spi_device_alert_test.1363824580
Short name T852
Test name
Test status
Simulation time 10586634 ps
CPU time 1.09 seconds
Started Aug 25 10:53:39 AM UTC 24
Finished Aug 25 10:53:55 AM UTC 24
Peak memory 215804 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1363824580 -assert nopostproc +UVM_TES
TNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_
regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_alert_test.1363824580
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/42.spi_device_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/42.spi_device_cfg_cmd.3177935560
Short name T844
Test name
Test status
Simulation time 29137286 ps
CPU time 2.81 seconds
Started Aug 25 10:53:32 AM UTC 24
Finished Aug 25 10:53:36 AM UTC 24
Peak memory 234060 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3177935560 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/spi
_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_cfg_cmd.3177935560
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/42.spi_device_cfg_cmd/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/42.spi_device_csb_read.1283968713
Short name T832
Test name
Test status
Simulation time 64470333 ps
CPU time 1.17 seconds
Started Aug 25 10:53:25 AM UTC 24
Finished Aug 25 10:53:28 AM UTC 24
Peak memory 215812 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1283968713 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/sp
i_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_csb_read.1283968713
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/42.spi_device_csb_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/42.spi_device_flash_all.3901822371
Short name T893
Test name
Test status
Simulation time 11679624546 ps
CPU time 60.43 seconds
Started Aug 25 10:53:37 AM UTC 24
Finished Aug 25 10:54:39 AM UTC 24
Peak memory 251488 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3901822371 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/s
pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_all.3901822371
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/42.spi_device_flash_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/42.spi_device_flash_and_tpm.1173690557
Short name T1003
Test name
Test status
Simulation time 37090054730 ps
CPU time 533.28 seconds
Started Aug 25 10:53:38 AM UTC 24
Finished Aug 25 11:02:54 AM UTC 24
Peak memory 265888 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1173690557 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
24/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_and_tpm.1173690557
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/42.spi_device_flash_and_tpm/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/42.spi_device_flash_and_tpm_min_idle.983844632
Short name T322
Test name
Test status
Simulation time 135497536039 ps
CPU time 421.01 seconds
Started Aug 25 10:53:38 AM UTC 24
Finished Aug 25 11:01:00 AM UTC 24
Peak memory 284232 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=983844632 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_24/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_and_tpm_min_idle.983844632
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/42.spi_device_flash_and_tpm_min_idle/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/42.spi_device_flash_mode.3879927977
Short name T857
Test name
Test status
Simulation time 1250117109 ps
CPU time 24.16 seconds
Started Aug 25 10:53:34 AM UTC 24
Finished Aug 25 10:54:00 AM UTC 24
Peak memory 245224 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3879927977 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/
spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_mode.3879927977
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/42.spi_device_flash_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/42.spi_device_flash_mode_ignore_cmds.2700021428
Short name T908
Test name
Test status
Simulation time 4690635729 ps
CPU time 80.41 seconds
Started Aug 25 10:53:36 AM UTC 24
Finished Aug 25 10:54:58 AM UTC 24
Peak memory 267872 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2700021428 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_mode_ignore_cmds.2700021428
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/42.spi_device_flash_mode_ignore_cmds/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/42.spi_device_intercept.1819284666
Short name T842
Test name
Test status
Simulation time 376086257 ps
CPU time 3.98 seconds
Started Aug 25 10:53:31 AM UTC 24
Finished Aug 25 10:53:36 AM UTC 24
Peak memory 245212 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1819284666 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/s
pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_intercept.1819284666
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/42.spi_device_intercept/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/42.spi_device_mailbox.1781792588
Short name T934
Test name
Test status
Simulation time 10703816191 ps
CPU time 135.08 seconds
Started Aug 25 10:53:32 AM UTC 24
Finished Aug 25 10:55:51 AM UTC 24
Peak memory 261732 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1781792588 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/spi
_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_mailbox.1781792588
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/42.spi_device_mailbox/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/42.spi_device_pass_addr_payload_swap.2015302792
Short name T299
Test name
Test status
Simulation time 6344920557 ps
CPU time 38.47 seconds
Started Aug 25 10:53:29 AM UTC 24
Finished Aug 25 10:54:09 AM UTC 24
Peak memory 245332 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2015302792 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_pass_addr_payload_swap.2015302792
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/42.spi_device_pass_addr_payload_swap/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/42.spi_device_pass_cmd_filtering.1761771722
Short name T846
Test name
Test status
Simulation time 3068010452 ps
CPU time 7.69 seconds
Started Aug 25 10:53:29 AM UTC 24
Finished Aug 25 10:53:38 AM UTC 24
Peak memory 235056 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1761771722 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_08_24/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_pass_cmd_filtering.1761771722
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/42.spi_device_pass_cmd_filtering/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/42.spi_device_read_buffer_direct.2709419870
Short name T848
Test name
Test status
Simulation time 266991933 ps
CPU time 7.18 seconds
Started Aug 25 10:53:36 AM UTC 24
Finished Aug 25 10:53:44 AM UTC 24
Peak memory 233368 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2709419870 -assert nopostproc +UVM_TESTNAME=spi_device
_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_read_buffer_direct.2709419870
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/42.spi_device_read_buffer_direct/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/42.spi_device_stress_all.2018440582
Short name T987
Test name
Test status
Simulation time 56294017722 ps
CPU time 236.6 seconds
Started Aug 25 10:53:38 AM UTC 24
Finished Aug 25 10:57:53 AM UTC 24
Peak memory 267836 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2018440582 -assert nopostproc +UVM_
TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra
tch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_stress_all.2018440582
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/42.spi_device_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/42.spi_device_tpm_all.958363901
Short name T869
Test name
Test status
Simulation time 5214445737 ps
CPU time 49.68 seconds
Started Aug 25 10:53:27 AM UTC 24
Finished Aug 25 10:54:19 AM UTC 24
Peak memory 227680 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=958363901 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/spi_
device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_all.958363901
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/42.spi_device_tpm_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/42.spi_device_tpm_read_hw_reg.2792886428
Short name T838
Test name
Test status
Simulation time 2068894914 ps
CPU time 4.06 seconds
Started Aug 25 10:53:26 AM UTC 24
Finished Aug 25 10:53:32 AM UTC 24
Peak memory 217160 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2792886428 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_24/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_read_hw_reg.2792886428
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/42.spi_device_tpm_read_hw_reg/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/42.spi_device_tpm_rw.2949637288
Short name T840
Test name
Test status
Simulation time 1286964822 ps
CPU time 4.17 seconds
Started Aug 25 10:53:29 AM UTC 24
Finished Aug 25 10:53:34 AM UTC 24
Peak memory 227460 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2949637288 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/spi_
device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_rw.2949637288
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/42.spi_device_tpm_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/42.spi_device_tpm_sts_read.3297320368
Short name T837
Test name
Test status
Simulation time 39287378 ps
CPU time 1.3 seconds
Started Aug 25 10:53:29 AM UTC 24
Finished Aug 25 10:53:31 AM UTC 24
Peak memory 215828 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3297320368 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_2
4/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_sts_read.3297320368
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/42.spi_device_tpm_sts_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/42.spi_device_upload.1663673151
Short name T845
Test name
Test status
Simulation time 100139495 ps
CPU time 3.34 seconds
Started Aug 25 10:53:32 AM UTC 24
Finished Aug 25 10:53:37 AM UTC 24
Peak memory 244948 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1663673151 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/spi_
device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_upload.1663673151
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/42.spi_device_upload/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/43.spi_device_alert_test.1905476708
Short name T866
Test name
Test status
Simulation time 17417318 ps
CPU time 1.1 seconds
Started Aug 25 10:54:11 AM UTC 24
Finished Aug 25 10:54:14 AM UTC 24
Peak memory 215684 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1905476708 -assert nopostproc +UVM_TES
TNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_
regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_alert_test.1905476708
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/43.spi_device_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/43.spi_device_cfg_cmd.1136442096
Short name T860
Test name
Test status
Simulation time 42259733 ps
CPU time 3.33 seconds
Started Aug 25 10:54:01 AM UTC 24
Finished Aug 25 10:54:06 AM UTC 24
Peak memory 245132 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1136442096 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/spi
_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_cfg_cmd.1136442096
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/43.spi_device_cfg_cmd/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/43.spi_device_csb_read.1231377753
Short name T853
Test name
Test status
Simulation time 44608863 ps
CPU time 1.16 seconds
Started Aug 25 10:53:51 AM UTC 24
Finished Aug 25 10:53:55 AM UTC 24
Peak memory 215812 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1231377753 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/sp
i_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_csb_read.1231377753
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/43.spi_device_csb_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/43.spi_device_flash_all.3795859997
Short name T979
Test name
Test status
Simulation time 134803472641 ps
CPU time 157.23 seconds
Started Aug 25 10:54:07 AM UTC 24
Finished Aug 25 10:56:47 AM UTC 24
Peak memory 261724 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3795859997 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/s
pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_all.3795859997
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/43.spi_device_flash_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/43.spi_device_flash_and_tpm.236301588
Short name T291
Test name
Test status
Simulation time 51230057616 ps
CPU time 183.21 seconds
Started Aug 25 10:54:09 AM UTC 24
Finished Aug 25 10:57:16 AM UTC 24
Peak memory 261792 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=236301588 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_2
4/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_and_tpm.236301588
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/43.spi_device_flash_and_tpm/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/43.spi_device_flash_and_tpm_min_idle.3649894940
Short name T999
Test name
Test status
Simulation time 38499099451 ps
CPU time 444.87 seconds
Started Aug 25 10:54:10 AM UTC 24
Finished Aug 25 11:01:42 AM UTC 24
Peak memory 267876 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3649894940 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_and_tpm_min_idle.3649894940
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/43.spi_device_flash_and_tpm_min_idle/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/43.spi_device_flash_mode.1957485113
Short name T879
Test name
Test status
Simulation time 9274673023 ps
CPU time 26.54 seconds
Started Aug 25 10:54:03 AM UTC 24
Finished Aug 25 10:54:31 AM UTC 24
Peak memory 247328 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1957485113 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/
spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_mode.1957485113
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/43.spi_device_flash_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/43.spi_device_flash_mode_ignore_cmds.1679870802
Short name T920
Test name
Test status
Simulation time 8630428253 ps
CPU time 77.75 seconds
Started Aug 25 10:54:04 AM UTC 24
Finished Aug 25 10:55:24 AM UTC 24
Peak memory 261732 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1679870802 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_mode_ignore_cmds.1679870802
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/43.spi_device_flash_mode_ignore_cmds/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/43.spi_device_intercept.3952740397
Short name T880
Test name
Test status
Simulation time 2415898155 ps
CPU time 31.79 seconds
Started Aug 25 10:53:58 AM UTC 24
Finished Aug 25 10:54:31 AM UTC 24
Peak memory 235040 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3952740397 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/s
pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_intercept.3952740397
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/43.spi_device_intercept/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/43.spi_device_mailbox.1963261808
Short name T873
Test name
Test status
Simulation time 2529763827 ps
CPU time 23.37 seconds
Started Aug 25 10:53:58 AM UTC 24
Finished Aug 25 10:54:23 AM UTC 24
Peak memory 249384 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1963261808 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/spi
_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_mailbox.1963261808
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/43.spi_device_mailbox/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/43.spi_device_pass_addr_payload_swap.4149260427
Short name T881
Test name
Test status
Simulation time 34175971400 ps
CPU time 36.21 seconds
Started Aug 25 10:53:56 AM UTC 24
Finished Aug 25 10:54:34 AM UTC 24
Peak memory 235032 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4149260427 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_pass_addr_payload_swap.4149260427
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/43.spi_device_pass_addr_payload_swap/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/43.spi_device_pass_cmd_filtering.3097326800
Short name T862
Test name
Test status
Simulation time 7233909560 ps
CPU time 11.27 seconds
Started Aug 25 10:53:56 AM UTC 24
Finished Aug 25 10:54:08 AM UTC 24
Peak memory 245420 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3097326800 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_08_24/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_pass_cmd_filtering.3097326800
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/43.spi_device_pass_cmd_filtering/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/43.spi_device_read_buffer_direct.2185555539
Short name T870
Test name
Test status
Simulation time 820756116 ps
CPU time 13.73 seconds
Started Aug 25 10:54:07 AM UTC 24
Finished Aug 25 10:54:22 AM UTC 24
Peak memory 231260 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2185555539 -assert nopostproc +UVM_TESTNAME=spi_device
_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_read_buffer_direct.2185555539
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/43.spi_device_read_buffer_direct/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/43.spi_device_stress_all.1868574843
Short name T174
Test name
Test status
Simulation time 119107613 ps
CPU time 1.57 seconds
Started Aug 25 10:54:10 AM UTC 24
Finished Aug 25 10:54:13 AM UTC 24
Peak memory 215760 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1868574843 -assert nopostproc +UVM_
TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra
tch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_stress_all.1868574843
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/43.spi_device_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/43.spi_device_tpm_all.429150909
Short name T890
Test name
Test status
Simulation time 7562700333 ps
CPU time 42.01 seconds
Started Aug 25 10:53:55 AM UTC 24
Finished Aug 25 10:54:38 AM UTC 24
Peak memory 231708 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=429150909 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/spi_
device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_all.429150909
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/43.spi_device_tpm_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/43.spi_device_tpm_read_hw_reg.2184685261
Short name T859
Test name
Test status
Simulation time 1273628006 ps
CPU time 8.82 seconds
Started Aug 25 10:53:52 AM UTC 24
Finished Aug 25 10:54:03 AM UTC 24
Peak memory 227500 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2184685261 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_24/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_read_hw_reg.2184685261
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/43.spi_device_tpm_read_hw_reg/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/43.spi_device_tpm_rw.3424718802
Short name T856
Test name
Test status
Simulation time 217334683 ps
CPU time 1.91 seconds
Started Aug 25 10:53:56 AM UTC 24
Finished Aug 25 10:53:59 AM UTC 24
Peak memory 216368 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3424718802 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/spi_
device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_rw.3424718802
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/43.spi_device_tpm_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/43.spi_device_tpm_sts_read.1737514343
Short name T854
Test name
Test status
Simulation time 23107450 ps
CPU time 1.18 seconds
Started Aug 25 10:53:55 AM UTC 24
Finished Aug 25 10:53:57 AM UTC 24
Peak memory 215872 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1737514343 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_2
4/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_sts_read.1737514343
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/43.spi_device_tpm_sts_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/43.spi_device_upload.2283321523
Short name T864
Test name
Test status
Simulation time 1247336050 ps
CPU time 10.66 seconds
Started Aug 25 10:53:59 AM UTC 24
Finished Aug 25 10:54:11 AM UTC 24
Peak memory 235044 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2283321523 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/spi_
device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_upload.2283321523
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/43.spi_device_upload/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/44.spi_device_alert_test.3334706723
Short name T882
Test name
Test status
Simulation time 14257441 ps
CPU time 1.08 seconds
Started Aug 25 10:54:31 AM UTC 24
Finished Aug 25 10:54:34 AM UTC 24
Peak memory 215748 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3334706723 -assert nopostproc +UVM_TES
TNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_
regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_alert_test.3334706723
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/44.spi_device_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/44.spi_device_cfg_cmd.3142118935
Short name T884
Test name
Test status
Simulation time 446119914 ps
CPU time 9.2 seconds
Started Aug 25 10:54:24 AM UTC 24
Finished Aug 25 10:54:34 AM UTC 24
Peak memory 234900 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3142118935 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/spi
_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_cfg_cmd.3142118935
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/44.spi_device_cfg_cmd/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/44.spi_device_csb_read.833153378
Short name T867
Test name
Test status
Simulation time 38303636 ps
CPU time 1.18 seconds
Started Aug 25 10:54:13 AM UTC 24
Finished Aug 25 10:54:15 AM UTC 24
Peak memory 215640 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=833153378 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/spi
_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_csb_read.833153378
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/44.spi_device_csb_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/44.spi_device_flash_all.374888740
Short name T897
Test name
Test status
Simulation time 1632506007 ps
CPU time 17.35 seconds
Started Aug 25 10:54:27 AM UTC 24
Finished Aug 25 10:54:46 AM UTC 24
Peak memory 249364 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=374888740 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/sp
i_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_all.374888740
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/44.spi_device_flash_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/44.spi_device_flash_and_tpm.1022092478
Short name T317
Test name
Test status
Simulation time 11209736530 ps
CPU time 257.5 seconds
Started Aug 25 10:54:27 AM UTC 24
Finished Aug 25 10:58:50 AM UTC 24
Peak memory 284432 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1022092478 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
24/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_and_tpm.1022092478
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/44.spi_device_flash_and_tpm/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/44.spi_device_flash_and_tpm_min_idle.3637172397
Short name T982
Test name
Test status
Simulation time 46579539766 ps
CPU time 140.95 seconds
Started Aug 25 10:54:27 AM UTC 24
Finished Aug 25 10:56:51 AM UTC 24
Peak memory 267960 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3637172397 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_and_tpm_min_idle.3637172397
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/44.spi_device_flash_and_tpm_min_idle/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/44.spi_device_flash_mode.3304526666
Short name T914
Test name
Test status
Simulation time 6872071807 ps
CPU time 40.83 seconds
Started Aug 25 10:54:24 AM UTC 24
Finished Aug 25 10:55:06 AM UTC 24
Peak memory 235092 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3304526666 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/
spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_mode.3304526666
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/44.spi_device_flash_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/44.spi_device_flash_mode_ignore_cmds.4210973095
Short name T78
Test name
Test status
Simulation time 77290015178 ps
CPU time 927.99 seconds
Started Aug 25 10:54:25 AM UTC 24
Finished Aug 25 11:10:06 AM UTC 24
Peak memory 278100 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4210973095 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_mode_ignore_cmds.4210973095
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/44.spi_device_flash_mode_ignore_cmds/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/44.spi_device_intercept.6765701
Short name T877
Test name
Test status
Simulation time 291422459 ps
CPU time 6.24 seconds
Started Aug 25 10:54:19 AM UTC 24
Finished Aug 25 10:54:27 AM UTC 24
Peak memory 245200 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=6765701 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/spi_
device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_intercept.6765701
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/44.spi_device_intercept/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/44.spi_device_mailbox.1522166582
Short name T878
Test name
Test status
Simulation time 481092408 ps
CPU time 6.71 seconds
Started Aug 25 10:54:22 AM UTC 24
Finished Aug 25 10:54:30 AM UTC 24
Peak memory 234904 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1522166582 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/spi
_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_mailbox.1522166582
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/44.spi_device_mailbox/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/44.spi_device_pass_addr_payload_swap.3816686420
Short name T883
Test name
Test status
Simulation time 6384092326 ps
CPU time 14.29 seconds
Started Aug 25 10:54:18 AM UTC 24
Finished Aug 25 10:54:34 AM UTC 24
Peak memory 261840 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3816686420 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_pass_addr_payload_swap.3816686420
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/44.spi_device_pass_addr_payload_swap/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/44.spi_device_pass_cmd_filtering.369942417
Short name T875
Test name
Test status
Simulation time 1044857478 ps
CPU time 6.71 seconds
Started Aug 25 10:54:18 AM UTC 24
Finished Aug 25 10:54:26 AM UTC 24
Peak memory 245200 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=369942417 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_08_24/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_pass_cmd_filtering.369942417
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/44.spi_device_pass_cmd_filtering/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/44.spi_device_read_buffer_direct.2210534085
Short name T896
Test name
Test status
Simulation time 897452142 ps
CPU time 15.62 seconds
Started Aug 25 10:54:26 AM UTC 24
Finished Aug 25 10:54:43 AM UTC 24
Peak memory 233384 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2210534085 -assert nopostproc +UVM_TESTNAME=spi_device
_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_read_buffer_direct.2210534085
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/44.spi_device_read_buffer_direct/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/44.spi_device_stress_all.3862210245
Short name T1000
Test name
Test status
Simulation time 74136146093 ps
CPU time 441.96 seconds
Started Aug 25 10:54:31 AM UTC 24
Finished Aug 25 11:02:01 AM UTC 24
Peak memory 265928 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3862210245 -assert nopostproc +UVM_
TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra
tch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_stress_all.3862210245
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/44.spi_device_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/44.spi_device_tpm_all.239131269
Short name T889
Test name
Test status
Simulation time 2950565498 ps
CPU time 22.61 seconds
Started Aug 25 10:54:14 AM UTC 24
Finished Aug 25 10:54:38 AM UTC 24
Peak memory 227612 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=239131269 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/spi_
device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_all.239131269
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/44.spi_device_tpm_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/44.spi_device_tpm_read_hw_reg.3337082037
Short name T872
Test name
Test status
Simulation time 516053122 ps
CPU time 7.48 seconds
Started Aug 25 10:54:14 AM UTC 24
Finished Aug 25 10:54:22 AM UTC 24
Peak memory 227548 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3337082037 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_24/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_read_hw_reg.3337082037
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/44.spi_device_tpm_read_hw_reg/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/44.spi_device_tpm_rw.3114207018
Short name T871
Test name
Test status
Simulation time 162789563 ps
CPU time 4.91 seconds
Started Aug 25 10:54:16 AM UTC 24
Finished Aug 25 10:54:22 AM UTC 24
Peak memory 227424 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3114207018 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/spi_
device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_rw.3114207018
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/44.spi_device_tpm_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/44.spi_device_tpm_sts_read.1087709298
Short name T868
Test name
Test status
Simulation time 152266966 ps
CPU time 1.3 seconds
Started Aug 25 10:54:15 AM UTC 24
Finished Aug 25 10:54:17 AM UTC 24
Peak memory 215872 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1087709298 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_2
4/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_sts_read.1087709298
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/44.spi_device_tpm_sts_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/44.spi_device_upload.2896217750
Short name T894
Test name
Test status
Simulation time 2690968392 ps
CPU time 16.93 seconds
Started Aug 25 10:54:23 AM UTC 24
Finished Aug 25 10:54:41 AM UTC 24
Peak memory 235028 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2896217750 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/spi_
device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_upload.2896217750
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/44.spi_device_upload/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/45.spi_device_alert_test.1629378980
Short name T902
Test name
Test status
Simulation time 26677446 ps
CPU time 1.12 seconds
Started Aug 25 10:54:48 AM UTC 24
Finished Aug 25 10:54:50 AM UTC 24
Peak memory 215684 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1629378980 -assert nopostproc +UVM_TES
TNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_
regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_alert_test.1629378980
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/45.spi_device_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/45.spi_device_cfg_cmd.1013326169
Short name T901
Test name
Test status
Simulation time 1022991027 ps
CPU time 8.15 seconds
Started Aug 25 10:54:40 AM UTC 24
Finished Aug 25 10:54:50 AM UTC 24
Peak memory 245220 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1013326169 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/spi
_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_cfg_cmd.1013326169
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/45.spi_device_cfg_cmd/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/45.spi_device_csb_read.3054909524
Short name T885
Test name
Test status
Simulation time 16191980 ps
CPU time 1.12 seconds
Started Aug 25 10:54:33 AM UTC 24
Finished Aug 25 10:54:35 AM UTC 24
Peak memory 215812 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3054909524 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/sp
i_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_csb_read.3054909524
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/45.spi_device_csb_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/45.spi_device_flash_all.2359481374
Short name T284
Test name
Test status
Simulation time 9777188680 ps
CPU time 60.22 seconds
Started Aug 25 10:54:41 AM UTC 24
Finished Aug 25 10:55:44 AM UTC 24
Peak memory 247408 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2359481374 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/s
pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_all.2359481374
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/45.spi_device_flash_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/45.spi_device_flash_and_tpm.1026574517
Short name T311
Test name
Test status
Simulation time 4196041218 ps
CPU time 55.34 seconds
Started Aug 25 10:54:43 AM UTC 24
Finished Aug 25 10:55:40 AM UTC 24
Peak memory 263940 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1026574517 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
24/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_and_tpm.1026574517
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/45.spi_device_flash_and_tpm/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/45.spi_device_flash_and_tpm_min_idle.2946416438
Short name T77
Test name
Test status
Simulation time 53262190728 ps
CPU time 854.6 seconds
Started Aug 25 10:54:44 AM UTC 24
Finished Aug 25 11:09:11 AM UTC 24
Peak memory 294548 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2946416438 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_and_tpm_min_idle.2946416438
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/45.spi_device_flash_and_tpm_min_idle/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/45.spi_device_flash_mode.3593294097
Short name T379
Test name
Test status
Simulation time 2024325975 ps
CPU time 42.8 seconds
Started Aug 25 10:54:40 AM UTC 24
Finished Aug 25 10:55:25 AM UTC 24
Peak memory 251352 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3593294097 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/
spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_mode.3593294097
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/45.spi_device_flash_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/45.spi_device_flash_mode_ignore_cmds.3843956460
Short name T963
Test name
Test status
Simulation time 30274589760 ps
CPU time 100.87 seconds
Started Aug 25 10:54:40 AM UTC 24
Finished Aug 25 10:56:24 AM UTC 24
Peak memory 265872 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3843956460 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_mode_ignore_cmds.3843956460
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/45.spi_device_flash_mode_ignore_cmds/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/45.spi_device_intercept.27239122
Short name T899
Test name
Test status
Simulation time 1345040556 ps
CPU time 6.83 seconds
Started Aug 25 10:54:38 AM UTC 24
Finished Aug 25 10:54:47 AM UTC 24
Peak memory 245148 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=27239122 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/spi
_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_intercept.27239122
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/45.spi_device_intercept/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/45.spi_device_mailbox.1961931436
Short name T911
Test name
Test status
Simulation time 5200331364 ps
CPU time 19.03 seconds
Started Aug 25 10:54:38 AM UTC 24
Finished Aug 25 10:54:59 AM UTC 24
Peak memory 245332 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1961931436 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/spi
_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_mailbox.1961931436
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/45.spi_device_mailbox/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/45.spi_device_pass_addr_payload_swap.2835762123
Short name T895
Test name
Test status
Simulation time 233430540 ps
CPU time 4.3 seconds
Started Aug 25 10:54:37 AM UTC 24
Finished Aug 25 10:54:43 AM UTC 24
Peak memory 245204 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2835762123 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_pass_addr_payload_swap.2835762123
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/45.spi_device_pass_addr_payload_swap/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/45.spi_device_pass_cmd_filtering.1205524109
Short name T907
Test name
Test status
Simulation time 11915248995 ps
CPU time 17.89 seconds
Started Aug 25 10:54:36 AM UTC 24
Finished Aug 25 10:54:55 AM UTC 24
Peak memory 241956 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1205524109 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_08_24/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_pass_cmd_filtering.1205524109
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/45.spi_device_pass_cmd_filtering/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/45.spi_device_read_buffer_direct.2505610469
Short name T898
Test name
Test status
Simulation time 325595516 ps
CPU time 4.7 seconds
Started Aug 25 10:54:40 AM UTC 24
Finished Aug 25 10:54:46 AM UTC 24
Peak memory 233744 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2505610469 -assert nopostproc +UVM_TESTNAME=spi_device
_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_read_buffer_direct.2505610469
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/45.spi_device_read_buffer_direct/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/45.spi_device_stress_all.3454287913
Short name T80
Test name
Test status
Simulation time 672253648408 ps
CPU time 1363.07 seconds
Started Aug 25 10:54:46 AM UTC 24
Finished Aug 25 11:17:48 AM UTC 24
Peak memory 300748 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3454287913 -assert nopostproc +UVM_
TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra
tch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_stress_all.3454287913
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/45.spi_device_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/45.spi_device_tpm_all.442360396
Short name T910
Test name
Test status
Simulation time 6137687791 ps
CPU time 22.17 seconds
Started Aug 25 10:54:35 AM UTC 24
Finished Aug 25 10:54:59 AM UTC 24
Peak memory 227548 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=442360396 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/spi_
device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_all.442360396
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/45.spi_device_tpm_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/45.spi_device_tpm_read_hw_reg.2965146015
Short name T887
Test name
Test status
Simulation time 10682180 ps
CPU time 1.11 seconds
Started Aug 25 10:54:35 AM UTC 24
Finished Aug 25 10:54:37 AM UTC 24
Peak memory 215808 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2965146015 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_24/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_read_hw_reg.2965146015
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/45.spi_device_tpm_read_hw_reg/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/45.spi_device_tpm_rw.3240771718
Short name T891
Test name
Test status
Simulation time 244422424 ps
CPU time 1.87 seconds
Started Aug 25 10:54:35 AM UTC 24
Finished Aug 25 10:54:38 AM UTC 24
Peak memory 226404 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3240771718 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/spi_
device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_rw.3240771718
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/45.spi_device_tpm_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/45.spi_device_tpm_sts_read.4071029896
Short name T888
Test name
Test status
Simulation time 59172952 ps
CPU time 1.14 seconds
Started Aug 25 10:54:35 AM UTC 24
Finished Aug 25 10:54:38 AM UTC 24
Peak memory 215824 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4071029896 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_2
4/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_sts_read.4071029896
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/45.spi_device_tpm_sts_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/45.spi_device_upload.3078285114
Short name T900
Test name
Test status
Simulation time 585367365 ps
CPU time 6.53 seconds
Started Aug 25 10:54:39 AM UTC 24
Finished Aug 25 10:54:47 AM UTC 24
Peak memory 245216 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3078285114 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/spi_
device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_upload.3078285114
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/45.spi_device_upload/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/46.spi_device_alert_test.2631866041
Short name T917
Test name
Test status
Simulation time 29383238 ps
CPU time 1.12 seconds
Started Aug 25 10:55:17 AM UTC 24
Finished Aug 25 10:55:19 AM UTC 24
Peak memory 215684 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2631866041 -assert nopostproc +UVM_TES
TNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_
regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_alert_test.2631866041
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/46.spi_device_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/46.spi_device_cfg_cmd.2091490239
Short name T916
Test name
Test status
Simulation time 14920286636 ps
CPU time 14.88 seconds
Started Aug 25 10:55:00 AM UTC 24
Finished Aug 25 10:55:16 AM UTC 24
Peak memory 234816 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2091490239 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/spi
_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_cfg_cmd.2091490239
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/46.spi_device_cfg_cmd/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/46.spi_device_csb_read.897407326
Short name T903
Test name
Test status
Simulation time 184409171 ps
CPU time 1.21 seconds
Started Aug 25 10:54:48 AM UTC 24
Finished Aug 25 10:54:50 AM UTC 24
Peak memory 215808 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=897407326 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/spi
_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_csb_read.897407326
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/46.spi_device_csb_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/46.spi_device_flash_all.2802657502
Short name T1007
Test name
Test status
Simulation time 88777620639 ps
CPU time 549.35 seconds
Started Aug 25 10:55:06 AM UTC 24
Finished Aug 25 11:04:24 AM UTC 24
Peak memory 263916 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2802657502 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/s
pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_all.2802657502
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/46.spi_device_flash_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/46.spi_device_flash_and_tpm.173462364
Short name T981
Test name
Test status
Simulation time 6286291480 ps
CPU time 101.12 seconds
Started Aug 25 10:55:07 AM UTC 24
Finished Aug 25 10:56:51 AM UTC 24
Peak memory 261768 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=173462364 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_2
4/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_and_tpm.173462364
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/46.spi_device_flash_and_tpm/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/46.spi_device_flash_and_tpm_min_idle.1132383071
Short name T976
Test name
Test status
Simulation time 119200098767 ps
CPU time 84.37 seconds
Started Aug 25 10:55:11 AM UTC 24
Finished Aug 25 10:56:39 AM UTC 24
Peak memory 251684 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1132383071 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_and_tpm_min_idle.1132383071
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/46.spi_device_flash_and_tpm_min_idle/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/46.spi_device_flash_mode.939203002
Short name T928
Test name
Test status
Simulation time 33776973195 ps
CPU time 44.8 seconds
Started Aug 25 10:55:00 AM UTC 24
Finished Aug 25 10:55:46 AM UTC 24
Peak memory 251488 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=939203002 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/s
pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_mode.939203002
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/46.spi_device_flash_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/46.spi_device_flash_mode_ignore_cmds.508030590
Short name T998
Test name
Test status
Simulation time 34191385062 ps
CPU time 372.59 seconds
Started Aug 25 10:55:01 AM UTC 24
Finished Aug 25 11:01:19 AM UTC 24
Peak memory 267992 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=508030590 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_24/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_mode_ignore_cmds.508030590
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/46.spi_device_flash_mode_ignore_cmds/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/46.spi_device_intercept.370811697
Short name T913
Test name
Test status
Simulation time 184128786 ps
CPU time 7.32 seconds
Started Aug 25 10:54:56 AM UTC 24
Finished Aug 25 10:55:05 AM UTC 24
Peak memory 245348 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=370811697 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/sp
i_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_intercept.370811697
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/46.spi_device_intercept/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/46.spi_device_mailbox.393757446
Short name T933
Test name
Test status
Simulation time 5378741706 ps
CPU time 51.41 seconds
Started Aug 25 10:54:56 AM UTC 24
Finished Aug 25 10:55:50 AM UTC 24
Peak memory 235032 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=393757446 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/spi_
device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_mailbox.393757446
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/46.spi_device_mailbox/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/46.spi_device_pass_addr_payload_swap.346020057
Short name T918
Test name
Test status
Simulation time 13882006122 ps
CPU time 23.29 seconds
Started Aug 25 10:54:55 AM UTC 24
Finished Aug 25 10:55:20 AM UTC 24
Peak memory 245456 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=346020057 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_24/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_pass_addr_payload_swap.346020057
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/46.spi_device_pass_addr_payload_swap/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/46.spi_device_pass_cmd_filtering.555785421
Short name T909
Test name
Test status
Simulation time 438252771 ps
CPU time 3.61 seconds
Started Aug 25 10:54:54 AM UTC 24
Finished Aug 25 10:54:59 AM UTC 24
Peak memory 234904 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=555785421 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_08_24/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_pass_cmd_filtering.555785421
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/46.spi_device_pass_cmd_filtering/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/46.spi_device_read_buffer_direct.486753404
Short name T915
Test name
Test status
Simulation time 520259444 ps
CPU time 6.14 seconds
Started Aug 25 10:55:04 AM UTC 24
Finished Aug 25 10:55:11 AM UTC 24
Peak memory 233540 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=486753404 -assert nopostproc +UVM_TESTNAME=spi_device_
base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_read_buffer_direct.486753404
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/46.spi_device_read_buffer_direct/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/46.spi_device_tpm_all.3379979735
Short name T876
Test name
Test status
Simulation time 34186366649 ps
CPU time 50.45 seconds
Started Aug 25 10:54:51 AM UTC 24
Finished Aug 25 10:55:43 AM UTC 24
Peak memory 227616 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3379979735 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/spi
_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_all.3379979735
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/46.spi_device_tpm_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/46.spi_device_tpm_read_hw_reg.1642355013
Short name T905
Test name
Test status
Simulation time 811451704 ps
CPU time 5.24 seconds
Started Aug 25 10:54:48 AM UTC 24
Finished Aug 25 10:54:55 AM UTC 24
Peak memory 227468 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1642355013 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_24/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_read_hw_reg.1642355013
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/46.spi_device_tpm_read_hw_reg/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/46.spi_device_tpm_rw.3055188438
Short name T906
Test name
Test status
Simulation time 161175743 ps
CPU time 3.21 seconds
Started Aug 25 10:54:51 AM UTC 24
Finished Aug 25 10:54:55 AM UTC 24
Peak memory 227456 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3055188438 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/spi_
device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_rw.3055188438
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/46.spi_device_tpm_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/46.spi_device_tpm_sts_read.4064634777
Short name T904
Test name
Test status
Simulation time 67829258 ps
CPU time 1.32 seconds
Started Aug 25 10:54:51 AM UTC 24
Finished Aug 25 10:54:53 AM UTC 24
Peak memory 215872 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4064634777 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_2
4/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_sts_read.4064634777
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/46.spi_device_tpm_sts_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/46.spi_device_upload.97772354
Short name T924
Test name
Test status
Simulation time 17803814744 ps
CPU time 29.94 seconds
Started Aug 25 10:55:00 AM UTC 24
Finished Aug 25 10:55:31 AM UTC 24
Peak memory 245096 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=97772354 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/spi_de
vice_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_upload.97772354
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/46.spi_device_upload/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/47.spi_device_alert_test.1097686609
Short name T932
Test name
Test status
Simulation time 41442621 ps
CPU time 1.1 seconds
Started Aug 25 10:55:47 AM UTC 24
Finished Aug 25 10:55:49 AM UTC 24
Peak memory 215684 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1097686609 -assert nopostproc +UVM_TES
TNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_
regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_alert_test.1097686609
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/47.spi_device_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/47.spi_device_cfg_cmd.2463931819
Short name T794
Test name
Test status
Simulation time 92652046 ps
CPU time 3.43 seconds
Started Aug 25 10:55:40 AM UTC 24
Finished Aug 25 10:55:45 AM UTC 24
Peak memory 245208 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2463931819 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/spi
_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_cfg_cmd.2463931819
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/47.spi_device_cfg_cmd/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/47.spi_device_csb_read.3443544576
Short name T919
Test name
Test status
Simulation time 51504153 ps
CPU time 1.13 seconds
Started Aug 25 10:55:20 AM UTC 24
Finished Aug 25 10:55:22 AM UTC 24
Peak memory 215520 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3443544576 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/sp
i_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_csb_read.3443544576
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/47.spi_device_csb_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/47.spi_device_flash_all.1269071089
Short name T995
Test name
Test status
Simulation time 17580299496 ps
CPU time 216.91 seconds
Started Aug 25 10:55:43 AM UTC 24
Finished Aug 25 10:59:25 AM UTC 24
Peak memory 261728 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1269071089 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/s
pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_all.1269071089
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/47.spi_device_flash_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/47.spi_device_flash_and_tpm.694962712
Short name T973
Test name
Test status
Simulation time 4890794893 ps
CPU time 45.41 seconds
Started Aug 25 10:55:45 AM UTC 24
Finished Aug 25 10:56:32 AM UTC 24
Peak memory 251536 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=694962712 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_2
4/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_and_tpm.694962712
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/47.spi_device_flash_and_tpm/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/47.spi_device_flash_and_tpm_min_idle.1620331417
Short name T966
Test name
Test status
Simulation time 4542495680 ps
CPU time 37.82 seconds
Started Aug 25 10:55:46 AM UTC 24
Finished Aug 25 10:56:26 AM UTC 24
Peak memory 265804 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1620331417 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_and_tpm_min_idle.1620331417
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/47.spi_device_flash_and_tpm_min_idle/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/47.spi_device_flash_mode.436638033
Short name T929
Test name
Test status
Simulation time 316579011 ps
CPU time 5.38 seconds
Started Aug 25 10:55:40 AM UTC 24
Finished Aug 25 10:55:47 AM UTC 24
Peak memory 234964 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=436638033 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/s
pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_mode.436638033
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/47.spi_device_flash_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/47.spi_device_flash_mode_ignore_cmds.767822194
Short name T270
Test name
Test status
Simulation time 3430233238 ps
CPU time 124.01 seconds
Started Aug 25 10:55:41 AM UTC 24
Finished Aug 25 10:57:48 AM UTC 24
Peak memory 280216 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=767822194 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_24/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_mode_ignore_cmds.767822194
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/47.spi_device_flash_mode_ignore_cmds/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/47.spi_device_intercept.1532615361
Short name T925
Test name
Test status
Simulation time 272649396 ps
CPU time 6.14 seconds
Started Aug 25 10:55:30 AM UTC 24
Finished Aug 25 10:55:37 AM UTC 24
Peak memory 245080 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1532615361 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/s
pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_intercept.1532615361
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/47.spi_device_intercept/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/47.spi_device_mailbox.4022643713
Short name T985
Test name
Test status
Simulation time 41923059588 ps
CPU time 120.95 seconds
Started Aug 25 10:55:32 AM UTC 24
Finished Aug 25 10:57:36 AM UTC 24
Peak memory 251424 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4022643713 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/spi
_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_mailbox.4022643713
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/47.spi_device_mailbox/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/47.spi_device_pass_addr_payload_swap.1492059413
Short name T955
Test name
Test status
Simulation time 32964857781 ps
CPU time 44.42 seconds
Started Aug 25 10:55:30 AM UTC 24
Finished Aug 25 10:56:16 AM UTC 24
Peak memory 251368 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1492059413 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_pass_addr_payload_swap.1492059413
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/47.spi_device_pass_addr_payload_swap/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/47.spi_device_pass_cmd_filtering.3737974847
Short name T930
Test name
Test status
Simulation time 6528576300 ps
CPU time 18.71 seconds
Started Aug 25 10:55:27 AM UTC 24
Finished Aug 25 10:55:48 AM UTC 24
Peak memory 245292 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3737974847 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_08_24/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_pass_cmd_filtering.3737974847
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/47.spi_device_pass_cmd_filtering/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/47.spi_device_read_buffer_direct.2109800366
Short name T948
Test name
Test status
Simulation time 1606853019 ps
CPU time 24.66 seconds
Started Aug 25 10:55:43 AM UTC 24
Finished Aug 25 10:56:10 AM UTC 24
Peak memory 233368 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2109800366 -assert nopostproc +UVM_TESTNAME=spi_device
_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_read_buffer_direct.2109800366
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/47.spi_device_read_buffer_direct/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/47.spi_device_stress_all.8134252
Short name T940
Test name
Test status
Simulation time 512665918 ps
CPU time 6.55 seconds
Started Aug 25 10:55:46 AM UTC 24
Finished Aug 25 10:55:54 AM UTC 24
Peak memory 229512 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=8134252 -assert nopostproc +UVM_TES
TNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_stress_all.8134252
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/47.spi_device_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/47.spi_device_tpm_all.812740251
Short name T946
Test name
Test status
Simulation time 5691935602 ps
CPU time 42.99 seconds
Started Aug 25 10:55:23 AM UTC 24
Finished Aug 25 10:56:08 AM UTC 24
Peak memory 227568 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=812740251 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/spi_
device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_all.812740251
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/47.spi_device_tpm_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/47.spi_device_tpm_read_hw_reg.3165460612
Short name T943
Test name
Test status
Simulation time 49228429682 ps
CPU time 39.72 seconds
Started Aug 25 10:55:21 AM UTC 24
Finished Aug 25 10:56:02 AM UTC 24
Peak memory 227620 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3165460612 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_24/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_read_hw_reg.3165460612
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/47.spi_device_tpm_read_hw_reg/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/47.spi_device_tpm_rw.1604989967
Short name T922
Test name
Test status
Simulation time 12682629 ps
CPU time 1.08 seconds
Started Aug 25 10:55:26 AM UTC 24
Finished Aug 25 10:55:28 AM UTC 24
Peak memory 215744 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1604989967 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/spi_
device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_rw.1604989967
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/47.spi_device_tpm_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/47.spi_device_tpm_sts_read.3220456273
Short name T921
Test name
Test status
Simulation time 42209342 ps
CPU time 1.17 seconds
Started Aug 25 10:55:24 AM UTC 24
Finished Aug 25 10:55:26 AM UTC 24
Peak memory 215872 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3220456273 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_2
4/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_sts_read.3220456273
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/47.spi_device_tpm_sts_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/47.spi_device_upload.1481961521
Short name T927
Test name
Test status
Simulation time 103066305 ps
CPU time 3.69 seconds
Started Aug 25 10:55:38 AM UTC 24
Finished Aug 25 10:55:43 AM UTC 24
Peak memory 245160 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1481961521 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/spi_
device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_upload.1481961521
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/47.spi_device_upload/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/48.spi_device_alert_test.3722417771
Short name T949
Test name
Test status
Simulation time 83388149 ps
CPU time 1.07 seconds
Started Aug 25 10:56:08 AM UTC 24
Finished Aug 25 10:56:10 AM UTC 24
Peak memory 215684 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3722417771 -assert nopostproc +UVM_TES
TNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_
regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_alert_test.3722417771
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/48.spi_device_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/48.spi_device_cfg_cmd.1841197380
Short name T945
Test name
Test status
Simulation time 432050600 ps
CPU time 5.89 seconds
Started Aug 25 10:55:55 AM UTC 24
Finished Aug 25 10:56:03 AM UTC 24
Peak memory 245212 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1841197380 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/spi
_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_cfg_cmd.1841197380
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/48.spi_device_cfg_cmd/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/48.spi_device_csb_read.4239234463
Short name T935
Test name
Test status
Simulation time 41854410 ps
CPU time 1.17 seconds
Started Aug 25 10:55:48 AM UTC 24
Finished Aug 25 10:55:51 AM UTC 24
Peak memory 215808 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4239234463 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/sp
i_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_csb_read.4239234463
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/48.spi_device_csb_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/48.spi_device_flash_all.3321643785
Short name T967
Test name
Test status
Simulation time 2393421220 ps
CPU time 20.99 seconds
Started Aug 25 10:56:04 AM UTC 24
Finished Aug 25 10:56:26 AM UTC 24
Peak memory 261740 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3321643785 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/s
pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_all.3321643785
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/48.spi_device_flash_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/48.spi_device_flash_and_tpm.836010281
Short name T990
Test name
Test status
Simulation time 25389916587 ps
CPU time 117.92 seconds
Started Aug 25 10:56:04 AM UTC 24
Finished Aug 25 10:58:04 AM UTC 24
Peak memory 263832 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=836010281 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_2
4/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_and_tpm.836010281
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/48.spi_device_flash_and_tpm/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/48.spi_device_flash_and_tpm_min_idle.293933631
Short name T307
Test name
Test status
Simulation time 24361526794 ps
CPU time 457.02 seconds
Started Aug 25 10:56:04 AM UTC 24
Finished Aug 25 11:03:48 AM UTC 24
Peak memory 276108 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=293933631 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_24/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_and_tpm_min_idle.293933631
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/48.spi_device_flash_and_tpm_min_idle/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/48.spi_device_flash_mode.1246664571
Short name T947
Test name
Test status
Simulation time 272613240 ps
CPU time 10.71 seconds
Started Aug 25 10:55:55 AM UTC 24
Finished Aug 25 10:56:08 AM UTC 24
Peak memory 245212 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1246664571 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/
spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_mode.1246664571
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/48.spi_device_flash_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/48.spi_device_flash_mode_ignore_cmds.1906741512
Short name T964
Test name
Test status
Simulation time 758553762 ps
CPU time 24.58 seconds
Started Aug 25 10:55:57 AM UTC 24
Finished Aug 25 10:56:24 AM UTC 24
Peak memory 245204 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1906741512 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_mode_ignore_cmds.1906741512
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/48.spi_device_flash_mode_ignore_cmds/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/48.spi_device_intercept.3710131796
Short name T961
Test name
Test status
Simulation time 2195078061 ps
CPU time 25.07 seconds
Started Aug 25 10:55:53 AM UTC 24
Finished Aug 25 10:56:20 AM UTC 24
Peak memory 234976 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3710131796 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/s
pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_intercept.3710131796
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/48.spi_device_intercept/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/48.spi_device_mailbox.1430813971
Short name T986
Test name
Test status
Simulation time 45173540476 ps
CPU time 108.52 seconds
Started Aug 25 10:55:54 AM UTC 24
Finished Aug 25 10:57:45 AM UTC 24
Peak memory 251432 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1430813971 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/spi
_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_mailbox.1430813971
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/48.spi_device_mailbox/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/48.spi_device_pass_addr_payload_swap.1998794560
Short name T941
Test name
Test status
Simulation time 663953000 ps
CPU time 3.43 seconds
Started Aug 25 10:55:52 AM UTC 24
Finished Aug 25 10:55:57 AM UTC 24
Peak memory 245200 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1998794560 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_pass_addr_payload_swap.1998794560
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/48.spi_device_pass_addr_payload_swap/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/48.spi_device_pass_cmd_filtering.2308212226
Short name T944
Test name
Test status
Simulation time 2648384485 ps
CPU time 9.1 seconds
Started Aug 25 10:55:52 AM UTC 24
Finished Aug 25 10:56:03 AM UTC 24
Peak memory 235056 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2308212226 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_08_24/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_pass_cmd_filtering.2308212226
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/48.spi_device_pass_cmd_filtering/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/48.spi_device_read_buffer_direct.1687902241
Short name T951
Test name
Test status
Simulation time 1728775659 ps
CPU time 9.16 seconds
Started Aug 25 10:55:59 AM UTC 24
Finished Aug 25 10:56:10 AM UTC 24
Peak memory 233648 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1687902241 -assert nopostproc +UVM_TESTNAME=spi_device
_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_read_buffer_direct.1687902241
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/48.spi_device_read_buffer_direct/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/48.spi_device_stress_all.3300449350
Short name T994
Test name
Test status
Simulation time 10499756441 ps
CPU time 191.82 seconds
Started Aug 25 10:56:05 AM UTC 24
Finished Aug 25 10:59:20 AM UTC 24
Peak memory 280332 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3300449350 -assert nopostproc +UVM_
TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra
tch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_stress_all.3300449350
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/48.spi_device_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/48.spi_device_tpm_all.1391153797
Short name T942
Test name
Test status
Simulation time 876551945 ps
CPU time 7.59 seconds
Started Aug 25 10:55:49 AM UTC 24
Finished Aug 25 10:55:58 AM UTC 24
Peak memory 227484 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1391153797 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/spi
_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_all.1391153797
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/48.spi_device_tpm_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/48.spi_device_tpm_read_hw_reg.4232025734
Short name T939
Test name
Test status
Simulation time 289901563 ps
CPU time 4.05 seconds
Started Aug 25 10:55:48 AM UTC 24
Finished Aug 25 10:55:54 AM UTC 24
Peak memory 227552 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4232025734 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_24/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_read_hw_reg.4232025734
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/48.spi_device_tpm_read_hw_reg/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/48.spi_device_tpm_rw.3870802075
Short name T937
Test name
Test status
Simulation time 29633590 ps
CPU time 1.07 seconds
Started Aug 25 10:55:50 AM UTC 24
Finished Aug 25 10:55:53 AM UTC 24
Peak memory 215744 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3870802075 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/spi_
device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_rw.3870802075
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/48.spi_device_tpm_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/48.spi_device_tpm_sts_read.2649433722
Short name T938
Test name
Test status
Simulation time 73628947 ps
CPU time 1.27 seconds
Started Aug 25 10:55:50 AM UTC 24
Finished Aug 25 10:55:53 AM UTC 24
Peak memory 215872 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2649433722 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_2
4/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_sts_read.2649433722
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/48.spi_device_tpm_sts_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/48.spi_device_upload.670357704
Short name T980
Test name
Test status
Simulation time 18708696615 ps
CPU time 54.2 seconds
Started Aug 25 10:55:54 AM UTC 24
Finished Aug 25 10:56:51 AM UTC 24
Peak memory 245272 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=670357704 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/spi_d
evice_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_upload.670357704
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/48.spi_device_upload/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/49.spi_device_alert_test.155225378
Short name T969
Test name
Test status
Simulation time 12508514 ps
CPU time 1.1 seconds
Started Aug 25 10:56:25 AM UTC 24
Finished Aug 25 10:56:27 AM UTC 24
Peak memory 215632 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=155225378 -assert nopostproc +UVM_TEST
NAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_alert_test.155225378
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/49.spi_device_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/49.spi_device_cfg_cmd.772772018
Short name T965
Test name
Test status
Simulation time 161647312 ps
CPU time 5.14 seconds
Started Aug 25 10:56:18 AM UTC 24
Finished Aug 25 10:56:24 AM UTC 24
Peak memory 235044 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=772772018 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/spi_
device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_cfg_cmd.772772018
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/49.spi_device_cfg_cmd/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/49.spi_device_csb_read.1242315605
Short name T950
Test name
Test status
Simulation time 56116289 ps
CPU time 1.12 seconds
Started Aug 25 10:56:08 AM UTC 24
Finished Aug 25 10:56:10 AM UTC 24
Peak memory 215812 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1242315605 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/sp
i_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_csb_read.1242315605
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/49.spi_device_csb_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/49.spi_device_flash_all.719225007
Short name T978
Test name
Test status
Simulation time 979115682 ps
CPU time 22.55 seconds
Started Aug 25 10:56:20 AM UTC 24
Finished Aug 25 10:56:44 AM UTC 24
Peak memory 247248 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=719225007 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/sp
i_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_all.719225007
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/49.spi_device_flash_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/49.spi_device_flash_and_tpm.3870430517
Short name T75
Test name
Test status
Simulation time 45875684988 ps
CPU time 710.28 seconds
Started Aug 25 10:56:21 AM UTC 24
Finished Aug 25 11:08:22 AM UTC 24
Peak memory 278160 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3870430517 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
24/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_and_tpm.3870430517
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/49.spi_device_flash_and_tpm/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/49.spi_device_flash_and_tpm_min_idle.626543689
Short name T989
Test name
Test status
Simulation time 6387532047 ps
CPU time 92.7 seconds
Started Aug 25 10:56:25 AM UTC 24
Finished Aug 25 10:58:00 AM UTC 24
Peak memory 267912 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=626543689 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_24/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_and_tpm_min_idle.626543689
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/49.spi_device_flash_and_tpm_min_idle/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/49.spi_device_flash_mode.838216516
Short name T968
Test name
Test status
Simulation time 189605662 ps
CPU time 5.94 seconds
Started Aug 25 10:56:19 AM UTC 24
Finished Aug 25 10:56:26 AM UTC 24
Peak memory 245220 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=838216516 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/s
pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_mode.838216516
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/49.spi_device_flash_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/49.spi_device_flash_mode_ignore_cmds.1008745629
Short name T996
Test name
Test status
Simulation time 16530622963 ps
CPU time 190.47 seconds
Started Aug 25 10:56:19 AM UTC 24
Finished Aug 25 10:59:33 AM UTC 24
Peak memory 261728 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1008745629 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_mode_ignore_cmds.1008745629
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/49.spi_device_flash_mode_ignore_cmds/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/49.spi_device_intercept.1695989799
Short name T959
Test name
Test status
Simulation time 35331135 ps
CPU time 3.24 seconds
Started Aug 25 10:56:14 AM UTC 24
Finished Aug 25 10:56:18 AM UTC 24
Peak memory 244956 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1695989799 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/s
pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_intercept.1695989799
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/49.spi_device_intercept/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/49.spi_device_mailbox.4093998918
Short name T984
Test name
Test status
Simulation time 20883978277 ps
CPU time 77.18 seconds
Started Aug 25 10:56:15 AM UTC 24
Finished Aug 25 10:57:34 AM UTC 24
Peak memory 261708 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4093998918 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/spi
_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_mailbox.4093998918
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/49.spi_device_mailbox/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/49.spi_device_pass_addr_payload_swap.29784642
Short name T958
Test name
Test status
Simulation time 30067810 ps
CPU time 3.26 seconds
Started Aug 25 10:56:14 AM UTC 24
Finished Aug 25 10:56:18 AM UTC 24
Peak memory 244972 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=29784642 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_24/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_pass_addr_payload_swap.29784642
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/49.spi_device_pass_addr_payload_swap/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/49.spi_device_pass_cmd_filtering.1871631917
Short name T960
Test name
Test status
Simulation time 1004139427 ps
CPU time 6.13 seconds
Started Aug 25 10:56:12 AM UTC 24
Finished Aug 25 10:56:19 AM UTC 24
Peak memory 234948 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1871631917 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_08_24/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_pass_cmd_filtering.1871631917
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/49.spi_device_pass_cmd_filtering/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/49.spi_device_read_buffer_direct.1887456166
Short name T977
Test name
Test status
Simulation time 2268552658 ps
CPU time 18.65 seconds
Started Aug 25 10:56:20 AM UTC 24
Finished Aug 25 10:56:39 AM UTC 24
Peak memory 233448 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1887456166 -assert nopostproc +UVM_TESTNAME=spi_device
_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_read_buffer_direct.1887456166
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/49.spi_device_read_buffer_direct/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/49.spi_device_stress_all.2743689317
Short name T1001
Test name
Test status
Simulation time 77316722852 ps
CPU time 339.07 seconds
Started Aug 25 10:56:25 AM UTC 24
Finished Aug 25 11:02:10 AM UTC 24
Peak memory 284268 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2743689317 -assert nopostproc +UVM_
TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra
tch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_stress_all.2743689317
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/49.spi_device_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/49.spi_device_tpm_all.3260195951
Short name T952
Test name
Test status
Simulation time 23351018 ps
CPU time 1.14 seconds
Started Aug 25 10:56:10 AM UTC 24
Finished Aug 25 10:56:12 AM UTC 24
Peak memory 215744 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3260195951 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/spi
_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_all.3260195951
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/49.spi_device_tpm_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/49.spi_device_tpm_read_hw_reg.1980110940
Short name T972
Test name
Test status
Simulation time 13697959441 ps
CPU time 19.57 seconds
Started Aug 25 10:56:09 AM UTC 24
Finished Aug 25 10:56:30 AM UTC 24
Peak memory 227576 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1980110940 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_24/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_read_hw_reg.1980110940
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/49.spi_device_tpm_read_hw_reg/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/49.spi_device_tpm_rw.4037883348
Short name T956
Test name
Test status
Simulation time 554613258 ps
CPU time 4.89 seconds
Started Aug 25 10:56:12 AM UTC 24
Finished Aug 25 10:56:17 AM UTC 24
Peak memory 227420 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4037883348 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/spi_
device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_rw.4037883348
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/49.spi_device_tpm_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/49.spi_device_tpm_sts_read.2712516631
Short name T954
Test name
Test status
Simulation time 180604323 ps
CPU time 1.37 seconds
Started Aug 25 10:56:11 AM UTC 24
Finished Aug 25 10:56:14 AM UTC 24
Peak memory 215872 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2712516631 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_2
4/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_sts_read.2712516631
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/49.spi_device_tpm_sts_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/49.spi_device_upload.2846600481
Short name T971
Test name
Test status
Simulation time 12921170804 ps
CPU time 11.03 seconds
Started Aug 25 10:56:17 AM UTC 24
Finished Aug 25 10:56:29 AM UTC 24
Peak memory 235088 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2846600481 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/spi_
device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_upload.2846600481
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/49.spi_device_upload/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/5.spi_device_alert_test.3742487453
Short name T421
Test name
Test status
Simulation time 29488657 ps
CPU time 1.04 seconds
Started Aug 25 10:42:42 AM UTC 24
Finished Aug 25 10:42:46 AM UTC 24
Peak memory 215684 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3742487453 -assert nopostproc +UVM_TES
TNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_
regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_alert_test.3742487453
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/5.spi_device_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/5.spi_device_cfg_cmd.179399869
Short name T90
Test name
Test status
Simulation time 501755599 ps
CPU time 3.15 seconds
Started Aug 25 10:42:37 AM UTC 24
Finished Aug 25 10:42:41 AM UTC 24
Peak memory 235044 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=179399869 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/spi_
device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_cfg_cmd.179399869
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/5.spi_device_cfg_cmd/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/5.spi_device_csb_read.2326110656
Short name T418
Test name
Test status
Simulation time 114293722 ps
CPU time 1.12 seconds
Started Aug 25 10:42:29 AM UTC 24
Finished Aug 25 10:42:31 AM UTC 24
Peak memory 215868 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2326110656 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/sp
i_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_csb_read.2326110656
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/5.spi_device_csb_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/5.spi_device_flash_all.222130992
Short name T240
Test name
Test status
Simulation time 37472291853 ps
CPU time 446.32 seconds
Started Aug 25 10:42:41 AM UTC 24
Finished Aug 25 10:50:14 AM UTC 24
Peak memory 265888 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=222130992 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/sp
i_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_all.222130992
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/5.spi_device_flash_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/5.spi_device_flash_and_tpm_min_idle.617581203
Short name T594
Test name
Test status
Simulation time 287241458284 ps
CPU time 384.45 seconds
Started Aug 25 10:42:42 AM UTC 24
Finished Aug 25 10:49:14 AM UTC 24
Peak memory 278136 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=617581203 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_24/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_and_tpm_min_idle.617581203
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/5.spi_device_flash_and_tpm_min_idle/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/5.spi_device_flash_mode.1240163038
Short name T183
Test name
Test status
Simulation time 193885258 ps
CPU time 3.75 seconds
Started Aug 25 10:42:37 AM UTC 24
Finished Aug 25 10:42:42 AM UTC 24
Peak memory 245140 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1240163038 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/
spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_mode.1240163038
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/5.spi_device_flash_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/5.spi_device_intercept.3405056565
Short name T177
Test name
Test status
Simulation time 3702707057 ps
CPU time 8.93 seconds
Started Aug 25 10:42:34 AM UTC 24
Finished Aug 25 10:42:44 AM UTC 24
Peak memory 244084 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3405056565 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/s
pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_intercept.3405056565
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/5.spi_device_intercept/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/5.spi_device_mailbox.1817511990
Short name T214
Test name
Test status
Simulation time 4937737308 ps
CPU time 11.1 seconds
Started Aug 25 10:42:34 AM UTC 24
Finished Aug 25 10:42:46 AM UTC 24
Peak memory 235088 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1817511990 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/spi
_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_mailbox.1817511990
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/5.spi_device_mailbox/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/5.spi_device_pass_addr_payload_swap.1600554732
Short name T419
Test name
Test status
Simulation time 30330569 ps
CPU time 3.19 seconds
Started Aug 25 10:42:34 AM UTC 24
Finished Aug 25 10:42:38 AM UTC 24
Peak memory 244840 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1600554732 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_pass_addr_payload_swap.1600554732
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/5.spi_device_pass_addr_payload_swap/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/5.spi_device_pass_cmd_filtering.2991767837
Short name T187
Test name
Test status
Simulation time 15485263702 ps
CPU time 43.69 seconds
Started Aug 25 10:42:32 AM UTC 24
Finished Aug 25 10:43:17 AM UTC 24
Peak memory 245332 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2991767837 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_08_24/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_pass_cmd_filtering.2991767837
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/5.spi_device_pass_cmd_filtering/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/5.spi_device_read_buffer_direct.3750243394
Short name T159
Test name
Test status
Simulation time 2002174007 ps
CPU time 8.18 seconds
Started Aug 25 10:42:39 AM UTC 24
Finished Aug 25 10:42:48 AM UTC 24
Peak memory 233368 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3750243394 -assert nopostproc +UVM_TESTNAME=spi_device
_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_read_buffer_direct.3750243394
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/5.spi_device_read_buffer_direct/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/5.spi_device_tpm_read_hw_reg.2669022949
Short name T420
Test name
Test status
Simulation time 5663353262 ps
CPU time 12.45 seconds
Started Aug 25 10:42:29 AM UTC 24
Finished Aug 25 10:42:43 AM UTC 24
Peak memory 227556 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2669022949 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_24/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_read_hw_reg.2669022949
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/5.spi_device_tpm_read_hw_reg/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/5.spi_device_tpm_rw.2830524345
Short name T69
Test name
Test status
Simulation time 22597253 ps
CPU time 1.27 seconds
Started Aug 25 10:42:32 AM UTC 24
Finished Aug 25 10:42:34 AM UTC 24
Peak memory 215868 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2830524345 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/spi_
device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_rw.2830524345
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/5.spi_device_tpm_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/5.spi_device_tpm_sts_read.4132440096
Short name T1
Test name
Test status
Simulation time 128267961 ps
CPU time 1.28 seconds
Started Aug 25 10:42:32 AM UTC 24
Finished Aug 25 10:42:34 AM UTC 24
Peak memory 215868 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4132440096 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_2
4/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_sts_read.4132440096
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/5.spi_device_tpm_sts_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/6.spi_device_alert_test.364797585
Short name T429
Test name
Test status
Simulation time 12975037 ps
CPU time 1.08 seconds
Started Aug 25 10:42:52 AM UTC 24
Finished Aug 25 10:42:54 AM UTC 24
Peak memory 215684 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=364797585 -assert nopostproc +UVM_TEST
NAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_alert_test.364797585
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/6.spi_device_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/6.spi_device_cfg_cmd.681174538
Short name T248
Test name
Test status
Simulation time 403705428 ps
CPU time 6.37 seconds
Started Aug 25 10:42:49 AM UTC 24
Finished Aug 25 10:42:57 AM UTC 24
Peak memory 245160 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=681174538 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/spi_
device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_cfg_cmd.681174538
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/6.spi_device_cfg_cmd/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/6.spi_device_csb_read.2377523438
Short name T423
Test name
Test status
Simulation time 60521941 ps
CPU time 1.04 seconds
Started Aug 25 10:42:44 AM UTC 24
Finished Aug 25 10:42:47 AM UTC 24
Peak memory 215808 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2377523438 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/sp
i_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_csb_read.2377523438
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/6.spi_device_csb_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/6.spi_device_flash_all.3865426885
Short name T583
Test name
Test status
Simulation time 56763645331 ps
CPU time 363 seconds
Started Aug 25 10:42:50 AM UTC 24
Finished Aug 25 10:48:59 AM UTC 24
Peak memory 263828 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3865426885 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/s
pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_all.3865426885
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/6.spi_device_flash_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/6.spi_device_flash_and_tpm.3734762799
Short name T61
Test name
Test status
Simulation time 29515500332 ps
CPU time 180.21 seconds
Started Aug 25 10:42:50 AM UTC 24
Finished Aug 25 10:45:54 AM UTC 24
Peak memory 265876 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3734762799 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
24/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_and_tpm.3734762799
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/6.spi_device_flash_and_tpm/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/6.spi_device_flash_and_tpm_min_idle.1271792730
Short name T541
Test name
Test status
Simulation time 44204057187 ps
CPU time 295.08 seconds
Started Aug 25 10:42:52 AM UTC 24
Finished Aug 25 10:47:52 AM UTC 24
Peak memory 251544 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1271792730 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_and_tpm_min_idle.1271792730
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/6.spi_device_flash_and_tpm_min_idle/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/6.spi_device_intercept.2959462311
Short name T87
Test name
Test status
Simulation time 1270774905 ps
CPU time 17.38 seconds
Started Aug 25 10:42:49 AM UTC 24
Finished Aug 25 10:43:08 AM UTC 24
Peak memory 234904 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2959462311 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/s
pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_intercept.2959462311
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/6.spi_device_intercept/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/6.spi_device_mailbox.4222307681
Short name T428
Test name
Test status
Simulation time 32331285 ps
CPU time 3 seconds
Started Aug 25 10:42:49 AM UTC 24
Finished Aug 25 10:42:53 AM UTC 24
Peak memory 244952 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4222307681 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/spi
_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_mailbox.4222307681
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/6.spi_device_mailbox/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/6.spi_device_pass_addr_payload_swap.1304720564
Short name T427
Test name
Test status
Simulation time 203210145 ps
CPU time 3.24 seconds
Started Aug 25 10:42:47 AM UTC 24
Finished Aug 25 10:42:52 AM UTC 24
Peak memory 234656 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1304720564 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_pass_addr_payload_swap.1304720564
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/6.spi_device_pass_addr_payload_swap/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/6.spi_device_pass_cmd_filtering.1925695621
Short name T58
Test name
Test status
Simulation time 1799115288 ps
CPU time 12.02 seconds
Started Aug 25 10:42:47 AM UTC 24
Finished Aug 25 10:43:00 AM UTC 24
Peak memory 245268 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1925695621 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_08_24/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_pass_cmd_filtering.1925695621
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/6.spi_device_pass_cmd_filtering/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/6.spi_device_read_buffer_direct.1280511536
Short name T160
Test name
Test status
Simulation time 236856947 ps
CPU time 5.27 seconds
Started Aug 25 10:42:50 AM UTC 24
Finished Aug 25 10:42:56 AM UTC 24
Peak memory 231264 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1280511536 -assert nopostproc +UVM_TESTNAME=spi_device
_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_read_buffer_direct.1280511536
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/6.spi_device_read_buffer_direct/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/6.spi_device_tpm_all.877323277
Short name T392
Test name
Test status
Simulation time 38428130564 ps
CPU time 42.84 seconds
Started Aug 25 10:42:47 AM UTC 24
Finished Aug 25 10:43:31 AM UTC 24
Peak memory 227612 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=877323277 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/spi_
device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_all.877323277
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/6.spi_device_tpm_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/6.spi_device_tpm_read_hw_reg.3209026421
Short name T424
Test name
Test status
Simulation time 168341605 ps
CPU time 1.43 seconds
Started Aug 25 10:42:47 AM UTC 24
Finished Aug 25 10:42:49 AM UTC 24
Peak memory 215876 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3209026421 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_24/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_read_hw_reg.3209026421
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/6.spi_device_tpm_read_hw_reg/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/6.spi_device_tpm_rw.3937028949
Short name T396
Test name
Test status
Simulation time 102366539 ps
CPU time 2.83 seconds
Started Aug 25 10:42:47 AM UTC 24
Finished Aug 25 10:42:51 AM UTC 24
Peak memory 227424 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3937028949 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/spi_
device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_rw.3937028949
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/6.spi_device_tpm_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/6.spi_device_tpm_sts_read.3136987826
Short name T425
Test name
Test status
Simulation time 52601693 ps
CPU time 1.34 seconds
Started Aug 25 10:42:47 AM UTC 24
Finished Aug 25 10:42:50 AM UTC 24
Peak memory 215868 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3136987826 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_2
4/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_sts_read.3136987826
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/6.spi_device_tpm_sts_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/6.spi_device_upload.859986216
Short name T224
Test name
Test status
Simulation time 1303443522 ps
CPU time 8.25 seconds
Started Aug 25 10:42:49 AM UTC 24
Finished Aug 25 10:42:58 AM UTC 24
Peak memory 234904 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=859986216 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/spi_d
evice_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_upload.859986216
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/6.spi_device_upload/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/7.spi_device_alert_test.305492791
Short name T435
Test name
Test status
Simulation time 23688668 ps
CPU time 1.11 seconds
Started Aug 25 10:43:07 AM UTC 24
Finished Aug 25 10:43:09 AM UTC 24
Peak memory 215684 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=305492791 -assert nopostproc +UVM_TEST
NAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_alert_test.305492791
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/7.spi_device_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/7.spi_device_cfg_cmd.1825365660
Short name T192
Test name
Test status
Simulation time 105564536 ps
CPU time 3.75 seconds
Started Aug 25 10:43:00 AM UTC 24
Finished Aug 25 10:43:05 AM UTC 24
Peak memory 234896 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1825365660 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/spi
_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_cfg_cmd.1825365660
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/7.spi_device_cfg_cmd/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/7.spi_device_csb_read.2554629342
Short name T430
Test name
Test status
Simulation time 23243277 ps
CPU time 1.19 seconds
Started Aug 25 10:42:52 AM UTC 24
Finished Aug 25 10:42:54 AM UTC 24
Peak memory 215808 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2554629342 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/sp
i_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_csb_read.2554629342
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/7.spi_device_csb_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/7.spi_device_flash_all.2807349110
Short name T64
Test name
Test status
Simulation time 2207854198 ps
CPU time 63.75 seconds
Started Aug 25 10:43:02 AM UTC 24
Finished Aug 25 10:44:08 AM UTC 24
Peak memory 278124 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2807349110 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/s
pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_all.2807349110
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/7.spi_device_flash_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/7.spi_device_flash_and_tpm.1542941626
Short name T712
Test name
Test status
Simulation time 76481361422 ps
CPU time 493.87 seconds
Started Aug 25 10:43:06 AM UTC 24
Finished Aug 25 10:51:28 AM UTC 24
Peak memory 261796 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1542941626 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
24/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_and_tpm.1542941626
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/7.spi_device_flash_and_tpm/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/7.spi_device_flash_and_tpm_min_idle.2816836245
Short name T269
Test name
Test status
Simulation time 78787189410 ps
CPU time 307.64 seconds
Started Aug 25 10:43:06 AM UTC 24
Finished Aug 25 10:48:19 AM UTC 24
Peak memory 263820 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2816836245 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_and_tpm_min_idle.2816836245
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/7.spi_device_flash_and_tpm_min_idle/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/7.spi_device_flash_mode.291320396
Short name T372
Test name
Test status
Simulation time 5908305260 ps
CPU time 34.7 seconds
Started Aug 25 10:43:00 AM UTC 24
Finished Aug 25 10:43:37 AM UTC 24
Peak memory 235160 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=291320396 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/s
pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_mode.291320396
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/7.spi_device_flash_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/7.spi_device_flash_mode_ignore_cmds.3808050695
Short name T336
Test name
Test status
Simulation time 168623989570 ps
CPU time 163.12 seconds
Started Aug 25 10:43:01 AM UTC 24
Finished Aug 25 10:45:48 AM UTC 24
Peak memory 261708 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3808050695 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_mode_ignore_cmds.3808050695
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/7.spi_device_flash_mode_ignore_cmds/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/7.spi_device_intercept.62628397
Short name T260
Test name
Test status
Simulation time 3624731805 ps
CPU time 9.22 seconds
Started Aug 25 10:42:57 AM UTC 24
Finished Aug 25 10:43:08 AM UTC 24
Peak memory 235096 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=62628397 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/spi
_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_intercept.62628397
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/7.spi_device_intercept/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/7.spi_device_mailbox.2897615667
Short name T191
Test name
Test status
Simulation time 2424489337 ps
CPU time 18.7 seconds
Started Aug 25 10:42:58 AM UTC 24
Finished Aug 25 10:43:18 AM UTC 24
Peak memory 249440 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2897615667 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/spi
_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_mailbox.2897615667
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/7.spi_device_mailbox/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/7.spi_device_pass_addr_payload_swap.3156345678
Short name T433
Test name
Test status
Simulation time 98937659 ps
CPU time 3.09 seconds
Started Aug 25 10:42:57 AM UTC 24
Finished Aug 25 10:43:01 AM UTC 24
Peak memory 234364 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3156345678 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_pass_addr_payload_swap.3156345678
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/7.spi_device_pass_addr_payload_swap/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/7.spi_device_pass_cmd_filtering.3504056248
Short name T215
Test name
Test status
Simulation time 78791936 ps
CPU time 3.3 seconds
Started Aug 25 10:42:56 AM UTC 24
Finished Aug 25 10:43:01 AM UTC 24
Peak memory 234944 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3504056248 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_08_24/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_pass_cmd_filtering.3504056248
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/7.spi_device_pass_cmd_filtering/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/7.spi_device_read_buffer_direct.640323285
Short name T162
Test name
Test status
Simulation time 1323648737 ps
CPU time 6.21 seconds
Started Aug 25 10:43:01 AM UTC 24
Finished Aug 25 10:43:09 AM UTC 24
Peak memory 233368 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=640323285 -assert nopostproc +UVM_TESTNAME=spi_device_
base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_read_buffer_direct.640323285
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/7.spi_device_read_buffer_direct/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/7.spi_device_stress_all.1694683275
Short name T301
Test name
Test status
Simulation time 65954917992 ps
CPU time 922.8 seconds
Started Aug 25 10:43:06 AM UTC 24
Finished Aug 25 10:58:41 AM UTC 24
Peak memory 280272 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1694683275 -assert nopostproc +UVM_
TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra
tch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_stress_all.1694683275
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/7.spi_device_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/7.spi_device_tpm_all.3740528108
Short name T404
Test name
Test status
Simulation time 9716507637 ps
CPU time 8.92 seconds
Started Aug 25 10:42:55 AM UTC 24
Finished Aug 25 10:43:05 AM UTC 24
Peak memory 227612 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3740528108 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/spi
_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_all.3740528108
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/7.spi_device_tpm_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/7.spi_device_tpm_read_hw_reg.3476331969
Short name T437
Test name
Test status
Simulation time 12282980243 ps
CPU time 16.94 seconds
Started Aug 25 10:42:54 AM UTC 24
Finished Aug 25 10:43:12 AM UTC 24
Peak memory 227564 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3476331969 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_24/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_read_hw_reg.3476331969
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/7.spi_device_tpm_read_hw_reg/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/7.spi_device_tpm_rw.2655446641
Short name T408
Test name
Test status
Simulation time 107945612 ps
CPU time 2 seconds
Started Aug 25 10:42:55 AM UTC 24
Finished Aug 25 10:42:58 AM UTC 24
Peak memory 226536 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2655446641 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/spi_
device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_rw.2655446641
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/7.spi_device_tpm_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/7.spi_device_tpm_sts_read.429920966
Short name T431
Test name
Test status
Simulation time 85789118 ps
CPU time 1.23 seconds
Started Aug 25 10:42:55 AM UTC 24
Finished Aug 25 10:42:57 AM UTC 24
Peak memory 215864 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=429920966 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24
/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_sts_read.429920966
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/7.spi_device_tpm_sts_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/7.spi_device_upload.762722702
Short name T434
Test name
Test status
Simulation time 41519066 ps
CPU time 2.93 seconds
Started Aug 25 10:43:00 AM UTC 24
Finished Aug 25 10:43:04 AM UTC 24
Peak memory 234632 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=762722702 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/spi_d
evice_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_upload.762722702
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/7.spi_device_upload/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/8.spi_device_alert_test.123421878
Short name T442
Test name
Test status
Simulation time 153538610 ps
CPU time 1.12 seconds
Started Aug 25 10:43:24 AM UTC 24
Finished Aug 25 10:43:27 AM UTC 24
Peak memory 215744 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=123421878 -assert nopostproc +UVM_TEST
NAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_alert_test.123421878
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/8.spi_device_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/8.spi_device_cfg_cmd.1095340202
Short name T256
Test name
Test status
Simulation time 2107426933 ps
CPU time 20.16 seconds
Started Aug 25 10:43:17 AM UTC 24
Finished Aug 25 10:43:38 AM UTC 24
Peak memory 245216 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1095340202 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/spi
_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_cfg_cmd.1095340202
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/8.spi_device_cfg_cmd/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/8.spi_device_csb_read.3818611492
Short name T436
Test name
Test status
Simulation time 45925472 ps
CPU time 1.21 seconds
Started Aug 25 10:43:08 AM UTC 24
Finished Aug 25 10:43:11 AM UTC 24
Peak memory 215580 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3818611492 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/sp
i_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_csb_read.3818611492
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/8.spi_device_csb_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/8.spi_device_flash_all.2404890123
Short name T608
Test name
Test status
Simulation time 139904859568 ps
CPU time 369.96 seconds
Started Aug 25 10:43:20 AM UTC 24
Finished Aug 25 10:49:36 AM UTC 24
Peak memory 267864 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2404890123 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/s
pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_all.2404890123
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/8.spi_device_flash_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/8.spi_device_flash_and_tpm.1904097495
Short name T84
Test name
Test status
Simulation time 6111432908 ps
CPU time 56.68 seconds
Started Aug 25 10:43:21 AM UTC 24
Finished Aug 25 10:44:19 AM UTC 24
Peak memory 261752 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1904097495 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
24/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_and_tpm.1904097495
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/8.spi_device_flash_and_tpm/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/8.spi_device_flash_and_tpm_min_idle.2048319601
Short name T343
Test name
Test status
Simulation time 2387482127 ps
CPU time 76.23 seconds
Started Aug 25 10:43:22 AM UTC 24
Finished Aug 25 10:44:41 AM UTC 24
Peak memory 265864 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2048319601 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_and_tpm_min_idle.2048319601
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/8.spi_device_flash_and_tpm_min_idle/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/8.spi_device_flash_mode.3447394138
Short name T163
Test name
Test status
Simulation time 505904897 ps
CPU time 7.41 seconds
Started Aug 25 10:43:17 AM UTC 24
Finished Aug 25 10:43:25 AM UTC 24
Peak memory 251364 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3447394138 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/
spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_mode.3447394138
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/8.spi_device_flash_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/8.spi_device_flash_mode_ignore_cmds.2672752526
Short name T441
Test name
Test status
Simulation time 17970058 ps
CPU time 1.24 seconds
Started Aug 25 10:43:18 AM UTC 24
Finished Aug 25 10:43:20 AM UTC 24
Peak memory 225676 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2672752526 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_mode_ignore_cmds.2672752526
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/8.spi_device_flash_mode_ignore_cmds/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/8.spi_device_intercept.2236314099
Short name T194
Test name
Test status
Simulation time 639681006 ps
CPU time 7.26 seconds
Started Aug 25 10:43:13 AM UTC 24
Finished Aug 25 10:43:22 AM UTC 24
Peak memory 235096 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2236314099 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/s
pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_intercept.2236314099
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/8.spi_device_intercept/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/8.spi_device_mailbox.3603869963
Short name T255
Test name
Test status
Simulation time 669580504 ps
CPU time 13.58 seconds
Started Aug 25 10:43:13 AM UTC 24
Finished Aug 25 10:43:28 AM UTC 24
Peak memory 245164 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3603869963 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/spi
_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_mailbox.3603869963
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/8.spi_device_mailbox/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/8.spi_device_pass_addr_payload_swap.4040306424
Short name T62
Test name
Test status
Simulation time 32052463608 ps
CPU time 42.23 seconds
Started Aug 25 10:43:12 AM UTC 24
Finished Aug 25 10:43:56 AM UTC 24
Peak memory 235020 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4040306424 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_pass_addr_payload_swap.4040306424
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/8.spi_device_pass_addr_payload_swap/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/8.spi_device_pass_cmd_filtering.683476004
Short name T439
Test name
Test status
Simulation time 31820468 ps
CPU time 3.26 seconds
Started Aug 25 10:43:11 AM UTC 24
Finished Aug 25 10:43:16 AM UTC 24
Peak memory 244940 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=683476004 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_08_24/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_pass_cmd_filtering.683476004
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/8.spi_device_pass_cmd_filtering/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/8.spi_device_read_buffer_direct.2462841984
Short name T444
Test name
Test status
Simulation time 1039579597 ps
CPU time 9.87 seconds
Started Aug 25 10:43:19 AM UTC 24
Finished Aug 25 10:43:30 AM UTC 24
Peak memory 231324 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2462841984 -assert nopostproc +UVM_TESTNAME=spi_device
_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_read_buffer_direct.2462841984
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/8.spi_device_read_buffer_direct/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/8.spi_device_stress_all.2523753655
Short name T173
Test name
Test status
Simulation time 159191299482 ps
CPU time 595.76 seconds
Started Aug 25 10:43:22 AM UTC 24
Finished Aug 25 10:53:27 AM UTC 24
Peak memory 284304 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2523753655 -assert nopostproc +UVM_
TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra
tch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_stress_all.2523753655
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/8.spi_device_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/8.spi_device_tpm_all.1500547208
Short name T391
Test name
Test status
Simulation time 7086033709 ps
CPU time 14.72 seconds
Started Aug 25 10:43:10 AM UTC 24
Finished Aug 25 10:43:26 AM UTC 24
Peak memory 227548 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1500547208 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/spi
_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_all.1500547208
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/8.spi_device_tpm_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/8.spi_device_tpm_read_hw_reg.2310482262
Short name T440
Test name
Test status
Simulation time 2498559392 ps
CPU time 8.49 seconds
Started Aug 25 10:43:09 AM UTC 24
Finished Aug 25 10:43:19 AM UTC 24
Peak memory 227560 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2310482262 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_24/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_read_hw_reg.2310482262
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/8.spi_device_tpm_read_hw_reg/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/8.spi_device_tpm_rw.2629063372
Short name T406
Test name
Test status
Simulation time 70456813 ps
CPU time 1.27 seconds
Started Aug 25 10:43:10 AM UTC 24
Finished Aug 25 10:43:13 AM UTC 24
Peak memory 215868 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2629063372 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/spi_
device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_rw.2629063372
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/8.spi_device_tpm_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/8.spi_device_tpm_sts_read.967740467
Short name T438
Test name
Test status
Simulation time 150238347 ps
CPU time 1.41 seconds
Started Aug 25 10:43:10 AM UTC 24
Finished Aug 25 10:43:13 AM UTC 24
Peak memory 215868 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=967740467 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24
/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_sts_read.967740467
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/8.spi_device_tpm_sts_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/8.spi_device_upload.2843750765
Short name T208
Test name
Test status
Simulation time 1959610703 ps
CPU time 13.91 seconds
Started Aug 25 10:43:14 AM UTC 24
Finished Aug 25 10:43:29 AM UTC 24
Peak memory 245348 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2843750765 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/spi_
device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_upload.2843750765
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/8.spi_device_upload/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/9.spi_device_alert_test.2264750298
Short name T448
Test name
Test status
Simulation time 118902660 ps
CPU time 1.12 seconds
Started Aug 25 10:43:46 AM UTC 24
Finished Aug 25 10:43:48 AM UTC 24
Peak memory 215680 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2264750298 -assert nopostproc +UVM_TES
TNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_
regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_alert_test.2264750298
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/9.spi_device_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/9.spi_device_cfg_cmd.28827696
Short name T203
Test name
Test status
Simulation time 731347407 ps
CPU time 4.78 seconds
Started Aug 25 10:43:35 AM UTC 24
Finished Aug 25 10:43:41 AM UTC 24
Peak memory 234904 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=28827696 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/spi_d
evice_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_cfg_cmd.28827696
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/9.spi_device_cfg_cmd/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/9.spi_device_csb_read.3858705511
Short name T443
Test name
Test status
Simulation time 33383085 ps
CPU time 1.16 seconds
Started Aug 25 10:43:26 AM UTC 24
Finished Aug 25 10:43:29 AM UTC 24
Peak memory 215808 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3858705511 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/sp
i_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_csb_read.3858705511
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/9.spi_device_csb_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/9.spi_device_flash_all.1854430225
Short name T285
Test name
Test status
Simulation time 271798990139 ps
CPU time 576.9 seconds
Started Aug 25 10:43:39 AM UTC 24
Finished Aug 25 10:53:25 AM UTC 24
Peak memory 267876 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1854430225 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/s
pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_all.1854430225
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/9.spi_device_flash_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/9.spi_device_flash_and_tpm.4265176336
Short name T571
Test name
Test status
Simulation time 176220243888 ps
CPU time 295.65 seconds
Started Aug 25 10:43:39 AM UTC 24
Finished Aug 25 10:48:40 AM UTC 24
Peak memory 261772 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4265176336 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
24/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_and_tpm.4265176336
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/9.spi_device_flash_and_tpm/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/9.spi_device_flash_mode.1645812186
Short name T373
Test name
Test status
Simulation time 1522764620 ps
CPU time 33.53 seconds
Started Aug 25 10:43:36 AM UTC 24
Finished Aug 25 10:44:12 AM UTC 24
Peak memory 245204 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1645812186 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/
spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_mode.1645812186
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/9.spi_device_flash_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/9.spi_device_flash_mode_ignore_cmds.2691733737
Short name T357
Test name
Test status
Simulation time 18429321365 ps
CPU time 156.79 seconds
Started Aug 25 10:43:37 AM UTC 24
Finished Aug 25 10:46:17 AM UTC 24
Peak memory 261856 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2691733737 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_mode_ignore_cmds.2691733737
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/9.spi_device_flash_mode_ignore_cmds/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/9.spi_device_intercept.3895780228
Short name T86
Test name
Test status
Simulation time 1643939393 ps
CPU time 19.68 seconds
Started Aug 25 10:43:31 AM UTC 24
Finished Aug 25 10:43:52 AM UTC 24
Peak memory 245228 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3895780228 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/s
pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_intercept.3895780228
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/9.spi_device_intercept/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/9.spi_device_mailbox.2151961643
Short name T190
Test name
Test status
Simulation time 602495507 ps
CPU time 19.08 seconds
Started Aug 25 10:43:33 AM UTC 24
Finished Aug 25 10:43:53 AM UTC 24
Peak memory 255452 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2151961643 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/spi
_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_mailbox.2151961643
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/9.spi_device_mailbox/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/9.spi_device_pass_addr_payload_swap.50318306
Short name T63
Test name
Test status
Simulation time 9238194939 ps
CPU time 35.4 seconds
Started Aug 25 10:43:29 AM UTC 24
Finished Aug 25 10:44:06 AM UTC 24
Peak memory 245332 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=50318306 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_24/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_pass_addr_payload_swap.50318306
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/9.spi_device_pass_addr_payload_swap/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/9.spi_device_pass_cmd_filtering.169929886
Short name T206
Test name
Test status
Simulation time 3497142149 ps
CPU time 9.13 seconds
Started Aug 25 10:43:29 AM UTC 24
Finished Aug 25 10:43:40 AM UTC 24
Peak memory 245328 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=169929886 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_08_24/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_pass_cmd_filtering.169929886
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/9.spi_device_pass_cmd_filtering/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/9.spi_device_read_buffer_direct.528863055
Short name T450
Test name
Test status
Simulation time 2274073262 ps
CPU time 20.97 seconds
Started Aug 25 10:43:38 AM UTC 24
Finished Aug 25 10:44:01 AM UTC 24
Peak memory 231396 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=528863055 -assert nopostproc +UVM_TESTNAME=spi_device_
base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_read_buffer_direct.528863055
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/9.spi_device_read_buffer_direct/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/9.spi_device_stress_all.3980315326
Short name T35
Test name
Test status
Simulation time 4134832403 ps
CPU time 81.59 seconds
Started Aug 25 10:43:42 AM UTC 24
Finished Aug 25 10:45:05 AM UTC 24
Peak memory 265800 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3980315326 -assert nopostproc +UVM_
TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra
tch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_stress_all.3980315326
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/9.spi_device_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/9.spi_device_tpm_all.68702523
Short name T380
Test name
Test status
Simulation time 1862778086 ps
CPU time 28.09 seconds
Started Aug 25 10:43:28 AM UTC 24
Finished Aug 25 10:43:58 AM UTC 24
Peak memory 227484 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=68702523 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/spi_d
evice_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_all.68702523
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/9.spi_device_tpm_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/9.spi_device_tpm_read_hw_reg.3218033662
Short name T447
Test name
Test status
Simulation time 988554335 ps
CPU time 8.47 seconds
Started Aug 25 10:43:27 AM UTC 24
Finished Aug 25 10:43:37 AM UTC 24
Peak memory 227428 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3218033662 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_24/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_read_hw_reg.3218033662
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/9.spi_device_tpm_read_hw_reg/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/9.spi_device_tpm_rw.3789929223
Short name T446
Test name
Test status
Simulation time 59792494 ps
CPU time 4.36 seconds
Started Aug 25 10:43:29 AM UTC 24
Finished Aug 25 10:43:35 AM UTC 24
Peak memory 227424 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3789929223 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/spi_
device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_rw.3789929223
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/9.spi_device_tpm_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/9.spi_device_tpm_sts_read.2106996480
Short name T445
Test name
Test status
Simulation time 26328832 ps
CPU time 1.14 seconds
Started Aug 25 10:43:29 AM UTC 24
Finished Aug 25 10:43:31 AM UTC 24
Peak memory 215868 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2106996480 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_2
4/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_sts_read.2106996480
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/9.spi_device_tpm_sts_read/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/coverage/default/9.spi_device_upload.3512563240
Short name T83
Test name
Test status
Simulation time 10676538922 ps
CPU time 37.01 seconds
Started Aug 25 10:43:33 AM UTC 24
Finished Aug 25 10:44:11 AM UTC 24
Peak memory 245336 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3512563240 -assert nopostproc +UVM_TESTNAME=spi_device_base_test
+UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/spi_
device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_upload.3512563240
Directory /workspaces/repo/scratch/os_regression_2024_08_24/spi_device_1r1w-sim-vcs/9.spi_device_upload/latest
0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%