| T826 |
/workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/41.spi_device_mailbox.3559285707 |
|
|
Aug 27 06:27:13 PM UTC 24 |
Aug 27 06:27:16 PM UTC 24 |
33743454 ps |
| T827 |
/workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/41.spi_device_pass_addr_payload_swap.3561935876 |
|
|
Aug 27 06:27:13 PM UTC 24 |
Aug 27 06:27:17 PM UTC 24 |
116127405 ps |
| T828 |
/workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/39.spi_device_mailbox.3330012038 |
|
|
Aug 27 06:26:46 PM UTC 24 |
Aug 27 06:27:18 PM UTC 24 |
3467536172 ps |
| T829 |
/workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/41.spi_device_cfg_cmd.3047761692 |
|
|
Aug 27 06:27:15 PM UTC 24 |
Aug 27 06:27:19 PM UTC 24 |
31797823 ps |
| T830 |
/workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/40.spi_device_read_buffer_direct.2832494187 |
|
|
Aug 27 06:27:04 PM UTC 24 |
Aug 27 06:27:19 PM UTC 24 |
3785465053 ps |
| T831 |
/workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/41.spi_device_intercept.1686957772 |
|
|
Aug 27 06:27:13 PM UTC 24 |
Aug 27 06:27:20 PM UTC 24 |
187157553 ps |
| T249 |
/workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/36.spi_device_flash_mode_ignore_cmds.1521473366 |
|
|
Aug 27 06:26:05 PM UTC 24 |
Aug 27 06:27:21 PM UTC 24 |
5477170783 ps |
| T832 |
/workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/41.spi_device_alert_test.1253508177 |
|
|
Aug 27 06:27:21 PM UTC 24 |
Aug 27 06:27:23 PM UTC 24 |
28276819 ps |
| T833 |
/workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/41.spi_device_pass_cmd_filtering.3871772293 |
|
|
Aug 27 06:27:13 PM UTC 24 |
Aug 27 06:27:24 PM UTC 24 |
1650635586 ps |
| T834 |
/workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/41.spi_device_flash_mode.3201816562 |
|
|
Aug 27 06:27:15 PM UTC 24 |
Aug 27 06:27:24 PM UTC 24 |
549288586 ps |
| T835 |
/workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/42.spi_device_csb_read.3752799770 |
|
|
Aug 27 06:27:22 PM UTC 24 |
Aug 27 06:27:24 PM UTC 24 |
48231020 ps |
| T836 |
/workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/40.spi_device_pass_addr_payload_swap.1034575295 |
|
|
Aug 27 06:27:00 PM UTC 24 |
Aug 27 06:27:25 PM UTC 24 |
17778266858 ps |
| T837 |
/workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/42.spi_device_tpm_sts_read.2006216047 |
|
|
Aug 27 06:27:26 PM UTC 24 |
Aug 27 06:27:28 PM UTC 24 |
46207422 ps |
| T838 |
/workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/38.spi_device_flash_all.748229173 |
|
|
Aug 27 06:26:34 PM UTC 24 |
Aug 27 06:27:29 PM UTC 24 |
17215504055 ps |
| T839 |
/workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/42.spi_device_tpm_rw.3814995030 |
|
|
Aug 27 06:27:26 PM UTC 24 |
Aug 27 06:27:30 PM UTC 24 |
559358133 ps |
| T840 |
/workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/41.spi_device_upload.249405917 |
|
|
Aug 27 06:27:15 PM UTC 24 |
Aug 27 06:27:31 PM UTC 24 |
8590154150 ps |
| T841 |
/workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/41.spi_device_read_buffer_direct.3533074282 |
|
|
Aug 27 06:27:18 PM UTC 24 |
Aug 27 06:27:32 PM UTC 24 |
700086431 ps |
| T842 |
/workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/26.spi_device_flash_and_tpm.4023652502 |
|
|
Aug 27 06:21:56 PM UTC 24 |
Aug 27 06:27:33 PM UTC 24 |
67599492555 ps |
| T843 |
/workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/42.spi_device_pass_addr_payload_swap.3924987236 |
|
|
Aug 27 06:27:30 PM UTC 24 |
Aug 27 06:27:34 PM UTC 24 |
478152900 ps |
| T844 |
/workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/42.spi_device_upload.1888621077 |
|
|
Aug 27 06:27:32 PM UTC 24 |
Aug 27 06:27:37 PM UTC 24 |
85911629 ps |
| T845 |
/workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/42.spi_device_tpm_read_hw_reg.3644183171 |
|
|
Aug 27 06:27:24 PM UTC 24 |
Aug 27 06:27:38 PM UTC 24 |
2036695447 ps |
| T846 |
/workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/42.spi_device_cfg_cmd.2350877632 |
|
|
Aug 27 06:27:34 PM UTC 24 |
Aug 27 06:27:41 PM UTC 24 |
190579117 ps |
| T847 |
/workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/42.spi_device_intercept.3180811876 |
|
|
Aug 27 06:27:31 PM UTC 24 |
Aug 27 06:27:41 PM UTC 24 |
266415967 ps |
| T848 |
/workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/42.spi_device_pass_cmd_filtering.3791237611 |
|
|
Aug 27 06:27:27 PM UTC 24 |
Aug 27 06:27:42 PM UTC 24 |
10315864480 ps |
| T849 |
/workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/42.spi_device_mailbox.3576850287 |
|
|
Aug 27 06:27:31 PM UTC 24 |
Aug 27 06:27:44 PM UTC 24 |
472362276 ps |
| T850 |
/workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/40.spi_device_flash_mode.1832738843 |
|
|
Aug 27 06:27:03 PM UTC 24 |
Aug 27 06:27:45 PM UTC 24 |
7427741726 ps |
| T851 |
/workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/41.spi_device_tpm_all.197967685 |
|
|
Aug 27 06:27:09 PM UTC 24 |
Aug 27 06:27:46 PM UTC 24 |
4749387891 ps |
| T852 |
/workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/42.spi_device_read_buffer_direct.708480500 |
|
|
Aug 27 06:27:38 PM UTC 24 |
Aug 27 06:27:47 PM UTC 24 |
715726541 ps |
| T853 |
/workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/42.spi_device_alert_test.2619337389 |
|
|
Aug 27 06:27:45 PM UTC 24 |
Aug 27 06:27:47 PM UTC 24 |
12811895 ps |
| T854 |
/workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/38.spi_device_flash_and_tpm.1038598084 |
|
|
Aug 27 06:26:34 PM UTC 24 |
Aug 27 06:27:47 PM UTC 24 |
2878125331 ps |
| T855 |
/workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/43.spi_device_csb_read.2712981288 |
|
|
Aug 27 06:27:46 PM UTC 24 |
Aug 27 06:27:48 PM UTC 24 |
52371709 ps |
| T856 |
/workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/41.spi_device_flash_mode_ignore_cmds.3620449081 |
|
|
Aug 27 06:27:16 PM UTC 24 |
Aug 27 06:27:48 PM UTC 24 |
3888662098 ps |
| T857 |
/workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/43.spi_device_tpm_sts_read.433505208 |
|
|
Aug 27 06:27:48 PM UTC 24 |
Aug 27 06:27:51 PM UTC 24 |
569778018 ps |
| T336 |
/workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/39.spi_device_flash_mode_ignore_cmds.4199578618 |
|
|
Aug 27 06:26:50 PM UTC 24 |
Aug 27 06:27:51 PM UTC 24 |
4034372989 ps |
| T858 |
/workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/42.spi_device_flash_all.2243152335 |
|
|
Aug 27 06:27:40 PM UTC 24 |
Aug 27 06:27:52 PM UTC 24 |
2448941479 ps |
| T859 |
/workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/43.spi_device_tpm_rw.3087026012 |
|
|
Aug 27 06:27:50 PM UTC 24 |
Aug 27 06:27:54 PM UTC 24 |
67496306 ps |
| T860 |
/workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/43.spi_device_intercept.3601005982 |
|
|
Aug 27 06:27:52 PM UTC 24 |
Aug 27 06:27:58 PM UTC 24 |
95874513 ps |
| T861 |
/workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/43.spi_device_pass_cmd_filtering.676727209 |
|
|
Aug 27 06:27:50 PM UTC 24 |
Aug 27 06:27:59 PM UTC 24 |
749552990 ps |
| T862 |
/workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/40.spi_device_flash_all.2116613969 |
|
|
Aug 27 06:27:06 PM UTC 24 |
Aug 27 06:28:02 PM UTC 24 |
10543383354 ps |
| T344 |
/workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/31.spi_device_flash_and_tpm.1572129746 |
|
|
Aug 27 06:24:08 PM UTC 24 |
Aug 27 06:28:04 PM UTC 24 |
88730019314 ps |
| T863 |
/workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/43.spi_device_mailbox.872058695 |
|
|
Aug 27 06:27:52 PM UTC 24 |
Aug 27 06:28:04 PM UTC 24 |
307635598 ps |
| T864 |
/workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/43.spi_device_cfg_cmd.2432715396 |
|
|
Aug 27 06:27:55 PM UTC 24 |
Aug 27 06:28:04 PM UTC 24 |
1659149647 ps |
| T865 |
/workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/41.spi_device_flash_all.3182873374 |
|
|
Aug 27 06:27:18 PM UTC 24 |
Aug 27 06:28:05 PM UTC 24 |
1703206715 ps |
| T866 |
/workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/43.spi_device_tpm_all.4205085708 |
|
|
Aug 27 06:27:48 PM UTC 24 |
Aug 27 06:28:09 PM UTC 24 |
4381576998 ps |
| T867 |
/workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/40.spi_device_flash_and_tpm.1557855050 |
|
|
Aug 27 06:27:06 PM UTC 24 |
Aug 27 06:28:09 PM UTC 24 |
4163699232 ps |
| T868 |
/workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/42.spi_device_flash_mode.3885728713 |
|
|
Aug 27 06:27:35 PM UTC 24 |
Aug 27 06:28:13 PM UTC 24 |
6705144042 ps |
| T869 |
/workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/43.spi_device_alert_test.1552294516 |
|
|
Aug 27 06:28:10 PM UTC 24 |
Aug 27 06:28:13 PM UTC 24 |
14659983 ps |
| T870 |
/workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/43.spi_device_pass_addr_payload_swap.3320333311 |
|
|
Aug 27 06:27:50 PM UTC 24 |
Aug 27 06:28:13 PM UTC 24 |
4679502226 ps |
| T871 |
/workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/44.spi_device_csb_read.2249680878 |
|
|
Aug 27 06:28:11 PM UTC 24 |
Aug 27 06:28:13 PM UTC 24 |
15814024 ps |
| T872 |
/workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/43.spi_device_upload.895438695 |
|
|
Aug 27 06:27:54 PM UTC 24 |
Aug 27 06:28:15 PM UTC 24 |
2442611878 ps |
| T873 |
/workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/34.spi_device_flash_mode_ignore_cmds.4088195564 |
|
|
Aug 27 06:25:33 PM UTC 24 |
Aug 27 06:28:16 PM UTC 24 |
19613268342 ps |
| T874 |
/workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/43.spi_device_flash_mode.931472956 |
|
|
Aug 27 06:27:59 PM UTC 24 |
Aug 27 06:28:16 PM UTC 24 |
17026813762 ps |
| T875 |
/workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/36.spi_device_flash_and_tpm_min_idle.1147280237 |
|
|
Aug 27 06:26:08 PM UTC 24 |
Aug 27 06:28:17 PM UTC 24 |
16266541234 ps |
| T876 |
/workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/44.spi_device_tpm_sts_read.2641480791 |
|
|
Aug 27 06:28:14 PM UTC 24 |
Aug 27 06:28:17 PM UTC 24 |
70609960 ps |
| T877 |
/workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/44.spi_device_tpm_rw.1482014477 |
|
|
Aug 27 06:28:14 PM UTC 24 |
Aug 27 06:28:20 PM UTC 24 |
743153019 ps |
| T878 |
/workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/38.spi_device_stress_all.497705394 |
|
|
Aug 27 06:26:37 PM UTC 24 |
Aug 27 06:28:21 PM UTC 24 |
16248876242 ps |
| T879 |
/workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/42.spi_device_tpm_all.2641912494 |
|
|
Aug 27 06:27:26 PM UTC 24 |
Aug 27 06:28:22 PM UTC 24 |
97272594798 ps |
| T880 |
/workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/43.spi_device_tpm_read_hw_reg.926037009 |
|
|
Aug 27 06:27:48 PM UTC 24 |
Aug 27 06:28:22 PM UTC 24 |
30427329758 ps |
| T881 |
/workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/44.spi_device_intercept.841811959 |
|
|
Aug 27 06:28:17 PM UTC 24 |
Aug 27 06:28:22 PM UTC 24 |
301339803 ps |
| T882 |
/workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/44.spi_device_tpm_read_hw_reg.3871092598 |
|
|
Aug 27 06:28:14 PM UTC 24 |
Aug 27 06:28:23 PM UTC 24 |
519271458 ps |
| T883 |
/workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/43.spi_device_read_buffer_direct.3085311437 |
|
|
Aug 27 06:28:04 PM UTC 24 |
Aug 27 06:28:25 PM UTC 24 |
2816828798 ps |
| T884 |
/workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/37.spi_device_flash_all.972932759 |
|
|
Aug 27 06:26:16 PM UTC 24 |
Aug 27 06:28:31 PM UTC 24 |
15397711136 ps |
| T885 |
/workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/30.spi_device_flash_mode_ignore_cmds.4129198449 |
|
|
Aug 27 06:23:29 PM UTC 24 |
Aug 27 06:28:31 PM UTC 24 |
73898041228 ps |
| T886 |
/workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/44.spi_device_cfg_cmd.1341018316 |
|
|
Aug 27 06:28:21 PM UTC 24 |
Aug 27 06:28:32 PM UTC 24 |
2210787468 ps |
| T887 |
/workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/44.spi_device_upload.2788319023 |
|
|
Aug 27 06:28:19 PM UTC 24 |
Aug 27 06:28:33 PM UTC 24 |
4049149865 ps |
| T337 |
/workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/29.spi_device_flash_mode_ignore_cmds.3345802875 |
|
|
Aug 27 06:22:58 PM UTC 24 |
Aug 27 06:28:34 PM UTC 24 |
28941079015 ps |
| T888 |
/workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/44.spi_device_alert_test.3182450091 |
|
|
Aug 27 06:28:32 PM UTC 24 |
Aug 27 06:28:35 PM UTC 24 |
15650551 ps |
| T889 |
/workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/44.spi_device_tpm_all.1255719844 |
|
|
Aug 27 06:28:14 PM UTC 24 |
Aug 27 06:28:35 PM UTC 24 |
4240984668 ps |
| T890 |
/workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/45.spi_device_csb_read.934498858 |
|
|
Aug 27 06:28:34 PM UTC 24 |
Aug 27 06:28:36 PM UTC 24 |
15442093 ps |
| T891 |
/workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/45.spi_device_tpm_sts_read.3079570459 |
|
|
Aug 27 06:28:35 PM UTC 24 |
Aug 27 06:28:38 PM UTC 24 |
80652710 ps |
| T892 |
/workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/43.spi_device_flash_all.1037645587 |
|
|
Aug 27 06:28:05 PM UTC 24 |
Aug 27 06:28:39 PM UTC 24 |
6075749938 ps |
| T893 |
/workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/42.spi_device_flash_and_tpm.2302872840 |
|
|
Aug 27 06:27:42 PM UTC 24 |
Aug 27 06:28:39 PM UTC 24 |
14200527526 ps |
| T894 |
/workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/45.spi_device_tpm_rw.3983893373 |
|
|
Aug 27 06:28:37 PM UTC 24 |
Aug 27 06:28:40 PM UTC 24 |
224701275 ps |
| T895 |
/workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/45.spi_device_pass_cmd_filtering.2901187352 |
|
|
Aug 27 06:28:37 PM UTC 24 |
Aug 27 06:28:41 PM UTC 24 |
311872186 ps |
| T896 |
/workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/45.spi_device_pass_addr_payload_swap.644537881 |
|
|
Aug 27 06:28:39 PM UTC 24 |
Aug 27 06:28:46 PM UTC 24 |
825076212 ps |
| T897 |
/workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/45.spi_device_intercept.769029501 |
|
|
Aug 27 06:28:41 PM UTC 24 |
Aug 27 06:28:46 PM UTC 24 |
149154856 ps |
| T898 |
/workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/44.spi_device_pass_cmd_filtering.648823622 |
|
|
Aug 27 06:28:16 PM UTC 24 |
Aug 27 06:28:47 PM UTC 24 |
8079787700 ps |
| T899 |
/workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/45.spi_device_cfg_cmd.3198157730 |
|
|
Aug 27 06:28:42 PM UTC 24 |
Aug 27 06:28:48 PM UTC 24 |
218180871 ps |
| T900 |
/workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/45.spi_device_upload.2590595002 |
|
|
Aug 27 06:28:41 PM UTC 24 |
Aug 27 06:28:51 PM UTC 24 |
1159572602 ps |
| T901 |
/workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/44.spi_device_pass_addr_payload_swap.1051565417 |
|
|
Aug 27 06:28:17 PM UTC 24 |
Aug 27 06:28:52 PM UTC 24 |
18714158094 ps |
| T902 |
/workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/44.spi_device_read_buffer_direct.294615059 |
|
|
Aug 27 06:28:23 PM UTC 24 |
Aug 27 06:28:53 PM UTC 24 |
2120716740 ps |
| T903 |
/workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/45.spi_device_read_buffer_direct.221879854 |
|
|
Aug 27 06:28:49 PM UTC 24 |
Aug 27 06:28:57 PM UTC 24 |
271556839 ps |
| T904 |
/workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/44.spi_device_flash_and_tpm_min_idle.1056395115 |
|
|
Aug 27 06:28:26 PM UTC 24 |
Aug 27 06:29:00 PM UTC 24 |
5794944754 ps |
| T905 |
/workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/45.spi_device_alert_test.1912911582 |
|
|
Aug 27 06:28:58 PM UTC 24 |
Aug 27 06:29:01 PM UTC 24 |
24519631 ps |
| T906 |
/workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/45.spi_device_tpm_read_hw_reg.2376386372 |
|
|
Aug 27 06:28:34 PM UTC 24 |
Aug 27 06:29:01 PM UTC 24 |
8150479839 ps |
| T907 |
/workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/46.spi_device_csb_read.1546427400 |
|
|
Aug 27 06:29:01 PM UTC 24 |
Aug 27 06:29:03 PM UTC 24 |
57279017 ps |
| T908 |
/workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/38.spi_device_flash_mode_ignore_cmds.3467256146 |
|
|
Aug 27 06:26:32 PM UTC 24 |
Aug 27 06:29:03 PM UTC 24 |
15247671805 ps |
| T909 |
/workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/44.spi_device_flash_mode.856239860 |
|
|
Aug 27 06:28:23 PM UTC 24 |
Aug 27 06:29:04 PM UTC 24 |
2245571691 ps |
| T910 |
/workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/45.spi_device_tpm_all.2119572002 |
|
|
Aug 27 06:28:35 PM UTC 24 |
Aug 27 06:29:05 PM UTC 24 |
1865330225 ps |
| T911 |
/workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/46.spi_device_tpm_sts_read.1555853671 |
|
|
Aug 27 06:29:04 PM UTC 24 |
Aug 27 06:29:06 PM UTC 24 |
57479393 ps |
| T329 |
/workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/22.spi_device_stress_all.3524503119 |
|
|
Aug 27 06:20:08 PM UTC 24 |
Aug 27 06:29:07 PM UTC 24 |
51071069788 ps |
| T912 |
/workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/46.spi_device_tpm_rw.3864268144 |
|
|
Aug 27 06:29:04 PM UTC 24 |
Aug 27 06:29:07 PM UTC 24 |
218787501 ps |
| T913 |
/workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/44.spi_device_flash_and_tpm.287473759 |
|
|
Aug 27 06:28:24 PM UTC 24 |
Aug 27 06:29:08 PM UTC 24 |
2983715910 ps |
| T914 |
/workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/46.spi_device_pass_cmd_filtering.2311635343 |
|
|
Aug 27 06:29:05 PM UTC 24 |
Aug 27 06:29:09 PM UTC 24 |
144072356 ps |
| T915 |
/workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/45.spi_device_mailbox.3164502168 |
|
|
Aug 27 06:28:41 PM UTC 24 |
Aug 27 06:29:10 PM UTC 24 |
5134101319 ps |
| T916 |
/workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/46.spi_device_intercept.2811111943 |
|
|
Aug 27 06:29:07 PM UTC 24 |
Aug 27 06:29:12 PM UTC 24 |
344027382 ps |
| T917 |
/workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/46.spi_device_tpm_read_hw_reg.2319475422 |
|
|
Aug 27 06:29:02 PM UTC 24 |
Aug 27 06:29:13 PM UTC 24 |
1091365817 ps |
| T918 |
/workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/46.spi_device_cfg_cmd.2433943807 |
|
|
Aug 27 06:29:09 PM UTC 24 |
Aug 27 06:29:14 PM UTC 24 |
135895371 ps |
| T343 |
/workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/32.spi_device_flash_mode_ignore_cmds.4242639798 |
|
|
Aug 27 06:24:21 PM UTC 24 |
Aug 27 06:29:15 PM UTC 24 |
210193654962 ps |
| T919 |
/workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/45.spi_device_flash_mode.2580913502 |
|
|
Aug 27 06:28:48 PM UTC 24 |
Aug 27 06:29:15 PM UTC 24 |
1114522675 ps |
| T920 |
/workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/45.spi_device_flash_mode_ignore_cmds.450763771 |
|
|
Aug 27 06:28:48 PM UTC 24 |
Aug 27 06:29:16 PM UTC 24 |
809681173 ps |
| T921 |
/workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/46.spi_device_tpm_all.2815185413 |
|
|
Aug 27 06:29:02 PM UTC 24 |
Aug 27 06:29:16 PM UTC 24 |
12293546705 ps |
| T922 |
/workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/46.spi_device_flash_mode.847110608 |
|
|
Aug 27 06:29:11 PM UTC 24 |
Aug 27 06:29:17 PM UTC 24 |
200195655 ps |
| T923 |
/workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/38.spi_device_flash_and_tpm_min_idle.2566589194 |
|
|
Aug 27 06:26:36 PM UTC 24 |
Aug 27 06:29:18 PM UTC 24 |
13245992095 ps |
| T924 |
/workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/46.spi_device_alert_test.381694693 |
|
|
Aug 27 06:29:17 PM UTC 24 |
Aug 27 06:29:19 PM UTC 24 |
56487185 ps |
| T925 |
/workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/47.spi_device_csb_read.1807214613 |
|
|
Aug 27 06:29:17 PM UTC 24 |
Aug 27 06:29:19 PM UTC 24 |
34887020 ps |
| T926 |
/workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/47.spi_device_tpm_read_hw_reg.2613937758 |
|
|
Aug 27 06:29:18 PM UTC 24 |
Aug 27 06:29:20 PM UTC 24 |
16070826 ps |
| T927 |
/workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/46.spi_device_pass_addr_payload_swap.1662624703 |
|
|
Aug 27 06:29:07 PM UTC 24 |
Aug 27 06:29:22 PM UTC 24 |
2018529605 ps |
| T928 |
/workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/47.spi_device_tpm_sts_read.3710432451 |
|
|
Aug 27 06:29:20 PM UTC 24 |
Aug 27 06:29:22 PM UTC 24 |
87425141 ps |
| T929 |
/workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/47.spi_device_tpm_rw.1015874510 |
|
|
Aug 27 06:29:20 PM UTC 24 |
Aug 27 06:29:23 PM UTC 24 |
165822343 ps |
| T930 |
/workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/42.spi_device_flash_mode_ignore_cmds.107147242 |
|
|
Aug 27 06:27:35 PM UTC 24 |
Aug 27 06:29:23 PM UTC 24 |
45643865978 ps |
| T931 |
/workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/47.spi_device_pass_cmd_filtering.2702086754 |
|
|
Aug 27 06:29:20 PM UTC 24 |
Aug 27 06:29:24 PM UTC 24 |
101722885 ps |
| T932 |
/workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/46.spi_device_read_buffer_direct.4145822397 |
|
|
Aug 27 06:29:13 PM UTC 24 |
Aug 27 06:29:24 PM UTC 24 |
407350498 ps |
| T217 |
/workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/12.spi_device_flash_all.1781995785 |
|
|
Aug 27 06:15:29 PM UTC 24 |
Aug 27 06:29:26 PM UTC 24 |
79972983958 ps |
| T933 |
/workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/47.spi_device_intercept.3048568419 |
|
|
Aug 27 06:29:23 PM UTC 24 |
Aug 27 06:29:27 PM UTC 24 |
169848822 ps |
| T934 |
/workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/47.spi_device_pass_addr_payload_swap.2797179052 |
|
|
Aug 27 06:29:21 PM UTC 24 |
Aug 27 06:29:30 PM UTC 24 |
500036040 ps |
| T935 |
/workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/44.spi_device_mailbox.3441729190 |
|
|
Aug 27 06:28:19 PM UTC 24 |
Aug 27 06:29:30 PM UTC 24 |
37601311263 ps |
| T936 |
/workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/47.spi_device_tpm_all.3966358544 |
|
|
Aug 27 06:29:20 PM UTC 24 |
Aug 27 06:29:36 PM UTC 24 |
5800682393 ps |
| T937 |
/workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/39.spi_device_flash_and_tpm.2365976941 |
|
|
Aug 27 06:26:52 PM UTC 24 |
Aug 27 06:29:37 PM UTC 24 |
59592805349 ps |
| T938 |
/workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/47.spi_device_read_buffer_direct.932181207 |
|
|
Aug 27 06:29:27 PM UTC 24 |
Aug 27 06:29:37 PM UTC 24 |
311562312 ps |
| T939 |
/workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/47.spi_device_cfg_cmd.4293242046 |
|
|
Aug 27 06:29:25 PM UTC 24 |
Aug 27 06:29:38 PM UTC 24 |
5054803190 ps |
| T940 |
/workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/44.spi_device_flash_mode_ignore_cmds.2421603076 |
|
|
Aug 27 06:28:23 PM UTC 24 |
Aug 27 06:29:38 PM UTC 24 |
6723148599 ps |
| T941 |
/workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/47.spi_device_alert_test.909126975 |
|
|
Aug 27 06:29:38 PM UTC 24 |
Aug 27 06:29:39 PM UTC 24 |
22364766 ps |
| T942 |
/workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/47.spi_device_stress_all.1445760566 |
|
|
Aug 27 06:29:37 PM UTC 24 |
Aug 27 06:29:40 PM UTC 24 |
58543846 ps |
| T943 |
/workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/45.spi_device_flash_and_tpm.327609198 |
|
|
Aug 27 06:28:52 PM UTC 24 |
Aug 27 06:29:41 PM UTC 24 |
1987879627 ps |
| T944 |
/workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/48.spi_device_tpm_read_hw_reg.2044430483 |
|
|
Aug 27 06:29:39 PM UTC 24 |
Aug 27 06:29:41 PM UTC 24 |
38032902 ps |
| T945 |
/workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/48.spi_device_csb_read.150413098 |
|
|
Aug 27 06:29:39 PM UTC 24 |
Aug 27 06:29:41 PM UTC 24 |
17468460 ps |
| T946 |
/workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/48.spi_device_tpm_sts_read.3245119530 |
|
|
Aug 27 06:29:41 PM UTC 24 |
Aug 27 06:29:43 PM UTC 24 |
220652094 ps |
| T947 |
/workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/48.spi_device_tpm_rw.2911231956 |
|
|
Aug 27 06:29:41 PM UTC 24 |
Aug 27 06:29:44 PM UTC 24 |
52075233 ps |
| T948 |
/workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/44.spi_device_flash_all.4226439070 |
|
|
Aug 27 06:28:24 PM UTC 24 |
Aug 27 06:29:44 PM UTC 24 |
3726221489 ps |
| T949 |
/workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/46.spi_device_upload.2141873318 |
|
|
Aug 27 06:29:08 PM UTC 24 |
Aug 27 06:29:45 PM UTC 24 |
25542885835 ps |
| T950 |
/workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/48.spi_device_pass_addr_payload_swap.2000519467 |
|
|
Aug 27 06:29:43 PM UTC 24 |
Aug 27 06:29:47 PM UTC 24 |
282022406 ps |
| T951 |
/workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/48.spi_device_intercept.3525403043 |
|
|
Aug 27 06:29:43 PM UTC 24 |
Aug 27 06:29:48 PM UTC 24 |
220600818 ps |
| T952 |
/workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/48.spi_device_upload.3310831201 |
|
|
Aug 27 06:29:44 PM UTC 24 |
Aug 27 06:29:49 PM UTC 24 |
628527144 ps |
| T953 |
/workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/47.spi_device_upload.2901617100 |
|
|
Aug 27 06:29:24 PM UTC 24 |
Aug 27 06:29:49 PM UTC 24 |
5115720720 ps |
| T954 |
/workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/47.spi_device_flash_mode.1359070391 |
|
|
Aug 27 06:29:25 PM UTC 24 |
Aug 27 06:29:50 PM UTC 24 |
1181083534 ps |
| T955 |
/workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/48.spi_device_pass_cmd_filtering.4294618353 |
|
|
Aug 27 06:29:43 PM UTC 24 |
Aug 27 06:29:52 PM UTC 24 |
396937669 ps |
| T956 |
/workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/47.spi_device_mailbox.712875767 |
|
|
Aug 27 06:29:23 PM UTC 24 |
Aug 27 06:29:53 PM UTC 24 |
1624780121 ps |
| T957 |
/workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/46.spi_device_mailbox.1560024795 |
|
|
Aug 27 06:29:08 PM UTC 24 |
Aug 27 06:29:55 PM UTC 24 |
35545319634 ps |
| T958 |
/workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/45.spi_device_flash_all.1554453464 |
|
|
Aug 27 06:28:49 PM UTC 24 |
Aug 27 06:29:55 PM UTC 24 |
43455395724 ps |
| T959 |
/workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/48.spi_device_read_buffer_direct.1095225048 |
|
|
Aug 27 06:29:48 PM UTC 24 |
Aug 27 06:29:56 PM UTC 24 |
2921708185 ps |
| T960 |
/workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/48.spi_device_alert_test.3800850758 |
|
|
Aug 27 06:29:55 PM UTC 24 |
Aug 27 06:29:57 PM UTC 24 |
27034789 ps |
| T961 |
/workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/48.spi_device_cfg_cmd.443345025 |
|
|
Aug 27 06:29:46 PM UTC 24 |
Aug 27 06:29:59 PM UTC 24 |
3491380154 ps |
| T962 |
/workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/49.spi_device_csb_read.2999102072 |
|
|
Aug 27 06:29:56 PM UTC 24 |
Aug 27 06:29:59 PM UTC 24 |
26822268 ps |
| T963 |
/workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/49.spi_device_tpm_read_hw_reg.2998176457 |
|
|
Aug 27 06:29:56 PM UTC 24 |
Aug 27 06:29:59 PM UTC 24 |
17103130 ps |
| T964 |
/workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/40.spi_device_mailbox.2982906312 |
|
|
Aug 27 06:27:02 PM UTC 24 |
Aug 27 06:30:00 PM UTC 24 |
48659359127 ps |
| T965 |
/workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/49.spi_device_tpm_sts_read.3562660113 |
|
|
Aug 27 06:29:58 PM UTC 24 |
Aug 27 06:30:01 PM UTC 24 |
180359899 ps |
| T330 |
/workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/42.spi_device_flash_and_tpm_min_idle.1070161253 |
|
|
Aug 27 06:27:42 PM UTC 24 |
Aug 27 06:30:01 PM UTC 24 |
13943440911 ps |
| T966 |
/workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/49.spi_device_tpm_rw.336762896 |
|
|
Aug 27 06:30:01 PM UTC 24 |
Aug 27 06:30:04 PM UTC 24 |
119761461 ps |
| T967 |
/workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/48.spi_device_tpm_all.2944479132 |
|
|
Aug 27 06:29:39 PM UTC 24 |
Aug 27 06:30:06 PM UTC 24 |
8948376479 ps |
| T968 |
/workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/26.spi_device_flash_mode_ignore_cmds.148666824 |
|
|
Aug 27 06:21:53 PM UTC 24 |
Aug 27 06:30:06 PM UTC 24 |
341138059894 ps |
| T969 |
/workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/49.spi_device_pass_addr_payload_swap.250638296 |
|
|
Aug 27 06:30:01 PM UTC 24 |
Aug 27 06:30:08 PM UTC 24 |
448440438 ps |
| T970 |
/workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/48.spi_device_flash_mode.164104625 |
|
|
Aug 27 06:29:46 PM UTC 24 |
Aug 27 06:30:08 PM UTC 24 |
1086324163 ps |
| T971 |
/workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/49.spi_device_pass_cmd_filtering.3857871803 |
|
|
Aug 27 06:30:01 PM UTC 24 |
Aug 27 06:30:08 PM UTC 24 |
602244068 ps |
| T972 |
/workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/49.spi_device_upload.1849895592 |
|
|
Aug 27 06:30:03 PM UTC 24 |
Aug 27 06:30:08 PM UTC 24 |
674008488 ps |
| T973 |
/workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/46.spi_device_flash_and_tpm_min_idle.468599319 |
|
|
Aug 27 06:29:17 PM UTC 24 |
Aug 27 06:30:10 PM UTC 24 |
23804485806 ps |
| T974 |
/workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/48.spi_device_flash_all.1006749277 |
|
|
Aug 27 06:29:50 PM UTC 24 |
Aug 27 06:30:10 PM UTC 24 |
2584706697 ps |
| T975 |
/workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/49.spi_device_cfg_cmd.606979591 |
|
|
Aug 27 06:30:05 PM UTC 24 |
Aug 27 06:30:10 PM UTC 24 |
472720975 ps |
| T976 |
/workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/49.spi_device_alert_test.4188725051 |
|
|
Aug 27 06:30:11 PM UTC 24 |
Aug 27 06:30:14 PM UTC 24 |
19789074 ps |
| T977 |
/workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/43.spi_device_flash_and_tpm_min_idle.278108073 |
|
|
Aug 27 06:28:05 PM UTC 24 |
Aug 27 06:30:16 PM UTC 24 |
5913852903 ps |
| T978 |
/workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/49.spi_device_intercept.526743916 |
|
|
Aug 27 06:30:02 PM UTC 24 |
Aug 27 06:30:17 PM UTC 24 |
6143633705 ps |
| T979 |
/workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/49.spi_device_read_buffer_direct.4175538689 |
|
|
Aug 27 06:30:10 PM UTC 24 |
Aug 27 06:30:22 PM UTC 24 |
2068589994 ps |
| T980 |
/workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/40.spi_device_flash_mode_ignore_cmds.3531532379 |
|
|
Aug 27 06:27:04 PM UTC 24 |
Aug 27 06:30:25 PM UTC 24 |
22440037992 ps |
| T981 |
/workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/49.spi_device_tpm_all.2695477112 |
|
|
Aug 27 06:29:58 PM UTC 24 |
Aug 27 06:30:30 PM UTC 24 |
5727494219 ps |
| T982 |
/workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/49.spi_device_flash_mode.3357682633 |
|
|
Aug 27 06:30:06 PM UTC 24 |
Aug 27 06:30:31 PM UTC 24 |
2235810452 ps |
| T983 |
/workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/49.spi_device_flash_mode_ignore_cmds.654621323 |
|
|
Aug 27 06:30:08 PM UTC 24 |
Aug 27 06:30:50 PM UTC 24 |
1279071176 ps |
| T984 |
/workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/48.spi_device_mailbox.2021648615 |
|
|
Aug 27 06:29:44 PM UTC 24 |
Aug 27 06:30:58 PM UTC 24 |
10318199605 ps |
| T985 |
/workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/46.spi_device_flash_mode_ignore_cmds.2355851574 |
|
|
Aug 27 06:29:11 PM UTC 24 |
Aug 27 06:31:09 PM UTC 24 |
29508119721 ps |
| T73 |
/workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/40.spi_device_flash_and_tpm_min_idle.3223203807 |
|
|
Aug 27 06:27:06 PM UTC 24 |
Aug 27 06:31:14 PM UTC 24 |
100244723809 ps |
| T986 |
/workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/47.spi_device_flash_and_tpm_min_idle.313719656 |
|
|
Aug 27 06:29:32 PM UTC 24 |
Aug 27 06:31:15 PM UTC 24 |
6383562903 ps |
| T74 |
/workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/43.spi_device_flash_and_tpm.240350668 |
|
|
Aug 27 06:28:05 PM UTC 24 |
Aug 27 06:31:16 PM UTC 24 |
20486337466 ps |
| T987 |
/workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/49.spi_device_flash_all.3634932725 |
|
|
Aug 27 06:30:10 PM UTC 24 |
Aug 27 06:31:16 PM UTC 24 |
21526531893 ps |
| T988 |
/workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/48.spi_device_stress_all.3442084557 |
|
|
Aug 27 06:29:54 PM UTC 24 |
Aug 27 06:31:18 PM UTC 24 |
8037871903 ps |
| T989 |
/workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/48.spi_device_flash_mode_ignore_cmds.3102525935 |
|
|
Aug 27 06:29:48 PM UTC 24 |
Aug 27 06:31:20 PM UTC 24 |
26176901861 ps |
| T75 |
/workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/34.spi_device_flash_and_tpm.1762196591 |
|
|
Aug 27 06:25:35 PM UTC 24 |
Aug 27 06:31:22 PM UTC 24 |
191926502423 ps |
| T990 |
/workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/49.spi_device_mailbox.2272896690 |
|
|
Aug 27 06:30:03 PM UTC 24 |
Aug 27 06:31:27 PM UTC 24 |
39690930603 ps |
| T991 |
/workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/49.spi_device_flash_and_tpm_min_idle.4235996416 |
|
|
Aug 27 06:30:10 PM UTC 24 |
Aug 27 06:31:46 PM UTC 24 |
10844896485 ps |
| T76 |
/workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/34.spi_device_stress_all.863474829 |
|
|
Aug 27 06:25:35 PM UTC 24 |
Aug 27 06:31:54 PM UTC 24 |
24979471721 ps |
| T992 |
/workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/31.spi_device_flash_and_tpm_min_idle.1538971064 |
|
|
Aug 27 06:24:09 PM UTC 24 |
Aug 27 06:31:58 PM UTC 24 |
875497392787 ps |
| T993 |
/workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/41.spi_device_flash_and_tpm.387763037 |
|
|
Aug 27 06:27:19 PM UTC 24 |
Aug 27 06:32:16 PM UTC 24 |
154161430181 ps |
| T994 |
/workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/45.spi_device_flash_and_tpm_min_idle.2518803158 |
|
|
Aug 27 06:28:53 PM UTC 24 |
Aug 27 06:32:20 PM UTC 24 |
290052989019 ps |
| T995 |
/workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/39.spi_device_flash_and_tpm_min_idle.1497210994 |
|
|
Aug 27 06:26:54 PM UTC 24 |
Aug 27 06:32:27 PM UTC 24 |
67061664906 ps |
| T996 |
/workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/39.spi_device_stress_all.1651736834 |
|
|
Aug 27 06:26:54 PM UTC 24 |
Aug 27 06:32:55 PM UTC 24 |
134242448670 ps |
| T997 |
/workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/45.spi_device_stress_all.3254481539 |
|
|
Aug 27 06:28:54 PM UTC 24 |
Aug 27 06:33:00 PM UTC 24 |
58158868265 ps |
| T998 |
/workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/41.spi_device_flash_and_tpm_min_idle.442551437 |
|
|
Aug 27 06:27:19 PM UTC 24 |
Aug 27 06:33:03 PM UTC 24 |
101509938215 ps |
| T999 |
/workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/5.spi_device_stress_all.2151062809 |
|
|
Aug 27 06:12:38 PM UTC 24 |
Aug 27 06:33:11 PM UTC 24 |
111025638747 ps |
| T1000 |
/workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/42.spi_device_stress_all.1886053943 |
|
|
Aug 27 06:27:43 PM UTC 24 |
Aug 27 06:33:46 PM UTC 24 |
30999159699 ps |
| T1001 |
/workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/49.spi_device_flash_and_tpm.1541209361 |
|
|
Aug 27 06:30:10 PM UTC 24 |
Aug 27 06:33:55 PM UTC 24 |
23398728027 ps |
| T1002 |
/workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/47.spi_device_flash_all.2715659163 |
|
|
Aug 27 06:29:28 PM UTC 24 |
Aug 27 06:33:58 PM UTC 24 |
72142005574 ps |
| T1003 |
/workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/43.spi_device_flash_mode_ignore_cmds.1363620825 |
|
|
Aug 27 06:28:00 PM UTC 24 |
Aug 27 06:33:58 PM UTC 24 |
155926060233 ps |
| T1004 |
/workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/46.spi_device_flash_and_tpm.605770936 |
|
|
Aug 27 06:29:15 PM UTC 24 |
Aug 27 06:34:02 PM UTC 24 |
590951874875 ps |
| T77 |
/workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/26.spi_device_flash_and_tpm_min_idle.3895356658 |
|
|
Aug 27 06:21:56 PM UTC 24 |
Aug 27 06:34:08 PM UTC 24 |
255826696401 ps |
| T78 |
/workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/36.spi_device_stress_all.28831477 |
|
|
Aug 27 06:26:08 PM UTC 24 |
Aug 27 06:34:12 PM UTC 24 |
87631974375 ps |
| T1005 |
/workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/36.spi_device_flash_and_tpm.3623827047 |
|
|
Aug 27 06:26:06 PM UTC 24 |
Aug 27 06:34:22 PM UTC 24 |
101058032391 ps |
| T1006 |
/workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/46.spi_device_flash_all.1090087338 |
|
|
Aug 27 06:29:15 PM UTC 24 |
Aug 27 06:34:22 PM UTC 24 |
144550200335 ps |
| T1007 |
/workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/48.spi_device_flash_and_tpm.1482593153 |
|
|
Aug 27 06:29:51 PM UTC 24 |
Aug 27 06:34:46 PM UTC 24 |
36273871881 ps |
| T345 |
/workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/43.spi_device_stress_all.3463639566 |
|
|
Aug 27 06:28:07 PM UTC 24 |
Aug 27 06:35:05 PM UTC 24 |
98419102644 ps |
| T348 |
/workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/39.spi_device_flash_all.3164646662 |
|
|
Aug 27 06:26:52 PM UTC 24 |
Aug 27 06:35:13 PM UTC 24 |
60163659807 ps |
| T1008 |
/workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/37.spi_device_stress_all.2846922303 |
|
|
Aug 27 06:26:22 PM UTC 24 |
Aug 27 06:35:38 PM UTC 24 |
228977655012 ps |
| T1009 |
/workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/47.spi_device_flash_mode_ignore_cmds.386735475 |
|
|
Aug 27 06:29:26 PM UTC 24 |
Aug 27 06:35:44 PM UTC 24 |
148083418289 ps |
| T1010 |
/workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/49.spi_device_stress_all.1384842492 |
|
|
Aug 27 06:30:10 PM UTC 24 |
Aug 27 06:36:06 PM UTC 24 |
232232205656 ps |
| T1011 |
/workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/44.spi_device_stress_all.317529455 |
|
|
Aug 27 06:28:32 PM UTC 24 |
Aug 27 06:37:56 PM UTC 24 |
33499816856 ps |
| T1012 |
/workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/46.spi_device_stress_all.458696863 |
|
|
Aug 27 06:29:17 PM UTC 24 |
Aug 27 06:38:59 PM UTC 24 |
214768899640 ps |
| T1013 |
/workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/48.spi_device_flash_and_tpm_min_idle.1679675992 |
|
|
Aug 27 06:29:51 PM UTC 24 |
Aug 27 06:39:02 PM UTC 24 |
205706333876 ps |
| T39 |
/workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/47.spi_device_flash_and_tpm.468383726 |
|
|
Aug 27 06:29:32 PM UTC 24 |
Aug 27 06:40:03 PM UTC 24 |
194877741927 ps |
| T1014 |
/workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/41.spi_device_stress_all.739296169 |
|
|
Aug 27 06:27:21 PM UTC 24 |
Aug 27 06:46:51 PM UTC 24 |
127217337873 ps |
| T1015 |
/workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/0.spi_device_mem_walk.2468397394 |
|
|
Aug 27 07:34:23 AM UTC 24 |
Aug 27 07:34:25 AM UTC 24 |
11815997 ps |
| T1016 |
/workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/0.spi_device_intr_test.3878601168 |
|
|
Aug 27 07:34:23 AM UTC 24 |
Aug 27 07:34:25 AM UTC 24 |
36533392 ps |
| T101 |
/workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/0.spi_device_csr_hw_reset.2421195451 |
|
|
Aug 27 07:34:23 AM UTC 24 |
Aug 27 07:34:26 AM UTC 24 |
67808103 ps |
| T133 |
/workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/0.spi_device_mem_partial_access.2268894849 |
|
|
Aug 27 07:34:23 AM UTC 24 |
Aug 27 07:34:26 AM UTC 24 |
70506827 ps |
| T134 |
/workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/0.spi_device_csr_rw.3146174190 |
|
|
Aug 27 07:34:23 AM UTC 24 |
Aug 27 07:34:26 AM UTC 24 |
59881245 ps |
| T1017 |
/workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/1.spi_device_mem_walk.1847580673 |
|
|
Aug 27 07:34:25 AM UTC 24 |
Aug 27 07:34:27 AM UTC 24 |
11571999 ps |
| T1018 |
/workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/1.spi_device_intr_test.2764897711 |
|
|
Aug 27 07:34:25 AM UTC 24 |
Aug 27 07:34:28 AM UTC 24 |
23430273 ps |
| T102 |
/workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/1.spi_device_csr_hw_reset.4235544938 |
|
|
Aug 27 07:34:26 AM UTC 24 |
Aug 27 07:34:28 AM UTC 24 |
23214687 ps |
| T93 |
/workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/0.spi_device_tl_errors.1087031330 |
|
|
Aug 27 07:34:23 AM UTC 24 |
Aug 27 07:34:28 AM UTC 24 |
116679177 ps |
| T159 |
/workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/1.spi_device_csr_rw.2044886647 |
|
|
Aug 27 07:34:26 AM UTC 24 |
Aug 27 07:34:29 AM UTC 24 |
133491650 ps |
| T135 |
/workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/1.spi_device_mem_partial_access.1288075686 |
|
|
Aug 27 07:34:25 AM UTC 24 |
Aug 27 07:34:29 AM UTC 24 |
56413840 ps |
| T160 |
/workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/0.spi_device_same_csr_outstanding.670334406 |
|
|
Aug 27 07:34:25 AM UTC 24 |
Aug 27 07:34:30 AM UTC 24 |
429324301 ps |
| T94 |
/workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/1.spi_device_tl_errors.2866605862 |
|
|
Aug 27 07:34:25 AM UTC 24 |
Aug 27 07:34:30 AM UTC 24 |
214774843 ps |
| T95 |
/workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/0.spi_device_csr_mem_rw_with_rand_reset.2187547207 |
|
|
Aug 27 07:34:25 AM UTC 24 |
Aug 27 07:34:30 AM UTC 24 |
157520987 ps |
| T1019 |
/workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/2.spi_device_intr_test.709466021 |
|
|
Aug 27 07:34:28 AM UTC 24 |
Aug 27 07:34:30 AM UTC 24 |
34661489 ps |
| T131 |
/workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/1.spi_device_csr_mem_rw_with_rand_reset.3111030677 |
|
|
Aug 27 07:34:27 AM UTC 24 |
Aug 27 07:34:31 AM UTC 24 |
180268817 ps |
| T1020 |
/workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/2.spi_device_mem_walk.1164666629 |
|
|
Aug 27 07:34:29 AM UTC 24 |
Aug 27 07:34:31 AM UTC 24 |
24354989 ps |
| T112 |
/workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/2.spi_device_tl_errors.3324824672 |
|
|
Aug 27 07:34:27 AM UTC 24 |
Aug 27 07:34:31 AM UTC 24 |
420095169 ps |
| T103 |
/workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/2.spi_device_csr_hw_reset.2973451095 |
|
|
Aug 27 07:34:29 AM UTC 24 |
Aug 27 07:34:32 AM UTC 24 |
24402714 ps |
| T136 |
/workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/2.spi_device_csr_rw.1368115575 |
|
|
Aug 27 07:34:29 AM UTC 24 |
Aug 27 07:34:32 AM UTC 24 |
313521232 ps |
| T137 |
/workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/2.spi_device_mem_partial_access.1091362989 |
|
|
Aug 27 07:34:29 AM UTC 24 |
Aug 27 07:34:32 AM UTC 24 |
211412005 ps |
| T161 |
/workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/1.spi_device_same_csr_outstanding.50896403 |
|
|
Aug 27 07:34:27 AM UTC 24 |
Aug 27 07:34:33 AM UTC 24 |
322687050 ps |
| T1021 |
/workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/3.spi_device_mem_walk.885846780 |
|
|
Aug 27 07:34:32 AM UTC 24 |
Aug 27 07:34:34 AM UTC 24 |
10942860 ps |
| T1022 |
/workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/3.spi_device_intr_test.1390279668 |
|
|
Aug 27 07:34:32 AM UTC 24 |
Aug 27 07:34:34 AM UTC 24 |
38757880 ps |
| T113 |
/workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/3.spi_device_tl_errors.2320152512 |
|
|
Aug 27 07:34:31 AM UTC 24 |
Aug 27 07:34:35 AM UTC 24 |
123681446 ps |
| T1023 |
/workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/3.spi_device_csr_hw_reset.2136781878 |
|
|
Aug 27 07:34:32 AM UTC 24 |
Aug 27 07:34:35 AM UTC 24 |
112356401 ps |
| T162 |
/workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/2.spi_device_same_csr_outstanding.3403841891 |
|
|
Aug 27 07:34:31 AM UTC 24 |
Aug 27 07:34:36 AM UTC 24 |
43260835 ps |
| T1024 |
/workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/0.spi_device_csr_bit_bash.936425599 |
|
|
Aug 27 07:34:23 AM UTC 24 |
Aug 27 07:34:36 AM UTC 24 |
183915028 ps |
| T169 |
/workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/3.spi_device_csr_rw.2913292478 |
|
|
Aug 27 07:34:32 AM UTC 24 |
Aug 27 07:34:37 AM UTC 24 |
269198742 ps |
| T132 |
/workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/2.spi_device_csr_mem_rw_with_rand_reset.4046703455 |
|
|
Aug 27 07:34:31 AM UTC 24 |
Aug 27 07:34:37 AM UTC 24 |
129082458 ps |
| T138 |
/workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/3.spi_device_mem_partial_access.938936538 |
|
|
Aug 27 07:34:32 AM UTC 24 |
Aug 27 07:34:37 AM UTC 24 |
120130660 ps |
| T1025 |
/workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/4.spi_device_intr_test.3091876661 |
|
|
Aug 27 07:34:35 AM UTC 24 |
Aug 27 07:34:38 AM UTC 24 |
16370637 ps |
| T1026 |
/workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/3.spi_device_same_csr_outstanding.4004819864 |
|
|
Aug 27 07:34:33 AM UTC 24 |
Aug 27 07:34:38 AM UTC 24 |
417513952 ps |
| T129 |
/workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/3.spi_device_csr_mem_rw_with_rand_reset.3334664585 |
|
|
Aug 27 07:34:33 AM UTC 24 |
Aug 27 07:34:39 AM UTC 24 |
51652640 ps |
| T1027 |
/workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/4.spi_device_mem_walk.3933866929 |
|
|
Aug 27 07:34:37 AM UTC 24 |
Aug 27 07:34:39 AM UTC 24 |
77592148 ps |
| T139 |
/workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/4.spi_device_mem_partial_access.4210663043 |
|
|
Aug 27 07:34:37 AM UTC 24 |
Aug 27 07:34:39 AM UTC 24 |
21045632 ps |
| T140 |
/workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/4.spi_device_csr_hw_reset.2179119585 |
|
|
Aug 27 07:34:37 AM UTC 24 |
Aug 27 07:34:40 AM UTC 24 |
835068957 ps |
| T170 |
/workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/4.spi_device_csr_rw.2350056011 |
|
|
Aug 27 07:34:38 AM UTC 24 |
Aug 27 07:34:41 AM UTC 24 |
45274449 ps |
| T114 |
/workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/0.spi_device_tl_intg_err.3907047021 |
|
|
Aug 27 07:34:23 AM UTC 24 |
Aug 27 07:34:42 AM UTC 24 |
1188047949 ps |
| T1028 |
/workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/5.spi_device_intr_test.1388063578 |
|
|
Aug 27 07:34:40 AM UTC 24 |
Aug 27 07:34:42 AM UTC 24 |
64689288 ps |
| T123 |
/workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/5.spi_device_tl_errors.3384187266 |
|
|
Aug 27 07:34:39 AM UTC 24 |
Aug 27 07:34:43 AM UTC 24 |
244622976 ps |
| T141 |
/workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/0.spi_device_csr_aliasing.1769674453 |
|
|
Aug 27 07:34:25 AM UTC 24 |
Aug 27 07:34:44 AM UTC 24 |
675869099 ps |
| T1029 |
/workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/5.spi_device_csr_rw.4031961024 |
|
|
Aug 27 07:34:40 AM UTC 24 |
Aug 27 07:34:44 AM UTC 24 |
229603355 ps |
| T115 |
/workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/1.spi_device_tl_intg_err.2918884772 |
|
|
Aug 27 07:34:25 AM UTC 24 |
Aug 27 07:34:44 AM UTC 24 |
561459941 ps |