| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
| 96.04 | 98.38 | 94.01 | 98.62 | 89.36 | 97.19 | 95.45 | 99.26 |
| T1030 | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/4.spi_device_same_csr_outstanding.610359426 | Aug 27 07:34:38 AM UTC 24 | Aug 27 07:34:44 AM UTC 24 | 228632335 ps | ||
| T127 | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/5.spi_device_csr_mem_rw_with_rand_reset.1015269769 | Aug 27 07:34:41 AM UTC 24 | Aug 27 07:34:44 AM UTC 24 | 49413088 ps | ||
| T124 | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/4.spi_device_tl_errors.2713889187 | Aug 27 07:34:35 AM UTC 24 | Aug 27 07:34:45 AM UTC 24 | 249210994 ps | ||
| T116 | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/3.spi_device_tl_intg_err.2449288922 | Aug 27 07:34:31 AM UTC 24 | Aug 27 07:34:45 AM UTC 24 | 786166328 ps | ||
| T125 | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/4.spi_device_csr_mem_rw_with_rand_reset.1674521147 | Aug 27 07:34:39 AM UTC 24 | Aug 27 07:34:45 AM UTC 24 | 662768235 ps | ||
| T1031 | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/6.spi_device_intr_test.3032596371 | Aug 27 07:34:44 AM UTC 24 | Aug 27 07:34:46 AM UTC 24 | 16608666 ps | ||
| T1032 | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/5.spi_device_same_csr_outstanding.4082887973 | Aug 27 07:34:40 AM UTC 24 | Aug 27 07:34:47 AM UTC 24 | 311110675 ps | ||
| T1033 | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/7.spi_device_intr_test.1689233198 | Aug 27 07:34:45 AM UTC 24 | Aug 27 07:34:47 AM UTC 24 | 13974306 ps | ||
| T142 | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/6.spi_device_csr_rw.2453233179 | Aug 27 07:34:44 AM UTC 24 | Aug 27 07:34:47 AM UTC 24 | 134840842 ps | ||
| T143 | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/1.spi_device_csr_aliasing.2281004718 | Aug 27 07:34:27 AM UTC 24 | Aug 27 07:34:47 AM UTC 24 | 6103790613 ps | ||
| T1034 | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/6.spi_device_same_csr_outstanding.220196102 | Aug 27 07:34:45 AM UTC 24 | Aug 27 07:34:48 AM UTC 24 | 237457758 ps | ||
| T171 | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/6.spi_device_csr_mem_rw_with_rand_reset.2910633814 | Aug 27 07:34:45 AM UTC 24 | Aug 27 07:34:48 AM UTC 24 | 116080729 ps | ||
| T144 | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/7.spi_device_csr_rw.1961746620 | Aug 27 07:34:45 AM UTC 24 | Aug 27 07:34:48 AM UTC 24 | 112355332 ps | ||
| T1035 | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/3.spi_device_csr_aliasing.2676089606 | Aug 27 07:34:33 AM UTC 24 | Aug 27 07:34:49 AM UTC 24 | 846487789 ps | ||
| T121 | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/6.spi_device_tl_errors.3022479324 | Aug 27 07:34:42 AM UTC 24 | Aug 27 07:34:49 AM UTC 24 | 771298437 ps | ||
| T1036 | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/8.spi_device_intr_test.1119327156 | Aug 27 07:34:47 AM UTC 24 | Aug 27 07:34:50 AM UTC 24 | 111462308 ps | ||
| T1037 | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/7.spi_device_csr_mem_rw_with_rand_reset.1874046439 | Aug 27 07:34:46 AM UTC 24 | Aug 27 07:34:50 AM UTC 24 | 26639755 ps | ||
| T126 | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/2.spi_device_tl_intg_err.2306624384 | Aug 27 07:34:28 AM UTC 24 | Aug 27 07:34:50 AM UTC 24 | 293684294 ps | ||
| T122 | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/7.spi_device_tl_errors.1323391527 | Aug 27 07:34:45 AM UTC 24 | Aug 27 07:34:51 AM UTC 24 | 826364825 ps | ||
| T1038 | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/7.spi_device_same_csr_outstanding.841377299 | Aug 27 07:34:46 AM UTC 24 | Aug 27 07:34:52 AM UTC 24 | 591605778 ps | ||
| T1039 | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/9.spi_device_intr_test.1827133526 | Aug 27 07:34:50 AM UTC 24 | Aug 27 07:34:52 AM UTC 24 | 67095863 ps | ||
| T145 | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/8.spi_device_csr_rw.3638893699 | Aug 27 07:34:48 AM UTC 24 | Aug 27 07:34:53 AM UTC 24 | 308340134 ps | ||
| T128 | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/8.spi_device_tl_errors.979015709 | Aug 27 07:34:46 AM UTC 24 | Aug 27 07:34:53 AM UTC 24 | 174277605 ps | ||
| T1040 | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/8.spi_device_same_csr_outstanding.2760623088 | Aug 27 07:34:49 AM UTC 24 | Aug 27 07:34:53 AM UTC 24 | 48053384 ps | ||
| T1041 | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/9.spi_device_csr_rw.1466280136 | Aug 27 07:34:50 AM UTC 24 | Aug 27 07:34:53 AM UTC 24 | 165828207 ps | ||
| T1042 | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/10.spi_device_intr_test.1990657863 | Aug 27 07:34:51 AM UTC 24 | Aug 27 07:34:53 AM UTC 24 | 11798833 ps | ||
| T130 | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/9.spi_device_tl_errors.4026031260 | Aug 27 07:34:50 AM UTC 24 | Aug 27 07:34:54 AM UTC 24 | 35113022 ps | ||
| T1043 | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/2.spi_device_csr_aliasing.736704116 | Aug 27 07:34:31 AM UTC 24 | Aug 27 07:34:54 AM UTC 24 | 6972238975 ps | ||
| T1044 | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/8.spi_device_csr_mem_rw_with_rand_reset.2034016318 | Aug 27 07:34:49 AM UTC 24 | Aug 27 07:34:54 AM UTC 24 | 56950830 ps | ||
| T203 | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/4.spi_device_tl_intg_err.4262541807 | Aug 27 07:34:35 AM UTC 24 | Aug 27 07:34:55 AM UTC 24 | 338484297 ps | ||
| T1045 | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/9.spi_device_csr_mem_rw_with_rand_reset.3743911996 | Aug 27 07:34:51 AM UTC 24 | Aug 27 07:34:55 AM UTC 24 | 127998893 ps | ||
| T1046 | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/10.spi_device_csr_rw.2656702049 | Aug 27 07:34:52 AM UTC 24 | Aug 27 07:34:56 AM UTC 24 | 27102231 ps | ||
| T1047 | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/9.spi_device_same_csr_outstanding.3870766709 | Aug 27 07:34:50 AM UTC 24 | Aug 27 07:34:56 AM UTC 24 | 58579505 ps | ||
| T1048 | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/11.spi_device_intr_test.2350380614 | Aug 27 07:34:54 AM UTC 24 | Aug 27 07:34:57 AM UTC 24 | 15962818 ps | ||
| T1049 | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/10.spi_device_same_csr_outstanding.220860847 | Aug 27 07:34:53 AM UTC 24 | Aug 27 07:34:57 AM UTC 24 | 25900464 ps | ||
| T1050 | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/10.spi_device_csr_mem_rw_with_rand_reset.1839499975 | Aug 27 07:34:53 AM UTC 24 | Aug 27 07:34:57 AM UTC 24 | 198152734 ps | ||
| T146 | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/3.spi_device_csr_bit_bash.1087731497 | Aug 27 07:34:33 AM UTC 24 | Aug 27 07:34:57 AM UTC 24 | 1398311958 ps | ||
| T199 | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/10.spi_device_tl_errors.1043120508 | Aug 27 07:34:51 AM UTC 24 | Aug 27 07:34:58 AM UTC 24 | 299431296 ps | ||
| T1051 | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/12.spi_device_intr_test.2779567445 | Aug 27 07:34:56 AM UTC 24 | Aug 27 07:34:58 AM UTC 24 | 37381391 ps | ||
| T147 | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/11.spi_device_csr_rw.546758615 | Aug 27 07:34:54 AM UTC 24 | Aug 27 07:34:58 AM UTC 24 | 256393076 ps | ||
| T172 | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/11.spi_device_same_csr_outstanding.2604196016 | Aug 27 07:34:55 AM UTC 24 | Aug 27 07:34:58 AM UTC 24 | 138641855 ps | ||
| T200 | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/11.spi_device_csr_mem_rw_with_rand_reset.2393821367 | Aug 27 07:34:55 AM UTC 24 | Aug 27 07:34:58 AM UTC 24 | 138659274 ps | ||
| T1052 | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/4.spi_device_csr_aliasing.2349237189 | Aug 27 07:34:38 AM UTC 24 | Aug 27 07:34:59 AM UTC 24 | 307039230 ps | ||
| T173 | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/12.spi_device_csr_rw.2530826670 | Aug 27 07:34:56 AM UTC 24 | Aug 27 07:35:00 AM UTC 24 | 75375350 ps | ||
| T1053 | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/11.spi_device_tl_errors.4231743120 | Aug 27 07:34:53 AM UTC 24 | Aug 27 07:35:00 AM UTC 24 | 375590050 ps | ||
| T1054 | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/13.spi_device_intr_test.359535293 | Aug 27 07:34:58 AM UTC 24 | Aug 27 07:35:00 AM UTC 24 | 18294387 ps | ||
| T174 | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/6.spi_device_tl_intg_err.1799361987 | Aug 27 07:34:44 AM UTC 24 | Aug 27 07:35:00 AM UTC 24 | 1286537527 ps | ||
| T1055 | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/12.spi_device_tl_errors.403715182 | Aug 27 07:34:55 AM UTC 24 | Aug 27 07:35:00 AM UTC 24 | 65835327 ps | ||
| T1056 | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/13.spi_device_csr_mem_rw_with_rand_reset.1804938900 | Aug 27 07:34:58 AM UTC 24 | Aug 27 07:35:01 AM UTC 24 | 104006777 ps | ||
| T1057 | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/1.spi_device_csr_bit_bash.1877672741 | Aug 27 07:34:26 AM UTC 24 | Aug 27 07:35:01 AM UTC 24 | 3691453154 ps | ||
| T1058 | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/14.spi_device_intr_test.3358364763 | Aug 27 07:34:59 AM UTC 24 | Aug 27 07:35:01 AM UTC 24 | 12652671 ps | ||
| T1059 | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/12.spi_device_csr_mem_rw_with_rand_reset.2828927 | Aug 27 07:34:57 AM UTC 24 | Aug 27 07:35:02 AM UTC 24 | 787302327 ps | ||
| T1060 | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/13.spi_device_csr_rw.76023149 | Aug 27 07:34:58 AM UTC 24 | Aug 27 07:35:02 AM UTC 24 | 195390777 ps | ||
| T1061 | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/34.spi_device_intr_test.2505865512 | Aug 27 07:35:11 AM UTC 24 | Aug 27 07:35:13 AM UTC 24 | 16285134 ps | ||
| T1062 | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/4.spi_device_csr_bit_bash.2731069916 | Aug 27 07:34:38 AM UTC 24 | Aug 27 07:35:02 AM UTC 24 | 735930843 ps | ||
| T175 | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/12.spi_device_same_csr_outstanding.1170385894 | Aug 27 07:34:57 AM UTC 24 | Aug 27 07:35:03 AM UTC 24 | 349169641 ps | ||
| T1063 | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/13.spi_device_same_csr_outstanding.2042305369 | Aug 27 07:34:58 AM UTC 24 | Aug 27 07:35:03 AM UTC 24 | 255298900 ps | ||
| T204 | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/8.spi_device_tl_intg_err.4147803364 | Aug 27 07:34:46 AM UTC 24 | Aug 27 07:35:03 AM UTC 24 | 8415087358 ps | ||
| T1064 | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/14.spi_device_csr_rw.2960964206 | Aug 27 07:35:01 AM UTC 24 | Aug 27 07:35:03 AM UTC 24 | 21436233 ps | ||
| T1065 | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/13.spi_device_tl_errors.322971356 | Aug 27 07:34:57 AM UTC 24 | Aug 27 07:35:03 AM UTC 24 | 309023605 ps | ||
| T1066 | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/14.spi_device_same_csr_outstanding.3226026816 | Aug 27 07:35:01 AM UTC 24 | Aug 27 07:35:04 AM UTC 24 | 141144692 ps | ||
| T1067 | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/15.spi_device_tl_errors.68121779 | Aug 27 07:35:01 AM UTC 24 | Aug 27 07:35:04 AM UTC 24 | 89470973 ps | ||
| T201 | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/7.spi_device_tl_intg_err.2720883482 | Aug 27 07:34:45 AM UTC 24 | Aug 27 07:35:04 AM UTC 24 | 913035912 ps | ||
| T1068 | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/15.spi_device_intr_test.3368664061 | Aug 27 07:35:02 AM UTC 24 | Aug 27 07:35:04 AM UTC 24 | 22215564 ps | ||
| T202 | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/5.spi_device_tl_intg_err.2461809705 | Aug 27 07:34:40 AM UTC 24 | Aug 27 07:35:04 AM UTC 24 | 856589174 ps | ||
| T1069 | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/9.spi_device_tl_intg_err.644145651 | Aug 27 07:34:50 AM UTC 24 | Aug 27 07:35:04 AM UTC 24 | 200545324 ps | ||
| T1070 | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/16.spi_device_intr_test.44128741 | Aug 27 07:35:03 AM UTC 24 | Aug 27 07:35:05 AM UTC 24 | 23614741 ps | ||
| T205 | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/10.spi_device_tl_intg_err.863059000 | Aug 27 07:34:51 AM UTC 24 | Aug 27 07:35:05 AM UTC 24 | 801245020 ps | ||
| T1071 | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/16.spi_device_csr_rw.1629231784 | Aug 27 07:35:03 AM UTC 24 | Aug 27 07:35:06 AM UTC 24 | 18045779 ps | ||
| T1072 | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/15.spi_device_csr_rw.1902308075 | Aug 27 07:35:02 AM UTC 24 | Aug 27 07:35:06 AM UTC 24 | 371734110 ps | ||
| T1073 | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/14.spi_device_csr_mem_rw_with_rand_reset.641185434 | Aug 27 07:35:01 AM UTC 24 | Aug 27 07:35:06 AM UTC 24 | 213163740 ps | ||
| T1074 | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/2.spi_device_csr_bit_bash.1782463407 | Aug 27 07:34:29 AM UTC 24 | Aug 27 07:35:06 AM UTC 24 | 1852195640 ps | ||
| T1075 | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/16.spi_device_tl_errors.3510339118 | Aug 27 07:35:03 AM UTC 24 | Aug 27 07:35:06 AM UTC 24 | 93646970 ps | ||
| T1076 | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/14.spi_device_tl_errors.109906451 | Aug 27 07:34:58 AM UTC 24 | Aug 27 07:35:06 AM UTC 24 | 1175930786 ps | ||
| T1077 | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/17.spi_device_intr_test.2214839270 | Aug 27 07:35:04 AM UTC 24 | Aug 27 07:35:06 AM UTC 24 | 17657862 ps | ||
| T1078 | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/15.spi_device_same_csr_outstanding.635128948 | Aug 27 07:35:02 AM UTC 24 | Aug 27 07:35:07 AM UTC 24 | 778465213 ps | ||
| T1079 | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/11.spi_device_tl_intg_err.1111752309 | Aug 27 07:34:53 AM UTC 24 | Aug 27 07:35:08 AM UTC 24 | 694959893 ps | ||
| T1080 | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/18.spi_device_intr_test.1915032869 | Aug 27 07:35:06 AM UTC 24 | Aug 27 07:35:08 AM UTC 24 | 77775862 ps | ||
| T1081 | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/17.spi_device_csr_rw.2648122258 | Aug 27 07:35:05 AM UTC 24 | Aug 27 07:35:08 AM UTC 24 | 77083523 ps | ||
| T1082 | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/18.spi_device_tl_errors.522207386 | Aug 27 07:35:05 AM UTC 24 | Aug 27 07:35:08 AM UTC 24 | 153371525 ps | ||
| T1083 | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/14.spi_device_tl_intg_err.377286030 | Aug 27 07:34:59 AM UTC 24 | Aug 27 07:35:08 AM UTC 24 | 102117993 ps | ||
| T1084 | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/17.spi_device_same_csr_outstanding.2623650002 | Aug 27 07:35:05 AM UTC 24 | Aug 27 07:35:08 AM UTC 24 | 96557857 ps | ||
| T1085 | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/15.spi_device_csr_mem_rw_with_rand_reset.1473948984 | Aug 27 07:35:02 AM UTC 24 | Aug 27 07:35:09 AM UTC 24 | 201194915 ps | ||
| T1086 | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/17.spi_device_csr_mem_rw_with_rand_reset.2398294517 | Aug 27 07:35:05 AM UTC 24 | Aug 27 07:35:09 AM UTC 24 | 93398965 ps | ||
| T1087 | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/18.spi_device_csr_rw.769801675 | Aug 27 07:35:06 AM UTC 24 | Aug 27 07:35:09 AM UTC 24 | 30395566 ps | ||
| T1088 | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/16.spi_device_same_csr_outstanding.414639438 | Aug 27 07:35:04 AM UTC 24 | Aug 27 07:35:09 AM UTC 24 | 2583510706 ps | ||
| T1089 | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/19.spi_device_intr_test.3280461518 | Aug 27 07:35:07 AM UTC 24 | Aug 27 07:35:09 AM UTC 24 | 16159496 ps | ||
| T1090 | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/16.spi_device_csr_mem_rw_with_rand_reset.4012771142 | Aug 27 07:35:04 AM UTC 24 | Aug 27 07:35:09 AM UTC 24 | 58189334 ps | ||
| T1091 | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/23.spi_device_intr_test.1551309095 | Aug 27 07:35:08 AM UTC 24 | Aug 27 07:35:10 AM UTC 24 | 17220231 ps | ||
| T1092 | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/21.spi_device_intr_test.3816342414 | Aug 27 07:35:08 AM UTC 24 | Aug 27 07:35:10 AM UTC 24 | 13191198 ps | ||
| T1093 | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/22.spi_device_intr_test.933026851 | Aug 27 07:35:08 AM UTC 24 | Aug 27 07:35:10 AM UTC 24 | 102883835 ps | ||
| T1094 | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/19.spi_device_csr_rw.4151415202 | Aug 27 07:35:07 AM UTC 24 | Aug 27 07:35:10 AM UTC 24 | 249638962 ps | ||
| T1095 | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/20.spi_device_intr_test.2256799836 | Aug 27 07:35:08 AM UTC 24 | Aug 27 07:35:10 AM UTC 24 | 18093491 ps | ||
| T1096 | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/15.spi_device_tl_intg_err.4055314087 | Aug 27 07:35:02 AM UTC 24 | Aug 27 07:35:10 AM UTC 24 | 232762748 ps | ||
| T1097 | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/17.spi_device_tl_errors.3529298426 | Aug 27 07:35:04 AM UTC 24 | Aug 27 07:35:11 AM UTC 24 | 1927943819 ps | ||
| T206 | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/12.spi_device_tl_intg_err.1750673704 | Aug 27 07:34:56 AM UTC 24 | Aug 27 07:35:11 AM UTC 24 | 211208597 ps | ||
| T1098 | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/19.spi_device_csr_mem_rw_with_rand_reset.1941670696 | Aug 27 07:35:08 AM UTC 24 | Aug 27 07:35:11 AM UTC 24 | 29777532 ps | ||
| T1099 | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/19.spi_device_same_csr_outstanding.1180927235 | Aug 27 07:35:07 AM UTC 24 | Aug 27 07:35:12 AM UTC 24 | 134456816 ps | ||
| T1100 | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/24.spi_device_intr_test.2214504452 | Aug 27 07:35:10 AM UTC 24 | Aug 27 07:35:12 AM UTC 24 | 46635091 ps | ||
| T1101 | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/25.spi_device_intr_test.3238713177 | Aug 27 07:35:10 AM UTC 24 | Aug 27 07:35:12 AM UTC 24 | 40060168 ps | ||
| T1102 | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/16.spi_device_tl_intg_err.2335484477 | Aug 27 07:35:03 AM UTC 24 | Aug 27 07:35:12 AM UTC 24 | 223557843 ps | ||
| T1103 | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/27.spi_device_intr_test.3275856949 | Aug 27 07:35:10 AM UTC 24 | Aug 27 07:35:12 AM UTC 24 | 55482189 ps | ||
| T1104 | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/26.spi_device_intr_test.371212984 | Aug 27 07:35:10 AM UTC 24 | Aug 27 07:35:12 AM UTC 24 | 16406441 ps | ||
| T1105 | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/29.spi_device_intr_test.784254267 | Aug 27 07:35:10 AM UTC 24 | Aug 27 07:35:12 AM UTC 24 | 33752062 ps | ||
| T1106 | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/30.spi_device_intr_test.484951680 | Aug 27 07:35:10 AM UTC 24 | Aug 27 07:35:12 AM UTC 24 | 46249997 ps | ||
| T1107 | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/32.spi_device_intr_test.2093313930 | Aug 27 07:35:10 AM UTC 24 | Aug 27 07:35:12 AM UTC 24 | 49014462 ps | ||
| T1108 | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/19.spi_device_tl_errors.3096376107 | Aug 27 07:35:07 AM UTC 24 | Aug 27 07:35:12 AM UTC 24 | 144543436 ps | ||
| T1109 | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/28.spi_device_intr_test.3366169560 | Aug 27 07:35:10 AM UTC 24 | Aug 27 07:35:12 AM UTC 24 | 62086488 ps | ||
| T1110 | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/31.spi_device_intr_test.3467637559 | Aug 27 07:35:10 AM UTC 24 | Aug 27 07:35:12 AM UTC 24 | 11829442 ps | ||
| T1111 | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/18.spi_device_same_csr_outstanding.3112740076 | Aug 27 07:35:07 AM UTC 24 | Aug 27 07:35:12 AM UTC 24 | 162227623 ps | ||
| T1112 | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/33.spi_device_intr_test.1492495122 | Aug 27 07:35:11 AM UTC 24 | Aug 27 07:35:13 AM UTC 24 | 13301607 ps | ||
| T1113 | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/36.spi_device_intr_test.1689488489 | Aug 27 07:35:11 AM UTC 24 | Aug 27 07:35:13 AM UTC 24 | 14064615 ps | ||
| T1114 | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/18.spi_device_csr_mem_rw_with_rand_reset.417554455 | Aug 27 07:35:07 AM UTC 24 | Aug 27 07:35:13 AM UTC 24 | 495704857 ps | ||
| T1115 | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/35.spi_device_intr_test.192765484 | Aug 27 07:35:11 AM UTC 24 | Aug 27 07:35:13 AM UTC 24 | 41766298 ps | ||
| T1116 | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/37.spi_device_intr_test.3804120000 | Aug 27 07:35:11 AM UTC 24 | Aug 27 07:35:13 AM UTC 24 | 185497189 ps | ||
| T1117 | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/38.spi_device_intr_test.1156848839 | Aug 27 07:35:11 AM UTC 24 | Aug 27 07:35:13 AM UTC 24 | 26532441 ps | ||
| T1118 | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/39.spi_device_intr_test.4126463385 | Aug 27 07:35:11 AM UTC 24 | Aug 27 07:35:13 AM UTC 24 | 14184521 ps | ||
| T1119 | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/41.spi_device_intr_test.198810013 | Aug 27 07:35:12 AM UTC 24 | Aug 27 07:35:14 AM UTC 24 | 18392427 ps | ||
| T207 | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/13.spi_device_tl_intg_err.3000971553 | Aug 27 07:34:57 AM UTC 24 | Aug 27 07:35:14 AM UTC 24 | 4111920267 ps | ||
| T1120 | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/42.spi_device_intr_test.3543670212 | Aug 27 07:35:12 AM UTC 24 | Aug 27 07:35:14 AM UTC 24 | 31927608 ps | ||
| T1121 | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/40.spi_device_intr_test.1600300285 | Aug 27 07:35:12 AM UTC 24 | Aug 27 07:35:14 AM UTC 24 | 47884196 ps | ||
| T1122 | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/44.spi_device_intr_test.1611187733 | Aug 27 07:35:13 AM UTC 24 | Aug 27 07:35:14 AM UTC 24 | 20092714 ps | ||
| T1123 | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/43.spi_device_intr_test.837233944 | Aug 27 07:35:12 AM UTC 24 | Aug 27 07:35:14 AM UTC 24 | 11632849 ps | ||
| T1124 | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/45.spi_device_intr_test.1361079737 | Aug 27 07:35:13 AM UTC 24 | Aug 27 07:35:14 AM UTC 24 | 16152110 ps | ||
| T1125 | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/49.spi_device_intr_test.2836792070 | Aug 27 07:35:13 AM UTC 24 | Aug 27 07:35:14 AM UTC 24 | 43234170 ps | ||
| T1126 | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/48.spi_device_intr_test.3680108146 | Aug 27 07:35:13 AM UTC 24 | Aug 27 07:35:15 AM UTC 24 | 104239391 ps | ||
| T1127 | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/47.spi_device_intr_test.1733338392 | Aug 27 07:35:13 AM UTC 24 | Aug 27 07:35:15 AM UTC 24 | 46613521 ps | ||
| T1128 | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/46.spi_device_intr_test.1361167500 | Aug 27 07:35:13 AM UTC 24 | Aug 27 07:35:15 AM UTC 24 | 12375303 ps | ||
| T1129 | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/17.spi_device_tl_intg_err.2165937185 | Aug 27 07:35:04 AM UTC 24 | Aug 27 07:35:20 AM UTC 24 | 594929744 ps | ||
| T1130 | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/19.spi_device_tl_intg_err.739673328 | Aug 27 07:35:07 AM UTC 24 | Aug 27 07:35:23 AM UTC 24 | 701796387 ps | ||
| T1131 | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/18.spi_device_tl_intg_err.1100673558 | Aug 27 07:35:06 AM UTC 24 | Aug 27 07:35:25 AM UTC 24 | 290564242 ps |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/0.spi_device_pass_addr_payload_swap.203693147 |
| Short name | T9 |
| Test name | |
| Test status | |
| Simulation time | 2776335257 ps |
| CPU time | 21.69 seconds |
| Started | Aug 27 06:07:42 PM UTC 24 |
| Finished | Aug 27 06:08:05 PM UTC 24 |
| Peak memory | 245336 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=203693147 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_26/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_pass_addr_payload_swap.203693147 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/0.spi_device_pass_addr_payload_swap/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/1.spi_device_flash_and_tpm.1826640386 |
| Short name | T41 |
| Test name | |
| Test status | |
| Simulation time | 3905834078 ps |
| CPU time | 62.48 seconds |
| Started | Aug 27 06:09:45 PM UTC 24 |
| Finished | Aug 27 06:10:50 PM UTC 24 |
| Peak memory | 278248 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1826640386 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_ 26/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_and_tpm.1826640386 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/1.spi_device_flash_and_tpm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/0.spi_device_flash_mode_ignore_cmds.457368863 |
| Short name | T13 |
| Test name | |
| Test status | |
| Simulation time | 1616509982 ps |
| CPU time | 18.7 seconds |
| Started | Aug 27 06:08:06 PM UTC 24 |
| Finished | Aug 27 06:08:26 PM UTC 24 |
| Peak memory | 234968 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=457368863 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_26/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_mode_ignore_cmds.457368863 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/0.spi_device_flash_mode_ignore_cmds/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/0.spi_device_stress_all.23632621 |
| Short name | T34 |
| Test name | |
| Test status | |
| Simulation time | 115643239725 ps |
| CPU time | 372.65 seconds |
| Started | Aug 27 06:08:27 PM UTC 24 |
| Finished | Aug 27 06:14:44 PM UTC 24 |
| Peak memory | 267940 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=23632621 -assert nopostproc +UVM_TE STNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_stress_all.23632621 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/0.spi_device_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/1.spi_device_tpm_all.1724628067 |
| Short name | T24 |
| Test name | |
| Test status | |
| Simulation time | 1243285490 ps |
| CPU time | 9.69 seconds |
| Started | Aug 27 06:08:42 PM UTC 24 |
| Finished | Aug 27 06:08:53 PM UTC 24 |
| Peak memory | 227428 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1724628067 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_all.1724628067 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/1.spi_device_tpm_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/0.spi_device_csr_mem_rw_with_rand_reset.2187547207 |
| Short name | T95 |
| Test name | |
| Test status | |
| Simulation time | 157520987 ps |
| CPU time | 3.82 seconds |
| Started | Aug 27 07:34:25 AM UTC 24 |
| Finished | Aug 27 07:34:30 AM UTC 24 |
| Peak memory | 229364 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000 000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb _random_seed=2187547207 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_ name 0.spi_device_csr_mem_rw_with_rand_reset.2187547207 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/0.spi_device_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/2.spi_device_stress_all.169436146 |
| Short name | T32 |
| Test name | |
| Test status | |
| Simulation time | 26824355224 ps |
| CPU time | 201.77 seconds |
| Started | Aug 27 06:10:28 PM UTC 24 |
| Finished | Aug 27 06:13:53 PM UTC 24 |
| Peak memory | 294544 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=169436146 -assert nopostproc +UVM_T ESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_stress_all.169436146 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/2.spi_device_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/0.spi_device_intercept.2009005352 |
| Short name | T14 |
| Test name | |
| Test status | |
| Simulation time | 6943503252 ps |
| CPU time | 40.3 seconds |
| Started | Aug 27 06:07:50 PM UTC 24 |
| Finished | Aug 27 06:08:32 PM UTC 24 |
| Peak memory | 235032 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2009005352 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/s pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_intercept.2009005352 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/0.spi_device_intercept/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/0.spi_device_ram_cfg.4186388876 |
| Short name | T3 |
| Test name | |
| Test status | |
| Simulation time | 46976619 ps |
| CPU time | 1.04 seconds |
| Started | Aug 27 06:07:32 PM UTC 24 |
| Finished | Aug 27 06:07:34 PM UTC 24 |
| Peak memory | 225676 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4186388876 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_ram_cfg.4186388876 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/0.spi_device_ram_cfg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/6.spi_device_flash_and_tpm.4187275754 |
| Short name | T193 |
| Test name | |
| Test status | |
| Simulation time | 11541617550 ps |
| CPU time | 150.38 seconds |
| Started | Aug 27 06:13:00 PM UTC 24 |
| Finished | Aug 27 06:15:33 PM UTC 24 |
| Peak memory | 276164 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4187275754 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_ 26/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_and_tpm.4187275754 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/6.spi_device_flash_and_tpm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/1.spi_device_stress_all.2028154670 |
| Short name | T23 |
| Test name | |
| Test status | |
| Simulation time | 24973025880 ps |
| CPU time | 154.15 seconds |
| Started | Aug 27 06:09:51 PM UTC 24 |
| Finished | Aug 27 06:12:28 PM UTC 24 |
| Peak memory | 280204 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2028154670 -assert nopostproc +UVM_ TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_stress_all.2028154670 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/1.spi_device_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/10.spi_device_stress_all.174400740 |
| Short name | T71 |
| Test name | |
| Test status | |
| Simulation time | 195686751137 ps |
| CPU time | 283.73 seconds |
| Started | Aug 27 06:14:46 PM UTC 24 |
| Finished | Aug 27 06:19:34 PM UTC 24 |
| Peak memory | 280208 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=174400740 -assert nopostproc +UVM_T ESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_stress_all.174400740 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/10.spi_device_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/0.spi_device_sec_cm.1444092592 |
| Short name | T16 |
| Test name | |
| Test status | |
| Simulation time | 808624267 ps |
| CPU time | 1.72 seconds |
| Started | Aug 27 06:08:33 PM UTC 24 |
| Finished | Aug 27 06:08:35 PM UTC 24 |
| Peak memory | 257916 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1444092592 -assert nopostproc +UVM_TEST NAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_sec_cm.1444092592 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/0.spi_device_sec_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/2.spi_device_flash_and_tpm_min_idle.2593247297 |
| Short name | T196 |
| Test name | |
| Test status | |
| Simulation time | 59612599736 ps |
| CPU time | 317.29 seconds |
| Started | Aug 27 06:10:26 PM UTC 24 |
| Finished | Aug 27 06:15:48 PM UTC 24 |
| Peak memory | 278224 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2593247297 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_26/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_and_tpm_min_idle.2593247297 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/2.spi_device_flash_and_tpm_min_idle/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/1.spi_device_read_buffer_direct.2813339935 |
| Short name | T45 |
| Test name | |
| Test status | |
| Simulation time | 546356587 ps |
| CPU time | 7.14 seconds |
| Started | Aug 27 06:09:44 PM UTC 24 |
| Finished | Aug 27 06:09:52 PM UTC 24 |
| Peak memory | 233616 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2813339935 -assert nopostproc +UVM_TESTNAME=spi_device _base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_read_buffer_direct.2813339935 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/1.spi_device_read_buffer_direct/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/9.spi_device_flash_and_tpm.2643637433 |
| Short name | T228 |
| Test name | |
| Test status | |
| Simulation time | 6076810951 ps |
| CPU time | 141.55 seconds |
| Started | Aug 27 06:14:12 PM UTC 24 |
| Finished | Aug 27 06:16:37 PM UTC 24 |
| Peak memory | 284312 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2643637433 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_ 26/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_and_tpm.2643637433 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/9.spi_device_flash_and_tpm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/7.spi_device_flash_and_tpm_min_idle.1056580234 |
| Short name | T195 |
| Test name | |
| Test status | |
| Simulation time | 3744287574 ps |
| CPU time | 110.71 seconds |
| Started | Aug 27 06:13:24 PM UTC 24 |
| Finished | Aug 27 06:15:17 PM UTC 24 |
| Peak memory | 284296 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1056580234 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_26/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_and_tpm_min_idle.1056580234 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/7.spi_device_flash_and_tpm_min_idle/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/0.spi_device_tl_intg_err.3907047021 |
| Short name | T114 |
| Test name | |
| Test status | |
| Simulation time | 1188047949 ps |
| CPU time | 17.76 seconds |
| Started | Aug 27 07:34:23 AM UTC 24 |
| Finished | Aug 27 07:34:42 AM UTC 24 |
| Peak memory | 227084 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3907047021 -assert nopostproc + UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_tl_intg_err.3907047021 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/0.spi_device_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/1.spi_device_tpm_read_hw_reg.3723934417 |
| Short name | T27 |
| Test name | |
| Test status | |
| Simulation time | 3808159082 ps |
| CPU time | 24.91 seconds |
| Started | Aug 27 06:08:40 PM UTC 24 |
| Finished | Aug 27 06:09:06 PM UTC 24 |
| Peak memory | 227552 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3723934417 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_26/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_read_hw_reg.3723934417 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/1.spi_device_tpm_read_hw_reg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/2.spi_device_csr_rw.1368115575 |
| Short name | T136 |
| Test name | |
| Test status | |
| Simulation time | 313521232 ps |
| CPU time | 1.82 seconds |
| Started | Aug 27 07:34:29 AM UTC 24 |
| Finished | Aug 27 07:34:32 AM UTC 24 |
| Peak memory | 223908 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1368115575 -assert nopostproc +UVM_TESTN AME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_csr_rw.1368115575 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/2.spi_device_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/10.spi_device_flash_and_tpm.1595622677 |
| Short name | T297 |
| Test name | |
| Test status | |
| Simulation time | 32455562088 ps |
| CPU time | 385.61 seconds |
| Started | Aug 27 06:14:44 PM UTC 24 |
| Finished | Aug 27 06:21:15 PM UTC 24 |
| Peak memory | 278144 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1595622677 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_ 26/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_and_tpm.1595622677 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/10.spi_device_flash_and_tpm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/16.spi_device_flash_all.1096445298 |
| Short name | T246 |
| Test name | |
| Test status | |
| Simulation time | 70245160383 ps |
| CPU time | 191.44 seconds |
| Started | Aug 27 06:17:06 PM UTC 24 |
| Finished | Aug 27 06:20:21 PM UTC 24 |
| Peak memory | 267928 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1096445298 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/s pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_all.1096445298 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/16.spi_device_flash_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/6.spi_device_tl_errors.3022479324 |
| Short name | T121 |
| Test name | |
| Test status | |
| Simulation time | 771298437 ps |
| CPU time | 6.85 seconds |
| Started | Aug 27 07:34:42 AM UTC 24 |
| Finished | Aug 27 07:34:49 AM UTC 24 |
| Peak memory | 225132 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3022479324 -assert nopostproc +UVM_TESTNAME =spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_08_26/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_tl_errors.3022479324 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/6.spi_device_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/11.spi_device_flash_mode_ignore_cmds.2657690805 |
| Short name | T225 |
| Test name | |
| Test status | |
| Simulation time | 8046552513 ps |
| CPU time | 113.07 seconds |
| Started | Aug 27 06:15:09 PM UTC 24 |
| Finished | Aug 27 06:17:04 PM UTC 24 |
| Peak memory | 263844 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2657690805 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_26/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_mode_ignore_cmds.2657690805 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/11.spi_device_flash_mode_ignore_cmds/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/0.spi_device_flash_and_tpm.1457106697 |
| Short name | T44 |
| Test name | |
| Test status | |
| Simulation time | 20507066468 ps |
| CPU time | 204.56 seconds |
| Started | Aug 27 06:08:15 PM UTC 24 |
| Finished | Aug 27 06:11:43 PM UTC 24 |
| Peak memory | 265896 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1457106697 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_ 26/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_and_tpm.1457106697 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/0.spi_device_flash_and_tpm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/13.spi_device_flash_and_tpm_min_idle.640341347 |
| Short name | T99 |
| Test name | |
| Test status | |
| Simulation time | 18149428616 ps |
| CPU time | 108.3 seconds |
| Started | Aug 27 06:15:56 PM UTC 24 |
| Finished | Aug 27 06:17:47 PM UTC 24 |
| Peak memory | 265828 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=640341347 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_26/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_and_tpm_min_idle.640341347 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/13.spi_device_flash_and_tpm_min_idle/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/29.spi_device_flash_mode_ignore_cmds.3345802875 |
| Short name | T337 |
| Test name | |
| Test status | |
| Simulation time | 28941079015 ps |
| CPU time | 330.38 seconds |
| Started | Aug 27 06:22:58 PM UTC 24 |
| Finished | Aug 27 06:28:34 PM UTC 24 |
| Peak memory | 263776 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3345802875 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_26/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_mode_ignore_cmds.3345802875 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/29.spi_device_flash_mode_ignore_cmds/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/16.spi_device_flash_and_tpm_min_idle.2319537859 |
| Short name | T341 |
| Test name | |
| Test status | |
| Simulation time | 59372135002 ps |
| CPU time | 536.86 seconds |
| Started | Aug 27 06:17:08 PM UTC 24 |
| Finished | Aug 27 06:26:12 PM UTC 24 |
| Peak memory | 276172 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2319537859 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_26/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_and_tpm_min_idle.2319537859 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/16.spi_device_flash_and_tpm_min_idle/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/5.spi_device_flash_mode_ignore_cmds.3061644596 |
| Short name | T281 |
| Test name | |
| Test status | |
| Simulation time | 712392731632 ps |
| CPU time | 514.6 seconds |
| Started | Aug 27 06:12:29 PM UTC 24 |
| Finished | Aug 27 06:21:10 PM UTC 24 |
| Peak memory | 282196 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3061644596 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_26/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_mode_ignore_cmds.3061644596 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/5.spi_device_flash_mode_ignore_cmds/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/7.spi_device_flash_mode.883371232 |
| Short name | T166 |
| Test name | |
| Test status | |
| Simulation time | 146903311 ps |
| CPU time | 10.23 seconds |
| Started | Aug 27 06:13:16 PM UTC 24 |
| Finished | Aug 27 06:13:27 PM UTC 24 |
| Peak memory | 245228 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=883371232 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/s pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_mode.883371232 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/7.spi_device_flash_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/1.spi_device_mailbox.398588970 |
| Short name | T118 |
| Test name | |
| Test status | |
| Simulation time | 2828845178 ps |
| CPU time | 30.54 seconds |
| Started | Aug 27 06:09:13 PM UTC 24 |
| Finished | Aug 27 06:09:45 PM UTC 24 |
| Peak memory | 251480 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=398588970 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_mailbox.398588970 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/1.spi_device_mailbox/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/4.spi_device_flash_mode_ignore_cmds.1989076625 |
| Short name | T58 |
| Test name | |
| Test status | |
| Simulation time | 3282082119 ps |
| CPU time | 77.72 seconds |
| Started | Aug 27 06:12:01 PM UTC 24 |
| Finished | Aug 27 06:13:21 PM UTC 24 |
| Peak memory | 263892 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1989076625 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_26/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_mode_ignore_cmds.1989076625 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/4.spi_device_flash_mode_ignore_cmds/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/0.spi_device_alert_test.2145809029 |
| Short name | T90 |
| Test name | |
| Test status | |
| Simulation time | 11869010 ps |
| CPU time | 1.06 seconds |
| Started | Aug 27 06:08:36 PM UTC 24 |
| Finished | Aug 27 06:08:38 PM UTC 24 |
| Peak memory | 215684 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2145809029 -assert nopostproc +UVM_TES TNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_alert_test.2145809029 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/0.spi_device_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/4.spi_device_tl_errors.2713889187 |
| Short name | T124 |
| Test name | |
| Test status | |
| Simulation time | 249210994 ps |
| CPU time | 7.91 seconds |
| Started | Aug 27 07:34:35 AM UTC 24 |
| Finished | Aug 27 07:34:45 AM UTC 24 |
| Peak memory | 227264 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2713889187 -assert nopostproc +UVM_TESTNAME =spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_08_26/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_tl_errors.2713889187 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/4.spi_device_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/17.spi_device_stress_all.1660632793 |
| Short name | T262 |
| Test name | |
| Test status | |
| Simulation time | 46098312747 ps |
| CPU time | 136.61 seconds |
| Started | Aug 27 06:17:40 PM UTC 24 |
| Finished | Aug 27 06:19:59 PM UTC 24 |
| Peak memory | 282308 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1660632793 -assert nopostproc +UVM_ TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_stress_all.1660632793 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/17.spi_device_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/20.spi_device_flash_mode_ignore_cmds.606709376 |
| Short name | T334 |
| Test name | |
| Test status | |
| Simulation time | 23771366581 ps |
| CPU time | 203.02 seconds |
| Started | Aug 27 06:19:18 PM UTC 24 |
| Finished | Aug 27 06:22:44 PM UTC 24 |
| Peak memory | 261728 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=606709376 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_26/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_mode_ignore_cmds.606709376 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/20.spi_device_flash_mode_ignore_cmds/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/12.spi_device_tl_intg_err.1750673704 |
| Short name | T206 |
| Test name | |
| Test status | |
| Simulation time | 211208597 ps |
| CPU time | 14.07 seconds |
| Started | Aug 27 07:34:56 AM UTC 24 |
| Finished | Aug 27 07:35:11 AM UTC 24 |
| Peak memory | 225148 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1750673704 -assert nopostproc + UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_tl_intg_err.1750673704 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/12.spi_device_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/21.spi_device_flash_and_tpm.3447844655 |
| Short name | T233 |
| Test name | |
| Test status | |
| Simulation time | 42348265856 ps |
| CPU time | 167.29 seconds |
| Started | Aug 27 06:19:45 PM UTC 24 |
| Finished | Aug 27 06:22:35 PM UTC 24 |
| Peak memory | 280256 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3447844655 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_ 26/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_and_tpm.3447844655 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/21.spi_device_flash_and_tpm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/1.spi_device_flash_mode_ignore_cmds.2747841187 |
| Short name | T40 |
| Test name | |
| Test status | |
| Simulation time | 16556125645 ps |
| CPU time | 66.53 seconds |
| Started | Aug 27 06:09:42 PM UTC 24 |
| Finished | Aug 27 06:10:50 PM UTC 24 |
| Peak memory | 263772 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2747841187 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_26/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_mode_ignore_cmds.2747841187 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/1.spi_device_flash_mode_ignore_cmds/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/26.spi_device_flash_and_tpm_min_idle.3895356658 |
| Short name | T77 |
| Test name | |
| Test status | |
| Simulation time | 255826696401 ps |
| CPU time | 723.26 seconds |
| Started | Aug 27 06:21:56 PM UTC 24 |
| Finished | Aug 27 06:34:08 PM UTC 24 |
| Peak memory | 294612 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3895356658 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_26/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_and_tpm_min_idle.3895356658 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/26.spi_device_flash_and_tpm_min_idle/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/30.spi_device_stress_all.3840471002 |
| Short name | T338 |
| Test name | |
| Test status | |
| Simulation time | 9353830175 ps |
| CPU time | 198.95 seconds |
| Started | Aug 27 06:23:42 PM UTC 24 |
| Finished | Aug 27 06:27:04 PM UTC 24 |
| Peak memory | 298644 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3840471002 -assert nopostproc +UVM_ TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_stress_all.3840471002 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/30.spi_device_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/2.spi_device_tl_intg_err.2306624384 |
| Short name | T126 |
| Test name | |
| Test status | |
| Simulation time | 293684294 ps |
| CPU time | 20.12 seconds |
| Started | Aug 27 07:34:28 AM UTC 24 |
| Finished | Aug 27 07:34:50 AM UTC 24 |
| Peak memory | 225260 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2306624384 -assert nopostproc + UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_tl_intg_err.2306624384 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/2.spi_device_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/19.spi_device_tl_intg_err.739673328 |
| Short name | T1130 |
| Test name | |
| Test status | |
| Simulation time | 701796387 ps |
| CPU time | 15.25 seconds |
| Started | Aug 27 07:35:07 AM UTC 24 |
| Finished | Aug 27 07:35:23 AM UTC 24 |
| Peak memory | 225336 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=739673328 -assert nopostproc +U VM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_tl_intg_err.739673328 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/19.spi_device_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/0.spi_device_mailbox.3289725703 |
| Short name | T11 |
| Test name | |
| Test status | |
| Simulation time | 4229431808 ps |
| CPU time | 21.19 seconds |
| Started | Aug 27 06:07:52 PM UTC 24 |
| Finished | Aug 27 06:08:15 PM UTC 24 |
| Peak memory | 251564 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3289725703 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_mailbox.3289725703 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/0.spi_device_mailbox/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/11.spi_device_stress_all.2876891860 |
| Short name | T85 |
| Test name | |
| Test status | |
| Simulation time | 6643204811 ps |
| CPU time | 44.99 seconds |
| Started | Aug 27 06:15:12 PM UTC 24 |
| Finished | Aug 27 06:15:59 PM UTC 24 |
| Peak memory | 265924 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2876891860 -assert nopostproc +UVM_ TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_stress_all.2876891860 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/11.spi_device_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/16.spi_device_flash_mode.1071959016 |
| Short name | T351 |
| Test name | |
| Test status | |
| Simulation time | 1341088196 ps |
| CPU time | 25.39 seconds |
| Started | Aug 27 06:17:05 PM UTC 24 |
| Finished | Aug 27 06:17:32 PM UTC 24 |
| Peak memory | 245328 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1071959016 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/ spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_mode.1071959016 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/16.spi_device_flash_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/20.spi_device_flash_and_tpm_min_idle.334545559 |
| Short name | T247 |
| Test name | |
| Test status | |
| Simulation time | 8869871633 ps |
| CPU time | 124.44 seconds |
| Started | Aug 27 06:19:26 PM UTC 24 |
| Finished | Aug 27 06:21:33 PM UTC 24 |
| Peak memory | 284080 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=334545559 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_26/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_and_tpm_min_idle.334545559 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/20.spi_device_flash_and_tpm_min_idle/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/26.spi_device_flash_mode_ignore_cmds.148666824 |
| Short name | T968 |
| Test name | |
| Test status | |
| Simulation time | 341138059894 ps |
| CPU time | 487.1 seconds |
| Started | Aug 27 06:21:53 PM UTC 24 |
| Finished | Aug 27 06:30:06 PM UTC 24 |
| Peak memory | 278100 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=148666824 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_26/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_mode_ignore_cmds.148666824 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/26.spi_device_flash_mode_ignore_cmds/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/34.spi_device_flash_mode.1565889999 |
| Short name | T354 |
| Test name | |
| Test status | |
| Simulation time | 3531104643 ps |
| CPU time | 11.85 seconds |
| Started | Aug 27 06:25:28 PM UTC 24 |
| Finished | Aug 27 06:25:41 PM UTC 24 |
| Peak memory | 251488 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1565889999 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/ spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_mode.1565889999 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/34.spi_device_flash_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/11.spi_device_tl_errors.4231743120 |
| Short name | T1053 |
| Test name | |
| Test status | |
| Simulation time | 375590050 ps |
| CPU time | 5.67 seconds |
| Started | Aug 27 07:34:53 AM UTC 24 |
| Finished | Aug 27 07:35:00 AM UTC 24 |
| Peak memory | 225260 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4231743120 -assert nopostproc +UVM_TESTNAME =spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_08_26/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_tl_errors.4231743120 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/11.spi_device_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/0.spi_device_csr_hw_reset.2421195451 |
| Short name | T101 |
| Test name | |
| Test status | |
| Simulation time | 67808103 ps |
| CPU time | 1.31 seconds |
| Started | Aug 27 07:34:23 AM UTC 24 |
| Finished | Aug 27 07:34:26 AM UTC 24 |
| Peak memory | 214380 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2421195451 -assert nopostproc +UVM _TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_csr_hw_reset.2421195451 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/0.spi_device_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/0.spi_device_csb_read.1003249054 |
| Short name | T1 |
| Test name | |
| Test status | |
| Simulation time | 125942029 ps |
| CPU time | 1.26 seconds |
| Started | Aug 27 06:07:28 PM UTC 24 |
| Finished | Aug 27 06:07:31 PM UTC 24 |
| Peak memory | 215616 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1003249054 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/sp i_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_csb_read.1003249054 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/0.spi_device_csb_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/0.spi_device_flash_and_tpm_min_idle.917958204 |
| Short name | T37 |
| Test name | |
| Test status | |
| Simulation time | 304182333478 ps |
| CPU time | 451.56 seconds |
| Started | Aug 27 06:08:24 PM UTC 24 |
| Finished | Aug 27 06:16:02 PM UTC 24 |
| Peak memory | 278152 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=917958204 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_26/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_and_tpm_min_idle.917958204 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/0.spi_device_flash_and_tpm_min_idle/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/0.spi_device_csr_aliasing.1769674453 |
| Short name | T141 |
| Test name | |
| Test status | |
| Simulation time | 675869099 ps |
| CPU time | 17.36 seconds |
| Started | Aug 27 07:34:25 AM UTC 24 |
| Finished | Aug 27 07:34:44 AM UTC 24 |
| Peak memory | 225200 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1769674453 -assert nopostproc +UVM _TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_csr_aliasing.1769674453 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/0.spi_device_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/0.spi_device_csr_bit_bash.936425599 |
| Short name | T1024 |
| Test name | |
| Test status | |
| Simulation time | 183915028 ps |
| CPU time | 11.69 seconds |
| Started | Aug 27 07:34:23 AM UTC 24 |
| Finished | Aug 27 07:34:36 AM UTC 24 |
| Peak memory | 214768 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=936425599 -assert nopostproc +UVM_ TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_csr_bit_bash.936425599 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/0.spi_device_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/0.spi_device_csr_rw.3146174190 |
| Short name | T134 |
| Test name | |
| Test status | |
| Simulation time | 59881245 ps |
| CPU time | 1.78 seconds |
| Started | Aug 27 07:34:23 AM UTC 24 |
| Finished | Aug 27 07:34:26 AM UTC 24 |
| Peak memory | 213668 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3146174190 -assert nopostproc +UVM_TESTN AME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_csr_rw.3146174190 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/0.spi_device_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/0.spi_device_intr_test.3878601168 |
| Short name | T1016 |
| Test name | |
| Test status | |
| Simulation time | 36533392 ps |
| CPU time | 1.03 seconds |
| Started | Aug 27 07:34:23 AM UTC 24 |
| Finished | Aug 27 07:34:25 AM UTC 24 |
| Peak memory | 211764 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3878601168 -assert nopostproc +UVM_TESTNAME =spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_08_26/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_intr_test.3878601168 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/0.spi_device_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/0.spi_device_mem_partial_access.2268894849 |
| Short name | T133 |
| Test name | |
| Test status | |
| Simulation time | 70506827 ps |
| CPU time | 1.67 seconds |
| Started | Aug 27 07:34:23 AM UTC 24 |
| Finished | Aug 27 07:34:26 AM UTC 24 |
| Peak memory | 223948 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2268894849 -assert nopos tproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re po/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_mem_partial_access.2268894849 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/0.spi_device_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/0.spi_device_mem_walk.2468397394 |
| Short name | T1015 |
| Test name | |
| Test status | |
| Simulation time | 11815997 ps |
| CPU time | 0.93 seconds |
| Started | Aug 27 07:34:23 AM UTC 24 |
| Finished | Aug 27 07:34:25 AM UTC 24 |
| Peak memory | 212732 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2468397394 -assert nopostproc +UVM _TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_mem_walk.2468397394 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/0.spi_device_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/0.spi_device_same_csr_outstanding.670334406 |
| Short name | T160 |
| Test name | |
| Test status | |
| Simulation time | 429324301 ps |
| CPU time | 3.57 seconds |
| Started | Aug 27 07:34:25 AM UTC 24 |
| Finished | Aug 27 07:34:30 AM UTC 24 |
| Peak memory | 225048 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=670334406 -assert nopo stproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r epo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_same_csr_outstanding.670334406 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/0.spi_device_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/0.spi_device_tl_errors.1087031330 |
| Short name | T93 |
| Test name | |
| Test status | |
| Simulation time | 116679177 ps |
| CPU time | 3.68 seconds |
| Started | Aug 27 07:34:23 AM UTC 24 |
| Finished | Aug 27 07:34:28 AM UTC 24 |
| Peak memory | 225132 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1087031330 -assert nopostproc +UVM_TESTNAME =spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_08_26/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_tl_errors.1087031330 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/0.spi_device_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/1.spi_device_csr_aliasing.2281004718 |
| Short name | T143 |
| Test name | |
| Test status | |
| Simulation time | 6103790613 ps |
| CPU time | 19.22 seconds |
| Started | Aug 27 07:34:27 AM UTC 24 |
| Finished | Aug 27 07:34:47 AM UTC 24 |
| Peak memory | 224664 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2281004718 -assert nopostproc +UVM _TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_csr_aliasing.2281004718 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/1.spi_device_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/1.spi_device_csr_bit_bash.1877672741 |
| Short name | T1057 |
| Test name | |
| Test status | |
| Simulation time | 3691453154 ps |
| CPU time | 34.09 seconds |
| Started | Aug 27 07:34:26 AM UTC 24 |
| Finished | Aug 27 07:35:01 AM UTC 24 |
| Peak memory | 225388 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1877672741 -assert nopostproc +UVM _TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_csr_bit_bash.1877672741 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/1.spi_device_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/1.spi_device_csr_hw_reset.4235544938 |
| Short name | T102 |
| Test name | |
| Test status | |
| Simulation time | 23214687 ps |
| CPU time | 1.42 seconds |
| Started | Aug 27 07:34:26 AM UTC 24 |
| Finished | Aug 27 07:34:28 AM UTC 24 |
| Peak memory | 213964 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4235544938 -assert nopostproc +UVM _TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_csr_hw_reset.4235544938 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/1.spi_device_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/1.spi_device_csr_mem_rw_with_rand_reset.3111030677 |
| Short name | T131 |
| Test name | |
| Test status | |
| Simulation time | 180268817 ps |
| CPU time | 3.03 seconds |
| Started | Aug 27 07:34:27 AM UTC 24 |
| Finished | Aug 27 07:34:31 AM UTC 24 |
| Peak memory | 226736 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000 000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb _random_seed=3111030677 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_ name 1.spi_device_csr_mem_rw_with_rand_reset.3111030677 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/1.spi_device_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/1.spi_device_csr_rw.2044886647 |
| Short name | T159 |
| Test name | |
| Test status | |
| Simulation time | 133491650 ps |
| CPU time | 1.97 seconds |
| Started | Aug 27 07:34:26 AM UTC 24 |
| Finished | Aug 27 07:34:29 AM UTC 24 |
| Peak memory | 213668 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2044886647 -assert nopostproc +UVM_TESTN AME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_csr_rw.2044886647 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/1.spi_device_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/1.spi_device_intr_test.2764897711 |
| Short name | T1018 |
| Test name | |
| Test status | |
| Simulation time | 23430273 ps |
| CPU time | 1.11 seconds |
| Started | Aug 27 07:34:25 AM UTC 24 |
| Finished | Aug 27 07:34:28 AM UTC 24 |
| Peak memory | 211764 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2764897711 -assert nopostproc +UVM_TESTNAME =spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_08_26/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_intr_test.2764897711 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/1.spi_device_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/1.spi_device_mem_partial_access.1288075686 |
| Short name | T135 |
| Test name | |
| Test status | |
| Simulation time | 56413840 ps |
| CPU time | 2.46 seconds |
| Started | Aug 27 07:34:25 AM UTC 24 |
| Finished | Aug 27 07:34:29 AM UTC 24 |
| Peak memory | 225344 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1288075686 -assert nopos tproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re po/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_mem_partial_access.1288075686 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/1.spi_device_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/1.spi_device_mem_walk.1847580673 |
| Short name | T1017 |
| Test name | |
| Test status | |
| Simulation time | 11571999 ps |
| CPU time | 0.9 seconds |
| Started | Aug 27 07:34:25 AM UTC 24 |
| Finished | Aug 27 07:34:27 AM UTC 24 |
| Peak memory | 211760 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1847580673 -assert nopostproc +UVM _TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_mem_walk.1847580673 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/1.spi_device_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/1.spi_device_same_csr_outstanding.50896403 |
| Short name | T161 |
| Test name | |
| Test status | |
| Simulation time | 322687050 ps |
| CPU time | 4.46 seconds |
| Started | Aug 27 07:34:27 AM UTC 24 |
| Finished | Aug 27 07:34:33 AM UTC 24 |
| Peak memory | 225128 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=50896403 -assert nopos tproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re po/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_same_csr_outstanding.50896403 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/1.spi_device_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/1.spi_device_tl_errors.2866605862 |
| Short name | T94 |
| Test name | |
| Test status | |
| Simulation time | 214774843 ps |
| CPU time | 3.55 seconds |
| Started | Aug 27 07:34:25 AM UTC 24 |
| Finished | Aug 27 07:34:30 AM UTC 24 |
| Peak memory | 227232 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2866605862 -assert nopostproc +UVM_TESTNAME =spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_08_26/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_tl_errors.2866605862 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/1.spi_device_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/1.spi_device_tl_intg_err.2918884772 |
| Short name | T115 |
| Test name | |
| Test status | |
| Simulation time | 561459941 ps |
| CPU time | 17.37 seconds |
| Started | Aug 27 07:34:25 AM UTC 24 |
| Finished | Aug 27 07:34:44 AM UTC 24 |
| Peak memory | 227048 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2918884772 -assert nopostproc + UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_tl_intg_err.2918884772 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/1.spi_device_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/10.spi_device_csr_mem_rw_with_rand_reset.1839499975 |
| Short name | T1050 |
| Test name | |
| Test status | |
| Simulation time | 198152734 ps |
| CPU time | 2.51 seconds |
| Started | Aug 27 07:34:53 AM UTC 24 |
| Finished | Aug 27 07:34:57 AM UTC 24 |
| Peak memory | 227376 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000 000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb _random_seed=1839499975 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_ name 10.spi_device_csr_mem_rw_with_rand_reset.1839499975 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/10.spi_device_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/10.spi_device_csr_rw.2656702049 |
| Short name | T1046 |
| Test name | |
| Test status | |
| Simulation time | 27102231 ps |
| CPU time | 2.41 seconds |
| Started | Aug 27 07:34:52 AM UTC 24 |
| Finished | Aug 27 07:34:56 AM UTC 24 |
| Peak memory | 225124 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2656702049 -assert nopostproc +UVM_TESTN AME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_csr_rw.2656702049 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/10.spi_device_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/10.spi_device_intr_test.1990657863 |
| Short name | T1042 |
| Test name | |
| Test status | |
| Simulation time | 11798833 ps |
| CPU time | 0.98 seconds |
| Started | Aug 27 07:34:51 AM UTC 24 |
| Finished | Aug 27 07:34:53 AM UTC 24 |
| Peak memory | 211772 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1990657863 -assert nopostproc +UVM_TESTNAME =spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_08_26/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_intr_test.1990657863 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/10.spi_device_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/10.spi_device_same_csr_outstanding.220860847 |
| Short name | T1049 |
| Test name | |
| Test status | |
| Simulation time | 25900464 ps |
| CPU time | 2.25 seconds |
| Started | Aug 27 07:34:53 AM UTC 24 |
| Finished | Aug 27 07:34:57 AM UTC 24 |
| Peak memory | 224988 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=220860847 -assert nopo stproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r epo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_same_csr_outstand ing.220860847 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/10.spi_device_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/10.spi_device_tl_errors.1043120508 |
| Short name | T199 |
| Test name | |
| Test status | |
| Simulation time | 299431296 ps |
| CPU time | 5.29 seconds |
| Started | Aug 27 07:34:51 AM UTC 24 |
| Finished | Aug 27 07:34:58 AM UTC 24 |
| Peak memory | 224160 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1043120508 -assert nopostproc +UVM_TESTNAME =spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_08_26/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_tl_errors.1043120508 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/10.spi_device_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/10.spi_device_tl_intg_err.863059000 |
| Short name | T205 |
| Test name | |
| Test status | |
| Simulation time | 801245020 ps |
| CPU time | 12.9 seconds |
| Started | Aug 27 07:34:51 AM UTC 24 |
| Finished | Aug 27 07:35:05 AM UTC 24 |
| Peak memory | 227104 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=863059000 -assert nopostproc +U VM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_tl_intg_err.863059000 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/10.spi_device_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/11.spi_device_csr_mem_rw_with_rand_reset.2393821367 |
| Short name | T200 |
| Test name | |
| Test status | |
| Simulation time | 138659274 ps |
| CPU time | 2.83 seconds |
| Started | Aug 27 07:34:55 AM UTC 24 |
| Finished | Aug 27 07:34:58 AM UTC 24 |
| Peak memory | 227236 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000 000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb _random_seed=2393821367 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_ name 11.spi_device_csr_mem_rw_with_rand_reset.2393821367 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/11.spi_device_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/11.spi_device_csr_rw.546758615 |
| Short name | T147 |
| Test name | |
| Test status | |
| Simulation time | 256393076 ps |
| CPU time | 2.22 seconds |
| Started | Aug 27 07:34:54 AM UTC 24 |
| Finished | Aug 27 07:34:58 AM UTC 24 |
| Peak memory | 225400 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=546758615 -assert nopostproc +UVM_TESTNA ME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_csr_rw.546758615 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/11.spi_device_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/11.spi_device_intr_test.2350380614 |
| Short name | T1048 |
| Test name | |
| Test status | |
| Simulation time | 15962818 ps |
| CPU time | 1.06 seconds |
| Started | Aug 27 07:34:54 AM UTC 24 |
| Finished | Aug 27 07:34:57 AM UTC 24 |
| Peak memory | 211772 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2350380614 -assert nopostproc +UVM_TESTNAME =spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_08_26/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_intr_test.2350380614 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/11.spi_device_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/11.spi_device_same_csr_outstanding.2604196016 |
| Short name | T172 |
| Test name | |
| Test status | |
| Simulation time | 138641855 ps |
| CPU time | 2.86 seconds |
| Started | Aug 27 07:34:55 AM UTC 24 |
| Finished | Aug 27 07:34:58 AM UTC 24 |
| Peak memory | 225080 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2604196016 -assert nop ostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_same_csr_outstan ding.2604196016 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/11.spi_device_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/11.spi_device_tl_intg_err.1111752309 |
| Short name | T1079 |
| Test name | |
| Test status | |
| Simulation time | 694959893 ps |
| CPU time | 13.02 seconds |
| Started | Aug 27 07:34:53 AM UTC 24 |
| Finished | Aug 27 07:35:08 AM UTC 24 |
| Peak memory | 224984 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1111752309 -assert nopostproc + UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_tl_intg_err.1111752309 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/11.spi_device_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/12.spi_device_csr_mem_rw_with_rand_reset.2828927 |
| Short name | T1059 |
| Test name | |
| Test status | |
| Simulation time | 787302327 ps |
| CPU time | 3.85 seconds |
| Started | Aug 27 07:34:57 AM UTC 24 |
| Finished | Aug 27 07:35:02 AM UTC 24 |
| Peak memory | 229300 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000 000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb _random_seed=2828927 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam e 12.spi_device_csr_mem_rw_with_rand_reset.2828927 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/12.spi_device_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/12.spi_device_csr_rw.2530826670 |
| Short name | T173 |
| Test name | |
| Test status | |
| Simulation time | 75375350 ps |
| CPU time | 2.82 seconds |
| Started | Aug 27 07:34:56 AM UTC 24 |
| Finished | Aug 27 07:35:00 AM UTC 24 |
| Peak memory | 225012 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2530826670 -assert nopostproc +UVM_TESTN AME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_csr_rw.2530826670 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/12.spi_device_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/12.spi_device_intr_test.2779567445 |
| Short name | T1051 |
| Test name | |
| Test status | |
| Simulation time | 37381391 ps |
| CPU time | 1.04 seconds |
| Started | Aug 27 07:34:56 AM UTC 24 |
| Finished | Aug 27 07:34:58 AM UTC 24 |
| Peak memory | 211772 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2779567445 -assert nopostproc +UVM_TESTNAME =spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_08_26/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_intr_test.2779567445 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/12.spi_device_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/12.spi_device_same_csr_outstanding.1170385894 |
| Short name | T175 |
| Test name | |
| Test status | |
| Simulation time | 349169641 ps |
| CPU time | 4.73 seconds |
| Started | Aug 27 07:34:57 AM UTC 24 |
| Finished | Aug 27 07:35:03 AM UTC 24 |
| Peak memory | 225120 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1170385894 -assert nop ostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_same_csr_outstan ding.1170385894 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/12.spi_device_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/12.spi_device_tl_errors.403715182 |
| Short name | T1055 |
| Test name | |
| Test status | |
| Simulation time | 65835327 ps |
| CPU time | 4.53 seconds |
| Started | Aug 27 07:34:55 AM UTC 24 |
| Finished | Aug 27 07:35:00 AM UTC 24 |
| Peak memory | 225200 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=403715182 -assert nopostproc +UVM_TESTNAME= spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_08_26/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_tl_errors.403715182 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/12.spi_device_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/13.spi_device_csr_mem_rw_with_rand_reset.1804938900 |
| Short name | T1056 |
| Test name | |
| Test status | |
| Simulation time | 104006777 ps |
| CPU time | 1.8 seconds |
| Started | Aug 27 07:34:58 AM UTC 24 |
| Finished | Aug 27 07:35:01 AM UTC 24 |
| Peak memory | 226084 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000 000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb _random_seed=1804938900 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_ name 13.spi_device_csr_mem_rw_with_rand_reset.1804938900 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/13.spi_device_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/13.spi_device_csr_rw.76023149 |
| Short name | T1060 |
| Test name | |
| Test status | |
| Simulation time | 195390777 ps |
| CPU time | 2.92 seconds |
| Started | Aug 27 07:34:58 AM UTC 24 |
| Finished | Aug 27 07:35:02 AM UTC 24 |
| Peak memory | 224984 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=76023149 -assert nopostproc +UVM_TESTNAM E=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_26/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_csr_rw.76023149 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/13.spi_device_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/13.spi_device_intr_test.359535293 |
| Short name | T1054 |
| Test name | |
| Test status | |
| Simulation time | 18294387 ps |
| CPU time | 1.02 seconds |
| Started | Aug 27 07:34:58 AM UTC 24 |
| Finished | Aug 27 07:35:00 AM UTC 24 |
| Peak memory | 211768 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=359535293 -assert nopostproc +UVM_TESTNAME= spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_08_26/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_intr_test.359535293 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/13.spi_device_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/13.spi_device_same_csr_outstanding.2042305369 |
| Short name | T1063 |
| Test name | |
| Test status | |
| Simulation time | 255298900 ps |
| CPU time | 3.74 seconds |
| Started | Aug 27 07:34:58 AM UTC 24 |
| Finished | Aug 27 07:35:03 AM UTC 24 |
| Peak memory | 225048 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2042305369 -assert nop ostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_same_csr_outstan ding.2042305369 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/13.spi_device_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/13.spi_device_tl_errors.322971356 |
| Short name | T1065 |
| Test name | |
| Test status | |
| Simulation time | 309023605 ps |
| CPU time | 5.26 seconds |
| Started | Aug 27 07:34:57 AM UTC 24 |
| Finished | Aug 27 07:35:03 AM UTC 24 |
| Peak memory | 225224 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=322971356 -assert nopostproc +UVM_TESTNAME= spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_08_26/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_tl_errors.322971356 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/13.spi_device_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/13.spi_device_tl_intg_err.3000971553 |
| Short name | T207 |
| Test name | |
| Test status | |
| Simulation time | 4111920267 ps |
| CPU time | 15.97 seconds |
| Started | Aug 27 07:34:57 AM UTC 24 |
| Finished | Aug 27 07:35:14 AM UTC 24 |
| Peak memory | 233552 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3000971553 -assert nopostproc + UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_tl_intg_err.3000971553 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/13.spi_device_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/14.spi_device_csr_mem_rw_with_rand_reset.641185434 |
| Short name | T1073 |
| Test name | |
| Test status | |
| Simulation time | 213163740 ps |
| CPU time | 4.51 seconds |
| Started | Aug 27 07:35:01 AM UTC 24 |
| Finished | Aug 27 07:35:06 AM UTC 24 |
| Peak memory | 227000 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000 000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb _random_seed=641185434 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n ame 14.spi_device_csr_mem_rw_with_rand_reset.641185434 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/14.spi_device_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/14.spi_device_csr_rw.2960964206 |
| Short name | T1064 |
| Test name | |
| Test status | |
| Simulation time | 21436233 ps |
| CPU time | 1.68 seconds |
| Started | Aug 27 07:35:01 AM UTC 24 |
| Finished | Aug 27 07:35:03 AM UTC 24 |
| Peak memory | 213672 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2960964206 -assert nopostproc +UVM_TESTN AME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_csr_rw.2960964206 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/14.spi_device_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/14.spi_device_intr_test.3358364763 |
| Short name | T1058 |
| Test name | |
| Test status | |
| Simulation time | 12652671 ps |
| CPU time | 1.01 seconds |
| Started | Aug 27 07:34:59 AM UTC 24 |
| Finished | Aug 27 07:35:01 AM UTC 24 |
| Peak memory | 211772 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3358364763 -assert nopostproc +UVM_TESTNAME =spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_08_26/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_intr_test.3358364763 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/14.spi_device_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/14.spi_device_same_csr_outstanding.3226026816 |
| Short name | T1066 |
| Test name | |
| Test status | |
| Simulation time | 141144692 ps |
| CPU time | 2.01 seconds |
| Started | Aug 27 07:35:01 AM UTC 24 |
| Finished | Aug 27 07:35:04 AM UTC 24 |
| Peak memory | 215056 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3226026816 -assert nop ostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_same_csr_outstan ding.3226026816 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/14.spi_device_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/14.spi_device_tl_errors.109906451 |
| Short name | T1076 |
| Test name | |
| Test status | |
| Simulation time | 1175930786 ps |
| CPU time | 6.92 seconds |
| Started | Aug 27 07:34:58 AM UTC 24 |
| Finished | Aug 27 07:35:06 AM UTC 24 |
| Peak memory | 227296 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=109906451 -assert nopostproc +UVM_TESTNAME= spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_08_26/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_tl_errors.109906451 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/14.spi_device_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/14.spi_device_tl_intg_err.377286030 |
| Short name | T1083 |
| Test name | |
| Test status | |
| Simulation time | 102117993 ps |
| CPU time | 7.43 seconds |
| Started | Aug 27 07:34:59 AM UTC 24 |
| Finished | Aug 27 07:35:08 AM UTC 24 |
| Peak memory | 227132 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=377286030 -assert nopostproc +U VM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_tl_intg_err.377286030 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/14.spi_device_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/15.spi_device_csr_mem_rw_with_rand_reset.1473948984 |
| Short name | T1085 |
| Test name | |
| Test status | |
| Simulation time | 201194915 ps |
| CPU time | 5.42 seconds |
| Started | Aug 27 07:35:02 AM UTC 24 |
| Finished | Aug 27 07:35:09 AM UTC 24 |
| Peak memory | 227100 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000 000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb _random_seed=1473948984 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_ name 15.spi_device_csr_mem_rw_with_rand_reset.1473948984 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/15.spi_device_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/15.spi_device_csr_rw.1902308075 |
| Short name | T1072 |
| Test name | |
| Test status | |
| Simulation time | 371734110 ps |
| CPU time | 3.23 seconds |
| Started | Aug 27 07:35:02 AM UTC 24 |
| Finished | Aug 27 07:35:06 AM UTC 24 |
| Peak memory | 225108 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1902308075 -assert nopostproc +UVM_TESTN AME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_csr_rw.1902308075 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/15.spi_device_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/15.spi_device_intr_test.3368664061 |
| Short name | T1068 |
| Test name | |
| Test status | |
| Simulation time | 22215564 ps |
| CPU time | 1.13 seconds |
| Started | Aug 27 07:35:02 AM UTC 24 |
| Finished | Aug 27 07:35:04 AM UTC 24 |
| Peak memory | 211772 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3368664061 -assert nopostproc +UVM_TESTNAME =spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_08_26/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_intr_test.3368664061 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/15.spi_device_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/15.spi_device_same_csr_outstanding.635128948 |
| Short name | T1078 |
| Test name | |
| Test status | |
| Simulation time | 778465213 ps |
| CPU time | 4.02 seconds |
| Started | Aug 27 07:35:02 AM UTC 24 |
| Finished | Aug 27 07:35:07 AM UTC 24 |
| Peak memory | 225072 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=635128948 -assert nopo stproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r epo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_same_csr_outstand ing.635128948 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/15.spi_device_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/15.spi_device_tl_errors.68121779 |
| Short name | T1067 |
| Test name | |
| Test status | |
| Simulation time | 89470973 ps |
| CPU time | 1.98 seconds |
| Started | Aug 27 07:35:01 AM UTC 24 |
| Finished | Aug 27 07:35:04 AM UTC 24 |
| Peak memory | 214044 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=68121779 -assert nopostproc +UVM_TESTNAME=s pi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_08_26/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_tl_errors.68121779 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/15.spi_device_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/15.spi_device_tl_intg_err.4055314087 |
| Short name | T1096 |
| Test name | |
| Test status | |
| Simulation time | 232762748 ps |
| CPU time | 7.56 seconds |
| Started | Aug 27 07:35:02 AM UTC 24 |
| Finished | Aug 27 07:35:10 AM UTC 24 |
| Peak memory | 227176 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4055314087 -assert nopostproc + UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_tl_intg_err.4055314087 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/15.spi_device_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/16.spi_device_csr_mem_rw_with_rand_reset.4012771142 |
| Short name | T1090 |
| Test name | |
| Test status | |
| Simulation time | 58189334 ps |
| CPU time | 3.98 seconds |
| Started | Aug 27 07:35:04 AM UTC 24 |
| Finished | Aug 27 07:35:09 AM UTC 24 |
| Peak memory | 227184 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000 000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb _random_seed=4012771142 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_ name 16.spi_device_csr_mem_rw_with_rand_reset.4012771142 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/16.spi_device_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/16.spi_device_csr_rw.1629231784 |
| Short name | T1071 |
| Test name | |
| Test status | |
| Simulation time | 18045779 ps |
| CPU time | 1.4 seconds |
| Started | Aug 27 07:35:03 AM UTC 24 |
| Finished | Aug 27 07:35:06 AM UTC 24 |
| Peak memory | 213672 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1629231784 -assert nopostproc +UVM_TESTN AME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_csr_rw.1629231784 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/16.spi_device_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/16.spi_device_intr_test.44128741 |
| Short name | T1070 |
| Test name | |
| Test status | |
| Simulation time | 23614741 ps |
| CPU time | 0.87 seconds |
| Started | Aug 27 07:35:03 AM UTC 24 |
| Finished | Aug 27 07:35:05 AM UTC 24 |
| Peak memory | 211764 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=44128741 -assert nopostproc +UVM_TESTNAME=s pi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_08_26/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_intr_test.44128741 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/16.spi_device_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/16.spi_device_same_csr_outstanding.414639438 |
| Short name | T1088 |
| Test name | |
| Test status | |
| Simulation time | 2583510706 ps |
| CPU time | 3.5 seconds |
| Started | Aug 27 07:35:04 AM UTC 24 |
| Finished | Aug 27 07:35:09 AM UTC 24 |
| Peak memory | 225008 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=414639438 -assert nopo stproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r epo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_same_csr_outstand ing.414639438 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/16.spi_device_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/16.spi_device_tl_errors.3510339118 |
| Short name | T1075 |
| Test name | |
| Test status | |
| Simulation time | 93646970 ps |
| CPU time | 2.16 seconds |
| Started | Aug 27 07:35:03 AM UTC 24 |
| Finished | Aug 27 07:35:06 AM UTC 24 |
| Peak memory | 225252 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3510339118 -assert nopostproc +UVM_TESTNAME =spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_08_26/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_tl_errors.3510339118 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/16.spi_device_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/16.spi_device_tl_intg_err.2335484477 |
| Short name | T1102 |
| Test name | |
| Test status | |
| Simulation time | 223557843 ps |
| CPU time | 7.5 seconds |
| Started | Aug 27 07:35:03 AM UTC 24 |
| Finished | Aug 27 07:35:12 AM UTC 24 |
| Peak memory | 227092 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2335484477 -assert nopostproc + UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_tl_intg_err.2335484477 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/16.spi_device_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/17.spi_device_csr_mem_rw_with_rand_reset.2398294517 |
| Short name | T1086 |
| Test name | |
| Test status | |
| Simulation time | 93398965 ps |
| CPU time | 2.84 seconds |
| Started | Aug 27 07:35:05 AM UTC 24 |
| Finished | Aug 27 07:35:09 AM UTC 24 |
| Peak memory | 227052 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000 000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb _random_seed=2398294517 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_ name 17.spi_device_csr_mem_rw_with_rand_reset.2398294517 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/17.spi_device_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/17.spi_device_csr_rw.2648122258 |
| Short name | T1081 |
| Test name | |
| Test status | |
| Simulation time | 77083523 ps |
| CPU time | 2.12 seconds |
| Started | Aug 27 07:35:05 AM UTC 24 |
| Finished | Aug 27 07:35:08 AM UTC 24 |
| Peak memory | 214908 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2648122258 -assert nopostproc +UVM_TESTN AME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_csr_rw.2648122258 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/17.spi_device_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/17.spi_device_intr_test.2214839270 |
| Short name | T1077 |
| Test name | |
| Test status | |
| Simulation time | 17657862 ps |
| CPU time | 0.97 seconds |
| Started | Aug 27 07:35:04 AM UTC 24 |
| Finished | Aug 27 07:35:06 AM UTC 24 |
| Peak memory | 211772 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2214839270 -assert nopostproc +UVM_TESTNAME =spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_08_26/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_intr_test.2214839270 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/17.spi_device_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/17.spi_device_same_csr_outstanding.2623650002 |
| Short name | T1084 |
| Test name | |
| Test status | |
| Simulation time | 96557857 ps |
| CPU time | 2.8 seconds |
| Started | Aug 27 07:35:05 AM UTC 24 |
| Finished | Aug 27 07:35:08 AM UTC 24 |
| Peak memory | 227052 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2623650002 -assert nop ostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_same_csr_outstan ding.2623650002 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/17.spi_device_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/17.spi_device_tl_errors.3529298426 |
| Short name | T1097 |
| Test name | |
| Test status | |
| Simulation time | 1927943819 ps |
| CPU time | 5.29 seconds |
| Started | Aug 27 07:35:04 AM UTC 24 |
| Finished | Aug 27 07:35:11 AM UTC 24 |
| Peak memory | 225196 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3529298426 -assert nopostproc +UVM_TESTNAME =spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_08_26/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_tl_errors.3529298426 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/17.spi_device_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/17.spi_device_tl_intg_err.2165937185 |
| Short name | T1129 |
| Test name | |
| Test status | |
| Simulation time | 594929744 ps |
| CPU time | 13.89 seconds |
| Started | Aug 27 07:35:04 AM UTC 24 |
| Finished | Aug 27 07:35:20 AM UTC 24 |
| Peak memory | 224996 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2165937185 -assert nopostproc + UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_tl_intg_err.2165937185 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/17.spi_device_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/18.spi_device_csr_mem_rw_with_rand_reset.417554455 |
| Short name | T1114 |
| Test name | |
| Test status | |
| Simulation time | 495704857 ps |
| CPU time | 3.89 seconds |
| Started | Aug 27 07:35:07 AM UTC 24 |
| Finished | Aug 27 07:35:13 AM UTC 24 |
| Peak memory | 229428 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000 000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb _random_seed=417554455 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n ame 18.spi_device_csr_mem_rw_with_rand_reset.417554455 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/18.spi_device_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/18.spi_device_csr_rw.769801675 |
| Short name | T1087 |
| Test name | |
| Test status | |
| Simulation time | 30395566 ps |
| CPU time | 1.81 seconds |
| Started | Aug 27 07:35:06 AM UTC 24 |
| Finished | Aug 27 07:35:09 AM UTC 24 |
| Peak memory | 223908 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=769801675 -assert nopostproc +UVM_TESTNA ME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_csr_rw.769801675 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/18.spi_device_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/18.spi_device_intr_test.1915032869 |
| Short name | T1080 |
| Test name | |
| Test status | |
| Simulation time | 77775862 ps |
| CPU time | 0.92 seconds |
| Started | Aug 27 07:35:06 AM UTC 24 |
| Finished | Aug 27 07:35:08 AM UTC 24 |
| Peak memory | 211772 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1915032869 -assert nopostproc +UVM_TESTNAME =spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_08_26/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_intr_test.1915032869 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/18.spi_device_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/18.spi_device_same_csr_outstanding.3112740076 |
| Short name | T1111 |
| Test name | |
| Test status | |
| Simulation time | 162227623 ps |
| CPU time | 4.4 seconds |
| Started | Aug 27 07:35:07 AM UTC 24 |
| Finished | Aug 27 07:35:12 AM UTC 24 |
| Peak memory | 225252 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3112740076 -assert nop ostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_same_csr_outstan ding.3112740076 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/18.spi_device_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/18.spi_device_tl_errors.522207386 |
| Short name | T1082 |
| Test name | |
| Test status | |
| Simulation time | 153371525 ps |
| CPU time | 2.14 seconds |
| Started | Aug 27 07:35:05 AM UTC 24 |
| Finished | Aug 27 07:35:08 AM UTC 24 |
| Peak memory | 227272 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=522207386 -assert nopostproc +UVM_TESTNAME= spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_08_26/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_tl_errors.522207386 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/18.spi_device_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/18.spi_device_tl_intg_err.1100673558 |
| Short name | T1131 |
| Test name | |
| Test status | |
| Simulation time | 290564242 ps |
| CPU time | 18.27 seconds |
| Started | Aug 27 07:35:06 AM UTC 24 |
| Finished | Aug 27 07:35:25 AM UTC 24 |
| Peak memory | 225044 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1100673558 -assert nopostproc + UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_tl_intg_err.1100673558 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/18.spi_device_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/19.spi_device_csr_mem_rw_with_rand_reset.1941670696 |
| Short name | T1098 |
| Test name | |
| Test status | |
| Simulation time | 29777532 ps |
| CPU time | 1.83 seconds |
| Started | Aug 27 07:35:08 AM UTC 24 |
| Finished | Aug 27 07:35:11 AM UTC 24 |
| Peak memory | 226064 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000 000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb _random_seed=1941670696 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_ name 19.spi_device_csr_mem_rw_with_rand_reset.1941670696 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/19.spi_device_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/19.spi_device_csr_rw.4151415202 |
| Short name | T1094 |
| Test name | |
| Test status | |
| Simulation time | 249638962 ps |
| CPU time | 2.22 seconds |
| Started | Aug 27 07:35:07 AM UTC 24 |
| Finished | Aug 27 07:35:10 AM UTC 24 |
| Peak memory | 224996 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4151415202 -assert nopostproc +UVM_TESTN AME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_csr_rw.4151415202 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/19.spi_device_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/19.spi_device_intr_test.3280461518 |
| Short name | T1089 |
| Test name | |
| Test status | |
| Simulation time | 16159496 ps |
| CPU time | 0.97 seconds |
| Started | Aug 27 07:35:07 AM UTC 24 |
| Finished | Aug 27 07:35:09 AM UTC 24 |
| Peak memory | 211772 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3280461518 -assert nopostproc +UVM_TESTNAME =spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_08_26/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_intr_test.3280461518 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/19.spi_device_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/19.spi_device_same_csr_outstanding.1180927235 |
| Short name | T1099 |
| Test name | |
| Test status | |
| Simulation time | 134456816 ps |
| CPU time | 3.5 seconds |
| Started | Aug 27 07:35:07 AM UTC 24 |
| Finished | Aug 27 07:35:12 AM UTC 24 |
| Peak memory | 225052 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1180927235 -assert nop ostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_same_csr_outstan ding.1180927235 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/19.spi_device_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/19.spi_device_tl_errors.3096376107 |
| Short name | T1108 |
| Test name | |
| Test status | |
| Simulation time | 144543436 ps |
| CPU time | 3.99 seconds |
| Started | Aug 27 07:35:07 AM UTC 24 |
| Finished | Aug 27 07:35:12 AM UTC 24 |
| Peak memory | 227440 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3096376107 -assert nopostproc +UVM_TESTNAME =spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_08_26/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_tl_errors.3096376107 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/19.spi_device_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/2.spi_device_csr_aliasing.736704116 |
| Short name | T1043 |
| Test name | |
| Test status | |
| Simulation time | 6972238975 ps |
| CPU time | 22.08 seconds |
| Started | Aug 27 07:34:31 AM UTC 24 |
| Finished | Aug 27 07:34:54 AM UTC 24 |
| Peak memory | 214944 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=736704116 -assert nopostproc +UVM_ TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_csr_aliasing.736704116 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/2.spi_device_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/2.spi_device_csr_bit_bash.1782463407 |
| Short name | T1074 |
| Test name | |
| Test status | |
| Simulation time | 1852195640 ps |
| CPU time | 35.3 seconds |
| Started | Aug 27 07:34:29 AM UTC 24 |
| Finished | Aug 27 07:35:06 AM UTC 24 |
| Peak memory | 216816 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1782463407 -assert nopostproc +UVM _TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_csr_bit_bash.1782463407 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/2.spi_device_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/2.spi_device_csr_hw_reset.2973451095 |
| Short name | T103 |
| Test name | |
| Test status | |
| Simulation time | 24402714 ps |
| CPU time | 1.21 seconds |
| Started | Aug 27 07:34:29 AM UTC 24 |
| Finished | Aug 27 07:34:32 AM UTC 24 |
| Peak memory | 214088 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2973451095 -assert nopostproc +UVM _TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_csr_hw_reset.2973451095 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/2.spi_device_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/2.spi_device_csr_mem_rw_with_rand_reset.4046703455 |
| Short name | T132 |
| Test name | |
| Test status | |
| Simulation time | 129082458 ps |
| CPU time | 4.83 seconds |
| Started | Aug 27 07:34:31 AM UTC 24 |
| Finished | Aug 27 07:34:37 AM UTC 24 |
| Peak memory | 229308 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000 000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb _random_seed=4046703455 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_ name 2.spi_device_csr_mem_rw_with_rand_reset.4046703455 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/2.spi_device_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/2.spi_device_intr_test.709466021 |
| Short name | T1019 |
| Test name | |
| Test status | |
| Simulation time | 34661489 ps |
| CPU time | 0.85 seconds |
| Started | Aug 27 07:34:28 AM UTC 24 |
| Finished | Aug 27 07:34:30 AM UTC 24 |
| Peak memory | 211768 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=709466021 -assert nopostproc +UVM_TESTNAME= spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_08_26/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_intr_test.709466021 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/2.spi_device_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/2.spi_device_mem_partial_access.1091362989 |
| Short name | T137 |
| Test name | |
| Test status | |
| Simulation time | 211412005 ps |
| CPU time | 2.08 seconds |
| Started | Aug 27 07:34:29 AM UTC 24 |
| Finished | Aug 27 07:34:32 AM UTC 24 |
| Peak memory | 225104 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1091362989 -assert nopos tproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re po/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_mem_partial_access.1091362989 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/2.spi_device_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/2.spi_device_mem_walk.1164666629 |
| Short name | T1020 |
| Test name | |
| Test status | |
| Simulation time | 24354989 ps |
| CPU time | 0.91 seconds |
| Started | Aug 27 07:34:29 AM UTC 24 |
| Finished | Aug 27 07:34:31 AM UTC 24 |
| Peak memory | 211760 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1164666629 -assert nopostproc +UVM _TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_mem_walk.1164666629 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/2.spi_device_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/2.spi_device_same_csr_outstanding.3403841891 |
| Short name | T162 |
| Test name | |
| Test status | |
| Simulation time | 43260835 ps |
| CPU time | 3.69 seconds |
| Started | Aug 27 07:34:31 AM UTC 24 |
| Finished | Aug 27 07:34:36 AM UTC 24 |
| Peak memory | 225012 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3403841891 -assert nop ostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_same_csr_outstand ing.3403841891 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/2.spi_device_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/2.spi_device_tl_errors.3324824672 |
| Short name | T112 |
| Test name | |
| Test status | |
| Simulation time | 420095169 ps |
| CPU time | 3.22 seconds |
| Started | Aug 27 07:34:27 AM UTC 24 |
| Finished | Aug 27 07:34:31 AM UTC 24 |
| Peak memory | 225208 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3324824672 -assert nopostproc +UVM_TESTNAME =spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_08_26/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_tl_errors.3324824672 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/2.spi_device_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/20.spi_device_intr_test.2256799836 |
| Short name | T1095 |
| Test name | |
| Test status | |
| Simulation time | 18093491 ps |
| CPU time | 1.11 seconds |
| Started | Aug 27 07:35:08 AM UTC 24 |
| Finished | Aug 27 07:35:10 AM UTC 24 |
| Peak memory | 211772 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2256799836 -assert nopostproc +UVM_TESTNAME =spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_08_26/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.spi_device_intr_test.2256799836 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/20.spi_device_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/21.spi_device_intr_test.3816342414 |
| Short name | T1092 |
| Test name | |
| Test status | |
| Simulation time | 13191198 ps |
| CPU time | 1 seconds |
| Started | Aug 27 07:35:08 AM UTC 24 |
| Finished | Aug 27 07:35:10 AM UTC 24 |
| Peak memory | 211772 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3816342414 -assert nopostproc +UVM_TESTNAME =spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_08_26/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.spi_device_intr_test.3816342414 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/21.spi_device_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/22.spi_device_intr_test.933026851 |
| Short name | T1093 |
| Test name | |
| Test status | |
| Simulation time | 102883835 ps |
| CPU time | 0.97 seconds |
| Started | Aug 27 07:35:08 AM UTC 24 |
| Finished | Aug 27 07:35:10 AM UTC 24 |
| Peak memory | 211768 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=933026851 -assert nopostproc +UVM_TESTNAME= spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_08_26/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.spi_device_intr_test.933026851 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/22.spi_device_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/23.spi_device_intr_test.1551309095 |
| Short name | T1091 |
| Test name | |
| Test status | |
| Simulation time | 17220231 ps |
| CPU time | 0.87 seconds |
| Started | Aug 27 07:35:08 AM UTC 24 |
| Finished | Aug 27 07:35:10 AM UTC 24 |
| Peak memory | 211772 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1551309095 -assert nopostproc +UVM_TESTNAME =spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_08_26/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.spi_device_intr_test.1551309095 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/23.spi_device_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/24.spi_device_intr_test.2214504452 |
| Short name | T1100 |
| Test name | |
| Test status | |
| Simulation time | 46635091 ps |
| CPU time | 0.96 seconds |
| Started | Aug 27 07:35:10 AM UTC 24 |
| Finished | Aug 27 07:35:12 AM UTC 24 |
| Peak memory | 211772 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2214504452 -assert nopostproc +UVM_TESTNAME =spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_08_26/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.spi_device_intr_test.2214504452 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/24.spi_device_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/25.spi_device_intr_test.3238713177 |
| Short name | T1101 |
| Test name | |
| Test status | |
| Simulation time | 40060168 ps |
| CPU time | 1.02 seconds |
| Started | Aug 27 07:35:10 AM UTC 24 |
| Finished | Aug 27 07:35:12 AM UTC 24 |
| Peak memory | 211772 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3238713177 -assert nopostproc +UVM_TESTNAME =spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_08_26/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.spi_device_intr_test.3238713177 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/25.spi_device_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/26.spi_device_intr_test.371212984 |
| Short name | T1104 |
| Test name | |
| Test status | |
| Simulation time | 16406441 ps |
| CPU time | 1.07 seconds |
| Started | Aug 27 07:35:10 AM UTC 24 |
| Finished | Aug 27 07:35:12 AM UTC 24 |
| Peak memory | 211768 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=371212984 -assert nopostproc +UVM_TESTNAME= spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_08_26/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.spi_device_intr_test.371212984 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/26.spi_device_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/27.spi_device_intr_test.3275856949 |
| Short name | T1103 |
| Test name | |
| Test status | |
| Simulation time | 55482189 ps |
| CPU time | 0.96 seconds |
| Started | Aug 27 07:35:10 AM UTC 24 |
| Finished | Aug 27 07:35:12 AM UTC 24 |
| Peak memory | 211772 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3275856949 -assert nopostproc +UVM_TESTNAME =spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_08_26/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.spi_device_intr_test.3275856949 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/27.spi_device_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/28.spi_device_intr_test.3366169560 |
| Short name | T1109 |
| Test name | |
| Test status | |
| Simulation time | 62086488 ps |
| CPU time | 1.17 seconds |
| Started | Aug 27 07:35:10 AM UTC 24 |
| Finished | Aug 27 07:35:12 AM UTC 24 |
| Peak memory | 211772 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3366169560 -assert nopostproc +UVM_TESTNAME =spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_08_26/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.spi_device_intr_test.3366169560 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/28.spi_device_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/29.spi_device_intr_test.784254267 |
| Short name | T1105 |
| Test name | |
| Test status | |
| Simulation time | 33752062 ps |
| CPU time | 0.91 seconds |
| Started | Aug 27 07:35:10 AM UTC 24 |
| Finished | Aug 27 07:35:12 AM UTC 24 |
| Peak memory | 211768 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=784254267 -assert nopostproc +UVM_TESTNAME= spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_08_26/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.spi_device_intr_test.784254267 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/29.spi_device_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/3.spi_device_csr_aliasing.2676089606 |
| Short name | T1035 |
| Test name | |
| Test status | |
| Simulation time | 846487789 ps |
| CPU time | 13.91 seconds |
| Started | Aug 27 07:34:33 AM UTC 24 |
| Finished | Aug 27 07:34:49 AM UTC 24 |
| Peak memory | 224992 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2676089606 -assert nopostproc +UVM _TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_csr_aliasing.2676089606 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/3.spi_device_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/3.spi_device_csr_bit_bash.1087731497 |
| Short name | T146 |
| Test name | |
| Test status | |
| Simulation time | 1398311958 ps |
| CPU time | 22.47 seconds |
| Started | Aug 27 07:34:33 AM UTC 24 |
| Finished | Aug 27 07:34:57 AM UTC 24 |
| Peak memory | 214896 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1087731497 -assert nopostproc +UVM _TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_csr_bit_bash.1087731497 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/3.spi_device_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/3.spi_device_csr_hw_reset.2136781878 |
| Short name | T1023 |
| Test name | |
| Test status | |
| Simulation time | 112356401 ps |
| CPU time | 1.73 seconds |
| Started | Aug 27 07:34:32 AM UTC 24 |
| Finished | Aug 27 07:34:35 AM UTC 24 |
| Peak memory | 214144 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2136781878 -assert nopostproc +UVM _TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_csr_hw_reset.2136781878 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/3.spi_device_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/3.spi_device_csr_mem_rw_with_rand_reset.3334664585 |
| Short name | T129 |
| Test name | |
| Test status | |
| Simulation time | 51652640 ps |
| CPU time | 3.5 seconds |
| Started | Aug 27 07:34:33 AM UTC 24 |
| Finished | Aug 27 07:34:39 AM UTC 24 |
| Peak memory | 229288 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000 000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb _random_seed=3334664585 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_ name 3.spi_device_csr_mem_rw_with_rand_reset.3334664585 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/3.spi_device_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/3.spi_device_csr_rw.2913292478 |
| Short name | T169 |
| Test name | |
| Test status | |
| Simulation time | 269198742 ps |
| CPU time | 2.69 seconds |
| Started | Aug 27 07:34:32 AM UTC 24 |
| Finished | Aug 27 07:34:37 AM UTC 24 |
| Peak memory | 216808 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2913292478 -assert nopostproc +UVM_TESTN AME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_csr_rw.2913292478 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/3.spi_device_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/3.spi_device_intr_test.1390279668 |
| Short name | T1022 |
| Test name | |
| Test status | |
| Simulation time | 38757880 ps |
| CPU time | 1.11 seconds |
| Started | Aug 27 07:34:32 AM UTC 24 |
| Finished | Aug 27 07:34:34 AM UTC 24 |
| Peak memory | 211764 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1390279668 -assert nopostproc +UVM_TESTNAME =spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_08_26/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_intr_test.1390279668 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/3.spi_device_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/3.spi_device_mem_partial_access.938936538 |
| Short name | T138 |
| Test name | |
| Test status | |
| Simulation time | 120130660 ps |
| CPU time | 3.28 seconds |
| Started | Aug 27 07:34:32 AM UTC 24 |
| Finished | Aug 27 07:34:37 AM UTC 24 |
| Peak memory | 224540 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=938936538 -assert nopost proc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep o/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_mem_partial_access.938936538 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/3.spi_device_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/3.spi_device_mem_walk.885846780 |
| Short name | T1021 |
| Test name | |
| Test status | |
| Simulation time | 10942860 ps |
| CPU time | 0.99 seconds |
| Started | Aug 27 07:34:32 AM UTC 24 |
| Finished | Aug 27 07:34:34 AM UTC 24 |
| Peak memory | 210704 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=885846780 -assert nopostproc +UVM_ TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_mem_walk.885846780 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/3.spi_device_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/3.spi_device_same_csr_outstanding.4004819864 |
| Short name | T1026 |
| Test name | |
| Test status | |
| Simulation time | 417513952 ps |
| CPU time | 3.43 seconds |
| Started | Aug 27 07:34:33 AM UTC 24 |
| Finished | Aug 27 07:34:38 AM UTC 24 |
| Peak memory | 225104 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4004819864 -assert nop ostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_same_csr_outstand ing.4004819864 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/3.spi_device_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/3.spi_device_tl_errors.2320152512 |
| Short name | T113 |
| Test name | |
| Test status | |
| Simulation time | 123681446 ps |
| CPU time | 2.63 seconds |
| Started | Aug 27 07:34:31 AM UTC 24 |
| Finished | Aug 27 07:34:35 AM UTC 24 |
| Peak memory | 225444 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2320152512 -assert nopostproc +UVM_TESTNAME =spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_08_26/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_tl_errors.2320152512 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/3.spi_device_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/3.spi_device_tl_intg_err.2449288922 |
| Short name | T116 |
| Test name | |
| Test status | |
| Simulation time | 786166328 ps |
| CPU time | 12.66 seconds |
| Started | Aug 27 07:34:31 AM UTC 24 |
| Finished | Aug 27 07:34:45 AM UTC 24 |
| Peak memory | 227200 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2449288922 -assert nopostproc + UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_tl_intg_err.2449288922 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/3.spi_device_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/30.spi_device_intr_test.484951680 |
| Short name | T1106 |
| Test name | |
| Test status | |
| Simulation time | 46249997 ps |
| CPU time | 0.94 seconds |
| Started | Aug 27 07:35:10 AM UTC 24 |
| Finished | Aug 27 07:35:12 AM UTC 24 |
| Peak memory | 211764 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=484951680 -assert nopostproc +UVM_TESTNAME= spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_08_26/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.spi_device_intr_test.484951680 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/30.spi_device_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/31.spi_device_intr_test.3467637559 |
| Short name | T1110 |
| Test name | |
| Test status | |
| Simulation time | 11829442 ps |
| CPU time | 1.08 seconds |
| Started | Aug 27 07:35:10 AM UTC 24 |
| Finished | Aug 27 07:35:12 AM UTC 24 |
| Peak memory | 211772 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3467637559 -assert nopostproc +UVM_TESTNAME =spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_08_26/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.spi_device_intr_test.3467637559 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/31.spi_device_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/32.spi_device_intr_test.2093313930 |
| Short name | T1107 |
| Test name | |
| Test status | |
| Simulation time | 49014462 ps |
| CPU time | 0.95 seconds |
| Started | Aug 27 07:35:10 AM UTC 24 |
| Finished | Aug 27 07:35:12 AM UTC 24 |
| Peak memory | 211772 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2093313930 -assert nopostproc +UVM_TESTNAME =spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_08_26/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.spi_device_intr_test.2093313930 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/32.spi_device_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/33.spi_device_intr_test.1492495122 |
| Short name | T1112 |
| Test name | |
| Test status | |
| Simulation time | 13301607 ps |
| CPU time | 0.89 seconds |
| Started | Aug 27 07:35:11 AM UTC 24 |
| Finished | Aug 27 07:35:13 AM UTC 24 |
| Peak memory | 211772 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1492495122 -assert nopostproc +UVM_TESTNAME =spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_08_26/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.spi_device_intr_test.1492495122 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/33.spi_device_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/34.spi_device_intr_test.2505865512 |
| Short name | T1061 |
| Test name | |
| Test status | |
| Simulation time | 16285134 ps |
| CPU time | 0.82 seconds |
| Started | Aug 27 07:35:11 AM UTC 24 |
| Finished | Aug 27 07:35:13 AM UTC 24 |
| Peak memory | 211772 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2505865512 -assert nopostproc +UVM_TESTNAME =spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_08_26/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.spi_device_intr_test.2505865512 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/34.spi_device_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/35.spi_device_intr_test.192765484 |
| Short name | T1115 |
| Test name | |
| Test status | |
| Simulation time | 41766298 ps |
| CPU time | 0.88 seconds |
| Started | Aug 27 07:35:11 AM UTC 24 |
| Finished | Aug 27 07:35:13 AM UTC 24 |
| Peak memory | 211768 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=192765484 -assert nopostproc +UVM_TESTNAME= spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_08_26/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.spi_device_intr_test.192765484 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/35.spi_device_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/36.spi_device_intr_test.1689488489 |
| Short name | T1113 |
| Test name | |
| Test status | |
| Simulation time | 14064615 ps |
| CPU time | 0.82 seconds |
| Started | Aug 27 07:35:11 AM UTC 24 |
| Finished | Aug 27 07:35:13 AM UTC 24 |
| Peak memory | 211772 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1689488489 -assert nopostproc +UVM_TESTNAME =spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_08_26/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.spi_device_intr_test.1689488489 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/36.spi_device_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/37.spi_device_intr_test.3804120000 |
| Short name | T1116 |
| Test name | |
| Test status | |
| Simulation time | 185497189 ps |
| CPU time | 0.8 seconds |
| Started | Aug 27 07:35:11 AM UTC 24 |
| Finished | Aug 27 07:35:13 AM UTC 24 |
| Peak memory | 211772 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3804120000 -assert nopostproc +UVM_TESTNAME =spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_08_26/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.spi_device_intr_test.3804120000 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/37.spi_device_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/38.spi_device_intr_test.1156848839 |
| Short name | T1117 |
| Test name | |
| Test status | |
| Simulation time | 26532441 ps |
| CPU time | 0.86 seconds |
| Started | Aug 27 07:35:11 AM UTC 24 |
| Finished | Aug 27 07:35:13 AM UTC 24 |
| Peak memory | 211772 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1156848839 -assert nopostproc +UVM_TESTNAME =spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_08_26/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.spi_device_intr_test.1156848839 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/38.spi_device_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/39.spi_device_intr_test.4126463385 |
| Short name | T1118 |
| Test name | |
| Test status | |
| Simulation time | 14184521 ps |
| CPU time | 0.92 seconds |
| Started | Aug 27 07:35:11 AM UTC 24 |
| Finished | Aug 27 07:35:13 AM UTC 24 |
| Peak memory | 211772 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4126463385 -assert nopostproc +UVM_TESTNAME =spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_08_26/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.spi_device_intr_test.4126463385 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/39.spi_device_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/4.spi_device_csr_aliasing.2349237189 |
| Short name | T1052 |
| Test name | |
| Test status | |
| Simulation time | 307039230 ps |
| CPU time | 20.12 seconds |
| Started | Aug 27 07:34:38 AM UTC 24 |
| Finished | Aug 27 07:34:59 AM UTC 24 |
| Peak memory | 225088 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2349237189 -assert nopostproc +UVM _TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_csr_aliasing.2349237189 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/4.spi_device_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/4.spi_device_csr_bit_bash.2731069916 |
| Short name | T1062 |
| Test name | |
| Test status | |
| Simulation time | 735930843 ps |
| CPU time | 23.18 seconds |
| Started | Aug 27 07:34:38 AM UTC 24 |
| Finished | Aug 27 07:35:02 AM UTC 24 |
| Peak memory | 214888 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2731069916 -assert nopostproc +UVM _TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_csr_bit_bash.2731069916 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/4.spi_device_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/4.spi_device_csr_hw_reset.2179119585 |
| Short name | T140 |
| Test name | |
| Test status | |
| Simulation time | 835068957 ps |
| CPU time | 2.01 seconds |
| Started | Aug 27 07:34:37 AM UTC 24 |
| Finished | Aug 27 07:34:40 AM UTC 24 |
| Peak memory | 226464 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2179119585 -assert nopostproc +UVM _TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_csr_hw_reset.2179119585 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/4.spi_device_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/4.spi_device_csr_mem_rw_with_rand_reset.1674521147 |
| Short name | T125 |
| Test name | |
| Test status | |
| Simulation time | 662768235 ps |
| CPU time | 4.89 seconds |
| Started | Aug 27 07:34:39 AM UTC 24 |
| Finished | Aug 27 07:34:45 AM UTC 24 |
| Peak memory | 229308 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000 000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb _random_seed=1674521147 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_ name 4.spi_device_csr_mem_rw_with_rand_reset.1674521147 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/4.spi_device_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/4.spi_device_csr_rw.2350056011 |
| Short name | T170 |
| Test name | |
| Test status | |
| Simulation time | 45274449 ps |
| CPU time | 1.73 seconds |
| Started | Aug 27 07:34:38 AM UTC 24 |
| Finished | Aug 27 07:34:41 AM UTC 24 |
| Peak memory | 213668 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2350056011 -assert nopostproc +UVM_TESTN AME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_csr_rw.2350056011 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/4.spi_device_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/4.spi_device_intr_test.3091876661 |
| Short name | T1025 |
| Test name | |
| Test status | |
| Simulation time | 16370637 ps |
| CPU time | 0.92 seconds |
| Started | Aug 27 07:34:35 AM UTC 24 |
| Finished | Aug 27 07:34:38 AM UTC 24 |
| Peak memory | 211764 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3091876661 -assert nopostproc +UVM_TESTNAME =spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_08_26/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_intr_test.3091876661 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/4.spi_device_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/4.spi_device_mem_partial_access.4210663043 |
| Short name | T139 |
| Test name | |
| Test status | |
| Simulation time | 21045632 ps |
| CPU time | 1.3 seconds |
| Started | Aug 27 07:34:37 AM UTC 24 |
| Finished | Aug 27 07:34:39 AM UTC 24 |
| Peak memory | 223948 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4210663043 -assert nopos tproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re po/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_mem_partial_access.4210663043 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/4.spi_device_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/4.spi_device_mem_walk.3933866929 |
| Short name | T1027 |
| Test name | |
| Test status | |
| Simulation time | 77592148 ps |
| CPU time | 0.98 seconds |
| Started | Aug 27 07:34:37 AM UTC 24 |
| Finished | Aug 27 07:34:39 AM UTC 24 |
| Peak memory | 211760 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3933866929 -assert nopostproc +UVM _TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_mem_walk.3933866929 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/4.spi_device_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/4.spi_device_same_csr_outstanding.610359426 |
| Short name | T1030 |
| Test name | |
| Test status | |
| Simulation time | 228632335 ps |
| CPU time | 5.06 seconds |
| Started | Aug 27 07:34:38 AM UTC 24 |
| Finished | Aug 27 07:34:44 AM UTC 24 |
| Peak memory | 225028 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=610359426 -assert nopo stproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r epo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_same_csr_outstanding.610359426 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/4.spi_device_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/4.spi_device_tl_intg_err.4262541807 |
| Short name | T203 |
| Test name | |
| Test status | |
| Simulation time | 338484297 ps |
| CPU time | 17.84 seconds |
| Started | Aug 27 07:34:35 AM UTC 24 |
| Finished | Aug 27 07:34:55 AM UTC 24 |
| Peak memory | 225084 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4262541807 -assert nopostproc + UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_tl_intg_err.4262541807 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/4.spi_device_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/40.spi_device_intr_test.1600300285 |
| Short name | T1121 |
| Test name | |
| Test status | |
| Simulation time | 47884196 ps |
| CPU time | 0.85 seconds |
| Started | Aug 27 07:35:12 AM UTC 24 |
| Finished | Aug 27 07:35:14 AM UTC 24 |
| Peak memory | 211772 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1600300285 -assert nopostproc +UVM_TESTNAME =spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_08_26/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.spi_device_intr_test.1600300285 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/40.spi_device_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/41.spi_device_intr_test.198810013 |
| Short name | T1119 |
| Test name | |
| Test status | |
| Simulation time | 18392427 ps |
| CPU time | 0.74 seconds |
| Started | Aug 27 07:35:12 AM UTC 24 |
| Finished | Aug 27 07:35:14 AM UTC 24 |
| Peak memory | 211768 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=198810013 -assert nopostproc +UVM_TESTNAME= spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_08_26/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.spi_device_intr_test.198810013 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/41.spi_device_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/42.spi_device_intr_test.3543670212 |
| Short name | T1120 |
| Test name | |
| Test status | |
| Simulation time | 31927608 ps |
| CPU time | 0.79 seconds |
| Started | Aug 27 07:35:12 AM UTC 24 |
| Finished | Aug 27 07:35:14 AM UTC 24 |
| Peak memory | 211772 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3543670212 -assert nopostproc +UVM_TESTNAME =spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_08_26/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.spi_device_intr_test.3543670212 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/42.spi_device_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/43.spi_device_intr_test.837233944 |
| Short name | T1123 |
| Test name | |
| Test status | |
| Simulation time | 11632849 ps |
| CPU time | 0.93 seconds |
| Started | Aug 27 07:35:12 AM UTC 24 |
| Finished | Aug 27 07:35:14 AM UTC 24 |
| Peak memory | 211768 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=837233944 -assert nopostproc +UVM_TESTNAME= spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_08_26/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.spi_device_intr_test.837233944 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/43.spi_device_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/44.spi_device_intr_test.1611187733 |
| Short name | T1122 |
| Test name | |
| Test status | |
| Simulation time | 20092714 ps |
| CPU time | 0.83 seconds |
| Started | Aug 27 07:35:13 AM UTC 24 |
| Finished | Aug 27 07:35:14 AM UTC 24 |
| Peak memory | 211772 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1611187733 -assert nopostproc +UVM_TESTNAME =spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_08_26/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.spi_device_intr_test.1611187733 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/44.spi_device_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/45.spi_device_intr_test.1361079737 |
| Short name | T1124 |
| Test name | |
| Test status | |
| Simulation time | 16152110 ps |
| CPU time | 0.84 seconds |
| Started | Aug 27 07:35:13 AM UTC 24 |
| Finished | Aug 27 07:35:14 AM UTC 24 |
| Peak memory | 211772 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1361079737 -assert nopostproc +UVM_TESTNAME =spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_08_26/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.spi_device_intr_test.1361079737 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/45.spi_device_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/46.spi_device_intr_test.1361167500 |
| Short name | T1128 |
| Test name | |
| Test status | |
| Simulation time | 12375303 ps |
| CPU time | 1.08 seconds |
| Started | Aug 27 07:35:13 AM UTC 24 |
| Finished | Aug 27 07:35:15 AM UTC 24 |
| Peak memory | 211772 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1361167500 -assert nopostproc +UVM_TESTNAME =spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_08_26/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.spi_device_intr_test.1361167500 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/46.spi_device_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/47.spi_device_intr_test.1733338392 |
| Short name | T1127 |
| Test name | |
| Test status | |
| Simulation time | 46613521 ps |
| CPU time | 0.96 seconds |
| Started | Aug 27 07:35:13 AM UTC 24 |
| Finished | Aug 27 07:35:15 AM UTC 24 |
| Peak memory | 211772 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1733338392 -assert nopostproc +UVM_TESTNAME =spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_08_26/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.spi_device_intr_test.1733338392 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/47.spi_device_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/48.spi_device_intr_test.3680108146 |
| Short name | T1126 |
| Test name | |
| Test status | |
| Simulation time | 104239391 ps |
| CPU time | 0.89 seconds |
| Started | Aug 27 07:35:13 AM UTC 24 |
| Finished | Aug 27 07:35:15 AM UTC 24 |
| Peak memory | 211772 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3680108146 -assert nopostproc +UVM_TESTNAME =spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_08_26/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.spi_device_intr_test.3680108146 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/48.spi_device_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/49.spi_device_intr_test.2836792070 |
| Short name | T1125 |
| Test name | |
| Test status | |
| Simulation time | 43234170 ps |
| CPU time | 0.83 seconds |
| Started | Aug 27 07:35:13 AM UTC 24 |
| Finished | Aug 27 07:35:14 AM UTC 24 |
| Peak memory | 211772 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2836792070 -assert nopostproc +UVM_TESTNAME =spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_08_26/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.spi_device_intr_test.2836792070 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/49.spi_device_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/5.spi_device_csr_mem_rw_with_rand_reset.1015269769 |
| Short name | T127 |
| Test name | |
| Test status | |
| Simulation time | 49413088 ps |
| CPU time | 1.82 seconds |
| Started | Aug 27 07:34:41 AM UTC 24 |
| Finished | Aug 27 07:34:44 AM UTC 24 |
| Peak memory | 224016 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000 000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb _random_seed=1015269769 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_ name 5.spi_device_csr_mem_rw_with_rand_reset.1015269769 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/5.spi_device_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/5.spi_device_csr_rw.4031961024 |
| Short name | T1029 |
| Test name | |
| Test status | |
| Simulation time | 229603355 ps |
| CPU time | 2.75 seconds |
| Started | Aug 27 07:34:40 AM UTC 24 |
| Finished | Aug 27 07:34:44 AM UTC 24 |
| Peak memory | 214840 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4031961024 -assert nopostproc +UVM_TESTN AME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_csr_rw.4031961024 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/5.spi_device_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/5.spi_device_intr_test.1388063578 |
| Short name | T1028 |
| Test name | |
| Test status | |
| Simulation time | 64689288 ps |
| CPU time | 1.1 seconds |
| Started | Aug 27 07:34:40 AM UTC 24 |
| Finished | Aug 27 07:34:42 AM UTC 24 |
| Peak memory | 211764 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1388063578 -assert nopostproc +UVM_TESTNAME =spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_08_26/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_intr_test.1388063578 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/5.spi_device_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/5.spi_device_same_csr_outstanding.4082887973 |
| Short name | T1032 |
| Test name | |
| Test status | |
| Simulation time | 311110675 ps |
| CPU time | 5.34 seconds |
| Started | Aug 27 07:34:40 AM UTC 24 |
| Finished | Aug 27 07:34:47 AM UTC 24 |
| Peak memory | 225312 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4082887973 -assert nop ostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_same_csr_outstand ing.4082887973 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/5.spi_device_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/5.spi_device_tl_errors.3384187266 |
| Short name | T123 |
| Test name | |
| Test status | |
| Simulation time | 244622976 ps |
| CPU time | 2.77 seconds |
| Started | Aug 27 07:34:39 AM UTC 24 |
| Finished | Aug 27 07:34:43 AM UTC 24 |
| Peak memory | 227244 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3384187266 -assert nopostproc +UVM_TESTNAME =spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_08_26/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_tl_errors.3384187266 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/5.spi_device_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/5.spi_device_tl_intg_err.2461809705 |
| Short name | T202 |
| Test name | |
| Test status | |
| Simulation time | 856589174 ps |
| CPU time | 22.48 seconds |
| Started | Aug 27 07:34:40 AM UTC 24 |
| Finished | Aug 27 07:35:04 AM UTC 24 |
| Peak memory | 227328 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2461809705 -assert nopostproc + UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_tl_intg_err.2461809705 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/5.spi_device_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/6.spi_device_csr_mem_rw_with_rand_reset.2910633814 |
| Short name | T171 |
| Test name | |
| Test status | |
| Simulation time | 116080729 ps |
| CPU time | 2.44 seconds |
| Started | Aug 27 07:34:45 AM UTC 24 |
| Finished | Aug 27 07:34:48 AM UTC 24 |
| Peak memory | 226988 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000 000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb _random_seed=2910633814 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_ name 6.spi_device_csr_mem_rw_with_rand_reset.2910633814 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/6.spi_device_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/6.spi_device_csr_rw.2453233179 |
| Short name | T142 |
| Test name | |
| Test status | |
| Simulation time | 134840842 ps |
| CPU time | 2.53 seconds |
| Started | Aug 27 07:34:44 AM UTC 24 |
| Finished | Aug 27 07:34:47 AM UTC 24 |
| Peak memory | 214840 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2453233179 -assert nopostproc +UVM_TESTN AME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_csr_rw.2453233179 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/6.spi_device_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/6.spi_device_intr_test.3032596371 |
| Short name | T1031 |
| Test name | |
| Test status | |
| Simulation time | 16608666 ps |
| CPU time | 0.92 seconds |
| Started | Aug 27 07:34:44 AM UTC 24 |
| Finished | Aug 27 07:34:46 AM UTC 24 |
| Peak memory | 211764 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3032596371 -assert nopostproc +UVM_TESTNAME =spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_08_26/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_intr_test.3032596371 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/6.spi_device_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/6.spi_device_same_csr_outstanding.220196102 |
| Short name | T1034 |
| Test name | |
| Test status | |
| Simulation time | 237457758 ps |
| CPU time | 2.25 seconds |
| Started | Aug 27 07:34:45 AM UTC 24 |
| Finished | Aug 27 07:34:48 AM UTC 24 |
| Peak memory | 224696 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=220196102 -assert nopo stproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r epo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_same_csr_outstanding.220196102 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/6.spi_device_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/6.spi_device_tl_intg_err.1799361987 |
| Short name | T174 |
| Test name | |
| Test status | |
| Simulation time | 1286537527 ps |
| CPU time | 15.46 seconds |
| Started | Aug 27 07:34:44 AM UTC 24 |
| Finished | Aug 27 07:35:00 AM UTC 24 |
| Peak memory | 227048 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1799361987 -assert nopostproc + UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_tl_intg_err.1799361987 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/6.spi_device_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/7.spi_device_csr_mem_rw_with_rand_reset.1874046439 |
| Short name | T1037 |
| Test name | |
| Test status | |
| Simulation time | 26639755 ps |
| CPU time | 2.46 seconds |
| Started | Aug 27 07:34:46 AM UTC 24 |
| Finished | Aug 27 07:34:50 AM UTC 24 |
| Peak memory | 227228 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000 000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb _random_seed=1874046439 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_ name 7.spi_device_csr_mem_rw_with_rand_reset.1874046439 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/7.spi_device_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/7.spi_device_csr_rw.1961746620 |
| Short name | T144 |
| Test name | |
| Test status | |
| Simulation time | 112355332 ps |
| CPU time | 2.38 seconds |
| Started | Aug 27 07:34:45 AM UTC 24 |
| Finished | Aug 27 07:34:48 AM UTC 24 |
| Peak memory | 225076 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1961746620 -assert nopostproc +UVM_TESTN AME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_csr_rw.1961746620 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/7.spi_device_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/7.spi_device_intr_test.1689233198 |
| Short name | T1033 |
| Test name | |
| Test status | |
| Simulation time | 13974306 ps |
| CPU time | 1.13 seconds |
| Started | Aug 27 07:34:45 AM UTC 24 |
| Finished | Aug 27 07:34:47 AM UTC 24 |
| Peak memory | 211764 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1689233198 -assert nopostproc +UVM_TESTNAME =spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_08_26/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_intr_test.1689233198 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/7.spi_device_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/7.spi_device_same_csr_outstanding.841377299 |
| Short name | T1038 |
| Test name | |
| Test status | |
| Simulation time | 591605778 ps |
| CPU time | 4.83 seconds |
| Started | Aug 27 07:34:46 AM UTC 24 |
| Finished | Aug 27 07:34:52 AM UTC 24 |
| Peak memory | 225044 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=841377299 -assert nopo stproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r epo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_same_csr_outstanding.841377299 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/7.spi_device_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/7.spi_device_tl_errors.1323391527 |
| Short name | T122 |
| Test name | |
| Test status | |
| Simulation time | 826364825 ps |
| CPU time | 4.72 seconds |
| Started | Aug 27 07:34:45 AM UTC 24 |
| Finished | Aug 27 07:34:51 AM UTC 24 |
| Peak memory | 227232 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1323391527 -assert nopostproc +UVM_TESTNAME =spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_08_26/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_tl_errors.1323391527 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/7.spi_device_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/7.spi_device_tl_intg_err.2720883482 |
| Short name | T201 |
| Test name | |
| Test status | |
| Simulation time | 913035912 ps |
| CPU time | 17.46 seconds |
| Started | Aug 27 07:34:45 AM UTC 24 |
| Finished | Aug 27 07:35:04 AM UTC 24 |
| Peak memory | 225132 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2720883482 -assert nopostproc + UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_tl_intg_err.2720883482 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/7.spi_device_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/8.spi_device_csr_mem_rw_with_rand_reset.2034016318 |
| Short name | T1044 |
| Test name | |
| Test status | |
| Simulation time | 56950830 ps |
| CPU time | 4.39 seconds |
| Started | Aug 27 07:34:49 AM UTC 24 |
| Finished | Aug 27 07:34:54 AM UTC 24 |
| Peak memory | 229160 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000 000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb _random_seed=2034016318 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_ name 8.spi_device_csr_mem_rw_with_rand_reset.2034016318 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/8.spi_device_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/8.spi_device_csr_rw.3638893699 |
| Short name | T145 |
| Test name | |
| Test status | |
| Simulation time | 308340134 ps |
| CPU time | 2.73 seconds |
| Started | Aug 27 07:34:48 AM UTC 24 |
| Finished | Aug 27 07:34:53 AM UTC 24 |
| Peak memory | 225044 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3638893699 -assert nopostproc +UVM_TESTN AME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_csr_rw.3638893699 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/8.spi_device_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/8.spi_device_intr_test.1119327156 |
| Short name | T1036 |
| Test name | |
| Test status | |
| Simulation time | 111462308 ps |
| CPU time | 1.07 seconds |
| Started | Aug 27 07:34:47 AM UTC 24 |
| Finished | Aug 27 07:34:50 AM UTC 24 |
| Peak memory | 211764 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1119327156 -assert nopostproc +UVM_TESTNAME =spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_08_26/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_intr_test.1119327156 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/8.spi_device_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/8.spi_device_same_csr_outstanding.2760623088 |
| Short name | T1040 |
| Test name | |
| Test status | |
| Simulation time | 48053384 ps |
| CPU time | 2.2 seconds |
| Started | Aug 27 07:34:49 AM UTC 24 |
| Finished | Aug 27 07:34:53 AM UTC 24 |
| Peak memory | 214820 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2760623088 -assert nop ostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_same_csr_outstand ing.2760623088 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/8.spi_device_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/8.spi_device_tl_errors.979015709 |
| Short name | T128 |
| Test name | |
| Test status | |
| Simulation time | 174277605 ps |
| CPU time | 5.64 seconds |
| Started | Aug 27 07:34:46 AM UTC 24 |
| Finished | Aug 27 07:34:53 AM UTC 24 |
| Peak memory | 227404 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=979015709 -assert nopostproc +UVM_TESTNAME= spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_08_26/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_tl_errors.979015709 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/8.spi_device_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/8.spi_device_tl_intg_err.4147803364 |
| Short name | T204 |
| Test name | |
| Test status | |
| Simulation time | 8415087358 ps |
| CPU time | 15.7 seconds |
| Started | Aug 27 07:34:46 AM UTC 24 |
| Finished | Aug 27 07:35:03 AM UTC 24 |
| Peak memory | 227248 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4147803364 -assert nopostproc + UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_tl_intg_err.4147803364 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/8.spi_device_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/9.spi_device_csr_mem_rw_with_rand_reset.3743911996 |
| Short name | T1045 |
| Test name | |
| Test status | |
| Simulation time | 127998893 ps |
| CPU time | 3.11 seconds |
| Started | Aug 27 07:34:51 AM UTC 24 |
| Finished | Aug 27 07:34:55 AM UTC 24 |
| Peak memory | 226420 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000 000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb _random_seed=3743911996 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_ name 9.spi_device_csr_mem_rw_with_rand_reset.3743911996 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/9.spi_device_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/9.spi_device_csr_rw.1466280136 |
| Short name | T1041 |
| Test name | |
| Test status | |
| Simulation time | 165828207 ps |
| CPU time | 1.76 seconds |
| Started | Aug 27 07:34:50 AM UTC 24 |
| Finished | Aug 27 07:34:53 AM UTC 24 |
| Peak memory | 213668 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1466280136 -assert nopostproc +UVM_TESTN AME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_csr_rw.1466280136 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/9.spi_device_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/9.spi_device_intr_test.1827133526 |
| Short name | T1039 |
| Test name | |
| Test status | |
| Simulation time | 67095863 ps |
| CPU time | 0.88 seconds |
| Started | Aug 27 07:34:50 AM UTC 24 |
| Finished | Aug 27 07:34:52 AM UTC 24 |
| Peak memory | 211764 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1827133526 -assert nopostproc +UVM_TESTNAME =spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_08_26/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_intr_test.1827133526 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/9.spi_device_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/9.spi_device_same_csr_outstanding.3870766709 |
| Short name | T1047 |
| Test name | |
| Test status | |
| Simulation time | 58579505 ps |
| CPU time | 4.97 seconds |
| Started | Aug 27 07:34:50 AM UTC 24 |
| Finished | Aug 27 07:34:56 AM UTC 24 |
| Peak memory | 225136 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3870766709 -assert nop ostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_same_csr_outstand ing.3870766709 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/9.spi_device_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/9.spi_device_tl_errors.4026031260 |
| Short name | T130 |
| Test name | |
| Test status | |
| Simulation time | 35113022 ps |
| CPU time | 2.54 seconds |
| Started | Aug 27 07:34:50 AM UTC 24 |
| Finished | Aug 27 07:34:54 AM UTC 24 |
| Peak memory | 225176 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4026031260 -assert nopostproc +UVM_TESTNAME =spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_08_26/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_tl_errors.4026031260 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/9.spi_device_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/9.spi_device_tl_intg_err.644145651 |
| Short name | T1069 |
| Test name | |
| Test status | |
| Simulation time | 200545324 ps |
| CPU time | 12.97 seconds |
| Started | Aug 27 07:34:50 AM UTC 24 |
| Finished | Aug 27 07:35:04 AM UTC 24 |
| Peak memory | 225140 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=644145651 -assert nopostproc +U VM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_tl_intg_err.644145651 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/9.spi_device_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/0.spi_device_cfg_cmd.2184688680 |
| Short name | T10 |
| Test name | |
| Test status | |
| Simulation time | 1928879861 ps |
| CPU time | 9.84 seconds |
| Started | Aug 27 06:07:56 PM UTC 24 |
| Finished | Aug 27 06:08:07 PM UTC 24 |
| Peak memory | 235024 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2184688680 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_cfg_cmd.2184688680 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/0.spi_device_cfg_cmd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/0.spi_device_flash_all.4169996960 |
| Short name | T49 |
| Test name | |
| Test status | |
| Simulation time | 25719609066 ps |
| CPU time | 287.17 seconds |
| Started | Aug 27 06:08:09 PM UTC 24 |
| Finished | Aug 27 06:13:01 PM UTC 24 |
| Peak memory | 263764 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4169996960 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/s pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_all.4169996960 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/0.spi_device_flash_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/0.spi_device_flash_mode.1021634247 |
| Short name | T15 |
| Test name | |
| Test status | |
| Simulation time | 4571852161 ps |
| CPU time | 30.26 seconds |
| Started | Aug 27 06:08:03 PM UTC 24 |
| Finished | Aug 27 06:08:34 PM UTC 24 |
| Peak memory | 245332 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1021634247 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/ spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_mode.1021634247 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/0.spi_device_flash_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/0.spi_device_pass_cmd_filtering.1797538171 |
| Short name | T7 |
| Test name | |
| Test status | |
| Simulation time | 430390217 ps |
| CPU time | 7.25 seconds |
| Started | Aug 27 06:07:41 PM UTC 24 |
| Finished | Aug 27 06:07:49 PM UTC 24 |
| Peak memory | 245200 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1797538171 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_08_26/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_pass_cmd_filtering.1797538171 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/0.spi_device_pass_cmd_filtering/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/0.spi_device_read_buffer_direct.3813392750 |
| Short name | T12 |
| Test name | |
| Test status | |
| Simulation time | 7183843311 ps |
| CPU time | 14.82 seconds |
| Started | Aug 27 06:08:07 PM UTC 24 |
| Finished | Aug 27 06:08:23 PM UTC 24 |
| Peak memory | 231396 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3813392750 -assert nopostproc +UVM_TESTNAME=spi_device _base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_read_buffer_direct.3813392750 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/0.spi_device_read_buffer_direct/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/0.spi_device_tpm_all.654822270 |
| Short name | T6 |
| Test name | |
| Test status | |
| Simulation time | 1438326648 ps |
| CPU time | 5.8 seconds |
| Started | Aug 27 06:07:35 PM UTC 24 |
| Finished | Aug 27 06:07:42 PM UTC 24 |
| Peak memory | 227404 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=654822270 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_all.654822270 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/0.spi_device_tpm_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/0.spi_device_tpm_read_hw_reg.508382647 |
| Short name | T8 |
| Test name | |
| Test status | |
| Simulation time | 6872485204 ps |
| CPU time | 15.23 seconds |
| Started | Aug 27 06:07:35 PM UTC 24 |
| Finished | Aug 27 06:07:51 PM UTC 24 |
| Peak memory | 227628 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=508382647 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08 _26/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_read_hw_reg.508382647 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/0.spi_device_tpm_read_hw_reg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/0.spi_device_tpm_rw.261573891 |
| Short name | T5 |
| Test name | |
| Test status | |
| Simulation time | 13225914 ps |
| CPU time | 1.06 seconds |
| Started | Aug 27 06:07:38 PM UTC 24 |
| Finished | Aug 27 06:07:40 PM UTC 24 |
| Peak memory | 215744 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=261573891 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/spi_d evice_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_rw.261573891 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/0.spi_device_tpm_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/0.spi_device_tpm_sts_read.2261436736 |
| Short name | T4 |
| Test name | |
| Test status | |
| Simulation time | 21365635 ps |
| CPU time | 1.14 seconds |
| Started | Aug 27 06:07:35 PM UTC 24 |
| Finished | Aug 27 06:07:37 PM UTC 24 |
| Peak memory | 215868 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2261436736 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_2 6/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_sts_read.2261436736 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/0.spi_device_tpm_sts_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/0.spi_device_upload.3389995484 |
| Short name | T18 |
| Test name | |
| Test status | |
| Simulation time | 46920697143 ps |
| CPU time | 71.89 seconds |
| Started | Aug 27 06:07:54 PM UTC 24 |
| Finished | Aug 27 06:09:07 PM UTC 24 |
| Peak memory | 251560 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3389995484 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_upload.3389995484 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/0.spi_device_upload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/1.spi_device_alert_test.4113587566 |
| Short name | T91 |
| Test name | |
| Test status | |
| Simulation time | 60782768 ps |
| CPU time | 1.1 seconds |
| Started | Aug 27 06:09:58 PM UTC 24 |
| Finished | Aug 27 06:10:00 PM UTC 24 |
| Peak memory | 215684 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4113587566 -assert nopostproc +UVM_TES TNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_alert_test.4113587566 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/1.spi_device_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/1.spi_device_cfg_cmd.2846492293 |
| Short name | T56 |
| Test name | |
| Test status | |
| Simulation time | 242855877 ps |
| CPU time | 3.25 seconds |
| Started | Aug 27 06:09:27 PM UTC 24 |
| Finished | Aug 27 06:09:31 PM UTC 24 |
| Peak memory | 235040 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2846492293 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_cfg_cmd.2846492293 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/1.spi_device_cfg_cmd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/1.spi_device_csb_read.1318856621 |
| Short name | T17 |
| Test name | |
| Test status | |
| Simulation time | 19747796 ps |
| CPU time | 1.14 seconds |
| Started | Aug 27 06:08:37 PM UTC 24 |
| Finished | Aug 27 06:08:39 PM UTC 24 |
| Peak memory | 215812 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1318856621 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/sp i_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_csb_read.1318856621 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/1.spi_device_csb_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/1.spi_device_flash_all.2844977173 |
| Short name | T96 |
| Test name | |
| Test status | |
| Simulation time | 42169309378 ps |
| CPU time | 218.71 seconds |
| Started | Aug 27 06:09:45 PM UTC 24 |
| Finished | Aug 27 06:13:28 PM UTC 24 |
| Peak memory | 267856 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2844977173 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/s pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_all.2844977173 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/1.spi_device_flash_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/1.spi_device_flash_and_tpm_min_idle.4059888858 |
| Short name | T48 |
| Test name | |
| Test status | |
| Simulation time | 29619688001 ps |
| CPU time | 117.92 seconds |
| Started | Aug 27 06:09:51 PM UTC 24 |
| Finished | Aug 27 06:11:51 PM UTC 24 |
| Peak memory | 261792 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4059888858 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_26/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_and_tpm_min_idle.4059888858 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/1.spi_device_flash_and_tpm_min_idle/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/1.spi_device_flash_mode.2524172660 |
| Short name | T117 |
| Test name | |
| Test status | |
| Simulation time | 410274078 ps |
| CPU time | 10.63 seconds |
| Started | Aug 27 06:09:32 PM UTC 24 |
| Finished | Aug 27 06:09:44 PM UTC 24 |
| Peak memory | 234964 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2524172660 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/ spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_mode.2524172660 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/1.spi_device_flash_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/1.spi_device_intercept.4139426479 |
| Short name | T69 |
| Test name | |
| Test status | |
| Simulation time | 256627498 ps |
| CPU time | 7.77 seconds |
| Started | Aug 27 06:09:09 PM UTC 24 |
| Finished | Aug 27 06:09:17 PM UTC 24 |
| Peak memory | 234904 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4139426479 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/s pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_intercept.4139426479 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/1.spi_device_intercept/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/1.spi_device_pass_addr_payload_swap.2708296951 |
| Short name | T19 |
| Test name | |
| Test status | |
| Simulation time | 1321124539 ps |
| CPU time | 3.44 seconds |
| Started | Aug 27 06:09:07 PM UTC 24 |
| Finished | Aug 27 06:09:12 PM UTC 24 |
| Peak memory | 234964 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2708296951 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_26/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_pass_addr_payload_swap.2708296951 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/1.spi_device_pass_addr_payload_swap/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/1.spi_device_pass_cmd_filtering.1332680058 |
| Short name | T53 |
| Test name | |
| Test status | |
| Simulation time | 7600096046 ps |
| CPU time | 24.84 seconds |
| Started | Aug 27 06:09:00 PM UTC 24 |
| Finished | Aug 27 06:09:26 PM UTC 24 |
| Peak memory | 245324 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1332680058 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_08_26/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_pass_cmd_filtering.1332680058 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/1.spi_device_pass_cmd_filtering/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/1.spi_device_sec_cm.1571634900 |
| Short name | T20 |
| Test name | |
| Test status | |
| Simulation time | 84107355 ps |
| CPU time | 1.79 seconds |
| Started | Aug 27 06:09:54 PM UTC 24 |
| Finished | Aug 27 06:09:57 PM UTC 24 |
| Peak memory | 257916 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1571634900 -assert nopostproc +UVM_TEST NAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_sec_cm.1571634900 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/1.spi_device_sec_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/1.spi_device_tpm_rw.1369753078 |
| Short name | T26 |
| Test name | |
| Test status | |
| Simulation time | 42262640 ps |
| CPU time | 1.2 seconds |
| Started | Aug 27 06:08:57 PM UTC 24 |
| Finished | Aug 27 06:09:00 PM UTC 24 |
| Peak memory | 215864 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1369753078 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_rw.1369753078 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/1.spi_device_tpm_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/1.spi_device_tpm_sts_read.738391918 |
| Short name | T25 |
| Test name | |
| Test status | |
| Simulation time | 217662045 ps |
| CPU time | 1.4 seconds |
| Started | Aug 27 06:08:54 PM UTC 24 |
| Finished | Aug 27 06:08:57 PM UTC 24 |
| Peak memory | 215864 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=738391918 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26 /spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_sts_read.738391918 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/1.spi_device_tpm_sts_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/1.spi_device_upload.2961724824 |
| Short name | T54 |
| Test name | |
| Test status | |
| Simulation time | 7761516533 ps |
| CPU time | 30.25 seconds |
| Started | Aug 27 06:09:18 PM UTC 24 |
| Finished | Aug 27 06:09:49 PM UTC 24 |
| Peak memory | 249556 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2961724824 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_upload.2961724824 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/1.spi_device_upload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/10.spi_device_alert_test.3447091703 |
| Short name | T414 |
| Test name | |
| Test status | |
| Simulation time | 20359119 ps |
| CPU time | 1.1 seconds |
| Started | Aug 27 06:14:49 PM UTC 24 |
| Finished | Aug 27 06:14:51 PM UTC 24 |
| Peak memory | 215744 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3447091703 -assert nopostproc +UVM_TES TNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_alert_test.3447091703 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/10.spi_device_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/10.spi_device_cfg_cmd.379149103 |
| Short name | T316 |
| Test name | |
| Test status | |
| Simulation time | 3493715059 ps |
| CPU time | 21.68 seconds |
| Started | Aug 27 06:14:34 PM UTC 24 |
| Finished | Aug 27 06:14:57 PM UTC 24 |
| Peak memory | 245344 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=379149103 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_cfg_cmd.379149103 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/10.spi_device_cfg_cmd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/10.spi_device_csb_read.4077261309 |
| Short name | T183 |
| Test name | |
| Test status | |
| Simulation time | 52705059 ps |
| CPU time | 1.17 seconds |
| Started | Aug 27 06:14:18 PM UTC 24 |
| Finished | Aug 27 06:14:20 PM UTC 24 |
| Peak memory | 215520 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4077261309 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/sp i_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_csb_read.4077261309 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/10.spi_device_csb_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/10.spi_device_flash_all.3896734750 |
| Short name | T80 |
| Test name | |
| Test status | |
| Simulation time | 33213842865 ps |
| CPU time | 70.13 seconds |
| Started | Aug 27 06:14:43 PM UTC 24 |
| Finished | Aug 27 06:15:55 PM UTC 24 |
| Peak memory | 265816 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3896734750 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/s pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_all.3896734750 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/10.spi_device_flash_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/10.spi_device_flash_and_tpm_min_idle.362151514 |
| Short name | T308 |
| Test name | |
| Test status | |
| Simulation time | 116529377613 ps |
| CPU time | 271.76 seconds |
| Started | Aug 27 06:14:45 PM UTC 24 |
| Finished | Aug 27 06:19:21 PM UTC 24 |
| Peak memory | 267988 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=362151514 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_26/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_and_tpm_min_idle.362151514 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/10.spi_device_flash_and_tpm_min_idle/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/10.spi_device_flash_mode.2859039032 |
| Short name | T267 |
| Test name | |
| Test status | |
| Simulation time | 36254186 ps |
| CPU time | 3.29 seconds |
| Started | Aug 27 06:14:38 PM UTC 24 |
| Finished | Aug 27 06:14:42 PM UTC 24 |
| Peak memory | 245144 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2859039032 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/ spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_mode.2859039032 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/10.spi_device_flash_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/10.spi_device_flash_mode_ignore_cmds.2709067205 |
| Short name | T209 |
| Test name | |
| Test status | |
| Simulation time | 743612359 ps |
| CPU time | 24 seconds |
| Started | Aug 27 06:14:38 PM UTC 24 |
| Finished | Aug 27 06:15:03 PM UTC 24 |
| Peak memory | 234904 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2709067205 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_26/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_mode_ignore_cmds.2709067205 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/10.spi_device_flash_mode_ignore_cmds/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/10.spi_device_intercept.4103455032 |
| Short name | T257 |
| Test name | |
| Test status | |
| Simulation time | 1991411940 ps |
| CPU time | 26.66 seconds |
| Started | Aug 27 06:14:24 PM UTC 24 |
| Finished | Aug 27 06:14:52 PM UTC 24 |
| Peak memory | 234904 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4103455032 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/s pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_intercept.4103455032 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/10.spi_device_intercept/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/10.spi_device_mailbox.1736351827 |
| Short name | T259 |
| Test name | |
| Test status | |
| Simulation time | 281151313 ps |
| CPU time | 8.57 seconds |
| Started | Aug 27 06:14:27 PM UTC 24 |
| Finished | Aug 27 06:14:37 PM UTC 24 |
| Peak memory | 245156 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1736351827 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_mailbox.1736351827 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/10.spi_device_mailbox/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/10.spi_device_pass_addr_payload_swap.4251627251 |
| Short name | T303 |
| Test name | |
| Test status | |
| Simulation time | 4219632379 ps |
| CPU time | 8.46 seconds |
| Started | Aug 27 06:14:23 PM UTC 24 |
| Finished | Aug 27 06:14:33 PM UTC 24 |
| Peak memory | 234968 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4251627251 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_26/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_pass_addr_payload_swap.4251627251 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/10.spi_device_pass_addr_payload_swap/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/10.spi_device_pass_cmd_filtering.568308531 |
| Short name | T282 |
| Test name | |
| Test status | |
| Simulation time | 20897671744 ps |
| CPU time | 45.51 seconds |
| Started | Aug 27 06:14:22 PM UTC 24 |
| Finished | Aug 27 06:15:09 PM UTC 24 |
| Peak memory | 261712 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=568308531 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _08_26/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_pass_cmd_filtering.568308531 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/10.spi_device_pass_cmd_filtering/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/10.spi_device_read_buffer_direct.3851837457 |
| Short name | T415 |
| Test name | |
| Test status | |
| Simulation time | 8417718077 ps |
| CPU time | 8.33 seconds |
| Started | Aug 27 06:14:43 PM UTC 24 |
| Finished | Aug 27 06:14:52 PM UTC 24 |
| Peak memory | 233496 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3851837457 -assert nopostproc +UVM_TESTNAME=spi_device _base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_read_buffer_direct.3851837457 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/10.spi_device_read_buffer_direct/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/10.spi_device_tpm_all.4047296179 |
| Short name | T373 |
| Test name | |
| Test status | |
| Simulation time | 6885525527 ps |
| CPU time | 25.53 seconds |
| Started | Aug 27 06:14:21 PM UTC 24 |
| Finished | Aug 27 06:14:48 PM UTC 24 |
| Peak memory | 227692 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4047296179 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_all.4047296179 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/10.spi_device_tpm_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/10.spi_device_tpm_read_hw_reg.126012601 |
| Short name | T413 |
| Test name | |
| Test status | |
| Simulation time | 4919737600 ps |
| CPU time | 14.74 seconds |
| Started | Aug 27 06:14:21 PM UTC 24 |
| Finished | Aug 27 06:14:37 PM UTC 24 |
| Peak memory | 227620 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=126012601 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08 _26/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_read_hw_reg.126012601 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/10.spi_device_tpm_read_hw_reg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/10.spi_device_tpm_rw.2895253163 |
| Short name | T189 |
| Test name | |
| Test status | |
| Simulation time | 82301049 ps |
| CPU time | 3.64 seconds |
| Started | Aug 27 06:14:22 PM UTC 24 |
| Finished | Aug 27 06:14:27 PM UTC 24 |
| Peak memory | 227484 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2895253163 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_rw.2895253163 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/10.spi_device_tpm_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/10.spi_device_tpm_sts_read.408157339 |
| Short name | T187 |
| Test name | |
| Test status | |
| Simulation time | 178923744 ps |
| CPU time | 1.1 seconds |
| Started | Aug 27 06:14:21 PM UTC 24 |
| Finished | Aug 27 06:14:23 PM UTC 24 |
| Peak memory | 215868 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=408157339 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26 /spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_sts_read.408157339 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/10.spi_device_tpm_sts_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/10.spi_device_upload.1035548883 |
| Short name | T230 |
| Test name | |
| Test status | |
| Simulation time | 6506262351 ps |
| CPU time | 12.66 seconds |
| Started | Aug 27 06:14:28 PM UTC 24 |
| Finished | Aug 27 06:14:42 PM UTC 24 |
| Peak memory | 235032 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1035548883 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_upload.1035548883 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/10.spi_device_upload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/11.spi_device_alert_test.1446556690 |
| Short name | T421 |
| Test name | |
| Test status | |
| Simulation time | 96359550 ps |
| CPU time | 1.08 seconds |
| Started | Aug 27 06:15:13 PM UTC 24 |
| Finished | Aug 27 06:15:16 PM UTC 24 |
| Peak memory | 215804 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1446556690 -assert nopostproc +UVM_TES TNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_alert_test.1446556690 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/11.spi_device_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/11.spi_device_cfg_cmd.861491727 |
| Short name | T324 |
| Test name | |
| Test status | |
| Simulation time | 695253176 ps |
| CPU time | 7.24 seconds |
| Started | Aug 27 06:15:04 PM UTC 24 |
| Finished | Aug 27 06:15:12 PM UTC 24 |
| Peak memory | 235024 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=861491727 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_cfg_cmd.861491727 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/11.spi_device_cfg_cmd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/11.spi_device_csb_read.3737420637 |
| Short name | T416 |
| Test name | |
| Test status | |
| Simulation time | 49239614 ps |
| CPU time | 0.94 seconds |
| Started | Aug 27 06:14:51 PM UTC 24 |
| Finished | Aug 27 06:14:53 PM UTC 24 |
| Peak memory | 215580 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3737420637 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/sp i_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_csb_read.3737420637 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/11.spi_device_csb_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/11.spi_device_flash_all.2097423181 |
| Short name | T213 |
| Test name | |
| Test status | |
| Simulation time | 5331908748 ps |
| CPU time | 30.78 seconds |
| Started | Aug 27 06:15:09 PM UTC 24 |
| Finished | Aug 27 06:15:41 PM UTC 24 |
| Peak memory | 261720 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2097423181 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/s pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_all.2097423181 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/11.spi_device_flash_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/11.spi_device_flash_and_tpm.1216552011 |
| Short name | T250 |
| Test name | |
| Test status | |
| Simulation time | 213544879021 ps |
| CPU time | 172.51 seconds |
| Started | Aug 27 06:15:10 PM UTC 24 |
| Finished | Aug 27 06:18:06 PM UTC 24 |
| Peak memory | 265448 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1216552011 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_ 26/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_and_tpm.1216552011 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/11.spi_device_flash_and_tpm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/11.spi_device_flash_and_tpm_min_idle.1359593784 |
| Short name | T367 |
| Test name | |
| Test status | |
| Simulation time | 870544344 ps |
| CPU time | 6.28 seconds |
| Started | Aug 27 06:15:10 PM UTC 24 |
| Finished | Aug 27 06:15:18 PM UTC 24 |
| Peak memory | 229112 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1359593784 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_26/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_and_tpm_min_idle.1359593784 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/11.spi_device_flash_and_tpm_min_idle/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/11.spi_device_flash_mode.1354848360 |
| Short name | T428 |
| Test name | |
| Test status | |
| Simulation time | 1385313594 ps |
| CPU time | 23.85 seconds |
| Started | Aug 27 06:15:09 PM UTC 24 |
| Finished | Aug 27 06:15:34 PM UTC 24 |
| Peak memory | 234936 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1354848360 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/ spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_mode.1354848360 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/11.spi_device_flash_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/11.spi_device_intercept.1631048013 |
| Short name | T238 |
| Test name | |
| Test status | |
| Simulation time | 220090153 ps |
| CPU time | 8.35 seconds |
| Started | Aug 27 06:14:58 PM UTC 24 |
| Finished | Aug 27 06:15:08 PM UTC 24 |
| Peak memory | 245220 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1631048013 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/s pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_intercept.1631048013 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/11.spi_device_intercept/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/11.spi_device_mailbox.1527064924 |
| Short name | T291 |
| Test name | |
| Test status | |
| Simulation time | 528599154 ps |
| CPU time | 4.67 seconds |
| Started | Aug 27 06:15:02 PM UTC 24 |
| Finished | Aug 27 06:15:08 PM UTC 24 |
| Peak memory | 245204 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1527064924 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_mailbox.1527064924 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/11.spi_device_mailbox/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/11.spi_device_pass_addr_payload_swap.558496219 |
| Short name | T298 |
| Test name | |
| Test status | |
| Simulation time | 7581130039 ps |
| CPU time | 15.88 seconds |
| Started | Aug 27 06:14:57 PM UTC 24 |
| Finished | Aug 27 06:15:14 PM UTC 24 |
| Peak memory | 251476 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=558496219 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_26/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_pass_addr_payload_swap.558496219 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/11.spi_device_pass_addr_payload_swap/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/11.spi_device_pass_cmd_filtering.2170073903 |
| Short name | T258 |
| Test name | |
| Test status | |
| Simulation time | 2800566032 ps |
| CPU time | 12.42 seconds |
| Started | Aug 27 06:14:56 PM UTC 24 |
| Finished | Aug 27 06:15:10 PM UTC 24 |
| Peak memory | 245344 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2170073903 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_08_26/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_pass_cmd_filtering.2170073903 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/11.spi_device_pass_cmd_filtering/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/11.spi_device_read_buffer_direct.1361580828 |
| Short name | T420 |
| Test name | |
| Test status | |
| Simulation time | 105662301 ps |
| CPU time | 4.98 seconds |
| Started | Aug 27 06:15:09 PM UTC 24 |
| Finished | Aug 27 06:15:15 PM UTC 24 |
| Peak memory | 233600 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1361580828 -assert nopostproc +UVM_TESTNAME=spi_device _base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_read_buffer_direct.1361580828 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/11.spi_device_read_buffer_direct/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/11.spi_device_tpm_all.2540073546 |
| Short name | T362 |
| Test name | |
| Test status | |
| Simulation time | 16087826317 ps |
| CPU time | 27.04 seconds |
| Started | Aug 27 06:14:53 PM UTC 24 |
| Finished | Aug 27 06:15:21 PM UTC 24 |
| Peak memory | 227740 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2540073546 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_all.2540073546 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/11.spi_device_tpm_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/11.spi_device_tpm_read_hw_reg.1235374899 |
| Short name | T419 |
| Test name | |
| Test status | |
| Simulation time | 2603211397 ps |
| CPU time | 7.91 seconds |
| Started | Aug 27 06:14:53 PM UTC 24 |
| Finished | Aug 27 06:15:02 PM UTC 24 |
| Peak memory | 227604 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1235374899 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_26/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_read_hw_reg.1235374899 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/11.spi_device_tpm_read_hw_reg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/11.spi_device_tpm_rw.249330617 |
| Short name | T418 |
| Test name | |
| Test status | |
| Simulation time | 219600169 ps |
| CPU time | 2.17 seconds |
| Started | Aug 27 06:14:54 PM UTC 24 |
| Finished | Aug 27 06:14:57 PM UTC 24 |
| Peak memory | 227400 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=249330617 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/spi_d evice_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_rw.249330617 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/11.spi_device_tpm_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/11.spi_device_tpm_sts_read.719809241 |
| Short name | T417 |
| Test name | |
| Test status | |
| Simulation time | 117139873 ps |
| CPU time | 1.26 seconds |
| Started | Aug 27 06:14:53 PM UTC 24 |
| Finished | Aug 27 06:14:55 PM UTC 24 |
| Peak memory | 215868 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=719809241 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26 /spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_sts_read.719809241 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/11.spi_device_tpm_sts_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/11.spi_device_upload.4209178722 |
| Short name | T271 |
| Test name | |
| Test status | |
| Simulation time | 54906397 ps |
| CPU time | 3.96 seconds |
| Started | Aug 27 06:15:02 PM UTC 24 |
| Finished | Aug 27 06:15:07 PM UTC 24 |
| Peak memory | 245144 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4209178722 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_upload.4209178722 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/11.spi_device_upload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/12.spi_device_alert_test.1529092381 |
| Short name | T429 |
| Test name | |
| Test status | |
| Simulation time | 35273226 ps |
| CPU time | 1.11 seconds |
| Started | Aug 27 06:15:34 PM UTC 24 |
| Finished | Aug 27 06:15:36 PM UTC 24 |
| Peak memory | 215744 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1529092381 -assert nopostproc +UVM_TES TNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_alert_test.1529092381 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/12.spi_device_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/12.spi_device_cfg_cmd.3267923296 |
| Short name | T295 |
| Test name | |
| Test status | |
| Simulation time | 3368666780 ps |
| CPU time | 13.91 seconds |
| Started | Aug 27 06:15:23 PM UTC 24 |
| Finished | Aug 27 06:15:38 PM UTC 24 |
| Peak memory | 234748 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3267923296 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_cfg_cmd.3267923296 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/12.spi_device_cfg_cmd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/12.spi_device_csb_read.3396704932 |
| Short name | T422 |
| Test name | |
| Test status | |
| Simulation time | 67075825 ps |
| CPU time | 1.14 seconds |
| Started | Aug 27 06:15:15 PM UTC 24 |
| Finished | Aug 27 06:15:17 PM UTC 24 |
| Peak memory | 215812 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3396704932 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/sp i_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_csb_read.3396704932 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/12.spi_device_csb_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/12.spi_device_flash_all.1781995785 |
| Short name | T217 |
| Test name | |
| Test status | |
| Simulation time | 79972983958 ps |
| CPU time | 826.31 seconds |
| Started | Aug 27 06:15:29 PM UTC 24 |
| Finished | Aug 27 06:29:26 PM UTC 24 |
| Peak memory | 284236 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1781995785 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/s pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_all.1781995785 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/12.spi_device_flash_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/12.spi_device_flash_and_tpm.2900460099 |
| Short name | T38 |
| Test name | |
| Test status | |
| Simulation time | 305138942511 ps |
| CPU time | 685.8 seconds |
| Started | Aug 27 06:15:29 PM UTC 24 |
| Finished | Aug 27 06:27:03 PM UTC 24 |
| Peak memory | 278124 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2900460099 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_ 26/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_and_tpm.2900460099 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/12.spi_device_flash_and_tpm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/12.spi_device_flash_and_tpm_min_idle.638681379 |
| Short name | T376 |
| Test name | |
| Test status | |
| Simulation time | 32284022313 ps |
| CPU time | 63.99 seconds |
| Started | Aug 27 06:15:30 PM UTC 24 |
| Finished | Aug 27 06:16:36 PM UTC 24 |
| Peak memory | 251636 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=638681379 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_26/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_and_tpm_min_idle.638681379 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/12.spi_device_flash_and_tpm_min_idle/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/12.spi_device_flash_mode.1269602873 |
| Short name | T427 |
| Test name | |
| Test status | |
| Simulation time | 185424682 ps |
| CPU time | 7.65 seconds |
| Started | Aug 27 06:15:23 PM UTC 24 |
| Finished | Aug 27 06:15:31 PM UTC 24 |
| Peak memory | 245196 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1269602873 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/ spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_mode.1269602873 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/12.spi_device_flash_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/12.spi_device_flash_mode_ignore_cmds.426087326 |
| Short name | T252 |
| Test name | |
| Test status | |
| Simulation time | 57851501606 ps |
| CPU time | 96.32 seconds |
| Started | Aug 27 06:15:25 PM UTC 24 |
| Finished | Aug 27 06:17:03 PM UTC 24 |
| Peak memory | 267856 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=426087326 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_26/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_mode_ignore_cmds.426087326 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/12.spi_device_flash_mode_ignore_cmds/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/12.spi_device_intercept.1972955205 |
| Short name | T261 |
| Test name | |
| Test status | |
| Simulation time | 209535126 ps |
| CPU time | 5.77 seconds |
| Started | Aug 27 06:15:21 PM UTC 24 |
| Finished | Aug 27 06:15:28 PM UTC 24 |
| Peak memory | 245220 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1972955205 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/s pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_intercept.1972955205 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/12.spi_device_intercept/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/12.spi_device_mailbox.2248515358 |
| Short name | T222 |
| Test name | |
| Test status | |
| Simulation time | 6814243067 ps |
| CPU time | 21.57 seconds |
| Started | Aug 27 06:15:21 PM UTC 24 |
| Finished | Aug 27 06:15:44 PM UTC 24 |
| Peak memory | 245288 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2248515358 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_mailbox.2248515358 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/12.spi_device_mailbox/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/12.spi_device_pass_addr_payload_swap.3370902501 |
| Short name | T307 |
| Test name | |
| Test status | |
| Simulation time | 7204828836 ps |
| CPU time | 9.18 seconds |
| Started | Aug 27 06:15:19 PM UTC 24 |
| Finished | Aug 27 06:15:29 PM UTC 24 |
| Peak memory | 245272 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3370902501 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_26/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_pass_addr_payload_swap.3370902501 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/12.spi_device_pass_addr_payload_swap/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/12.spi_device_pass_cmd_filtering.237100263 |
| Short name | T280 |
| Test name | |
| Test status | |
| Simulation time | 2265665730 ps |
| CPU time | 6.7 seconds |
| Started | Aug 27 06:15:19 PM UTC 24 |
| Finished | Aug 27 06:15:27 PM UTC 24 |
| Peak memory | 235060 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=237100263 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _08_26/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_pass_cmd_filtering.237100263 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/12.spi_device_pass_cmd_filtering/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/12.spi_device_read_buffer_direct.1418539708 |
| Short name | T434 |
| Test name | |
| Test status | |
| Simulation time | 1239762818 ps |
| CPU time | 18.05 seconds |
| Started | Aug 27 06:15:28 PM UTC 24 |
| Finished | Aug 27 06:15:47 PM UTC 24 |
| Peak memory | 231324 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1418539708 -assert nopostproc +UVM_TESTNAME=spi_device _base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_read_buffer_direct.1418539708 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/12.spi_device_read_buffer_direct/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/12.spi_device_stress_all.3869667703 |
| Short name | T366 |
| Test name | |
| Test status | |
| Simulation time | 25220400503 ps |
| CPU time | 240.28 seconds |
| Started | Aug 27 06:15:32 PM UTC 24 |
| Finished | Aug 27 06:19:36 PM UTC 24 |
| Peak memory | 265852 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3869667703 -assert nopostproc +UVM_ TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_stress_all.3869667703 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/12.spi_device_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/12.spi_device_tpm_all.1071595229 |
| Short name | T372 |
| Test name | |
| Test status | |
| Simulation time | 16035941605 ps |
| CPU time | 34.34 seconds |
| Started | Aug 27 06:15:18 PM UTC 24 |
| Finished | Aug 27 06:15:54 PM UTC 24 |
| Peak memory | 227584 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1071595229 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_all.1071595229 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/12.spi_device_tpm_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/12.spi_device_tpm_read_hw_reg.1318618320 |
| Short name | T425 |
| Test name | |
| Test status | |
| Simulation time | 1370412504 ps |
| CPU time | 5.88 seconds |
| Started | Aug 27 06:15:17 PM UTC 24 |
| Finished | Aug 27 06:15:24 PM UTC 24 |
| Peak memory | 227404 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1318618320 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_26/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_read_hw_reg.1318618320 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/12.spi_device_tpm_read_hw_reg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/12.spi_device_tpm_rw.3010877976 |
| Short name | T424 |
| Test name | |
| Test status | |
| Simulation time | 105417517 ps |
| CPU time | 1.54 seconds |
| Started | Aug 27 06:15:18 PM UTC 24 |
| Finished | Aug 27 06:15:21 PM UTC 24 |
| Peak memory | 216452 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3010877976 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_rw.3010877976 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/12.spi_device_tpm_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/12.spi_device_tpm_sts_read.2098603646 |
| Short name | T423 |
| Test name | |
| Test status | |
| Simulation time | 121401515 ps |
| CPU time | 1.25 seconds |
| Started | Aug 27 06:15:18 PM UTC 24 |
| Finished | Aug 27 06:15:20 PM UTC 24 |
| Peak memory | 215872 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2098603646 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_2 6/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_sts_read.2098603646 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/12.spi_device_tpm_sts_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/12.spi_device_upload.3451766584 |
| Short name | T426 |
| Test name | |
| Test status | |
| Simulation time | 717840282 ps |
| CPU time | 4.18 seconds |
| Started | Aug 27 06:15:23 PM UTC 24 |
| Finished | Aug 27 06:15:28 PM UTC 24 |
| Peak memory | 244972 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3451766584 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_upload.3451766584 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/12.spi_device_upload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/13.spi_device_alert_test.3799875514 |
| Short name | T86 |
| Test name | |
| Test status | |
| Simulation time | 11390346 ps |
| CPU time | 1.07 seconds |
| Started | Aug 27 06:15:58 PM UTC 24 |
| Finished | Aug 27 06:16:00 PM UTC 24 |
| Peak memory | 215744 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3799875514 -assert nopostproc +UVM_TES TNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_alert_test.3799875514 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/13.spi_device_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/13.spi_device_cfg_cmd.107850105 |
| Short name | T79 |
| Test name | |
| Test status | |
| Simulation time | 74940657 ps |
| CPU time | 4.71 seconds |
| Started | Aug 27 06:15:48 PM UTC 24 |
| Finished | Aug 27 06:15:54 PM UTC 24 |
| Peak memory | 245284 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=107850105 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_cfg_cmd.107850105 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/13.spi_device_cfg_cmd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/13.spi_device_csb_read.1830617639 |
| Short name | T430 |
| Test name | |
| Test status | |
| Simulation time | 24804062 ps |
| CPU time | 1.22 seconds |
| Started | Aug 27 06:15:35 PM UTC 24 |
| Finished | Aug 27 06:15:38 PM UTC 24 |
| Peak memory | 215520 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1830617639 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/sp i_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_csb_read.1830617639 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/13.spi_device_csb_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/13.spi_device_flash_all.2020466947 |
| Short name | T218 |
| Test name | |
| Test status | |
| Simulation time | 66271397028 ps |
| CPU time | 222.19 seconds |
| Started | Aug 27 06:15:55 PM UTC 24 |
| Finished | Aug 27 06:19:40 PM UTC 24 |
| Peak memory | 267852 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2020466947 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/s pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_all.2020466947 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/13.spi_device_flash_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/13.spi_device_flash_and_tpm.3050519773 |
| Short name | T155 |
| Test name | |
| Test status | |
| Simulation time | 6025555316 ps |
| CPU time | 57.55 seconds |
| Started | Aug 27 06:15:55 PM UTC 24 |
| Finished | Aug 27 06:16:54 PM UTC 24 |
| Peak memory | 267824 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3050519773 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_ 26/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_and_tpm.3050519773 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/13.spi_device_flash_and_tpm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/13.spi_device_flash_mode.3649831619 |
| Short name | T84 |
| Test name | |
| Test status | |
| Simulation time | 183052578 ps |
| CPU time | 5.07 seconds |
| Started | Aug 27 06:15:51 PM UTC 24 |
| Finished | Aug 27 06:15:58 PM UTC 24 |
| Peak memory | 245200 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3649831619 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/ spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_mode.3649831619 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/13.spi_device_flash_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/13.spi_device_flash_mode_ignore_cmds.3083120119 |
| Short name | T241 |
| Test name | |
| Test status | |
| Simulation time | 55932299625 ps |
| CPU time | 412.73 seconds |
| Started | Aug 27 06:15:53 PM UTC 24 |
| Finished | Aug 27 06:22:50 PM UTC 24 |
| Peak memory | 278160 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3083120119 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_26/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_mode_ignore_cmds.3083120119 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/13.spi_device_flash_mode_ignore_cmds/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/13.spi_device_intercept.2425360268 |
| Short name | T242 |
| Test name | |
| Test status | |
| Simulation time | 95939420 ps |
| CPU time | 4.53 seconds |
| Started | Aug 27 06:15:45 PM UTC 24 |
| Finished | Aug 27 06:15:51 PM UTC 24 |
| Peak memory | 234964 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2425360268 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/s pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_intercept.2425360268 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/13.spi_device_intercept/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/13.spi_device_mailbox.3460159033 |
| Short name | T311 |
| Test name | |
| Test status | |
| Simulation time | 822567107 ps |
| CPU time | 16.66 seconds |
| Started | Aug 27 06:15:48 PM UTC 24 |
| Finished | Aug 27 06:16:06 PM UTC 24 |
| Peak memory | 245204 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3460159033 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_mailbox.3460159033 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/13.spi_device_mailbox/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/13.spi_device_pass_addr_payload_swap.3297966792 |
| Short name | T231 |
| Test name | |
| Test status | |
| Simulation time | 3585627710 ps |
| CPU time | 22.69 seconds |
| Started | Aug 27 06:15:44 PM UTC 24 |
| Finished | Aug 27 06:16:08 PM UTC 24 |
| Peak memory | 245328 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3297966792 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_26/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_pass_addr_payload_swap.3297966792 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/13.spi_device_pass_addr_payload_swap/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/13.spi_device_pass_cmd_filtering.2599637465 |
| Short name | T284 |
| Test name | |
| Test status | |
| Simulation time | 2548304464 ps |
| CPU time | 8.41 seconds |
| Started | Aug 27 06:15:42 PM UTC 24 |
| Finished | Aug 27 06:15:52 PM UTC 24 |
| Peak memory | 235088 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2599637465 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_08_26/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_pass_cmd_filtering.2599637465 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/13.spi_device_pass_cmd_filtering/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/13.spi_device_read_buffer_direct.2901384604 |
| Short name | T437 |
| Test name | |
| Test status | |
| Simulation time | 15590871687 ps |
| CPU time | 13.48 seconds |
| Started | Aug 27 06:15:54 PM UTC 24 |
| Finished | Aug 27 06:16:08 PM UTC 24 |
| Peak memory | 233704 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2901384604 -assert nopostproc +UVM_TESTNAME=spi_device _base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_read_buffer_direct.2901384604 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/13.spi_device_read_buffer_direct/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/13.spi_device_stress_all.2802774131 |
| Short name | T536 |
| Test name | |
| Test status | |
| Simulation time | 241587761763 ps |
| CPU time | 255.94 seconds |
| Started | Aug 27 06:15:56 PM UTC 24 |
| Finished | Aug 27 06:20:16 PM UTC 24 |
| Peak memory | 265860 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2802774131 -assert nopostproc +UVM_ TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_stress_all.2802774131 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/13.spi_device_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/13.spi_device_tpm_all.1631985844 |
| Short name | T83 |
| Test name | |
| Test status | |
| Simulation time | 720678137 ps |
| CPU time | 17.6 seconds |
| Started | Aug 27 06:15:39 PM UTC 24 |
| Finished | Aug 27 06:15:57 PM UTC 24 |
| Peak memory | 227424 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1631985844 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_all.1631985844 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/13.spi_device_tpm_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/13.spi_device_tpm_read_hw_reg.1402407708 |
| Short name | T431 |
| Test name | |
| Test status | |
| Simulation time | 25541531 ps |
| CPU time | 1.08 seconds |
| Started | Aug 27 06:15:39 PM UTC 24 |
| Finished | Aug 27 06:15:41 PM UTC 24 |
| Peak memory | 215804 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1402407708 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_26/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_read_hw_reg.1402407708 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/13.spi_device_tpm_read_hw_reg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/13.spi_device_tpm_rw.2259068255 |
| Short name | T433 |
| Test name | |
| Test status | |
| Simulation time | 1423825501 ps |
| CPU time | 3.72 seconds |
| Started | Aug 27 06:15:42 PM UTC 24 |
| Finished | Aug 27 06:15:47 PM UTC 24 |
| Peak memory | 227424 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2259068255 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_rw.2259068255 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/13.spi_device_tpm_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/13.spi_device_tpm_sts_read.1351692527 |
| Short name | T432 |
| Test name | |
| Test status | |
| Simulation time | 58130837 ps |
| CPU time | 1.13 seconds |
| Started | Aug 27 06:15:41 PM UTC 24 |
| Finished | Aug 27 06:15:43 PM UTC 24 |
| Peak memory | 215872 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1351692527 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_2 6/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_sts_read.1351692527 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/13.spi_device_tpm_sts_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/13.spi_device_upload.2144845034 |
| Short name | T81 |
| Test name | |
| Test status | |
| Simulation time | 551375733 ps |
| CPU time | 5.47 seconds |
| Started | Aug 27 06:15:48 PM UTC 24 |
| Finished | Aug 27 06:15:55 PM UTC 24 |
| Peak memory | 234920 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2144845034 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_upload.2144845034 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/13.spi_device_upload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/14.spi_device_alert_test.3341590028 |
| Short name | T441 |
| Test name | |
| Test status | |
| Simulation time | 47941319 ps |
| CPU time | 1.17 seconds |
| Started | Aug 27 06:16:17 PM UTC 24 |
| Finished | Aug 27 06:16:19 PM UTC 24 |
| Peak memory | 215744 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3341590028 -assert nopostproc +UVM_TES TNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_alert_test.3341590028 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/14.spi_device_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/14.spi_device_cfg_cmd.89296270 |
| Short name | T292 |
| Test name | |
| Test status | |
| Simulation time | 464260374 ps |
| CPU time | 3.87 seconds |
| Started | Aug 27 06:16:09 PM UTC 24 |
| Finished | Aug 27 06:16:14 PM UTC 24 |
| Peak memory | 234956 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=89296270 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/spi_d evice_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_cfg_cmd.89296270 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/14.spi_device_cfg_cmd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/14.spi_device_csb_read.3744202300 |
| Short name | T87 |
| Test name | |
| Test status | |
| Simulation time | 51624664 ps |
| CPU time | 1.14 seconds |
| Started | Aug 27 06:15:58 PM UTC 24 |
| Finished | Aug 27 06:16:01 PM UTC 24 |
| Peak memory | 215812 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3744202300 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/sp i_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_csb_read.3744202300 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/14.spi_device_csb_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/14.spi_device_flash_all.1350588130 |
| Short name | T300 |
| Test name | |
| Test status | |
| Simulation time | 43619835527 ps |
| CPU time | 374.42 seconds |
| Started | Aug 27 06:16:12 PM UTC 24 |
| Finished | Aug 27 06:22:31 PM UTC 24 |
| Peak memory | 261724 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1350588130 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/s pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_all.1350588130 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/14.spi_device_flash_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/14.spi_device_flash_and_tpm.3434038091 |
| Short name | T507 |
| Test name | |
| Test status | |
| Simulation time | 87853586196 ps |
| CPU time | 196.47 seconds |
| Started | Aug 27 06:16:13 PM UTC 24 |
| Finished | Aug 27 06:19:33 PM UTC 24 |
| Peak memory | 278144 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3434038091 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_ 26/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_and_tpm.3434038091 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/14.spi_device_flash_and_tpm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/14.spi_device_flash_and_tpm_min_idle.17614448 |
| Short name | T570 |
| Test name | |
| Test status | |
| Simulation time | 178386292394 ps |
| CPU time | 300.39 seconds |
| Started | Aug 27 06:16:14 PM UTC 24 |
| Finished | Aug 27 06:21:19 PM UTC 24 |
| Peak memory | 268068 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=17614448 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_26/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_and_tpm_min_idle.17614448 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/14.spi_device_flash_and_tpm_min_idle/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/14.spi_device_flash_mode.4045226230 |
| Short name | T440 |
| Test name | |
| Test status | |
| Simulation time | 31236569 ps |
| CPU time | 3.22 seconds |
| Started | Aug 27 06:16:09 PM UTC 24 |
| Finished | Aug 27 06:16:13 PM UTC 24 |
| Peak memory | 234964 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4045226230 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/ spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_mode.4045226230 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/14.spi_device_flash_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/14.spi_device_flash_mode_ignore_cmds.2670952116 |
| Short name | T154 |
| Test name | |
| Test status | |
| Simulation time | 12316186297 ps |
| CPU time | 39.91 seconds |
| Started | Aug 27 06:16:10 PM UTC 24 |
| Finished | Aug 27 06:16:52 PM UTC 24 |
| Peak memory | 261844 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2670952116 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_26/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_mode_ignore_cmds.2670952116 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/14.spi_device_flash_mode_ignore_cmds/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/14.spi_device_intercept.4136833840 |
| Short name | T320 |
| Test name | |
| Test status | |
| Simulation time | 1914038204 ps |
| CPU time | 16.85 seconds |
| Started | Aug 27 06:16:05 PM UTC 24 |
| Finished | Aug 27 06:16:23 PM UTC 24 |
| Peak memory | 245200 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4136833840 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/s pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_intercept.4136833840 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/14.spi_device_intercept/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/14.spi_device_mailbox.1365662667 |
| Short name | T439 |
| Test name | |
| Test status | |
| Simulation time | 215614904 ps |
| CPU time | 3.57 seconds |
| Started | Aug 27 06:16:06 PM UTC 24 |
| Finished | Aug 27 06:16:10 PM UTC 24 |
| Peak memory | 245220 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1365662667 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_mailbox.1365662667 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/14.spi_device_mailbox/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/14.spi_device_pass_addr_payload_swap.609934917 |
| Short name | T305 |
| Test name | |
| Test status | |
| Simulation time | 35248269752 ps |
| CPU time | 28.75 seconds |
| Started | Aug 27 06:16:05 PM UTC 24 |
| Finished | Aug 27 06:16:35 PM UTC 24 |
| Peak memory | 251488 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=609934917 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_26/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_pass_addr_payload_swap.609934917 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/14.spi_device_pass_addr_payload_swap/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/14.spi_device_pass_cmd_filtering.2356280402 |
| Short name | T239 |
| Test name | |
| Test status | |
| Simulation time | 2706337011 ps |
| CPU time | 6.29 seconds |
| Started | Aug 27 06:16:03 PM UTC 24 |
| Finished | Aug 27 06:16:10 PM UTC 24 |
| Peak memory | 245288 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2356280402 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_08_26/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_pass_cmd_filtering.2356280402 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/14.spi_device_pass_cmd_filtering/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/14.spi_device_read_buffer_direct.3180669647 |
| Short name | T442 |
| Test name | |
| Test status | |
| Simulation time | 408444866 ps |
| CPU time | 6.75 seconds |
| Started | Aug 27 06:16:12 PM UTC 24 |
| Finished | Aug 27 06:16:19 PM UTC 24 |
| Peak memory | 233464 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3180669647 -assert nopostproc +UVM_TESTNAME=spi_device _base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_read_buffer_direct.3180669647 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/14.spi_device_read_buffer_direct/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/14.spi_device_stress_all.220160955 |
| Short name | T340 |
| Test name | |
| Test status | |
| Simulation time | 336297421369 ps |
| CPU time | 635.42 seconds |
| Started | Aug 27 06:16:15 PM UTC 24 |
| Finished | Aug 27 06:26:59 PM UTC 24 |
| Peak memory | 284304 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=220160955 -assert nopostproc +UVM_T ESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_stress_all.220160955 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/14.spi_device_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/14.spi_device_tpm_all.4083869067 |
| Short name | T364 |
| Test name | |
| Test status | |
| Simulation time | 1884827367 ps |
| CPU time | 29.78 seconds |
| Started | Aug 27 06:16:02 PM UTC 24 |
| Finished | Aug 27 06:16:33 PM UTC 24 |
| Peak memory | 231520 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4083869067 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_all.4083869067 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/14.spi_device_tpm_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/14.spi_device_tpm_read_hw_reg.1687496679 |
| Short name | T438 |
| Test name | |
| Test status | |
| Simulation time | 552471210 ps |
| CPU time | 8.64 seconds |
| Started | Aug 27 06:15:59 PM UTC 24 |
| Finished | Aug 27 06:16:09 PM UTC 24 |
| Peak memory | 227544 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1687496679 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_26/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_read_hw_reg.1687496679 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/14.spi_device_tpm_read_hw_reg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/14.spi_device_tpm_rw.3298091092 |
| Short name | T436 |
| Test name | |
| Test status | |
| Simulation time | 29962472 ps |
| CPU time | 1.92 seconds |
| Started | Aug 27 06:16:02 PM UTC 24 |
| Finished | Aug 27 06:16:05 PM UTC 24 |
| Peak memory | 226644 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3298091092 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_rw.3298091092 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/14.spi_device_tpm_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/14.spi_device_tpm_sts_read.4026853461 |
| Short name | T435 |
| Test name | |
| Test status | |
| Simulation time | 75209016 ps |
| CPU time | 1.11 seconds |
| Started | Aug 27 06:16:02 PM UTC 24 |
| Finished | Aug 27 06:16:04 PM UTC 24 |
| Peak memory | 215872 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4026853461 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_2 6/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_sts_read.4026853461 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/14.spi_device_tpm_sts_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/14.spi_device_upload.1903136894 |
| Short name | T318 |
| Test name | |
| Test status | |
| Simulation time | 476955522 ps |
| CPU time | 7.64 seconds |
| Started | Aug 27 06:16:07 PM UTC 24 |
| Finished | Aug 27 06:16:15 PM UTC 24 |
| Peak memory | 245204 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1903136894 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_upload.1903136894 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/14.spi_device_upload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/15.spi_device_alert_test.2081147452 |
| Short name | T152 |
| Test name | |
| Test status | |
| Simulation time | 39263915 ps |
| CPU time | 1.03 seconds |
| Started | Aug 27 06:16:48 PM UTC 24 |
| Finished | Aug 27 06:16:50 PM UTC 24 |
| Peak memory | 215744 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2081147452 -assert nopostproc +UVM_TES TNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_alert_test.2081147452 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/15.spi_device_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/15.spi_device_cfg_cmd.1965122035 |
| Short name | T323 |
| Test name | |
| Test status | |
| Simulation time | 168696752 ps |
| CPU time | 3.48 seconds |
| Started | Aug 27 06:16:36 PM UTC 24 |
| Finished | Aug 27 06:16:41 PM UTC 24 |
| Peak memory | 234960 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1965122035 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_cfg_cmd.1965122035 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/15.spi_device_cfg_cmd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/15.spi_device_csb_read.3394744012 |
| Short name | T443 |
| Test name | |
| Test status | |
| Simulation time | 26129003 ps |
| CPU time | 1.18 seconds |
| Started | Aug 27 06:16:20 PM UTC 24 |
| Finished | Aug 27 06:16:22 PM UTC 24 |
| Peak memory | 215808 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3394744012 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/sp i_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_csb_read.3394744012 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/15.spi_device_csb_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/15.spi_device_flash_all.984631283 |
| Short name | T229 |
| Test name | |
| Test status | |
| Simulation time | 12786057783 ps |
| CPU time | 67.59 seconds |
| Started | Aug 27 06:16:42 PM UTC 24 |
| Finished | Aug 27 06:17:51 PM UTC 24 |
| Peak memory | 261704 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=984631283 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/sp i_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_all.984631283 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/15.spi_device_flash_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/15.spi_device_flash_and_tpm.1831487232 |
| Short name | T468 |
| Test name | |
| Test status | |
| Simulation time | 2616491821 ps |
| CPU time | 62.47 seconds |
| Started | Aug 27 06:16:45 PM UTC 24 |
| Finished | Aug 27 06:17:49 PM UTC 24 |
| Peak memory | 261788 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1831487232 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_ 26/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_and_tpm.1831487232 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/15.spi_device_flash_and_tpm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/15.spi_device_flash_and_tpm_min_idle.926662198 |
| Short name | T289 |
| Test name | |
| Test status | |
| Simulation time | 104033761555 ps |
| CPU time | 396.17 seconds |
| Started | Aug 27 06:16:45 PM UTC 24 |
| Finished | Aug 27 06:23:26 PM UTC 24 |
| Peak memory | 267956 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=926662198 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_26/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_and_tpm_min_idle.926662198 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/15.spi_device_flash_and_tpm_min_idle/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/15.spi_device_flash_mode.3393376028 |
| Short name | T151 |
| Test name | |
| Test status | |
| Simulation time | 2984324050 ps |
| CPU time | 8.66 seconds |
| Started | Aug 27 06:16:37 PM UTC 24 |
| Finished | Aug 27 06:16:47 PM UTC 24 |
| Peak memory | 245328 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3393376028 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/ spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_mode.3393376028 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/15.spi_device_flash_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/15.spi_device_flash_mode_ignore_cmds.544194520 |
| Short name | T457 |
| Test name | |
| Test status | |
| Simulation time | 15295587119 ps |
| CPU time | 37.33 seconds |
| Started | Aug 27 06:16:37 PM UTC 24 |
| Finished | Aug 27 06:17:16 PM UTC 24 |
| Peak memory | 235156 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=544194520 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_26/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_mode_ignore_cmds.544194520 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/15.spi_device_flash_mode_ignore_cmds/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/15.spi_device_intercept.3066521743 |
| Short name | T221 |
| Test name | |
| Test status | |
| Simulation time | 2612840484 ps |
| CPU time | 30.29 seconds |
| Started | Aug 27 06:16:29 PM UTC 24 |
| Finished | Aug 27 06:17:01 PM UTC 24 |
| Peak memory | 245288 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3066521743 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/s pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_intercept.3066521743 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/15.spi_device_intercept/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/15.spi_device_mailbox.50986706 |
| Short name | T149 |
| Test name | |
| Test status | |
| Simulation time | 2497546028 ps |
| CPU time | 10.68 seconds |
| Started | Aug 27 06:16:34 PM UTC 24 |
| Finished | Aug 27 06:16:45 PM UTC 24 |
| Peak memory | 245268 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=50986706 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/spi_d evice_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_mailbox.50986706 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/15.spi_device_mailbox/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/15.spi_device_pass_addr_payload_swap.1307261538 |
| Short name | T447 |
| Test name | |
| Test status | |
| Simulation time | 2332283042 ps |
| CPU time | 8.81 seconds |
| Started | Aug 27 06:16:28 PM UTC 24 |
| Finished | Aug 27 06:16:38 PM UTC 24 |
| Peak memory | 235032 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1307261538 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_26/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_pass_addr_payload_swap.1307261538 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/15.spi_device_pass_addr_payload_swap/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/15.spi_device_pass_cmd_filtering.1923641975 |
| Short name | T272 |
| Test name | |
| Test status | |
| Simulation time | 14139387396 ps |
| CPU time | 46.92 seconds |
| Started | Aug 27 06:16:27 PM UTC 24 |
| Finished | Aug 27 06:17:15 PM UTC 24 |
| Peak memory | 245428 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1923641975 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_08_26/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_pass_cmd_filtering.1923641975 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/15.spi_device_pass_cmd_filtering/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/15.spi_device_read_buffer_direct.1489070576 |
| Short name | T148 |
| Test name | |
| Test status | |
| Simulation time | 146946624 ps |
| CPU time | 4.58 seconds |
| Started | Aug 27 06:16:39 PM UTC 24 |
| Finished | Aug 27 06:16:44 PM UTC 24 |
| Peak memory | 233368 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1489070576 -assert nopostproc +UVM_TESTNAME=spi_device _base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_read_buffer_direct.1489070576 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/15.spi_device_read_buffer_direct/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/15.spi_device_stress_all.220950084 |
| Short name | T190 |
| Test name | |
| Test status | |
| Simulation time | 1141468254 ps |
| CPU time | 10.9 seconds |
| Started | Aug 27 06:16:46 PM UTC 24 |
| Finished | Aug 27 06:16:58 PM UTC 24 |
| Peak memory | 247392 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=220950084 -assert nopostproc +UVM_T ESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_stress_all.220950084 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/15.spi_device_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/15.spi_device_tpm_all.2245257352 |
| Short name | T449 |
| Test name | |
| Test status | |
| Simulation time | 17139634685 ps |
| CPU time | 36.68 seconds |
| Started | Aug 27 06:16:24 PM UTC 24 |
| Finished | Aug 27 06:17:02 PM UTC 24 |
| Peak memory | 227552 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2245257352 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_all.2245257352 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/15.spi_device_tpm_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/15.spi_device_tpm_read_hw_reg.1159073881 |
| Short name | T446 |
| Test name | |
| Test status | |
| Simulation time | 5018454900 ps |
| CPU time | 10.58 seconds |
| Started | Aug 27 06:16:24 PM UTC 24 |
| Finished | Aug 27 06:16:35 PM UTC 24 |
| Peak memory | 227468 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1159073881 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_26/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_read_hw_reg.1159073881 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/15.spi_device_tpm_read_hw_reg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/15.spi_device_tpm_rw.216264808 |
| Short name | T445 |
| Test name | |
| Test status | |
| Simulation time | 21122073 ps |
| CPU time | 1.11 seconds |
| Started | Aug 27 06:16:25 PM UTC 24 |
| Finished | Aug 27 06:16:27 PM UTC 24 |
| Peak memory | 215744 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=216264808 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/spi_d evice_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_rw.216264808 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/15.spi_device_tpm_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/15.spi_device_tpm_sts_read.2563110787 |
| Short name | T444 |
| Test name | |
| Test status | |
| Simulation time | 77508316 ps |
| CPU time | 1.08 seconds |
| Started | Aug 27 06:16:24 PM UTC 24 |
| Finished | Aug 27 06:16:26 PM UTC 24 |
| Peak memory | 215872 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2563110787 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_2 6/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_sts_read.2563110787 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/15.spi_device_tpm_sts_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/15.spi_device_upload.2597985149 |
| Short name | T150 |
| Test name | |
| Test status | |
| Simulation time | 1091320933 ps |
| CPU time | 9.29 seconds |
| Started | Aug 27 06:16:36 PM UTC 24 |
| Finished | Aug 27 06:16:46 PM UTC 24 |
| Peak memory | 234872 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2597985149 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_upload.2597985149 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/15.spi_device_upload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/16.spi_device_alert_test.3130499093 |
| Short name | T454 |
| Test name | |
| Test status | |
| Simulation time | 43797321 ps |
| CPU time | 1.05 seconds |
| Started | Aug 27 06:17:12 PM UTC 24 |
| Finished | Aug 27 06:17:14 PM UTC 24 |
| Peak memory | 215804 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3130499093 -assert nopostproc +UVM_TES TNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_alert_test.3130499093 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/16.spi_device_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/16.spi_device_cfg_cmd.3692331496 |
| Short name | T451 |
| Test name | |
| Test status | |
| Simulation time | 171576899 ps |
| CPU time | 2.65 seconds |
| Started | Aug 27 06:17:03 PM UTC 24 |
| Finished | Aug 27 06:17:07 PM UTC 24 |
| Peak memory | 245216 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3692331496 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_cfg_cmd.3692331496 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/16.spi_device_cfg_cmd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/16.spi_device_csb_read.2143785693 |
| Short name | T153 |
| Test name | |
| Test status | |
| Simulation time | 61657766 ps |
| CPU time | 1.16 seconds |
| Started | Aug 27 06:16:48 PM UTC 24 |
| Finished | Aug 27 06:16:50 PM UTC 24 |
| Peak memory | 215520 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2143785693 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/sp i_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_csb_read.2143785693 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/16.spi_device_csb_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/16.spi_device_flash_and_tpm.978320030 |
| Short name | T255 |
| Test name | |
| Test status | |
| Simulation time | 3851801689 ps |
| CPU time | 48.98 seconds |
| Started | Aug 27 06:17:07 PM UTC 24 |
| Finished | Aug 27 06:17:58 PM UTC 24 |
| Peak memory | 251548 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=978320030 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_2 6/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_and_tpm.978320030 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/16.spi_device_flash_and_tpm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/16.spi_device_flash_mode_ignore_cmds.1484322532 |
| Short name | T495 |
| Test name | |
| Test status | |
| Simulation time | 17525859238 ps |
| CPU time | 116.07 seconds |
| Started | Aug 27 06:17:05 PM UTC 24 |
| Finished | Aug 27 06:19:03 PM UTC 24 |
| Peak memory | 261780 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1484322532 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_26/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_mode_ignore_cmds.1484322532 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/16.spi_device_flash_mode_ignore_cmds/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/16.spi_device_intercept.3749211201 |
| Short name | T321 |
| Test name | |
| Test status | |
| Simulation time | 687344614 ps |
| CPU time | 4.53 seconds |
| Started | Aug 27 06:16:59 PM UTC 24 |
| Finished | Aug 27 06:17:04 PM UTC 24 |
| Peak memory | 234964 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3749211201 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/s pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_intercept.3749211201 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/16.spi_device_intercept/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/16.spi_device_mailbox.864086061 |
| Short name | T470 |
| Test name | |
| Test status | |
| Simulation time | 4211612159 ps |
| CPU time | 57.29 seconds |
| Started | Aug 27 06:17:00 PM UTC 24 |
| Finished | Aug 27 06:17:59 PM UTC 24 |
| Peak memory | 251492 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=864086061 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_mailbox.864086061 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/16.spi_device_mailbox/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/16.spi_device_pass_addr_payload_swap.3033971402 |
| Short name | T453 |
| Test name | |
| Test status | |
| Simulation time | 488654086 ps |
| CPU time | 11.84 seconds |
| Started | Aug 27 06:16:57 PM UTC 24 |
| Finished | Aug 27 06:17:10 PM UTC 24 |
| Peak memory | 251424 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3033971402 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_26/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_pass_addr_payload_swap.3033971402 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/16.spi_device_pass_addr_payload_swap/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/16.spi_device_pass_cmd_filtering.3146516651 |
| Short name | T294 |
| Test name | |
| Test status | |
| Simulation time | 3060871907 ps |
| CPU time | 7.43 seconds |
| Started | Aug 27 06:16:55 PM UTC 24 |
| Finished | Aug 27 06:17:04 PM UTC 24 |
| Peak memory | 235032 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3146516651 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_08_26/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_pass_cmd_filtering.3146516651 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/16.spi_device_pass_cmd_filtering/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/16.spi_device_read_buffer_direct.2840424231 |
| Short name | T462 |
| Test name | |
| Test status | |
| Simulation time | 2262514737 ps |
| CPU time | 16.64 seconds |
| Started | Aug 27 06:17:05 PM UTC 24 |
| Finished | Aug 27 06:17:23 PM UTC 24 |
| Peak memory | 233516 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2840424231 -assert nopostproc +UVM_TESTNAME=spi_device _base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_read_buffer_direct.2840424231 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/16.spi_device_read_buffer_direct/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/16.spi_device_stress_all.797299684 |
| Short name | T176 |
| Test name | |
| Test status | |
| Simulation time | 47495442 ps |
| CPU time | 1.41 seconds |
| Started | Aug 27 06:17:10 PM UTC 24 |
| Finished | Aug 27 06:17:12 PM UTC 24 |
| Peak memory | 215804 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=797299684 -assert nopostproc +UVM_T ESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_stress_all.797299684 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/16.spi_device_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/16.spi_device_tpm_all.3034116399 |
| Short name | T452 |
| Test name | |
| Test status | |
| Simulation time | 9728322138 ps |
| CPU time | 14.5 seconds |
| Started | Aug 27 06:16:52 PM UTC 24 |
| Finished | Aug 27 06:17:08 PM UTC 24 |
| Peak memory | 231776 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3034116399 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_all.3034116399 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/16.spi_device_tpm_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/16.spi_device_tpm_read_hw_reg.1906967693 |
| Short name | T450 |
| Test name | |
| Test status | |
| Simulation time | 44351487327 ps |
| CPU time | 13.32 seconds |
| Started | Aug 27 06:16:51 PM UTC 24 |
| Finished | Aug 27 06:17:06 PM UTC 24 |
| Peak memory | 229576 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1906967693 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_26/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_read_hw_reg.1906967693 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/16.spi_device_tpm_read_hw_reg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/16.spi_device_tpm_rw.2982274786 |
| Short name | T448 |
| Test name | |
| Test status | |
| Simulation time | 329320575 ps |
| CPU time | 2.63 seconds |
| Started | Aug 27 06:16:54 PM UTC 24 |
| Finished | Aug 27 06:16:57 PM UTC 24 |
| Peak memory | 229524 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2982274786 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_rw.2982274786 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/16.spi_device_tpm_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/16.spi_device_tpm_sts_read.2797495013 |
| Short name | T156 |
| Test name | |
| Test status | |
| Simulation time | 68749019 ps |
| CPU time | 1.41 seconds |
| Started | Aug 27 06:16:54 PM UTC 24 |
| Finished | Aug 27 06:16:56 PM UTC 24 |
| Peak memory | 215872 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2797495013 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_2 6/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_sts_read.2797495013 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/16.spi_device_tpm_sts_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/16.spi_device_upload.1988425042 |
| Short name | T274 |
| Test name | |
| Test status | |
| Simulation time | 3287015819 ps |
| CPU time | 8.26 seconds |
| Started | Aug 27 06:17:03 PM UTC 24 |
| Finished | Aug 27 06:17:12 PM UTC 24 |
| Peak memory | 235156 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1988425042 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_upload.1988425042 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/16.spi_device_upload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/17.spi_device_alert_test.192041341 |
| Short name | T466 |
| Test name | |
| Test status | |
| Simulation time | 14303793 ps |
| CPU time | 1.05 seconds |
| Started | Aug 27 06:17:43 PM UTC 24 |
| Finished | Aug 27 06:17:46 PM UTC 24 |
| Peak memory | 215684 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=192041341 -assert nopostproc +UVM_TEST NAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_alert_test.192041341 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/17.spi_device_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/17.spi_device_cfg_cmd.2856866563 |
| Short name | T286 |
| Test name | |
| Test status | |
| Simulation time | 442342045 ps |
| CPU time | 3.27 seconds |
| Started | Aug 27 06:17:23 PM UTC 24 |
| Finished | Aug 27 06:17:28 PM UTC 24 |
| Peak memory | 234960 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2856866563 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_cfg_cmd.2856866563 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/17.spi_device_cfg_cmd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/17.spi_device_csb_read.2830379939 |
| Short name | T456 |
| Test name | |
| Test status | |
| Simulation time | 15972602 ps |
| CPU time | 1.17 seconds |
| Started | Aug 27 06:17:13 PM UTC 24 |
| Finished | Aug 27 06:17:15 PM UTC 24 |
| Peak memory | 215808 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2830379939 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/sp i_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_csb_read.2830379939 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/17.spi_device_csb_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/17.spi_device_flash_all.712421204 |
| Short name | T288 |
| Test name | |
| Test status | |
| Simulation time | 35694833901 ps |
| CPU time | 154.1 seconds |
| Started | Aug 27 06:17:30 PM UTC 24 |
| Finished | Aug 27 06:20:07 PM UTC 24 |
| Peak memory | 278096 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=712421204 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/sp i_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_all.712421204 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/17.spi_device_flash_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/17.spi_device_flash_and_tpm.1925113414 |
| Short name | T487 |
| Test name | |
| Test status | |
| Simulation time | 3481464140 ps |
| CPU time | 73.09 seconds |
| Started | Aug 27 06:17:33 PM UTC 24 |
| Finished | Aug 27 06:18:48 PM UTC 24 |
| Peak memory | 263828 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1925113414 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_ 26/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_and_tpm.1925113414 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/17.spi_device_flash_and_tpm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/17.spi_device_flash_and_tpm_min_idle.1285799609 |
| Short name | T290 |
| Test name | |
| Test status | |
| Simulation time | 215488745928 ps |
| CPU time | 522.31 seconds |
| Started | Aug 27 06:17:33 PM UTC 24 |
| Finished | Aug 27 06:26:22 PM UTC 24 |
| Peak memory | 278132 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1285799609 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_26/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_and_tpm_min_idle.1285799609 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/17.spi_device_flash_and_tpm_min_idle/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/17.spi_device_flash_mode.3157716118 |
| Short name | T356 |
| Test name | |
| Test status | |
| Simulation time | 3805581150 ps |
| CPU time | 65.04 seconds |
| Started | Aug 27 06:17:25 PM UTC 24 |
| Finished | Aug 27 06:18:32 PM UTC 24 |
| Peak memory | 245396 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3157716118 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/ spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_mode.3157716118 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/17.spi_device_flash_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/17.spi_device_flash_mode_ignore_cmds.642991845 |
| Short name | T224 |
| Test name | |
| Test status | |
| Simulation time | 59271723907 ps |
| CPU time | 481.26 seconds |
| Started | Aug 27 06:17:29 PM UTC 24 |
| Finished | Aug 27 06:25:36 PM UTC 24 |
| Peak memory | 263828 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=642991845 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_26/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_mode_ignore_cmds.642991845 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/17.spi_device_flash_mode_ignore_cmds/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/17.spi_device_intercept.4054461977 |
| Short name | T455 |
| Test name | |
| Test status | |
| Simulation time | 13482929562 ps |
| CPU time | 22.52 seconds |
| Started | Aug 27 06:17:19 PM UTC 24 |
| Finished | Aug 27 06:17:43 PM UTC 24 |
| Peak memory | 245348 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4054461977 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/s pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_intercept.4054461977 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/17.spi_device_intercept/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/17.spi_device_mailbox.211041176 |
| Short name | T287 |
| Test name | |
| Test status | |
| Simulation time | 37947844063 ps |
| CPU time | 102.95 seconds |
| Started | Aug 27 06:17:19 PM UTC 24 |
| Finished | Aug 27 06:19:04 PM UTC 24 |
| Peak memory | 251496 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=211041176 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_mailbox.211041176 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/17.spi_device_mailbox/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/17.spi_device_pass_addr_payload_swap.2426589731 |
| Short name | T309 |
| Test name | |
| Test status | |
| Simulation time | 786255555 ps |
| CPU time | 10.25 seconds |
| Started | Aug 27 06:17:18 PM UTC 24 |
| Finished | Aug 27 06:17:29 PM UTC 24 |
| Peak memory | 234904 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2426589731 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_26/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_pass_addr_payload_swap.2426589731 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/17.spi_device_pass_addr_payload_swap/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/17.spi_device_pass_cmd_filtering.3701202024 |
| Short name | T463 |
| Test name | |
| Test status | |
| Simulation time | 2697708811 ps |
| CPU time | 9.38 seconds |
| Started | Aug 27 06:17:17 PM UTC 24 |
| Finished | Aug 27 06:17:28 PM UTC 24 |
| Peak memory | 261720 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3701202024 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_08_26/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_pass_cmd_filtering.3701202024 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/17.spi_device_pass_cmd_filtering/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/17.spi_device_read_buffer_direct.1958239430 |
| Short name | T465 |
| Test name | |
| Test status | |
| Simulation time | 628761895 ps |
| CPU time | 9.49 seconds |
| Started | Aug 27 06:17:29 PM UTC 24 |
| Finished | Aug 27 06:17:40 PM UTC 24 |
| Peak memory | 231312 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1958239430 -assert nopostproc +UVM_TESTNAME=spi_device _base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_read_buffer_direct.1958239430 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/17.spi_device_read_buffer_direct/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/17.spi_device_tpm_all.3687879911 |
| Short name | T458 |
| Test name | |
| Test status | |
| Simulation time | 18251424 ps |
| CPU time | 1.15 seconds |
| Started | Aug 27 06:17:16 PM UTC 24 |
| Finished | Aug 27 06:17:18 PM UTC 24 |
| Peak memory | 215688 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3687879911 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_all.3687879911 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/17.spi_device_tpm_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/17.spi_device_tpm_read_hw_reg.2406917023 |
| Short name | T461 |
| Test name | |
| Test status | |
| Simulation time | 501211532 ps |
| CPU time | 6.82 seconds |
| Started | Aug 27 06:17:14 PM UTC 24 |
| Finished | Aug 27 06:17:22 PM UTC 24 |
| Peak memory | 227544 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2406917023 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_26/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_read_hw_reg.2406917023 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/17.spi_device_tpm_read_hw_reg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/17.spi_device_tpm_rw.4256281988 |
| Short name | T460 |
| Test name | |
| Test status | |
| Simulation time | 224139306 ps |
| CPU time | 4.51 seconds |
| Started | Aug 27 06:17:16 PM UTC 24 |
| Finished | Aug 27 06:17:22 PM UTC 24 |
| Peak memory | 227504 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4256281988 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_rw.4256281988 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/17.spi_device_tpm_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/17.spi_device_tpm_sts_read.3690224013 |
| Short name | T459 |
| Test name | |
| Test status | |
| Simulation time | 80100308 ps |
| CPU time | 1.13 seconds |
| Started | Aug 27 06:17:16 PM UTC 24 |
| Finished | Aug 27 06:17:18 PM UTC 24 |
| Peak memory | 215872 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3690224013 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_2 6/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_sts_read.3690224013 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/17.spi_device_tpm_sts_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/17.spi_device_upload.1047424432 |
| Short name | T464 |
| Test name | |
| Test status | |
| Simulation time | 1832226664 ps |
| CPU time | 7.61 seconds |
| Started | Aug 27 06:17:23 PM UTC 24 |
| Finished | Aug 27 06:17:32 PM UTC 24 |
| Peak memory | 261540 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1047424432 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_upload.1047424432 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/17.spi_device_upload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/18.spi_device_alert_test.1816191239 |
| Short name | T480 |
| Test name | |
| Test status | |
| Simulation time | 22276337 ps |
| CPU time | 1.13 seconds |
| Started | Aug 27 06:18:22 PM UTC 24 |
| Finished | Aug 27 06:18:24 PM UTC 24 |
| Peak memory | 215744 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1816191239 -assert nopostproc +UVM_TES TNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_alert_test.1816191239 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/18.spi_device_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/18.spi_device_cfg_cmd.310861023 |
| Short name | T314 |
| Test name | |
| Test status | |
| Simulation time | 1633802495 ps |
| CPU time | 4.34 seconds |
| Started | Aug 27 06:18:02 PM UTC 24 |
| Finished | Aug 27 06:18:07 PM UTC 24 |
| Peak memory | 234900 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=310861023 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_cfg_cmd.310861023 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/18.spi_device_cfg_cmd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/18.spi_device_csb_read.645803332 |
| Short name | T467 |
| Test name | |
| Test status | |
| Simulation time | 15461187 ps |
| CPU time | 1.18 seconds |
| Started | Aug 27 06:17:47 PM UTC 24 |
| Finished | Aug 27 06:17:49 PM UTC 24 |
| Peak memory | 215520 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=645803332 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_csb_read.645803332 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/18.spi_device_csb_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/18.spi_device_flash_all.1826238629 |
| Short name | T489 |
| Test name | |
| Test status | |
| Simulation time | 5872199799 ps |
| CPU time | 40.82 seconds |
| Started | Aug 27 06:18:09 PM UTC 24 |
| Finished | Aug 27 06:18:51 PM UTC 24 |
| Peak memory | 251492 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1826238629 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/s pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_all.1826238629 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/18.spi_device_flash_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/18.spi_device_flash_and_tpm.2857650838 |
| Short name | T327 |
| Test name | |
| Test status | |
| Simulation time | 20536318844 ps |
| CPU time | 117.91 seconds |
| Started | Aug 27 06:18:10 PM UTC 24 |
| Finished | Aug 27 06:20:10 PM UTC 24 |
| Peak memory | 251584 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2857650838 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_ 26/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_and_tpm.2857650838 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/18.spi_device_flash_and_tpm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/18.spi_device_flash_and_tpm_min_idle.3791410349 |
| Short name | T580 |
| Test name | |
| Test status | |
| Simulation time | 75026402504 ps |
| CPU time | 200.79 seconds |
| Started | Aug 27 06:18:18 PM UTC 24 |
| Finished | Aug 27 06:21:42 PM UTC 24 |
| Peak memory | 263836 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3791410349 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_26/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_and_tpm_min_idle.3791410349 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/18.spi_device_flash_and_tpm_min_idle/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/18.spi_device_flash_mode.2693472198 |
| Short name | T477 |
| Test name | |
| Test status | |
| Simulation time | 165794610 ps |
| CPU time | 8.6 seconds |
| Started | Aug 27 06:18:07 PM UTC 24 |
| Finished | Aug 27 06:18:17 PM UTC 24 |
| Peak memory | 245140 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2693472198 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/ spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_mode.2693472198 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/18.spi_device_flash_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/18.spi_device_flash_mode_ignore_cmds.3500265794 |
| Short name | T490 |
| Test name | |
| Test status | |
| Simulation time | 17715920579 ps |
| CPU time | 49.68 seconds |
| Started | Aug 27 06:18:07 PM UTC 24 |
| Finished | Aug 27 06:18:58 PM UTC 24 |
| Peak memory | 261840 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3500265794 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_26/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_mode_ignore_cmds.3500265794 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/18.spi_device_flash_mode_ignore_cmds/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/18.spi_device_intercept.2202025998 |
| Short name | T475 |
| Test name | |
| Test status | |
| Simulation time | 801866766 ps |
| CPU time | 5.93 seconds |
| Started | Aug 27 06:18:01 PM UTC 24 |
| Finished | Aug 27 06:18:07 PM UTC 24 |
| Peak memory | 245220 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2202025998 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/s pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_intercept.2202025998 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/18.spi_device_intercept/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/18.spi_device_mailbox.2541880014 |
| Short name | T293 |
| Test name | |
| Test status | |
| Simulation time | 841328417 ps |
| CPU time | 19.04 seconds |
| Started | Aug 27 06:18:01 PM UTC 24 |
| Finished | Aug 27 06:18:21 PM UTC 24 |
| Peak memory | 245224 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2541880014 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_mailbox.2541880014 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/18.spi_device_mailbox/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/18.spi_device_pass_addr_payload_swap.723343667 |
| Short name | T265 |
| Test name | |
| Test status | |
| Simulation time | 1132979945 ps |
| CPU time | 17.91 seconds |
| Started | Aug 27 06:17:59 PM UTC 24 |
| Finished | Aug 27 06:18:18 PM UTC 24 |
| Peak memory | 251304 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=723343667 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_26/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_pass_addr_payload_swap.723343667 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/18.spi_device_pass_addr_payload_swap/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/18.spi_device_pass_cmd_filtering.2101197278 |
| Short name | T474 |
| Test name | |
| Test status | |
| Simulation time | 828897597 ps |
| CPU time | 11.02 seconds |
| Started | Aug 27 06:17:54 PM UTC 24 |
| Finished | Aug 27 06:18:06 PM UTC 24 |
| Peak memory | 234956 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2101197278 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_08_26/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_pass_cmd_filtering.2101197278 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/18.spi_device_pass_cmd_filtering/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/18.spi_device_read_buffer_direct.1481302755 |
| Short name | T479 |
| Test name | |
| Test status | |
| Simulation time | 3333527920 ps |
| CPU time | 12.57 seconds |
| Started | Aug 27 06:18:09 PM UTC 24 |
| Finished | Aug 27 06:18:22 PM UTC 24 |
| Peak memory | 229464 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1481302755 -assert nopostproc +UVM_TESTNAME=spi_device _base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_read_buffer_direct.1481302755 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/18.spi_device_read_buffer_direct/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/18.spi_device_stress_all.2177751377 |
| Short name | T478 |
| Test name | |
| Test status | |
| Simulation time | 154334122 ps |
| CPU time | 1.49 seconds |
| Started | Aug 27 06:18:19 PM UTC 24 |
| Finished | Aug 27 06:18:22 PM UTC 24 |
| Peak memory | 215708 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2177751377 -assert nopostproc +UVM_ TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_stress_all.2177751377 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/18.spi_device_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/18.spi_device_tpm_all.3158697802 |
| Short name | T473 |
| Test name | |
| Test status | |
| Simulation time | 2098508881 ps |
| CPU time | 9.89 seconds |
| Started | Aug 27 06:17:50 PM UTC 24 |
| Finished | Aug 27 06:18:01 PM UTC 24 |
| Peak memory | 227500 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3158697802 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_all.3158697802 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/18.spi_device_tpm_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/18.spi_device_tpm_read_hw_reg.2506526388 |
| Short name | T472 |
| Test name | |
| Test status | |
| Simulation time | 1050106118 ps |
| CPU time | 8.6 seconds |
| Started | Aug 27 06:17:50 PM UTC 24 |
| Finished | Aug 27 06:18:00 PM UTC 24 |
| Peak memory | 227516 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2506526388 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_26/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_read_hw_reg.2506526388 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/18.spi_device_tpm_read_hw_reg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/18.spi_device_tpm_rw.3431892424 |
| Short name | T471 |
| Test name | |
| Test status | |
| Simulation time | 102042893 ps |
| CPU time | 6.18 seconds |
| Started | Aug 27 06:17:52 PM UTC 24 |
| Finished | Aug 27 06:17:59 PM UTC 24 |
| Peak memory | 227500 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3431892424 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_rw.3431892424 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/18.spi_device_tpm_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/18.spi_device_tpm_sts_read.1883045335 |
| Short name | T469 |
| Test name | |
| Test status | |
| Simulation time | 36454553 ps |
| CPU time | 1.05 seconds |
| Started | Aug 27 06:17:51 PM UTC 24 |
| Finished | Aug 27 06:17:53 PM UTC 24 |
| Peak memory | 215872 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1883045335 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_2 6/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_sts_read.1883045335 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/18.spi_device_tpm_sts_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/18.spi_device_upload.302712076 |
| Short name | T476 |
| Test name | |
| Test status | |
| Simulation time | 206993333 ps |
| CPU time | 5.36 seconds |
| Started | Aug 27 06:18:02 PM UTC 24 |
| Finished | Aug 27 06:18:08 PM UTC 24 |
| Peak memory | 234964 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=302712076 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/spi_d evice_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_upload.302712076 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/18.spi_device_upload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/19.spi_device_alert_test.1864643339 |
| Short name | T492 |
| Test name | |
| Test status | |
| Simulation time | 16082930 ps |
| CPU time | 1.15 seconds |
| Started | Aug 27 06:18:59 PM UTC 24 |
| Finished | Aug 27 06:19:01 PM UTC 24 |
| Peak memory | 215744 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1864643339 -assert nopostproc +UVM_TES TNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_alert_test.1864643339 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/19.spi_device_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/19.spi_device_cfg_cmd.528095203 |
| Short name | T491 |
| Test name | |
| Test status | |
| Simulation time | 5151048599 ps |
| CPU time | 10.48 seconds |
| Started | Aug 27 06:18:47 PM UTC 24 |
| Finished | Aug 27 06:18:59 PM UTC 24 |
| Peak memory | 245284 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=528095203 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_cfg_cmd.528095203 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/19.spi_device_cfg_cmd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/19.spi_device_csb_read.4120204542 |
| Short name | T481 |
| Test name | |
| Test status | |
| Simulation time | 16407528 ps |
| CPU time | 1.14 seconds |
| Started | Aug 27 06:18:23 PM UTC 24 |
| Finished | Aug 27 06:18:25 PM UTC 24 |
| Peak memory | 215812 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4120204542 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/sp i_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_csb_read.4120204542 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/19.spi_device_csb_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/19.spi_device_flash_all.1487119937 |
| Short name | T339 |
| Test name | |
| Test status | |
| Simulation time | 43026494358 ps |
| CPU time | 395.99 seconds |
| Started | Aug 27 06:18:50 PM UTC 24 |
| Finished | Aug 27 06:25:32 PM UTC 24 |
| Peak memory | 261712 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1487119937 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/s pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_all.1487119937 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/19.spi_device_flash_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/19.spi_device_flash_and_tpm.4146270296 |
| Short name | T331 |
| Test name | |
| Test status | |
| Simulation time | 113610710177 ps |
| CPU time | 304.87 seconds |
| Started | Aug 27 06:18:52 PM UTC 24 |
| Finished | Aug 27 06:24:02 PM UTC 24 |
| Peak memory | 261808 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4146270296 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_ 26/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_and_tpm.4146270296 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/19.spi_device_flash_and_tpm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/19.spi_device_flash_and_tpm_min_idle.2015081383 |
| Short name | T375 |
| Test name | |
| Test status | |
| Simulation time | 5917122247 ps |
| CPU time | 49.97 seconds |
| Started | Aug 27 06:18:54 PM UTC 24 |
| Finished | Aug 27 06:19:45 PM UTC 24 |
| Peak memory | 251604 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2015081383 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_26/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_and_tpm_min_idle.2015081383 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/19.spi_device_flash_and_tpm_min_idle/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/19.spi_device_flash_mode.2106702461 |
| Short name | T358 |
| Test name | |
| Test status | |
| Simulation time | 992107931 ps |
| CPU time | 9.64 seconds |
| Started | Aug 27 06:18:47 PM UTC 24 |
| Finished | Aug 27 06:18:58 PM UTC 24 |
| Peak memory | 245216 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2106702461 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/ spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_mode.2106702461 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/19.spi_device_flash_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/19.spi_device_flash_mode_ignore_cmds.3926015595 |
| Short name | T524 |
| Test name | |
| Test status | |
| Simulation time | 12170250632 ps |
| CPU time | 69.13 seconds |
| Started | Aug 27 06:18:49 PM UTC 24 |
| Finished | Aug 27 06:20:00 PM UTC 24 |
| Peak memory | 263764 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3926015595 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_26/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_mode_ignore_cmds.3926015595 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/19.spi_device_flash_mode_ignore_cmds/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/19.spi_device_intercept.119766456 |
| Short name | T485 |
| Test name | |
| Test status | |
| Simulation time | 286140395 ps |
| CPU time | 3.98 seconds |
| Started | Aug 27 06:18:33 PM UTC 24 |
| Finished | Aug 27 06:18:38 PM UTC 24 |
| Peak memory | 234900 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=119766456 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/sp i_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_intercept.119766456 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/19.spi_device_intercept/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/19.spi_device_mailbox.1461770821 |
| Short name | T310 |
| Test name | |
| Test status | |
| Simulation time | 2606171582 ps |
| CPU time | 38.63 seconds |
| Started | Aug 27 06:18:40 PM UTC 24 |
| Finished | Aug 27 06:19:20 PM UTC 24 |
| Peak memory | 245396 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1461770821 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_mailbox.1461770821 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/19.spi_device_mailbox/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/19.spi_device_pass_addr_payload_swap.1959127569 |
| Short name | T315 |
| Test name | |
| Test status | |
| Simulation time | 1859210011 ps |
| CPU time | 24.48 seconds |
| Started | Aug 27 06:18:32 PM UTC 24 |
| Finished | Aug 27 06:18:58 PM UTC 24 |
| Peak memory | 245332 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1959127569 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_26/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_pass_addr_payload_swap.1959127569 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/19.spi_device_pass_addr_payload_swap/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/19.spi_device_pass_cmd_filtering.1482972334 |
| Short name | T488 |
| Test name | |
| Test status | |
| Simulation time | 3675832083 ps |
| CPU time | 17.03 seconds |
| Started | Aug 27 06:18:30 PM UTC 24 |
| Finished | Aug 27 06:18:49 PM UTC 24 |
| Peak memory | 235032 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1482972334 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_08_26/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_pass_cmd_filtering.1482972334 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/19.spi_device_pass_cmd_filtering/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/19.spi_device_read_buffer_direct.2291199931 |
| Short name | T497 |
| Test name | |
| Test status | |
| Simulation time | 1134658111 ps |
| CPU time | 15.64 seconds |
| Started | Aug 27 06:18:50 PM UTC 24 |
| Finished | Aug 27 06:19:07 PM UTC 24 |
| Peak memory | 231324 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2291199931 -assert nopostproc +UVM_TESTNAME=spi_device _base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_read_buffer_direct.2291199931 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/19.spi_device_read_buffer_direct/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/19.spi_device_stress_all.159404155 |
| Short name | T177 |
| Test name | |
| Test status | |
| Simulation time | 9506999706 ps |
| CPU time | 169.46 seconds |
| Started | Aug 27 06:18:59 PM UTC 24 |
| Finished | Aug 27 06:21:51 PM UTC 24 |
| Peak memory | 278176 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=159404155 -assert nopostproc +UVM_T ESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_stress_all.159404155 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/19.spi_device_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/19.spi_device_tpm_all.3783406512 |
| Short name | T377 |
| Test name | |
| Test status | |
| Simulation time | 1859818180 ps |
| CPU time | 25.49 seconds |
| Started | Aug 27 06:18:25 PM UTC 24 |
| Finished | Aug 27 06:18:52 PM UTC 24 |
| Peak memory | 227424 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3783406512 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_all.3783406512 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/19.spi_device_tpm_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/19.spi_device_tpm_read_hw_reg.1223740768 |
| Short name | T483 |
| Test name | |
| Test status | |
| Simulation time | 248616911 ps |
| CPU time | 3.01 seconds |
| Started | Aug 27 06:18:25 PM UTC 24 |
| Finished | Aug 27 06:18:29 PM UTC 24 |
| Peak memory | 217092 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1223740768 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_26/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_read_hw_reg.1223740768 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/19.spi_device_tpm_read_hw_reg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/19.spi_device_tpm_rw.3726267835 |
| Short name | T484 |
| Test name | |
| Test status | |
| Simulation time | 42206851 ps |
| CPU time | 1.26 seconds |
| Started | Aug 27 06:18:30 PM UTC 24 |
| Finished | Aug 27 06:18:33 PM UTC 24 |
| Peak memory | 215868 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3726267835 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_rw.3726267835 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/19.spi_device_tpm_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/19.spi_device_tpm_sts_read.3218238801 |
| Short name | T482 |
| Test name | |
| Test status | |
| Simulation time | 91124517 ps |
| CPU time | 1.47 seconds |
| Started | Aug 27 06:18:27 PM UTC 24 |
| Finished | Aug 27 06:18:29 PM UTC 24 |
| Peak memory | 215872 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3218238801 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_2 6/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_sts_read.3218238801 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/19.spi_device_tpm_sts_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/19.spi_device_upload.3220172955 |
| Short name | T486 |
| Test name | |
| Test status | |
| Simulation time | 387639581 ps |
| CPU time | 4.01 seconds |
| Started | Aug 27 06:18:41 PM UTC 24 |
| Finished | Aug 27 06:18:46 PM UTC 24 |
| Peak memory | 245192 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3220172955 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_upload.3220172955 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/19.spi_device_upload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/2.spi_device_alert_test.1416992641 |
| Short name | T92 |
| Test name | |
| Test status | |
| Simulation time | 13671657 ps |
| CPU time | 1.11 seconds |
| Started | Aug 27 06:10:40 PM UTC 24 |
| Finished | Aug 27 06:10:42 PM UTC 24 |
| Peak memory | 215684 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1416992641 -assert nopostproc +UVM_TES TNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_alert_test.1416992641 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/2.spi_device_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/2.spi_device_cfg_cmd.3118806503 |
| Short name | T57 |
| Test name | |
| Test status | |
| Simulation time | 1077736864 ps |
| CPU time | 19.9 seconds |
| Started | Aug 27 06:10:15 PM UTC 24 |
| Finished | Aug 27 06:10:36 PM UTC 24 |
| Peak memory | 234904 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3118806503 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_cfg_cmd.3118806503 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/2.spi_device_cfg_cmd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/2.spi_device_csb_read.1726517236 |
| Short name | T28 |
| Test name | |
| Test status | |
| Simulation time | 45852078 ps |
| CPU time | 1.12 seconds |
| Started | Aug 27 06:09:59 PM UTC 24 |
| Finished | Aug 27 06:10:01 PM UTC 24 |
| Peak memory | 215808 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1726517236 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/sp i_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_csb_read.1726517236 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/2.spi_device_csb_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/2.spi_device_flash_all.1335274763 |
| Short name | T51 |
| Test name | |
| Test status | |
| Simulation time | 22865448186 ps |
| CPU time | 96.24 seconds |
| Started | Aug 27 06:10:23 PM UTC 24 |
| Finished | Aug 27 06:12:01 PM UTC 24 |
| Peak memory | 251476 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1335274763 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/s pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_all.1335274763 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/2.spi_device_flash_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/2.spi_device_flash_and_tpm.4142840934 |
| Short name | T88 |
| Test name | |
| Test status | |
| Simulation time | 21777135019 ps |
| CPU time | 106.37 seconds |
| Started | Aug 27 06:10:24 PM UTC 24 |
| Finished | Aug 27 06:12:12 PM UTC 24 |
| Peak memory | 263824 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4142840934 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_ 26/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_and_tpm.4142840934 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/2.spi_device_flash_and_tpm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/2.spi_device_flash_mode.4131828344 |
| Short name | T47 |
| Test name | |
| Test status | |
| Simulation time | 159812934 ps |
| CPU time | 3.37 seconds |
| Started | Aug 27 06:10:15 PM UTC 24 |
| Finished | Aug 27 06:10:20 PM UTC 24 |
| Peak memory | 245208 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4131828344 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/ spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_mode.4131828344 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/2.spi_device_flash_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/2.spi_device_flash_mode_ignore_cmds.1760173059 |
| Short name | T89 |
| Test name | |
| Test status | |
| Simulation time | 17826428012 ps |
| CPU time | 135.92 seconds |
| Started | Aug 27 06:10:19 PM UTC 24 |
| Finished | Aug 27 06:12:38 PM UTC 24 |
| Peak memory | 261716 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1760173059 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_26/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_mode_ignore_cmds.1760173059 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/2.spi_device_flash_mode_ignore_cmds/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/2.spi_device_intercept.721242209 |
| Short name | T270 |
| Test name | |
| Test status | |
| Simulation time | 63970800 ps |
| CPU time | 3.78 seconds |
| Started | Aug 27 06:10:09 PM UTC 24 |
| Finished | Aug 27 06:10:14 PM UTC 24 |
| Peak memory | 234984 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=721242209 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/sp i_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_intercept.721242209 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/2.spi_device_intercept/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/2.spi_device_mailbox.966098633 |
| Short name | T66 |
| Test name | |
| Test status | |
| Simulation time | 4920417424 ps |
| CPU time | 26.81 seconds |
| Started | Aug 27 06:10:11 PM UTC 24 |
| Finished | Aug 27 06:10:39 PM UTC 24 |
| Peak memory | 251628 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=966098633 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_mailbox.966098633 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/2.spi_device_mailbox/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/2.spi_device_pass_addr_payload_swap.372841431 |
| Short name | T55 |
| Test name | |
| Test status | |
| Simulation time | 224012688 ps |
| CPU time | 5.31 seconds |
| Started | Aug 27 06:10:08 PM UTC 24 |
| Finished | Aug 27 06:10:15 PM UTC 24 |
| Peak memory | 234972 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=372841431 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_26/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_pass_addr_payload_swap.372841431 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/2.spi_device_pass_addr_payload_swap/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/2.spi_device_pass_cmd_filtering.1401110231 |
| Short name | T215 |
| Test name | |
| Test status | |
| Simulation time | 36971998 ps |
| CPU time | 2.94 seconds |
| Started | Aug 27 06:10:08 PM UTC 24 |
| Finished | Aug 27 06:10:12 PM UTC 24 |
| Peak memory | 245348 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1401110231 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_08_26/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_pass_cmd_filtering.1401110231 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/2.spi_device_pass_cmd_filtering/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/2.spi_device_read_buffer_direct.2559863589 |
| Short name | T46 |
| Test name | |
| Test status | |
| Simulation time | 1591742385 ps |
| CPU time | 18 seconds |
| Started | Aug 27 06:10:21 PM UTC 24 |
| Finished | Aug 27 06:10:40 PM UTC 24 |
| Peak memory | 233592 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2559863589 -assert nopostproc +UVM_TESTNAME=spi_device _base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_read_buffer_direct.2559863589 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/2.spi_device_read_buffer_direct/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/2.spi_device_sec_cm.4064513536 |
| Short name | T21 |
| Test name | |
| Test status | |
| Simulation time | 81906496 ps |
| CPU time | 1.51 seconds |
| Started | Aug 27 06:10:37 PM UTC 24 |
| Finished | Aug 27 06:10:40 PM UTC 24 |
| Peak memory | 257916 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4064513536 -assert nopostproc +UVM_TEST NAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_sec_cm.4064513536 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/2.spi_device_sec_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/2.spi_device_tpm_all.3429509237 |
| Short name | T36 |
| Test name | |
| Test status | |
| Simulation time | 1324975330 ps |
| CPU time | 17.95 seconds |
| Started | Aug 27 06:10:02 PM UTC 24 |
| Finished | Aug 27 06:10:22 PM UTC 24 |
| Peak memory | 227492 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3429509237 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_all.3429509237 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/2.spi_device_tpm_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/2.spi_device_tpm_read_hw_reg.3141334423 |
| Short name | T29 |
| Test name | |
| Test status | |
| Simulation time | 442222524 ps |
| CPU time | 3.67 seconds |
| Started | Aug 27 06:10:01 PM UTC 24 |
| Finished | Aug 27 06:10:06 PM UTC 24 |
| Peak memory | 227424 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3141334423 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_26/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_read_hw_reg.3141334423 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/2.spi_device_tpm_read_hw_reg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/2.spi_device_tpm_rw.3060863394 |
| Short name | T31 |
| Test name | |
| Test status | |
| Simulation time | 88957912 ps |
| CPU time | 2.83 seconds |
| Started | Aug 27 06:10:07 PM UTC 24 |
| Finished | Aug 27 06:10:11 PM UTC 24 |
| Peak memory | 227548 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3060863394 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_rw.3060863394 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/2.spi_device_tpm_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/2.spi_device_tpm_sts_read.2969950647 |
| Short name | T30 |
| Test name | |
| Test status | |
| Simulation time | 352220499 ps |
| CPU time | 1.46 seconds |
| Started | Aug 27 06:10:05 PM UTC 24 |
| Finished | Aug 27 06:10:07 PM UTC 24 |
| Peak memory | 215868 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2969950647 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_2 6/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_sts_read.2969950647 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/2.spi_device_tpm_sts_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/2.spi_device_upload.1849919540 |
| Short name | T65 |
| Test name | |
| Test status | |
| Simulation time | 368976605 ps |
| CPU time | 4.37 seconds |
| Started | Aug 27 06:10:13 PM UTC 24 |
| Finished | Aug 27 06:10:19 PM UTC 24 |
| Peak memory | 234960 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1849919540 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_upload.1849919540 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/2.spi_device_upload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/20.spi_device_alert_test.1418484535 |
| Short name | T504 |
| Test name | |
| Test status | |
| Simulation time | 19388109 ps |
| CPU time | 1.14 seconds |
| Started | Aug 27 06:19:26 PM UTC 24 |
| Finished | Aug 27 06:19:28 PM UTC 24 |
| Peak memory | 215608 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1418484535 -assert nopostproc +UVM_TES TNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_alert_test.1418484535 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/20.spi_device_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/20.spi_device_cfg_cmd.588863031 |
| Short name | T322 |
| Test name | |
| Test status | |
| Simulation time | 469129924 ps |
| CPU time | 8.08 seconds |
| Started | Aug 27 06:19:16 PM UTC 24 |
| Finished | Aug 27 06:19:25 PM UTC 24 |
| Peak memory | 234900 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=588863031 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_cfg_cmd.588863031 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/20.spi_device_cfg_cmd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/20.spi_device_csb_read.2483448458 |
| Short name | T493 |
| Test name | |
| Test status | |
| Simulation time | 68716297 ps |
| CPU time | 1.18 seconds |
| Started | Aug 27 06:19:00 PM UTC 24 |
| Finished | Aug 27 06:19:02 PM UTC 24 |
| Peak memory | 215808 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2483448458 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/sp i_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_csb_read.2483448458 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/20.spi_device_csb_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/20.spi_device_flash_all.1699997455 |
| Short name | T501 |
| Test name | |
| Test status | |
| Simulation time | 59244341 ps |
| CPU time | 1.19 seconds |
| Started | Aug 27 06:19:22 PM UTC 24 |
| Finished | Aug 27 06:19:24 PM UTC 24 |
| Peak memory | 225680 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1699997455 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/s pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_all.1699997455 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/20.spi_device_flash_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/20.spi_device_flash_and_tpm.3246242389 |
| Short name | T637 |
| Test name | |
| Test status | |
| Simulation time | 109889583986 ps |
| CPU time | 219.62 seconds |
| Started | Aug 27 06:19:26 PM UTC 24 |
| Finished | Aug 27 06:23:09 PM UTC 24 |
| Peak memory | 268052 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3246242389 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_ 26/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_and_tpm.3246242389 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/20.spi_device_flash_and_tpm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/20.spi_device_flash_mode.2160844067 |
| Short name | T503 |
| Test name | |
| Test status | |
| Simulation time | 1149870163 ps |
| CPU time | 7.19 seconds |
| Started | Aug 27 06:19:16 PM UTC 24 |
| Finished | Aug 27 06:19:25 PM UTC 24 |
| Peak memory | 251356 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2160844067 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/ spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_mode.2160844067 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/20.spi_device_flash_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/20.spi_device_intercept.1742320770 |
| Short name | T512 |
| Test name | |
| Test status | |
| Simulation time | 3876196977 ps |
| CPU time | 33.75 seconds |
| Started | Aug 27 06:19:08 PM UTC 24 |
| Finished | Aug 27 06:19:43 PM UTC 24 |
| Peak memory | 245332 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1742320770 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/s pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_intercept.1742320770 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/20.spi_device_intercept/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/20.spi_device_mailbox.10724711 |
| Short name | T279 |
| Test name | |
| Test status | |
| Simulation time | 1043264261 ps |
| CPU time | 6.43 seconds |
| Started | Aug 27 06:19:09 PM UTC 24 |
| Finished | Aug 27 06:19:16 PM UTC 24 |
| Peak memory | 234956 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=10724711 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/spi_d evice_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_mailbox.10724711 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/20.spi_device_mailbox/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/20.spi_device_pass_addr_payload_swap.3085688598 |
| Short name | T499 |
| Test name | |
| Test status | |
| Simulation time | 729629942 ps |
| CPU time | 9.24 seconds |
| Started | Aug 27 06:19:05 PM UTC 24 |
| Finished | Aug 27 06:19:16 PM UTC 24 |
| Peak memory | 251364 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3085688598 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_26/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_pass_addr_payload_swap.3085688598 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/20.spi_device_pass_addr_payload_swap/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/20.spi_device_pass_cmd_filtering.634390678 |
| Short name | T296 |
| Test name | |
| Test status | |
| Simulation time | 5671827636 ps |
| CPU time | 22.67 seconds |
| Started | Aug 27 06:19:05 PM UTC 24 |
| Finished | Aug 27 06:19:29 PM UTC 24 |
| Peak memory | 235028 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=634390678 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _08_26/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_pass_cmd_filtering.634390678 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/20.spi_device_pass_cmd_filtering/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/20.spi_device_read_buffer_direct.1252886584 |
| Short name | T502 |
| Test name | |
| Test status | |
| Simulation time | 212580777 ps |
| CPU time | 2.68 seconds |
| Started | Aug 27 06:19:21 PM UTC 24 |
| Finished | Aug 27 06:19:24 PM UTC 24 |
| Peak memory | 231312 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1252886584 -assert nopostproc +UVM_TESTNAME=spi_device _base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_read_buffer_direct.1252886584 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/20.spi_device_read_buffer_direct/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/20.spi_device_stress_all.3509977188 |
| Short name | T505 |
| Test name | |
| Test status | |
| Simulation time | 87397799 ps |
| CPU time | 1.1 seconds |
| Started | Aug 27 06:19:26 PM UTC 24 |
| Finished | Aug 27 06:19:28 PM UTC 24 |
| Peak memory | 216292 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3509977188 -assert nopostproc +UVM_ TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_stress_all.3509977188 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/20.spi_device_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/20.spi_device_tpm_all.3147206908 |
| Short name | T516 |
| Test name | |
| Test status | |
| Simulation time | 28277744221 ps |
| CPU time | 48.29 seconds |
| Started | Aug 27 06:19:02 PM UTC 24 |
| Finished | Aug 27 06:19:51 PM UTC 24 |
| Peak memory | 227584 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3147206908 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_all.3147206908 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/20.spi_device_tpm_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/20.spi_device_tpm_read_hw_reg.959829801 |
| Short name | T494 |
| Test name | |
| Test status | |
| Simulation time | 100395397 ps |
| CPU time | 1.46 seconds |
| Started | Aug 27 06:19:00 PM UTC 24 |
| Finished | Aug 27 06:19:03 PM UTC 24 |
| Peak memory | 215868 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=959829801 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08 _26/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_read_hw_reg.959829801 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/20.spi_device_tpm_read_hw_reg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/20.spi_device_tpm_rw.4234265556 |
| Short name | T498 |
| Test name | |
| Test status | |
| Simulation time | 1002698586 ps |
| CPU time | 6 seconds |
| Started | Aug 27 06:19:04 PM UTC 24 |
| Finished | Aug 27 06:19:11 PM UTC 24 |
| Peak memory | 227436 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4234265556 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_rw.4234265556 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/20.spi_device_tpm_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/20.spi_device_tpm_sts_read.1667974915 |
| Short name | T496 |
| Test name | |
| Test status | |
| Simulation time | 69439385 ps |
| CPU time | 1.48 seconds |
| Started | Aug 27 06:19:04 PM UTC 24 |
| Finished | Aug 27 06:19:06 PM UTC 24 |
| Peak memory | 215872 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1667974915 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_2 6/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_sts_read.1667974915 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/20.spi_device_tpm_sts_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/20.spi_device_upload.2776143162 |
| Short name | T500 |
| Test name | |
| Test status | |
| Simulation time | 347833294 ps |
| CPU time | 2.7 seconds |
| Started | Aug 27 06:19:12 PM UTC 24 |
| Finished | Aug 27 06:19:16 PM UTC 24 |
| Peak memory | 246952 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2776143162 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_upload.2776143162 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/20.spi_device_upload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/21.spi_device_alert_test.445724848 |
| Short name | T515 |
| Test name | |
| Test status | |
| Simulation time | 29568174 ps |
| CPU time | 1.12 seconds |
| Started | Aug 27 06:19:49 PM UTC 24 |
| Finished | Aug 27 06:19:51 PM UTC 24 |
| Peak memory | 215744 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=445724848 -assert nopostproc +UVM_TEST NAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_alert_test.445724848 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/21.spi_device_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/21.spi_device_cfg_cmd.3727098989 |
| Short name | T319 |
| Test name | |
| Test status | |
| Simulation time | 2665974994 ps |
| CPU time | 9.7 seconds |
| Started | Aug 27 06:19:36 PM UTC 24 |
| Finished | Aug 27 06:19:47 PM UTC 24 |
| Peak memory | 234964 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3727098989 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_cfg_cmd.3727098989 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/21.spi_device_cfg_cmd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/21.spi_device_csb_read.2362015686 |
| Short name | T506 |
| Test name | |
| Test status | |
| Simulation time | 20692161 ps |
| CPU time | 1.23 seconds |
| Started | Aug 27 06:19:27 PM UTC 24 |
| Finished | Aug 27 06:19:30 PM UTC 24 |
| Peak memory | 215808 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2362015686 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/sp i_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_csb_read.2362015686 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/21.spi_device_csb_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/21.spi_device_flash_all.724943490 |
| Short name | T332 |
| Test name | |
| Test status | |
| Simulation time | 189114680493 ps |
| CPU time | 268.27 seconds |
| Started | Aug 27 06:19:44 PM UTC 24 |
| Finished | Aug 27 06:24:16 PM UTC 24 |
| Peak memory | 265868 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=724943490 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/sp i_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_all.724943490 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/21.spi_device_flash_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/21.spi_device_flash_and_tpm_min_idle.3268803559 |
| Short name | T561 |
| Test name | |
| Test status | |
| Simulation time | 3553656933 ps |
| CPU time | 74.43 seconds |
| Started | Aug 27 06:19:47 PM UTC 24 |
| Finished | Aug 27 06:21:03 PM UTC 24 |
| Peak memory | 268024 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3268803559 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_26/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_and_tpm_min_idle.3268803559 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/21.spi_device_flash_and_tpm_min_idle/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/21.spi_device_flash_mode.3727438133 |
| Short name | T357 |
| Test name | |
| Test status | |
| Simulation time | 274240202 ps |
| CPU time | 5.99 seconds |
| Started | Aug 27 06:19:38 PM UTC 24 |
| Finished | Aug 27 06:19:45 PM UTC 24 |
| Peak memory | 247268 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3727438133 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/ spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_mode.3727438133 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/21.spi_device_flash_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/21.spi_device_flash_mode_ignore_cmds.4265054750 |
| Short name | T539 |
| Test name | |
| Test status | |
| Simulation time | 16488477676 ps |
| CPU time | 35.66 seconds |
| Started | Aug 27 06:19:41 PM UTC 24 |
| Finished | Aug 27 06:20:18 PM UTC 24 |
| Peak memory | 261716 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4265054750 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_26/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_mode_ignore_cmds.4265054750 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/21.spi_device_flash_mode_ignore_cmds/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/21.spi_device_intercept.425607998 |
| Short name | T513 |
| Test name | |
| Test status | |
| Simulation time | 4005935231 ps |
| CPU time | 11.5 seconds |
| Started | Aug 27 06:19:35 PM UTC 24 |
| Finished | Aug 27 06:19:47 PM UTC 24 |
| Peak memory | 231728 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=425607998 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/sp i_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_intercept.425607998 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/21.spi_device_intercept/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/21.spi_device_mailbox.3915180429 |
| Short name | T234 |
| Test name | |
| Test status | |
| Simulation time | 17269272245 ps |
| CPU time | 29.03 seconds |
| Started | Aug 27 06:19:35 PM UTC 24 |
| Finished | Aug 27 06:20:05 PM UTC 24 |
| Peak memory | 245408 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3915180429 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_mailbox.3915180429 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/21.spi_device_mailbox/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/21.spi_device_pass_addr_payload_swap.3104353377 |
| Short name | T326 |
| Test name | |
| Test status | |
| Simulation time | 7315645023 ps |
| CPU time | 13.93 seconds |
| Started | Aug 27 06:19:34 PM UTC 24 |
| Finished | Aug 27 06:19:49 PM UTC 24 |
| Peak memory | 234972 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3104353377 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_26/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_pass_addr_payload_swap.3104353377 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/21.spi_device_pass_addr_payload_swap/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/21.spi_device_pass_cmd_filtering.818412847 |
| Short name | T509 |
| Test name | |
| Test status | |
| Simulation time | 104160194 ps |
| CPU time | 2.88 seconds |
| Started | Aug 27 06:19:31 PM UTC 24 |
| Finished | Aug 27 06:19:35 PM UTC 24 |
| Peak memory | 233464 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=818412847 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _08_26/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_pass_cmd_filtering.818412847 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/21.spi_device_pass_cmd_filtering/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/21.spi_device_read_buffer_direct.3069598578 |
| Short name | T514 |
| Test name | |
| Test status | |
| Simulation time | 373528124 ps |
| CPU time | 5.19 seconds |
| Started | Aug 27 06:19:43 PM UTC 24 |
| Finished | Aug 27 06:19:49 PM UTC 24 |
| Peak memory | 231324 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3069598578 -assert nopostproc +UVM_TESTNAME=spi_device _base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_read_buffer_direct.3069598578 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/21.spi_device_read_buffer_direct/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/21.spi_device_stress_all.1816794471 |
| Short name | T531 |
| Test name | |
| Test status | |
| Simulation time | 5967901218 ps |
| CPU time | 23.02 seconds |
| Started | Aug 27 06:19:48 PM UTC 24 |
| Finished | Aug 27 06:20:12 PM UTC 24 |
| Peak memory | 235156 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1816794471 -assert nopostproc +UVM_ TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_stress_all.1816794471 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/21.spi_device_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/21.spi_device_tpm_all.2036924959 |
| Short name | T517 |
| Test name | |
| Test status | |
| Simulation time | 8208160732 ps |
| CPU time | 20.82 seconds |
| Started | Aug 27 06:19:30 PM UTC 24 |
| Finished | Aug 27 06:19:52 PM UTC 24 |
| Peak memory | 227624 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2036924959 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_all.2036924959 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/21.spi_device_tpm_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/21.spi_device_tpm_read_hw_reg.2032974697 |
| Short name | T525 |
| Test name | |
| Test status | |
| Simulation time | 27922670714 ps |
| CPU time | 31.86 seconds |
| Started | Aug 27 06:19:30 PM UTC 24 |
| Finished | Aug 27 06:20:03 PM UTC 24 |
| Peak memory | 227616 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2032974697 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_26/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_read_hw_reg.2032974697 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/21.spi_device_tpm_read_hw_reg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/21.spi_device_tpm_rw.3175862705 |
| Short name | T510 |
| Test name | |
| Test status | |
| Simulation time | 90520545 ps |
| CPU time | 3.08 seconds |
| Started | Aug 27 06:19:31 PM UTC 24 |
| Finished | Aug 27 06:19:35 PM UTC 24 |
| Peak memory | 227560 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3175862705 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_rw.3175862705 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/21.spi_device_tpm_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/21.spi_device_tpm_sts_read.1852342421 |
| Short name | T508 |
| Test name | |
| Test status | |
| Simulation time | 33796113 ps |
| CPU time | 1.3 seconds |
| Started | Aug 27 06:19:31 PM UTC 24 |
| Finished | Aug 27 06:19:33 PM UTC 24 |
| Peak memory | 215872 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1852342421 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_2 6/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_sts_read.1852342421 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/21.spi_device_tpm_sts_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/21.spi_device_upload.3546881374 |
| Short name | T511 |
| Test name | |
| Test status | |
| Simulation time | 1153038784 ps |
| CPU time | 4.54 seconds |
| Started | Aug 27 06:19:36 PM UTC 24 |
| Finished | Aug 27 06:19:42 PM UTC 24 |
| Peak memory | 245160 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3546881374 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_upload.3546881374 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/21.spi_device_upload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/22.spi_device_alert_test.2769825973 |
| Short name | T529 |
| Test name | |
| Test status | |
| Simulation time | 12912197 ps |
| CPU time | 1.12 seconds |
| Started | Aug 27 06:20:08 PM UTC 24 |
| Finished | Aug 27 06:20:10 PM UTC 24 |
| Peak memory | 215744 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2769825973 -assert nopostproc +UVM_TES TNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_alert_test.2769825973 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/22.spi_device_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/22.spi_device_cfg_cmd.3398587970 |
| Short name | T532 |
| Test name | |
| Test status | |
| Simulation time | 3796915282 ps |
| CPU time | 10.93 seconds |
| Started | Aug 27 06:20:01 PM UTC 24 |
| Finished | Aug 27 06:20:13 PM UTC 24 |
| Peak memory | 234960 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3398587970 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_cfg_cmd.3398587970 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/22.spi_device_cfg_cmd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/22.spi_device_csb_read.2286293970 |
| Short name | T518 |
| Test name | |
| Test status | |
| Simulation time | 23021139 ps |
| CPU time | 1.12 seconds |
| Started | Aug 27 06:19:51 PM UTC 24 |
| Finished | Aug 27 06:19:53 PM UTC 24 |
| Peak memory | 215520 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2286293970 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/sp i_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_csb_read.2286293970 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/22.spi_device_csb_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/22.spi_device_flash_all.401102958 |
| Short name | T526 |
| Test name | |
| Test status | |
| Simulation time | 13607416 ps |
| CPU time | 1.16 seconds |
| Started | Aug 27 06:20:04 PM UTC 24 |
| Finished | Aug 27 06:20:06 PM UTC 24 |
| Peak memory | 225736 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=401102958 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/sp i_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_all.401102958 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/22.spi_device_flash_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/22.spi_device_flash_and_tpm.4137696705 |
| Short name | T597 |
| Test name | |
| Test status | |
| Simulation time | 132318338438 ps |
| CPU time | 124.83 seconds |
| Started | Aug 27 06:20:06 PM UTC 24 |
| Finished | Aug 27 06:22:13 PM UTC 24 |
| Peak memory | 261836 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4137696705 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_ 26/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_and_tpm.4137696705 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/22.spi_device_flash_and_tpm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/22.spi_device_flash_and_tpm_min_idle.3546155353 |
| Short name | T703 |
| Test name | |
| Test status | |
| Simulation time | 32941938364 ps |
| CPU time | 306.84 seconds |
| Started | Aug 27 06:20:08 PM UTC 24 |
| Finished | Aug 27 06:25:19 PM UTC 24 |
| Peak memory | 267940 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3546155353 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_26/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_and_tpm_min_idle.3546155353 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/22.spi_device_flash_and_tpm_min_idle/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/22.spi_device_flash_mode.3894963731 |
| Short name | T528 |
| Test name | |
| Test status | |
| Simulation time | 501202965 ps |
| CPU time | 5.85 seconds |
| Started | Aug 27 06:20:01 PM UTC 24 |
| Finished | Aug 27 06:20:08 PM UTC 24 |
| Peak memory | 245212 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3894963731 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/ spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_mode.3894963731 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/22.spi_device_flash_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/22.spi_device_flash_mode_ignore_cmds.2491428459 |
| Short name | T301 |
| Test name | |
| Test status | |
| Simulation time | 1501101388 ps |
| CPU time | 30.59 seconds |
| Started | Aug 27 06:20:01 PM UTC 24 |
| Finished | Aug 27 06:20:33 PM UTC 24 |
| Peak memory | 251352 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2491428459 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_26/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_mode_ignore_cmds.2491428459 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/22.spi_device_flash_mode_ignore_cmds/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/22.spi_device_intercept.3936767786 |
| Short name | T522 |
| Test name | |
| Test status | |
| Simulation time | 1294258684 ps |
| CPU time | 3.48 seconds |
| Started | Aug 27 06:19:55 PM UTC 24 |
| Finished | Aug 27 06:19:59 PM UTC 24 |
| Peak memory | 235028 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3936767786 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/s pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_intercept.3936767786 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/22.spi_device_intercept/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/22.spi_device_mailbox.1821888315 |
| Short name | T538 |
| Test name | |
| Test status | |
| Simulation time | 6228535974 ps |
| CPU time | 20.07 seconds |
| Started | Aug 27 06:19:56 PM UTC 24 |
| Finished | Aug 27 06:20:17 PM UTC 24 |
| Peak memory | 245392 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1821888315 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_mailbox.1821888315 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/22.spi_device_mailbox/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/22.spi_device_pass_addr_payload_swap.552267989 |
| Short name | T304 |
| Test name | |
| Test status | |
| Simulation time | 2809321824 ps |
| CPU time | 19.87 seconds |
| Started | Aug 27 06:19:54 PM UTC 24 |
| Finished | Aug 27 06:20:15 PM UTC 24 |
| Peak memory | 251428 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=552267989 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_26/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_pass_addr_payload_swap.552267989 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/22.spi_device_pass_addr_payload_swap/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/22.spi_device_pass_cmd_filtering.929648926 |
| Short name | T527 |
| Test name | |
| Test status | |
| Simulation time | 2999329373 ps |
| CPU time | 11.72 seconds |
| Started | Aug 27 06:19:53 PM UTC 24 |
| Finished | Aug 27 06:20:06 PM UTC 24 |
| Peak memory | 245264 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=929648926 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _08_26/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_pass_cmd_filtering.929648926 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/22.spi_device_pass_cmd_filtering/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/22.spi_device_read_buffer_direct.1226757103 |
| Short name | T533 |
| Test name | |
| Test status | |
| Simulation time | 3024220987 ps |
| CPU time | 11.14 seconds |
| Started | Aug 27 06:20:01 PM UTC 24 |
| Finished | Aug 27 06:20:13 PM UTC 24 |
| Peak memory | 233452 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1226757103 -assert nopostproc +UVM_TESTNAME=spi_device _base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_read_buffer_direct.1226757103 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/22.spi_device_read_buffer_direct/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/22.spi_device_stress_all.3524503119 |
| Short name | T329 |
| Test name | |
| Test status | |
| Simulation time | 51071069788 ps |
| CPU time | 532.44 seconds |
| Started | Aug 27 06:20:08 PM UTC 24 |
| Finished | Aug 27 06:29:07 PM UTC 24 |
| Peak memory | 294560 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3524503119 -assert nopostproc +UVM_ TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_stress_all.3524503119 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/22.spi_device_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/22.spi_device_tpm_all.2984877883 |
| Short name | T521 |
| Test name | |
| Test status | |
| Simulation time | 494364797 ps |
| CPU time | 3.12 seconds |
| Started | Aug 27 06:19:51 PM UTC 24 |
| Finished | Aug 27 06:19:55 PM UTC 24 |
| Peak memory | 227424 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2984877883 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_all.2984877883 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/22.spi_device_tpm_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/22.spi_device_tpm_read_hw_reg.3519579639 |
| Short name | T523 |
| Test name | |
| Test status | |
| Simulation time | 9865754764 ps |
| CPU time | 7.47 seconds |
| Started | Aug 27 06:19:51 PM UTC 24 |
| Finished | Aug 27 06:19:59 PM UTC 24 |
| Peak memory | 227632 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3519579639 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_26/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_read_hw_reg.3519579639 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/22.spi_device_tpm_read_hw_reg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/22.spi_device_tpm_rw.3744966600 |
| Short name | T519 |
| Test name | |
| Test status | |
| Simulation time | 50550499 ps |
| CPU time | 1.11 seconds |
| Started | Aug 27 06:19:52 PM UTC 24 |
| Finished | Aug 27 06:19:54 PM UTC 24 |
| Peak memory | 215868 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3744966600 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_rw.3744966600 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/22.spi_device_tpm_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/22.spi_device_tpm_sts_read.3798001755 |
| Short name | T520 |
| Test name | |
| Test status | |
| Simulation time | 119069258 ps |
| CPU time | 1.29 seconds |
| Started | Aug 27 06:19:52 PM UTC 24 |
| Finished | Aug 27 06:19:54 PM UTC 24 |
| Peak memory | 215872 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3798001755 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_2 6/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_sts_read.3798001755 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/22.spi_device_tpm_sts_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/22.spi_device_upload.2606159806 |
| Short name | T535 |
| Test name | |
| Test status | |
| Simulation time | 4931948054 ps |
| CPU time | 18.09 seconds |
| Started | Aug 27 06:19:56 PM UTC 24 |
| Finished | Aug 27 06:20:15 PM UTC 24 |
| Peak memory | 235092 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2606159806 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_upload.2606159806 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/22.spi_device_upload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/23.spi_device_alert_test.90744075 |
| Short name | T545 |
| Test name | |
| Test status | |
| Simulation time | 13760844 ps |
| CPU time | 1.08 seconds |
| Started | Aug 27 06:20:26 PM UTC 24 |
| Finished | Aug 27 06:20:28 PM UTC 24 |
| Peak memory | 215680 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=90744075 -assert nopostproc +UVM_TESTN AME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_alert_test.90744075 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/23.spi_device_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/23.spi_device_cfg_cmd.4199272032 |
| Short name | T554 |
| Test name | |
| Test status | |
| Simulation time | 7132451155 ps |
| CPU time | 20.61 seconds |
| Started | Aug 27 06:20:17 PM UTC 24 |
| Finished | Aug 27 06:20:39 PM UTC 24 |
| Peak memory | 234996 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4199272032 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_cfg_cmd.4199272032 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/23.spi_device_cfg_cmd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/23.spi_device_csb_read.835936984 |
| Short name | T530 |
| Test name | |
| Test status | |
| Simulation time | 12795260 ps |
| CPU time | 1.1 seconds |
| Started | Aug 27 06:20:09 PM UTC 24 |
| Finished | Aug 27 06:20:11 PM UTC 24 |
| Peak memory | 215812 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=835936984 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_csb_read.835936984 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/23.spi_device_csb_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/23.spi_device_flash_all.679967011 |
| Short name | T558 |
| Test name | |
| Test status | |
| Simulation time | 1176839278 ps |
| CPU time | 32.73 seconds |
| Started | Aug 27 06:20:20 PM UTC 24 |
| Finished | Aug 27 06:20:54 PM UTC 24 |
| Peak memory | 251488 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=679967011 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/sp i_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_all.679967011 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/23.spi_device_flash_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/23.spi_device_flash_and_tpm.3638028492 |
| Short name | T654 |
| Test name | |
| Test status | |
| Simulation time | 44642063705 ps |
| CPU time | 198.92 seconds |
| Started | Aug 27 06:20:22 PM UTC 24 |
| Finished | Aug 27 06:23:44 PM UTC 24 |
| Peak memory | 261788 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3638028492 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_ 26/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_and_tpm.3638028492 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/23.spi_device_flash_and_tpm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/23.spi_device_flash_and_tpm_min_idle.3340945519 |
| Short name | T658 |
| Test name | |
| Test status | |
| Simulation time | 78950856319 ps |
| CPU time | 199.75 seconds |
| Started | Aug 27 06:20:26 PM UTC 24 |
| Finished | Aug 27 06:23:48 PM UTC 24 |
| Peak memory | 267932 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3340945519 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_26/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_and_tpm_min_idle.3340945519 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/23.spi_device_flash_and_tpm_min_idle/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/23.spi_device_flash_mode.474011676 |
| Short name | T544 |
| Test name | |
| Test status | |
| Simulation time | 268591360 ps |
| CPU time | 7.11 seconds |
| Started | Aug 27 06:20:17 PM UTC 24 |
| Finished | Aug 27 06:20:25 PM UTC 24 |
| Peak memory | 247264 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=474011676 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/s pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_mode.474011676 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/23.spi_device_flash_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/23.spi_device_flash_mode_ignore_cmds.3982798815 |
| Short name | T569 |
| Test name | |
| Test status | |
| Simulation time | 3906090077 ps |
| CPU time | 57.25 seconds |
| Started | Aug 27 06:20:19 PM UTC 24 |
| Finished | Aug 27 06:21:18 PM UTC 24 |
| Peak memory | 251544 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3982798815 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_26/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_mode_ignore_cmds.3982798815 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/23.spi_device_flash_mode_ignore_cmds/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/23.spi_device_intercept.3383154993 |
| Short name | T540 |
| Test name | |
| Test status | |
| Simulation time | 774442979 ps |
| CPU time | 7.58 seconds |
| Started | Aug 27 06:20:16 PM UTC 24 |
| Finished | Aug 27 06:20:24 PM UTC 24 |
| Peak memory | 245220 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3383154993 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/s pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_intercept.3383154993 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/23.spi_device_intercept/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/23.spi_device_mailbox.3400603487 |
| Short name | T542 |
| Test name | |
| Test status | |
| Simulation time | 542566819 ps |
| CPU time | 7.65 seconds |
| Started | Aug 27 06:20:16 PM UTC 24 |
| Finished | Aug 27 06:20:24 PM UTC 24 |
| Peak memory | 234960 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3400603487 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_mailbox.3400603487 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/23.spi_device_mailbox/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/23.spi_device_pass_addr_payload_swap.1093889043 |
| Short name | T549 |
| Test name | |
| Test status | |
| Simulation time | 1030727319 ps |
| CPU time | 16.36 seconds |
| Started | Aug 27 06:20:14 PM UTC 24 |
| Finished | Aug 27 06:20:32 PM UTC 24 |
| Peak memory | 245160 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1093889043 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_26/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_pass_addr_payload_swap.1093889043 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/23.spi_device_pass_addr_payload_swap/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/23.spi_device_pass_cmd_filtering.1529322498 |
| Short name | T232 |
| Test name | |
| Test status | |
| Simulation time | 2354425296 ps |
| CPU time | 3.54 seconds |
| Started | Aug 27 06:20:14 PM UTC 24 |
| Finished | Aug 27 06:20:19 PM UTC 24 |
| Peak memory | 235092 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1529322498 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_08_26/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_pass_cmd_filtering.1529322498 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/23.spi_device_pass_cmd_filtering/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/23.spi_device_read_buffer_direct.1603548089 |
| Short name | T551 |
| Test name | |
| Test status | |
| Simulation time | 649644806 ps |
| CPU time | 13.76 seconds |
| Started | Aug 27 06:20:19 PM UTC 24 |
| Finished | Aug 27 06:20:34 PM UTC 24 |
| Peak memory | 231260 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1603548089 -assert nopostproc +UVM_TESTNAME=spi_device _base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_read_buffer_direct.1603548089 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/23.spi_device_read_buffer_direct/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/23.spi_device_stress_all.1715692256 |
| Short name | T178 |
| Test name | |
| Test status | |
| Simulation time | 22835112461 ps |
| CPU time | 117.27 seconds |
| Started | Aug 27 06:20:26 PM UTC 24 |
| Finished | Aug 27 06:22:25 PM UTC 24 |
| Peak memory | 276180 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1715692256 -assert nopostproc +UVM_ TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_stress_all.1715692256 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/23.spi_device_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/23.spi_device_tpm_all.658792167 |
| Short name | T546 |
| Test name | |
| Test status | |
| Simulation time | 3214391373 ps |
| CPU time | 15.68 seconds |
| Started | Aug 27 06:20:12 PM UTC 24 |
| Finished | Aug 27 06:20:29 PM UTC 24 |
| Peak memory | 227584 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=658792167 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_all.658792167 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/23.spi_device_tpm_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/23.spi_device_tpm_read_hw_reg.1403230460 |
| Short name | T541 |
| Test name | |
| Test status | |
| Simulation time | 921270974 ps |
| CPU time | 11.7 seconds |
| Started | Aug 27 06:20:12 PM UTC 24 |
| Finished | Aug 27 06:20:24 PM UTC 24 |
| Peak memory | 227420 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1403230460 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_26/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_read_hw_reg.1403230460 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/23.spi_device_tpm_read_hw_reg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/23.spi_device_tpm_rw.157055731 |
| Short name | T537 |
| Test name | |
| Test status | |
| Simulation time | 247958386 ps |
| CPU time | 2.1 seconds |
| Started | Aug 27 06:20:13 PM UTC 24 |
| Finished | Aug 27 06:20:16 PM UTC 24 |
| Peak memory | 227424 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=157055731 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/spi_d evice_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_rw.157055731 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/23.spi_device_tpm_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/23.spi_device_tpm_sts_read.3337582963 |
| Short name | T534 |
| Test name | |
| Test status | |
| Simulation time | 77442006 ps |
| CPU time | 1.45 seconds |
| Started | Aug 27 06:20:12 PM UTC 24 |
| Finished | Aug 27 06:20:14 PM UTC 24 |
| Peak memory | 215872 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3337582963 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_2 6/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_sts_read.3337582963 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/23.spi_device_tpm_sts_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/23.spi_device_upload.675850750 |
| Short name | T543 |
| Test name | |
| Test status | |
| Simulation time | 155888209 ps |
| CPU time | 7.07 seconds |
| Started | Aug 27 06:20:17 PM UTC 24 |
| Finished | Aug 27 06:20:25 PM UTC 24 |
| Peak memory | 245164 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=675850750 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/spi_d evice_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_upload.675850750 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/23.spi_device_upload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/24.spi_device_alert_test.1679551625 |
| Short name | T560 |
| Test name | |
| Test status | |
| Simulation time | 12960773 ps |
| CPU time | 1.05 seconds |
| Started | Aug 27 06:20:58 PM UTC 24 |
| Finished | Aug 27 06:21:01 PM UTC 24 |
| Peak memory | 215804 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1679551625 -assert nopostproc +UVM_TES TNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_alert_test.1679551625 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/24.spi_device_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/24.spi_device_cfg_cmd.3739740356 |
| Short name | T556 |
| Test name | |
| Test status | |
| Simulation time | 436147312 ps |
| CPU time | 4.13 seconds |
| Started | Aug 27 06:20:38 PM UTC 24 |
| Finished | Aug 27 06:20:43 PM UTC 24 |
| Peak memory | 234996 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3739740356 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_cfg_cmd.3739740356 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/24.spi_device_cfg_cmd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/24.spi_device_csb_read.3228149508 |
| Short name | T547 |
| Test name | |
| Test status | |
| Simulation time | 52006858 ps |
| CPU time | 1.15 seconds |
| Started | Aug 27 06:20:27 PM UTC 24 |
| Finished | Aug 27 06:20:29 PM UTC 24 |
| Peak memory | 215812 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3228149508 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/sp i_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_csb_read.3228149508 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/24.spi_device_csb_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/24.spi_device_flash_all.2757236892 |
| Short name | T724 |
| Test name | |
| Test status | |
| Simulation time | 42668205493 ps |
| CPU time | 298.97 seconds |
| Started | Aug 27 06:20:40 PM UTC 24 |
| Finished | Aug 27 06:25:43 PM UTC 24 |
| Peak memory | 267860 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2757236892 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/s pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_all.2757236892 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/24.spi_device_flash_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/24.spi_device_flash_and_tpm.4228108245 |
| Short name | T587 |
| Test name | |
| Test status | |
| Simulation time | 24888681122 ps |
| CPU time | 75.68 seconds |
| Started | Aug 27 06:20:44 PM UTC 24 |
| Finished | Aug 27 06:22:01 PM UTC 24 |
| Peak memory | 263828 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4228108245 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_ 26/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_and_tpm.4228108245 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/24.spi_device_flash_and_tpm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/24.spi_device_flash_and_tpm_min_idle.538340387 |
| Short name | T614 |
| Test name | |
| Test status | |
| Simulation time | 39250979582 ps |
| CPU time | 105.52 seconds |
| Started | Aug 27 06:20:50 PM UTC 24 |
| Finished | Aug 27 06:22:38 PM UTC 24 |
| Peak memory | 245388 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=538340387 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_26/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_and_tpm_min_idle.538340387 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/24.spi_device_flash_and_tpm_min_idle/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/24.spi_device_flash_mode.2064704111 |
| Short name | T562 |
| Test name | |
| Test status | |
| Simulation time | 1121750740 ps |
| CPU time | 23.43 seconds |
| Started | Aug 27 06:20:39 PM UTC 24 |
| Finished | Aug 27 06:21:04 PM UTC 24 |
| Peak memory | 251424 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2064704111 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/ spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_mode.2064704111 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/24.spi_device_flash_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/24.spi_device_flash_mode_ignore_cmds.2613585487 |
| Short name | T632 |
| Test name | |
| Test status | |
| Simulation time | 13949073833 ps |
| CPU time | 136.62 seconds |
| Started | Aug 27 06:20:40 PM UTC 24 |
| Finished | Aug 27 06:22:59 PM UTC 24 |
| Peak memory | 251472 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2613585487 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_26/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_mode_ignore_cmds.2613585487 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/24.spi_device_flash_mode_ignore_cmds/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/24.spi_device_intercept.1725001100 |
| Short name | T559 |
| Test name | |
| Test status | |
| Simulation time | 7387510050 ps |
| CPU time | 21.81 seconds |
| Started | Aug 27 06:20:34 PM UTC 24 |
| Finished | Aug 27 06:20:57 PM UTC 24 |
| Peak memory | 241956 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1725001100 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/s pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_intercept.1725001100 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/24.spi_device_intercept/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/24.spi_device_mailbox.740145588 |
| Short name | T585 |
| Test name | |
| Test status | |
| Simulation time | 10172659218 ps |
| CPU time | 77.23 seconds |
| Started | Aug 27 06:20:34 PM UTC 24 |
| Finished | Aug 27 06:21:54 PM UTC 24 |
| Peak memory | 251488 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=740145588 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_mailbox.740145588 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/24.spi_device_mailbox/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/24.spi_device_pass_addr_payload_swap.1669490667 |
| Short name | T313 |
| Test name | |
| Test status | |
| Simulation time | 159915477 ps |
| CPU time | 5.8 seconds |
| Started | Aug 27 06:20:33 PM UTC 24 |
| Finished | Aug 27 06:20:40 PM UTC 24 |
| Peak memory | 245268 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1669490667 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_26/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_pass_addr_payload_swap.1669490667 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/24.spi_device_pass_addr_payload_swap/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/24.spi_device_pass_cmd_filtering.2844604689 |
| Short name | T553 |
| Test name | |
| Test status | |
| Simulation time | 1161795174 ps |
| CPU time | 3.54 seconds |
| Started | Aug 27 06:20:33 PM UTC 24 |
| Finished | Aug 27 06:20:37 PM UTC 24 |
| Peak memory | 234904 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2844604689 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_08_26/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_pass_cmd_filtering.2844604689 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/24.spi_device_pass_cmd_filtering/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/24.spi_device_read_buffer_direct.2110241116 |
| Short name | T557 |
| Test name | |
| Test status | |
| Simulation time | 334444360 ps |
| CPU time | 7.25 seconds |
| Started | Aug 27 06:20:40 PM UTC 24 |
| Finished | Aug 27 06:20:49 PM UTC 24 |
| Peak memory | 231260 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2110241116 -assert nopostproc +UVM_TESTNAME=spi_device _base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_read_buffer_direct.2110241116 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/24.spi_device_read_buffer_direct/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/24.spi_device_stress_all.2740530038 |
| Short name | T715 |
| Test name | |
| Test status | |
| Simulation time | 43232013985 ps |
| CPU time | 273.69 seconds |
| Started | Aug 27 06:20:55 PM UTC 24 |
| Finished | Aug 27 06:25:33 PM UTC 24 |
| Peak memory | 284316 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2740530038 -assert nopostproc +UVM_ TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_stress_all.2740530038 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/24.spi_device_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/24.spi_device_tpm_all.1743349908 |
| Short name | T564 |
| Test name | |
| Test status | |
| Simulation time | 7009490268 ps |
| CPU time | 37.13 seconds |
| Started | Aug 27 06:20:28 PM UTC 24 |
| Finished | Aug 27 06:21:07 PM UTC 24 |
| Peak memory | 227740 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1743349908 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_all.1743349908 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/24.spi_device_tpm_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/24.spi_device_tpm_read_hw_reg.1691456369 |
| Short name | T552 |
| Test name | |
| Test status | |
| Simulation time | 1701696603 ps |
| CPU time | 9.19 seconds |
| Started | Aug 27 06:20:27 PM UTC 24 |
| Finished | Aug 27 06:20:37 PM UTC 24 |
| Peak memory | 227476 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1691456369 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_26/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_read_hw_reg.1691456369 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/24.spi_device_tpm_read_hw_reg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/24.spi_device_tpm_rw.2261164845 |
| Short name | T550 |
| Test name | |
| Test status | |
| Simulation time | 63956511 ps |
| CPU time | 2.27 seconds |
| Started | Aug 27 06:20:30 PM UTC 24 |
| Finished | Aug 27 06:20:33 PM UTC 24 |
| Peak memory | 227544 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2261164845 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_rw.2261164845 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/24.spi_device_tpm_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/24.spi_device_tpm_sts_read.3606454380 |
| Short name | T548 |
| Test name | |
| Test status | |
| Simulation time | 137197040 ps |
| CPU time | 1.16 seconds |
| Started | Aug 27 06:20:30 PM UTC 24 |
| Finished | Aug 27 06:20:32 PM UTC 24 |
| Peak memory | 215872 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3606454380 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_2 6/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_sts_read.3606454380 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/24.spi_device_tpm_sts_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/24.spi_device_upload.2978422386 |
| Short name | T555 |
| Test name | |
| Test status | |
| Simulation time | 289299350 ps |
| CPU time | 3.43 seconds |
| Started | Aug 27 06:20:35 PM UTC 24 |
| Finished | Aug 27 06:20:39 PM UTC 24 |
| Peak memory | 245220 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2978422386 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_upload.2978422386 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/24.spi_device_upload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/25.spi_device_alert_test.1233638768 |
| Short name | T575 |
| Test name | |
| Test status | |
| Simulation time | 51739872 ps |
| CPU time | 1.04 seconds |
| Started | Aug 27 06:21:30 PM UTC 24 |
| Finished | Aug 27 06:21:32 PM UTC 24 |
| Peak memory | 215744 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1233638768 -assert nopostproc +UVM_TES TNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_alert_test.1233638768 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/25.spi_device_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/25.spi_device_cfg_cmd.2247835661 |
| Short name | T572 |
| Test name | |
| Test status | |
| Simulation time | 356021163 ps |
| CPU time | 7.55 seconds |
| Started | Aug 27 06:21:18 PM UTC 24 |
| Finished | Aug 27 06:21:26 PM UTC 24 |
| Peak memory | 234900 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2247835661 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_cfg_cmd.2247835661 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/25.spi_device_cfg_cmd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/25.spi_device_csb_read.4146199893 |
| Short name | T563 |
| Test name | |
| Test status | |
| Simulation time | 20044699 ps |
| CPU time | 1.17 seconds |
| Started | Aug 27 06:21:02 PM UTC 24 |
| Finished | Aug 27 06:21:04 PM UTC 24 |
| Peak memory | 215812 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4146199893 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/sp i_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_csb_read.4146199893 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/25.spi_device_csb_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/25.spi_device_flash_all.4096209865 |
| Short name | T600 |
| Test name | |
| Test status | |
| Simulation time | 4621315316 ps |
| CPU time | 56.75 seconds |
| Started | Aug 27 06:21:20 PM UTC 24 |
| Finished | Aug 27 06:22:19 PM UTC 24 |
| Peak memory | 249368 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4096209865 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/s pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_all.4096209865 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/25.spi_device_flash_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/25.spi_device_flash_and_tpm.3727451560 |
| Short name | T581 |
| Test name | |
| Test status | |
| Simulation time | 2076499567 ps |
| CPU time | 20.68 seconds |
| Started | Aug 27 06:21:21 PM UTC 24 |
| Finished | Aug 27 06:21:43 PM UTC 24 |
| Peak memory | 251444 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3727451560 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_ 26/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_and_tpm.3727451560 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/25.spi_device_flash_and_tpm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/25.spi_device_flash_and_tpm_min_idle.578503535 |
| Short name | T777 |
| Test name | |
| Test status | |
| Simulation time | 71889980587 ps |
| CPU time | 301.17 seconds |
| Started | Aug 27 06:21:27 PM UTC 24 |
| Finished | Aug 27 06:26:32 PM UTC 24 |
| Peak memory | 267912 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=578503535 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_26/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_and_tpm_min_idle.578503535 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/25.spi_device_flash_and_tpm_min_idle/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/25.spi_device_flash_mode.1544049174 |
| Short name | T352 |
| Test name | |
| Test status | |
| Simulation time | 289642386 ps |
| CPU time | 8.08 seconds |
| Started | Aug 27 06:21:19 PM UTC 24 |
| Finished | Aug 27 06:21:28 PM UTC 24 |
| Peak memory | 235088 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1544049174 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/ spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_mode.1544049174 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/25.spi_device_flash_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/25.spi_device_flash_mode_ignore_cmds.4108456153 |
| Short name | T622 |
| Test name | |
| Test status | |
| Simulation time | 45010104814 ps |
| CPU time | 84.66 seconds |
| Started | Aug 27 06:21:20 PM UTC 24 |
| Finished | Aug 27 06:22:47 PM UTC 24 |
| Peak memory | 265804 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4108456153 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_26/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_mode_ignore_cmds.4108456153 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/25.spi_device_flash_mode_ignore_cmds/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/25.spi_device_intercept.2339760856 |
| Short name | T235 |
| Test name | |
| Test status | |
| Simulation time | 6173322367 ps |
| CPU time | 8.08 seconds |
| Started | Aug 27 06:21:11 PM UTC 24 |
| Finished | Aug 27 06:21:21 PM UTC 24 |
| Peak memory | 235092 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2339760856 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/s pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_intercept.2339760856 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/25.spi_device_intercept/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/25.spi_device_mailbox.3854909724 |
| Short name | T312 |
| Test name | |
| Test status | |
| Simulation time | 273987309 ps |
| CPU time | 6 seconds |
| Started | Aug 27 06:21:12 PM UTC 24 |
| Finished | Aug 27 06:21:19 PM UTC 24 |
| Peak memory | 234896 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3854909724 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_mailbox.3854909724 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/25.spi_device_mailbox/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/25.spi_device_pass_addr_payload_swap.1193241330 |
| Short name | T568 |
| Test name | |
| Test status | |
| Simulation time | 694711781 ps |
| CPU time | 6.4 seconds |
| Started | Aug 27 06:21:09 PM UTC 24 |
| Finished | Aug 27 06:21:16 PM UTC 24 |
| Peak memory | 245156 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1193241330 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_26/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_pass_addr_payload_swap.1193241330 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/25.spi_device_pass_addr_payload_swap/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/25.spi_device_pass_cmd_filtering.135067222 |
| Short name | T573 |
| Test name | |
| Test status | |
| Simulation time | 1332611542 ps |
| CPU time | 18.5 seconds |
| Started | Aug 27 06:21:09 PM UTC 24 |
| Finished | Aug 27 06:21:28 PM UTC 24 |
| Peak memory | 245196 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=135067222 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _08_26/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_pass_cmd_filtering.135067222 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/25.spi_device_pass_cmd_filtering/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/25.spi_device_read_buffer_direct.2195391776 |
| Short name | T577 |
| Test name | |
| Test status | |
| Simulation time | 4307005648 ps |
| CPU time | 14.56 seconds |
| Started | Aug 27 06:21:20 PM UTC 24 |
| Finished | Aug 27 06:21:36 PM UTC 24 |
| Peak memory | 231380 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2195391776 -assert nopostproc +UVM_TESTNAME=spi_device _base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_read_buffer_direct.2195391776 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/25.spi_device_read_buffer_direct/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/25.spi_device_stress_all.1905332995 |
| Short name | T181 |
| Test name | |
| Test status | |
| Simulation time | 29631241456 ps |
| CPU time | 248.04 seconds |
| Started | Aug 27 06:21:29 PM UTC 24 |
| Finished | Aug 27 06:25:41 PM UTC 24 |
| Peak memory | 280268 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1905332995 -assert nopostproc +UVM_ TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_stress_all.1905332995 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/25.spi_device_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/25.spi_device_tpm_all.2179731044 |
| Short name | T565 |
| Test name | |
| Test status | |
| Simulation time | 38678800 ps |
| CPU time | 1.11 seconds |
| Started | Aug 27 06:21:05 PM UTC 24 |
| Finished | Aug 27 06:21:07 PM UTC 24 |
| Peak memory | 215748 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2179731044 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_all.2179731044 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/25.spi_device_tpm_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/25.spi_device_tpm_read_hw_reg.2497160167 |
| Short name | T574 |
| Test name | |
| Test status | |
| Simulation time | 5318192526 ps |
| CPU time | 24.93 seconds |
| Started | Aug 27 06:21:04 PM UTC 24 |
| Finished | Aug 27 06:21:30 PM UTC 24 |
| Peak memory | 227528 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2497160167 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_26/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_read_hw_reg.2497160167 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/25.spi_device_tpm_read_hw_reg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/25.spi_device_tpm_rw.2895752493 |
| Short name | T567 |
| Test name | |
| Test status | |
| Simulation time | 106804439 ps |
| CPU time | 1.81 seconds |
| Started | Aug 27 06:21:07 PM UTC 24 |
| Finished | Aug 27 06:21:10 PM UTC 24 |
| Peak memory | 226384 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2895752493 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_rw.2895752493 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/25.spi_device_tpm_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/25.spi_device_tpm_sts_read.3247503768 |
| Short name | T566 |
| Test name | |
| Test status | |
| Simulation time | 144623081 ps |
| CPU time | 1.27 seconds |
| Started | Aug 27 06:21:05 PM UTC 24 |
| Finished | Aug 27 06:21:07 PM UTC 24 |
| Peak memory | 215872 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3247503768 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_2 6/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_sts_read.3247503768 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/25.spi_device_tpm_sts_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/25.spi_device_upload.2992064976 |
| Short name | T571 |
| Test name | |
| Test status | |
| Simulation time | 162748032 ps |
| CPU time | 3.19 seconds |
| Started | Aug 27 06:21:15 PM UTC 24 |
| Finished | Aug 27 06:21:20 PM UTC 24 |
| Peak memory | 234968 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2992064976 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_upload.2992064976 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/25.spi_device_upload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/26.spi_device_alert_test.1893142105 |
| Short name | T589 |
| Test name | |
| Test status | |
| Simulation time | 11789851 ps |
| CPU time | 1.05 seconds |
| Started | Aug 27 06:22:03 PM UTC 24 |
| Finished | Aug 27 06:22:05 PM UTC 24 |
| Peak memory | 215804 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1893142105 -assert nopostproc +UVM_TES TNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_alert_test.1893142105 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/26.spi_device_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/26.spi_device_cfg_cmd.2502067535 |
| Short name | T214 |
| Test name | |
| Test status | |
| Simulation time | 291633820 ps |
| CPU time | 4 seconds |
| Started | Aug 27 06:21:50 PM UTC 24 |
| Finished | Aug 27 06:21:55 PM UTC 24 |
| Peak memory | 234960 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2502067535 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_cfg_cmd.2502067535 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/26.spi_device_cfg_cmd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/26.spi_device_csb_read.273525944 |
| Short name | T576 |
| Test name | |
| Test status | |
| Simulation time | 17879731 ps |
| CPU time | 1.12 seconds |
| Started | Aug 27 06:21:31 PM UTC 24 |
| Finished | Aug 27 06:21:33 PM UTC 24 |
| Peak memory | 215812 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=273525944 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_csb_read.273525944 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/26.spi_device_csb_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/26.spi_device_flash_all.324530942 |
| Short name | T610 |
| Test name | |
| Test status | |
| Simulation time | 7186003709 ps |
| CPU time | 38.66 seconds |
| Started | Aug 27 06:21:55 PM UTC 24 |
| Finished | Aug 27 06:22:35 PM UTC 24 |
| Peak memory | 261792 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=324530942 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/sp i_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_all.324530942 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/26.spi_device_flash_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/26.spi_device_flash_and_tpm.4023652502 |
| Short name | T842 |
| Test name | |
| Test status | |
| Simulation time | 67599492555 ps |
| CPU time | 332.82 seconds |
| Started | Aug 27 06:21:56 PM UTC 24 |
| Finished | Aug 27 06:27:33 PM UTC 24 |
| Peak memory | 284292 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4023652502 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_ 26/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_and_tpm.4023652502 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/26.spi_device_flash_and_tpm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/26.spi_device_flash_mode.2376767772 |
| Short name | T601 |
| Test name | |
| Test status | |
| Simulation time | 1153302060 ps |
| CPU time | 26.02 seconds |
| Started | Aug 27 06:21:53 PM UTC 24 |
| Finished | Aug 27 06:22:20 PM UTC 24 |
| Peak memory | 245196 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2376767772 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/ spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_mode.2376767772 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/26.spi_device_flash_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/26.spi_device_intercept.792708918 |
| Short name | T591 |
| Test name | |
| Test status | |
| Simulation time | 4094967122 ps |
| CPU time | 22.17 seconds |
| Started | Aug 27 06:21:43 PM UTC 24 |
| Finished | Aug 27 06:22:06 PM UTC 24 |
| Peak memory | 245284 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=792708918 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/sp i_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_intercept.792708918 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/26.spi_device_intercept/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/26.spi_device_mailbox.172746406 |
| Short name | T582 |
| Test name | |
| Test status | |
| Simulation time | 103240499 ps |
| CPU time | 3 seconds |
| Started | Aug 27 06:21:45 PM UTC 24 |
| Finished | Aug 27 06:21:49 PM UTC 24 |
| Peak memory | 234672 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=172746406 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_mailbox.172746406 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/26.spi_device_mailbox/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/26.spi_device_pass_addr_payload_swap.1278453381 |
| Short name | T609 |
| Test name | |
| Test status | |
| Simulation time | 94270997679 ps |
| CPU time | 51.93 seconds |
| Started | Aug 27 06:21:40 PM UTC 24 |
| Finished | Aug 27 06:22:34 PM UTC 24 |
| Peak memory | 235036 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1278453381 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_26/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_pass_addr_payload_swap.1278453381 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/26.spi_device_pass_addr_payload_swap/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/26.spi_device_pass_cmd_filtering.1326852654 |
| Short name | T583 |
| Test name | |
| Test status | |
| Simulation time | 16224091382 ps |
| CPU time | 12.83 seconds |
| Started | Aug 27 06:21:38 PM UTC 24 |
| Finished | Aug 27 06:21:52 PM UTC 24 |
| Peak memory | 245336 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1326852654 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_08_26/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_pass_cmd_filtering.1326852654 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/26.spi_device_pass_cmd_filtering/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/26.spi_device_read_buffer_direct.2172088292 |
| Short name | T588 |
| Test name | |
| Test status | |
| Simulation time | 619989344 ps |
| CPU time | 6.36 seconds |
| Started | Aug 27 06:21:54 PM UTC 24 |
| Finished | Aug 27 06:22:02 PM UTC 24 |
| Peak memory | 233564 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2172088292 -assert nopostproc +UVM_TESTNAME=spi_device _base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_read_buffer_direct.2172088292 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/26.spi_device_read_buffer_direct/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/26.spi_device_stress_all.2845670018 |
| Short name | T613 |
| Test name | |
| Test status | |
| Simulation time | 5975556902 ps |
| CPU time | 34.73 seconds |
| Started | Aug 27 06:22:01 PM UTC 24 |
| Finished | Aug 27 06:22:37 PM UTC 24 |
| Peak memory | 235092 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2845670018 -assert nopostproc +UVM_ TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_stress_all.2845670018 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/26.spi_device_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/26.spi_device_tpm_all.706465188 |
| Short name | T584 |
| Test name | |
| Test status | |
| Simulation time | 9655259421 ps |
| CPU time | 17.96 seconds |
| Started | Aug 27 06:21:34 PM UTC 24 |
| Finished | Aug 27 06:21:53 PM UTC 24 |
| Peak memory | 227612 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=706465188 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_all.706465188 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/26.spi_device_tpm_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/26.spi_device_tpm_read_hw_reg.2046215512 |
| Short name | T593 |
| Test name | |
| Test status | |
| Simulation time | 6815977073 ps |
| CPU time | 34.09 seconds |
| Started | Aug 27 06:21:34 PM UTC 24 |
| Finished | Aug 27 06:22:09 PM UTC 24 |
| Peak memory | 227548 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2046215512 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_26/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_read_hw_reg.2046215512 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/26.spi_device_tpm_read_hw_reg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/26.spi_device_tpm_rw.1353575245 |
| Short name | T579 |
| Test name | |
| Test status | |
| Simulation time | 42138753 ps |
| CPU time | 1.74 seconds |
| Started | Aug 27 06:21:37 PM UTC 24 |
| Finished | Aug 27 06:21:40 PM UTC 24 |
| Peak memory | 226768 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1353575245 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_rw.1353575245 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/26.spi_device_tpm_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/26.spi_device_tpm_sts_read.3047523473 |
| Short name | T578 |
| Test name | |
| Test status | |
| Simulation time | 16646324 ps |
| CPU time | 1.11 seconds |
| Started | Aug 27 06:21:35 PM UTC 24 |
| Finished | Aug 27 06:21:37 PM UTC 24 |
| Peak memory | 215872 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3047523473 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_2 6/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_sts_read.3047523473 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/26.spi_device_tpm_sts_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/26.spi_device_upload.1775493082 |
| Short name | T586 |
| Test name | |
| Test status | |
| Simulation time | 1329134649 ps |
| CPU time | 8.11 seconds |
| Started | Aug 27 06:21:46 PM UTC 24 |
| Finished | Aug 27 06:21:55 PM UTC 24 |
| Peak memory | 245140 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1775493082 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_upload.1775493082 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/26.spi_device_upload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/27.spi_device_alert_test.996822924 |
| Short name | T605 |
| Test name | |
| Test status | |
| Simulation time | 38152893 ps |
| CPU time | 1.08 seconds |
| Started | Aug 27 06:22:27 PM UTC 24 |
| Finished | Aug 27 06:22:29 PM UTC 24 |
| Peak memory | 215684 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=996822924 -assert nopostproc +UVM_TEST NAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_alert_test.996822924 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/27.spi_device_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/27.spi_device_cfg_cmd.3975114507 |
| Short name | T599 |
| Test name | |
| Test status | |
| Simulation time | 30515812 ps |
| CPU time | 2.75 seconds |
| Started | Aug 27 06:22:15 PM UTC 24 |
| Finished | Aug 27 06:22:19 PM UTC 24 |
| Peak memory | 234084 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3975114507 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_cfg_cmd.3975114507 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/27.spi_device_cfg_cmd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/27.spi_device_csb_read.3617263300 |
| Short name | T590 |
| Test name | |
| Test status | |
| Simulation time | 121506258 ps |
| CPU time | 1.07 seconds |
| Started | Aug 27 06:22:03 PM UTC 24 |
| Finished | Aug 27 06:22:05 PM UTC 24 |
| Peak memory | 215580 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3617263300 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/sp i_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_csb_read.3617263300 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/27.spi_device_csb_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/27.spi_device_flash_all.1816485827 |
| Short name | T666 |
| Test name | |
| Test status | |
| Simulation time | 12229276295 ps |
| CPU time | 97.93 seconds |
| Started | Aug 27 06:22:21 PM UTC 24 |
| Finished | Aug 27 06:24:01 PM UTC 24 |
| Peak memory | 261792 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1816485827 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/s pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_all.1816485827 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/27.spi_device_flash_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/27.spi_device_flash_and_tpm.2160655676 |
| Short name | T669 |
| Test name | |
| Test status | |
| Simulation time | 23165652965 ps |
| CPU time | 103.63 seconds |
| Started | Aug 27 06:22:24 PM UTC 24 |
| Finished | Aug 27 06:24:10 PM UTC 24 |
| Peak memory | 261748 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2160655676 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_ 26/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_and_tpm.2160655676 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/27.spi_device_flash_and_tpm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/27.spi_device_flash_and_tpm_min_idle.2919719218 |
| Short name | T748 |
| Test name | |
| Test status | |
| Simulation time | 123101493863 ps |
| CPU time | 216.94 seconds |
| Started | Aug 27 06:22:27 PM UTC 24 |
| Finished | Aug 27 06:26:07 PM UTC 24 |
| Peak memory | 276116 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2919719218 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_26/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_and_tpm_min_idle.2919719218 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/27.spi_device_flash_and_tpm_min_idle/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/27.spi_device_flash_mode.4102197928 |
| Short name | T606 |
| Test name | |
| Test status | |
| Simulation time | 1056296525 ps |
| CPU time | 11.87 seconds |
| Started | Aug 27 06:22:18 PM UTC 24 |
| Finished | Aug 27 06:22:31 PM UTC 24 |
| Peak memory | 245260 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4102197928 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/ spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_mode.4102197928 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/27.spi_device_flash_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/27.spi_device_flash_mode_ignore_cmds.3265083968 |
| Short name | T693 |
| Test name | |
| Test status | |
| Simulation time | 80053720757 ps |
| CPU time | 154.75 seconds |
| Started | Aug 27 06:22:20 PM UTC 24 |
| Finished | Aug 27 06:24:57 PM UTC 24 |
| Peak memory | 267860 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3265083968 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_26/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_mode_ignore_cmds.3265083968 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/27.spi_device_flash_mode_ignore_cmds/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/27.spi_device_intercept.2800606101 |
| Short name | T607 |
| Test name | |
| Test status | |
| Simulation time | 16311846514 ps |
| CPU time | 18.13 seconds |
| Started | Aug 27 06:22:12 PM UTC 24 |
| Finished | Aug 27 06:22:31 PM UTC 24 |
| Peak memory | 245332 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2800606101 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/s pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_intercept.2800606101 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/27.spi_device_intercept/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/27.spi_device_mailbox.3999627032 |
| Short name | T598 |
| Test name | |
| Test status | |
| Simulation time | 58524375 ps |
| CPU time | 2.84 seconds |
| Started | Aug 27 06:22:13 PM UTC 24 |
| Finished | Aug 27 06:22:17 PM UTC 24 |
| Peak memory | 233660 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3999627032 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_mailbox.3999627032 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/27.spi_device_mailbox/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/27.spi_device_pass_addr_payload_swap.3199940808 |
| Short name | T602 |
| Test name | |
| Test status | |
| Simulation time | 4686050837 ps |
| CPU time | 11.36 seconds |
| Started | Aug 27 06:22:11 PM UTC 24 |
| Finished | Aug 27 06:22:23 PM UTC 24 |
| Peak memory | 247340 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3199940808 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_26/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_pass_addr_payload_swap.3199940808 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/27.spi_device_pass_addr_payload_swap/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/27.spi_device_pass_cmd_filtering.2960149737 |
| Short name | T603 |
| Test name | |
| Test status | |
| Simulation time | 2438303618 ps |
| CPU time | 13.06 seconds |
| Started | Aug 27 06:22:11 PM UTC 24 |
| Finished | Aug 27 06:22:25 PM UTC 24 |
| Peak memory | 245340 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2960149737 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_08_26/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_pass_cmd_filtering.2960149737 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/27.spi_device_pass_cmd_filtering/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/27.spi_device_read_buffer_direct.1551222543 |
| Short name | T604 |
| Test name | |
| Test status | |
| Simulation time | 101382543 ps |
| CPU time | 5.38 seconds |
| Started | Aug 27 06:22:20 PM UTC 24 |
| Finished | Aug 27 06:22:26 PM UTC 24 |
| Peak memory | 233568 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1551222543 -assert nopostproc +UVM_TESTNAME=spi_device _base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_read_buffer_direct.1551222543 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/27.spi_device_read_buffer_direct/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/27.spi_device_stress_all.2700193254 |
| Short name | T180 |
| Test name | |
| Test status | |
| Simulation time | 70647623711 ps |
| CPU time | 173.04 seconds |
| Started | Aug 27 06:22:27 PM UTC 24 |
| Finished | Aug 27 06:25:23 PM UTC 24 |
| Peak memory | 261796 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2700193254 -assert nopostproc +UVM_ TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_stress_all.2700193254 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/27.spi_device_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/27.spi_device_tpm_all.2074271190 |
| Short name | T596 |
| Test name | |
| Test status | |
| Simulation time | 3282942199 ps |
| CPU time | 5.51 seconds |
| Started | Aug 27 06:22:06 PM UTC 24 |
| Finished | Aug 27 06:22:13 PM UTC 24 |
| Peak memory | 229600 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2074271190 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_all.2074271190 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/27.spi_device_tpm_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/27.spi_device_tpm_read_hw_reg.1535267100 |
| Short name | T592 |
| Test name | |
| Test status | |
| Simulation time | 14918028 ps |
| CPU time | 1.07 seconds |
| Started | Aug 27 06:22:06 PM UTC 24 |
| Finished | Aug 27 06:22:08 PM UTC 24 |
| Peak memory | 215804 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1535267100 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_26/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_read_hw_reg.1535267100 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/27.spi_device_tpm_read_hw_reg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/27.spi_device_tpm_rw.3643844198 |
| Short name | T595 |
| Test name | |
| Test status | |
| Simulation time | 341548150 ps |
| CPU time | 2.17 seconds |
| Started | Aug 27 06:22:09 PM UTC 24 |
| Finished | Aug 27 06:22:12 PM UTC 24 |
| Peak memory | 227392 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3643844198 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_rw.3643844198 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/27.spi_device_tpm_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/27.spi_device_tpm_sts_read.2485028272 |
| Short name | T594 |
| Test name | |
| Test status | |
| Simulation time | 46714427 ps |
| CPU time | 0.9 seconds |
| Started | Aug 27 06:22:08 PM UTC 24 |
| Finished | Aug 27 06:22:10 PM UTC 24 |
| Peak memory | 215872 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2485028272 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_2 6/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_sts_read.2485028272 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/27.spi_device_tpm_sts_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/27.spi_device_upload.1749077743 |
| Short name | T618 |
| Test name | |
| Test status | |
| Simulation time | 17929783787 ps |
| CPU time | 26.92 seconds |
| Started | Aug 27 06:22:15 PM UTC 24 |
| Finished | Aug 27 06:22:43 PM UTC 24 |
| Peak memory | 251484 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1749077743 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_upload.1749077743 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/27.spi_device_upload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/28.spi_device_alert_test.241650751 |
| Short name | T624 |
| Test name | |
| Test status | |
| Simulation time | 17719511 ps |
| CPU time | 1.03 seconds |
| Started | Aug 27 06:22:46 PM UTC 24 |
| Finished | Aug 27 06:22:49 PM UTC 24 |
| Peak memory | 215744 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=241650751 -assert nopostproc +UVM_TEST NAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_alert_test.241650751 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/28.spi_device_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/28.spi_device_cfg_cmd.4245047406 |
| Short name | T631 |
| Test name | |
| Test status | |
| Simulation time | 1680519057 ps |
| CPU time | 17.08 seconds |
| Started | Aug 27 06:22:39 PM UTC 24 |
| Finished | Aug 27 06:22:57 PM UTC 24 |
| Peak memory | 245240 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4245047406 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_cfg_cmd.4245047406 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/28.spi_device_cfg_cmd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/28.spi_device_csb_read.620121047 |
| Short name | T608 |
| Test name | |
| Test status | |
| Simulation time | 16562411 ps |
| CPU time | 1.12 seconds |
| Started | Aug 27 06:22:30 PM UTC 24 |
| Finished | Aug 27 06:22:32 PM UTC 24 |
| Peak memory | 215520 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=620121047 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_csb_read.620121047 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/28.spi_device_csb_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/28.spi_device_flash_all.937077113 |
| Short name | T302 |
| Test name | |
| Test status | |
| Simulation time | 2089821671 ps |
| CPU time | 39.44 seconds |
| Started | Aug 27 06:22:42 PM UTC 24 |
| Finished | Aug 27 06:23:23 PM UTC 24 |
| Peak memory | 261444 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=937077113 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/sp i_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_all.937077113 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/28.spi_device_flash_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/28.spi_device_flash_and_tpm.2562087464 |
| Short name | T634 |
| Test name | |
| Test status | |
| Simulation time | 636124432 ps |
| CPU time | 19.4 seconds |
| Started | Aug 27 06:22:45 PM UTC 24 |
| Finished | Aug 27 06:23:06 PM UTC 24 |
| Peak memory | 245328 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2562087464 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_ 26/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_and_tpm.2562087464 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/28.spi_device_flash_and_tpm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/28.spi_device_flash_and_tpm_min_idle.3496943660 |
| Short name | T668 |
| Test name | |
| Test status | |
| Simulation time | 5451178783 ps |
| CPU time | 80.88 seconds |
| Started | Aug 27 06:22:45 PM UTC 24 |
| Finished | Aug 27 06:24:08 PM UTC 24 |
| Peak memory | 261812 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3496943660 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_26/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_and_tpm_min_idle.3496943660 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/28.spi_device_flash_and_tpm_min_idle/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/28.spi_device_flash_mode.4189847432 |
| Short name | T353 |
| Test name | |
| Test status | |
| Simulation time | 681849240 ps |
| CPU time | 8.79 seconds |
| Started | Aug 27 06:22:39 PM UTC 24 |
| Finished | Aug 27 06:22:49 PM UTC 24 |
| Peak memory | 234856 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4189847432 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/ spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_mode.4189847432 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/28.spi_device_flash_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/28.spi_device_flash_mode_ignore_cmds.2155560107 |
| Short name | T651 |
| Test name | |
| Test status | |
| Simulation time | 8384654349 ps |
| CPU time | 52.75 seconds |
| Started | Aug 27 06:22:40 PM UTC 24 |
| Finished | Aug 27 06:23:35 PM UTC 24 |
| Peak memory | 265872 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2155560107 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_26/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_mode_ignore_cmds.2155560107 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/28.spi_device_flash_mode_ignore_cmds/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/28.spi_device_intercept.2270949149 |
| Short name | T621 |
| Test name | |
| Test status | |
| Simulation time | 1125615450 ps |
| CPU time | 8.49 seconds |
| Started | Aug 27 06:22:36 PM UTC 24 |
| Finished | Aug 27 06:22:46 PM UTC 24 |
| Peak memory | 234964 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2270949149 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/s pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_intercept.2270949149 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/28.spi_device_intercept/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/28.spi_device_mailbox.3227052406 |
| Short name | T616 |
| Test name | |
| Test status | |
| Simulation time | 174509163 ps |
| CPU time | 2.84 seconds |
| Started | Aug 27 06:22:36 PM UTC 24 |
| Finished | Aug 27 06:22:40 PM UTC 24 |
| Peak memory | 244940 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3227052406 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_mailbox.3227052406 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/28.spi_device_mailbox/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/28.spi_device_pass_addr_payload_swap.2310959933 |
| Short name | T617 |
| Test name | |
| Test status | |
| Simulation time | 140331467 ps |
| CPU time | 3.02 seconds |
| Started | Aug 27 06:22:36 PM UTC 24 |
| Finished | Aug 27 06:22:40 PM UTC 24 |
| Peak memory | 234284 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2310959933 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_26/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_pass_addr_payload_swap.2310959933 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/28.spi_device_pass_addr_payload_swap/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/28.spi_device_pass_cmd_filtering.20825349 |
| Short name | T615 |
| Test name | |
| Test status | |
| Simulation time | 248801289 ps |
| CPU time | 3.22 seconds |
| Started | Aug 27 06:22:35 PM UTC 24 |
| Finished | Aug 27 06:22:39 PM UTC 24 |
| Peak memory | 245204 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=20825349 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_26/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_pass_cmd_filtering.20825349 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/28.spi_device_pass_cmd_filtering/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/28.spi_device_read_buffer_direct.3673123379 |
| Short name | T623 |
| Test name | |
| Test status | |
| Simulation time | 209670833 ps |
| CPU time | 4.05 seconds |
| Started | Aug 27 06:22:42 PM UTC 24 |
| Finished | Aug 27 06:22:47 PM UTC 24 |
| Peak memory | 231156 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3673123379 -assert nopostproc +UVM_TESTNAME=spi_device _base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_read_buffer_direct.3673123379 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/28.spi_device_read_buffer_direct/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/28.spi_device_stress_all.1588536108 |
| Short name | T306 |
| Test name | |
| Test status | |
| Simulation time | 51313547737 ps |
| CPU time | 178.45 seconds |
| Started | Aug 27 06:22:45 PM UTC 24 |
| Finished | Aug 27 06:25:46 PM UTC 24 |
| Peak memory | 265872 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1588536108 -assert nopostproc +UVM_ TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_stress_all.1588536108 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/28.spi_device_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/28.spi_device_tpm_all.426919443 |
| Short name | T639 |
| Test name | |
| Test status | |
| Simulation time | 4728243720 ps |
| CPU time | 35.82 seconds |
| Started | Aug 27 06:22:33 PM UTC 24 |
| Finished | Aug 27 06:23:10 PM UTC 24 |
| Peak memory | 227628 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=426919443 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_all.426919443 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/28.spi_device_tpm_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/28.spi_device_tpm_read_hw_reg.3641363356 |
| Short name | T620 |
| Test name | |
| Test status | |
| Simulation time | 2652797220 ps |
| CPU time | 10.61 seconds |
| Started | Aug 27 06:22:33 PM UTC 24 |
| Finished | Aug 27 06:22:45 PM UTC 24 |
| Peak memory | 227556 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3641363356 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_26/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_read_hw_reg.3641363356 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/28.spi_device_tpm_read_hw_reg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/28.spi_device_tpm_rw.2535496093 |
| Short name | T612 |
| Test name | |
| Test status | |
| Simulation time | 30631332 ps |
| CPU time | 1.09 seconds |
| Started | Aug 27 06:22:33 PM UTC 24 |
| Finished | Aug 27 06:22:35 PM UTC 24 |
| Peak memory | 215868 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2535496093 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_rw.2535496093 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/28.spi_device_tpm_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/28.spi_device_tpm_sts_read.1779365167 |
| Short name | T611 |
| Test name | |
| Test status | |
| Simulation time | 79276454 ps |
| CPU time | 1.14 seconds |
| Started | Aug 27 06:22:33 PM UTC 24 |
| Finished | Aug 27 06:22:35 PM UTC 24 |
| Peak memory | 215872 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1779365167 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_2 6/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_sts_read.1779365167 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/28.spi_device_tpm_sts_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/28.spi_device_upload.590929692 |
| Short name | T619 |
| Test name | |
| Test status | |
| Simulation time | 241033923 ps |
| CPU time | 5.07 seconds |
| Started | Aug 27 06:22:38 PM UTC 24 |
| Finished | Aug 27 06:22:44 PM UTC 24 |
| Peak memory | 235032 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=590929692 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/spi_d evice_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_upload.590929692 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/28.spi_device_upload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/29.spi_device_alert_test.159661827 |
| Short name | T640 |
| Test name | |
| Test status | |
| Simulation time | 36951822 ps |
| CPU time | 1.08 seconds |
| Started | Aug 27 06:23:10 PM UTC 24 |
| Finished | Aug 27 06:23:12 PM UTC 24 |
| Peak memory | 215396 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=159661827 -assert nopostproc +UVM_TEST NAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_alert_test.159661827 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/29.spi_device_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/29.spi_device_cfg_cmd.3455764280 |
| Short name | T635 |
| Test name | |
| Test status | |
| Simulation time | 1841728293 ps |
| CPU time | 8.02 seconds |
| Started | Aug 27 06:22:57 PM UTC 24 |
| Finished | Aug 27 06:23:06 PM UTC 24 |
| Peak memory | 234900 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3455764280 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_cfg_cmd.3455764280 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/29.spi_device_cfg_cmd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/29.spi_device_csb_read.1056740634 |
| Short name | T625 |
| Test name | |
| Test status | |
| Simulation time | 34187401 ps |
| CPU time | 1.15 seconds |
| Started | Aug 27 06:22:46 PM UTC 24 |
| Finished | Aug 27 06:22:49 PM UTC 24 |
| Peak memory | 215812 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1056740634 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/sp i_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_csb_read.1056740634 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/29.spi_device_csb_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/29.spi_device_flash_all.2156518418 |
| Short name | T659 |
| Test name | |
| Test status | |
| Simulation time | 2571580005 ps |
| CPU time | 41.62 seconds |
| Started | Aug 27 06:23:05 PM UTC 24 |
| Finished | Aug 27 06:23:48 PM UTC 24 |
| Peak memory | 251556 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2156518418 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/s pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_all.2156518418 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/29.spi_device_flash_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/29.spi_device_flash_and_tpm.675089036 |
| Short name | T157 |
| Test name | |
| Test status | |
| Simulation time | 46012801814 ps |
| CPU time | 156.67 seconds |
| Started | Aug 27 06:23:06 PM UTC 24 |
| Finished | Aug 27 06:25:46 PM UTC 24 |
| Peak memory | 267908 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=675089036 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_2 6/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_and_tpm.675089036 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/29.spi_device_flash_and_tpm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/29.spi_device_flash_and_tpm_min_idle.279698634 |
| Short name | T346 |
| Test name | |
| Test status | |
| Simulation time | 101670889280 ps |
| CPU time | 109.24 seconds |
| Started | Aug 27 06:23:08 PM UTC 24 |
| Finished | Aug 27 06:24:59 PM UTC 24 |
| Peak memory | 278200 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=279698634 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_26/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_and_tpm_min_idle.279698634 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/29.spi_device_flash_and_tpm_min_idle/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/29.spi_device_flash_mode.2132712314 |
| Short name | T636 |
| Test name | |
| Test status | |
| Simulation time | 616405462 ps |
| CPU time | 9.02 seconds |
| Started | Aug 27 06:22:57 PM UTC 24 |
| Finished | Aug 27 06:23:07 PM UTC 24 |
| Peak memory | 234964 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2132712314 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/ spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_mode.2132712314 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/29.spi_device_flash_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/29.spi_device_intercept.3716156482 |
| Short name | T633 |
| Test name | |
| Test status | |
| Simulation time | 1008600745 ps |
| CPU time | 10.52 seconds |
| Started | Aug 27 06:22:52 PM UTC 24 |
| Finished | Aug 27 06:23:04 PM UTC 24 |
| Peak memory | 234980 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3716156482 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/s pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_intercept.3716156482 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/29.spi_device_intercept/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/29.spi_device_mailbox.739406091 |
| Short name | T649 |
| Test name | |
| Test status | |
| Simulation time | 14743428937 ps |
| CPU time | 33.78 seconds |
| Started | Aug 27 06:22:54 PM UTC 24 |
| Finished | Aug 27 06:23:30 PM UTC 24 |
| Peak memory | 249432 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=739406091 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_mailbox.739406091 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/29.spi_device_mailbox/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/29.spi_device_pass_addr_payload_swap.1510608779 |
| Short name | T629 |
| Test name | |
| Test status | |
| Simulation time | 626361954 ps |
| CPU time | 3.49 seconds |
| Started | Aug 27 06:22:51 PM UTC 24 |
| Finished | Aug 27 06:22:56 PM UTC 24 |
| Peak memory | 234900 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1510608779 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_26/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_pass_addr_payload_swap.1510608779 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/29.spi_device_pass_addr_payload_swap/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/29.spi_device_pass_cmd_filtering.2362450708 |
| Short name | T628 |
| Test name | |
| Test status | |
| Simulation time | 279482379 ps |
| CPU time | 3.06 seconds |
| Started | Aug 27 06:22:51 PM UTC 24 |
| Finished | Aug 27 06:22:55 PM UTC 24 |
| Peak memory | 234076 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2362450708 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_08_26/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_pass_cmd_filtering.2362450708 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/29.spi_device_pass_cmd_filtering/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/29.spi_device_read_buffer_direct.2446928499 |
| Short name | T638 |
| Test name | |
| Test status | |
| Simulation time | 523433329 ps |
| CPU time | 7.14 seconds |
| Started | Aug 27 06:23:01 PM UTC 24 |
| Finished | Aug 27 06:23:09 PM UTC 24 |
| Peak memory | 233728 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2446928499 -assert nopostproc +UVM_TESTNAME=spi_device _base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_read_buffer_direct.2446928499 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/29.spi_device_read_buffer_direct/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/29.spi_device_stress_all.3655980874 |
| Short name | T675 |
| Test name | |
| Test status | |
| Simulation time | 2693332374 ps |
| CPU time | 64.88 seconds |
| Started | Aug 27 06:23:09 PM UTC 24 |
| Finished | Aug 27 06:24:15 PM UTC 24 |
| Peak memory | 278160 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3655980874 -assert nopostproc +UVM_ TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_stress_all.3655980874 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/29.spi_device_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/29.spi_device_tpm_all.1514251604 |
| Short name | T646 |
| Test name | |
| Test status | |
| Simulation time | 18709800766 ps |
| CPU time | 32.87 seconds |
| Started | Aug 27 06:22:49 PM UTC 24 |
| Finished | Aug 27 06:23:23 PM UTC 24 |
| Peak memory | 227696 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1514251604 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_all.1514251604 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/29.spi_device_tpm_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/29.spi_device_tpm_read_hw_reg.1024738701 |
| Short name | T626 |
| Test name | |
| Test status | |
| Simulation time | 28307821 ps |
| CPU time | 1.07 seconds |
| Started | Aug 27 06:22:48 PM UTC 24 |
| Finished | Aug 27 06:22:50 PM UTC 24 |
| Peak memory | 215804 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1024738701 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_26/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_read_hw_reg.1024738701 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/29.spi_device_tpm_read_hw_reg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/29.spi_device_tpm_rw.3943086844 |
| Short name | T630 |
| Test name | |
| Test status | |
| Simulation time | 443898182 ps |
| CPU time | 3.91 seconds |
| Started | Aug 27 06:22:51 PM UTC 24 |
| Finished | Aug 27 06:22:56 PM UTC 24 |
| Peak memory | 227420 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3943086844 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_rw.3943086844 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/29.spi_device_tpm_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/29.spi_device_tpm_sts_read.3961357453 |
| Short name | T627 |
| Test name | |
| Test status | |
| Simulation time | 28161384 ps |
| CPU time | 1.11 seconds |
| Started | Aug 27 06:22:51 PM UTC 24 |
| Finished | Aug 27 06:22:53 PM UTC 24 |
| Peak memory | 215872 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3961357453 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_2 6/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_sts_read.3961357453 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/29.spi_device_tpm_sts_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/29.spi_device_upload.452699994 |
| Short name | T650 |
| Test name | |
| Test status | |
| Simulation time | 23317707869 ps |
| CPU time | 34.46 seconds |
| Started | Aug 27 06:22:57 PM UTC 24 |
| Finished | Aug 27 06:23:33 PM UTC 24 |
| Peak memory | 245400 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=452699994 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/spi_d evice_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_upload.452699994 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/29.spi_device_upload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/3.spi_device_alert_test.74066430 |
| Short name | T379 |
| Test name | |
| Test status | |
| Simulation time | 11772434 ps |
| CPU time | 1.12 seconds |
| Started | Aug 27 06:11:34 PM UTC 24 |
| Finished | Aug 27 06:11:36 PM UTC 24 |
| Peak memory | 215680 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=74066430 -assert nopostproc +UVM_TESTN AME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_alert_test.74066430 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/3.spi_device_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/3.spi_device_cfg_cmd.1104018497 |
| Short name | T119 |
| Test name | |
| Test status | |
| Simulation time | 2653543495 ps |
| CPU time | 31.22 seconds |
| Started | Aug 27 06:10:58 PM UTC 24 |
| Finished | Aug 27 06:11:30 PM UTC 24 |
| Peak memory | 245288 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1104018497 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_cfg_cmd.1104018497 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/3.spi_device_cfg_cmd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/3.spi_device_csb_read.1252996900 |
| Short name | T378 |
| Test name | |
| Test status | |
| Simulation time | 89819302 ps |
| CPU time | 0.98 seconds |
| Started | Aug 27 06:10:40 PM UTC 24 |
| Finished | Aug 27 06:10:42 PM UTC 24 |
| Peak memory | 215808 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1252996900 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/sp i_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_csb_read.1252996900 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/3.spi_device_csb_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/3.spi_device_flash_all.2625026109 |
| Short name | T59 |
| Test name | |
| Test status | |
| Simulation time | 4650492798 ps |
| CPU time | 20.13 seconds |
| Started | Aug 27 06:11:11 PM UTC 24 |
| Finished | Aug 27 06:11:32 PM UTC 24 |
| Peak memory | 247332 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2625026109 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/s pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_all.2625026109 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/3.spi_device_flash_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/3.spi_device_flash_and_tpm.2443444228 |
| Short name | T70 |
| Test name | |
| Test status | |
| Simulation time | 46906241484 ps |
| CPU time | 270.03 seconds |
| Started | Aug 27 06:11:18 PM UTC 24 |
| Finished | Aug 27 06:15:53 PM UTC 24 |
| Peak memory | 261904 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2443444228 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_ 26/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_and_tpm.2443444228 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/3.spi_device_flash_and_tpm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/3.spi_device_flash_and_tpm_min_idle.2825300344 |
| Short name | T63 |
| Test name | |
| Test status | |
| Simulation time | 18142964442 ps |
| CPU time | 68.36 seconds |
| Started | Aug 27 06:11:21 PM UTC 24 |
| Finished | Aug 27 06:12:31 PM UTC 24 |
| Peak memory | 267912 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2825300344 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_26/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_and_tpm_min_idle.2825300344 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/3.spi_device_flash_and_tpm_min_idle/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/3.spi_device_flash_mode.2534193988 |
| Short name | T108 |
| Test name | |
| Test status | |
| Simulation time | 1573547554 ps |
| CPU time | 8.24 seconds |
| Started | Aug 27 06:10:59 PM UTC 24 |
| Finished | Aug 27 06:11:08 PM UTC 24 |
| Peak memory | 245212 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2534193988 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/ spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_mode.2534193988 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/3.spi_device_flash_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/3.spi_device_flash_mode_ignore_cmds.639706667 |
| Short name | T192 |
| Test name | |
| Test status | |
| Simulation time | 44844166331 ps |
| CPU time | 259.1 seconds |
| Started | Aug 27 06:10:59 PM UTC 24 |
| Finished | Aug 27 06:15:22 PM UTC 24 |
| Peak memory | 263784 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=639706667 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_26/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_mode_ignore_cmds.639706667 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/3.spi_device_flash_mode_ignore_cmds/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/3.spi_device_intercept.3149965839 |
| Short name | T106 |
| Test name | |
| Test status | |
| Simulation time | 134589532 ps |
| CPU time | 4.31 seconds |
| Started | Aug 27 06:10:52 PM UTC 24 |
| Finished | Aug 27 06:10:57 PM UTC 24 |
| Peak memory | 235040 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3149965839 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/s pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_intercept.3149965839 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/3.spi_device_intercept/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/3.spi_device_mailbox.3934670336 |
| Short name | T216 |
| Test name | |
| Test status | |
| Simulation time | 9413126036 ps |
| CPU time | 53.89 seconds |
| Started | Aug 27 06:10:53 PM UTC 24 |
| Finished | Aug 27 06:11:49 PM UTC 24 |
| Peak memory | 245344 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3934670336 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_mailbox.3934670336 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/3.spi_device_mailbox/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/3.spi_device_pass_addr_payload_swap.3687940539 |
| Short name | T107 |
| Test name | |
| Test status | |
| Simulation time | 258971972 ps |
| CPU time | 5.55 seconds |
| Started | Aug 27 06:10:51 PM UTC 24 |
| Finished | Aug 27 06:10:58 PM UTC 24 |
| Peak memory | 234912 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3687940539 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_26/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_pass_addr_payload_swap.3687940539 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/3.spi_device_pass_addr_payload_swap/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/3.spi_device_pass_cmd_filtering.3438749686 |
| Short name | T244 |
| Test name | |
| Test status | |
| Simulation time | 54057898609 ps |
| CPU time | 52.23 seconds |
| Started | Aug 27 06:10:51 PM UTC 24 |
| Finished | Aug 27 06:11:45 PM UTC 24 |
| Peak memory | 261712 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3438749686 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_08_26/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_pass_cmd_filtering.3438749686 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/3.spi_device_pass_cmd_filtering/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/3.spi_device_read_buffer_direct.4030303485 |
| Short name | T109 |
| Test name | |
| Test status | |
| Simulation time | 991065326 ps |
| CPU time | 6.86 seconds |
| Started | Aug 27 06:11:09 PM UTC 24 |
| Finished | Aug 27 06:11:17 PM UTC 24 |
| Peak memory | 231268 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4030303485 -assert nopostproc +UVM_TESTNAME=spi_device _base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_read_buffer_direct.4030303485 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/3.spi_device_read_buffer_direct/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/3.spi_device_sec_cm.1140317782 |
| Short name | T22 |
| Test name | |
| Test status | |
| Simulation time | 115700545 ps |
| CPU time | 1.47 seconds |
| Started | Aug 27 06:11:31 PM UTC 24 |
| Finished | Aug 27 06:11:34 PM UTC 24 |
| Peak memory | 257920 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1140317782 -assert nopostproc +UVM_TEST NAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_sec_cm.1140317782 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/3.spi_device_sec_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/3.spi_device_stress_all.349753733 |
| Short name | T325 |
| Test name | |
| Test status | |
| Simulation time | 249296581605 ps |
| CPU time | 606.53 seconds |
| Started | Aug 27 06:11:31 PM UTC 24 |
| Finished | Aug 27 06:21:45 PM UTC 24 |
| Peak memory | 280176 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=349753733 -assert nopostproc +UVM_T ESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_stress_all.349753733 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/3.spi_device_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/3.spi_device_tpm_all.1715022286 |
| Short name | T42 |
| Test name | |
| Test status | |
| Simulation time | 591673635 ps |
| CPU time | 6.31 seconds |
| Started | Aug 27 06:10:44 PM UTC 24 |
| Finished | Aug 27 06:10:51 PM UTC 24 |
| Peak memory | 227416 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1715022286 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_all.1715022286 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/3.spi_device_tpm_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/3.spi_device_tpm_read_hw_reg.276332512 |
| Short name | T105 |
| Test name | |
| Test status | |
| Simulation time | 983197473 ps |
| CPU time | 12.32 seconds |
| Started | Aug 27 06:10:44 PM UTC 24 |
| Finished | Aug 27 06:10:57 PM UTC 24 |
| Peak memory | 227500 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=276332512 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08 _26/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_read_hw_reg.276332512 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/3.spi_device_tpm_read_hw_reg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/3.spi_device_tpm_rw.4042812510 |
| Short name | T43 |
| Test name | |
| Test status | |
| Simulation time | 536595326 ps |
| CPU time | 4.16 seconds |
| Started | Aug 27 06:10:47 PM UTC 24 |
| Finished | Aug 27 06:10:52 PM UTC 24 |
| Peak memory | 227416 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4042812510 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_rw.4042812510 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/3.spi_device_tpm_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/3.spi_device_tpm_sts_read.1767218056 |
| Short name | T67 |
| Test name | |
| Test status | |
| Simulation time | 114872493 ps |
| CPU time | 1.74 seconds |
| Started | Aug 27 06:10:44 PM UTC 24 |
| Finished | Aug 27 06:10:46 PM UTC 24 |
| Peak memory | 215868 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1767218056 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_2 6/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_sts_read.1767218056 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/3.spi_device_tpm_sts_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/3.spi_device_upload.3525570409 |
| Short name | T110 |
| Test name | |
| Test status | |
| Simulation time | 949354688 ps |
| CPU time | 21.29 seconds |
| Started | Aug 27 06:10:57 PM UTC 24 |
| Finished | Aug 27 06:11:20 PM UTC 24 |
| Peak memory | 261608 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3525570409 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_upload.3525570409 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/3.spi_device_upload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/30.spi_device_alert_test.3064793569 |
| Short name | T655 |
| Test name | |
| Test status | |
| Simulation time | 92489873 ps |
| CPU time | 1.09 seconds |
| Started | Aug 27 06:23:45 PM UTC 24 |
| Finished | Aug 27 06:23:47 PM UTC 24 |
| Peak memory | 215740 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3064793569 -assert nopostproc +UVM_TES TNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_alert_test.3064793569 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/30.spi_device_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/30.spi_device_cfg_cmd.1750106733 |
| Short name | T652 |
| Test name | |
| Test status | |
| Simulation time | 941054330 ps |
| CPU time | 14.1 seconds |
| Started | Aug 27 06:23:26 PM UTC 24 |
| Finished | Aug 27 06:23:41 PM UTC 24 |
| Peak memory | 245328 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1750106733 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_cfg_cmd.1750106733 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/30.spi_device_cfg_cmd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/30.spi_device_csb_read.2058185899 |
| Short name | T641 |
| Test name | |
| Test status | |
| Simulation time | 59729721 ps |
| CPU time | 1.14 seconds |
| Started | Aug 27 06:23:10 PM UTC 24 |
| Finished | Aug 27 06:23:13 PM UTC 24 |
| Peak memory | 215516 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2058185899 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/sp i_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_csb_read.2058185899 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/30.spi_device_csb_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/30.spi_device_flash_all.3408662352 |
| Short name | T663 |
| Test name | |
| Test status | |
| Simulation time | 9299277226 ps |
| CPU time | 20.36 seconds |
| Started | Aug 27 06:23:32 PM UTC 24 |
| Finished | Aug 27 06:23:54 PM UTC 24 |
| Peak memory | 247440 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3408662352 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/s pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_all.3408662352 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/30.spi_device_flash_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/30.spi_device_flash_and_tpm.3372789796 |
| Short name | T158 |
| Test name | |
| Test status | |
| Simulation time | 11643388427 ps |
| CPU time | 142.83 seconds |
| Started | Aug 27 06:23:34 PM UTC 24 |
| Finished | Aug 27 06:25:59 PM UTC 24 |
| Peak memory | 265868 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3372789796 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_ 26/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_and_tpm.3372789796 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/30.spi_device_flash_and_tpm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/30.spi_device_flash_and_tpm_min_idle.82791752 |
| Short name | T347 |
| Test name | |
| Test status | |
| Simulation time | 68865288594 ps |
| CPU time | 181.58 seconds |
| Started | Aug 27 06:23:36 PM UTC 24 |
| Finished | Aug 27 06:26:41 PM UTC 24 |
| Peak memory | 261788 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=82791752 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_26/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_and_tpm_min_idle.82791752 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/30.spi_device_flash_and_tpm_min_idle/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/30.spi_device_flash_mode.3845726941 |
| Short name | T653 |
| Test name | |
| Test status | |
| Simulation time | 798830255 ps |
| CPU time | 14.83 seconds |
| Started | Aug 27 06:23:28 PM UTC 24 |
| Finished | Aug 27 06:23:43 PM UTC 24 |
| Peak memory | 245216 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3845726941 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/ spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_mode.3845726941 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/30.spi_device_flash_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/30.spi_device_flash_mode_ignore_cmds.4129198449 |
| Short name | T885 |
| Test name | |
| Test status | |
| Simulation time | 73898041228 ps |
| CPU time | 297.91 seconds |
| Started | Aug 27 06:23:29 PM UTC 24 |
| Finished | Aug 27 06:28:31 PM UTC 24 |
| Peak memory | 261716 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4129198449 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_26/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_mode_ignore_cmds.4129198449 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/30.spi_device_flash_mode_ignore_cmds/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/30.spi_device_intercept.1347617435 |
| Short name | T648 |
| Test name | |
| Test status | |
| Simulation time | 333158666 ps |
| CPU time | 3.19 seconds |
| Started | Aug 27 06:23:23 PM UTC 24 |
| Finished | Aug 27 06:23:28 PM UTC 24 |
| Peak memory | 234904 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1347617435 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/s pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_intercept.1347617435 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/30.spi_device_intercept/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/30.spi_device_mailbox.4239114308 |
| Short name | T752 |
| Test name | |
| Test status | |
| Simulation time | 71511332477 ps |
| CPU time | 161.15 seconds |
| Started | Aug 27 06:23:25 PM UTC 24 |
| Finished | Aug 27 06:26:09 PM UTC 24 |
| Peak memory | 261712 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4239114308 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_mailbox.4239114308 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/30.spi_device_mailbox/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/30.spi_device_pass_addr_payload_swap.3399434847 |
| Short name | T647 |
| Test name | |
| Test status | |
| Simulation time | 136737516 ps |
| CPU time | 3.26 seconds |
| Started | Aug 27 06:23:21 PM UTC 24 |
| Finished | Aug 27 06:23:25 PM UTC 24 |
| Peak memory | 234924 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3399434847 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_26/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_pass_addr_payload_swap.3399434847 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/30.spi_device_pass_addr_payload_swap/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/30.spi_device_pass_cmd_filtering.2004639300 |
| Short name | T660 |
| Test name | |
| Test status | |
| Simulation time | 7627413649 ps |
| CPU time | 31.19 seconds |
| Started | Aug 27 06:23:19 PM UTC 24 |
| Finished | Aug 27 06:23:51 PM UTC 24 |
| Peak memory | 247340 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2004639300 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_08_26/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_pass_cmd_filtering.2004639300 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/30.spi_device_pass_cmd_filtering/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/30.spi_device_read_buffer_direct.560572629 |
| Short name | T657 |
| Test name | |
| Test status | |
| Simulation time | 908730319 ps |
| CPU time | 15.67 seconds |
| Started | Aug 27 06:23:31 PM UTC 24 |
| Finished | Aug 27 06:23:48 PM UTC 24 |
| Peak memory | 233440 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=560572629 -assert nopostproc +UVM_TESTNAME=spi_device_ base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_read_buffer_direct.560572629 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/30.spi_device_read_buffer_direct/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/30.spi_device_tpm_all.3332283994 |
| Short name | T645 |
| Test name | |
| Test status | |
| Simulation time | 688292244 ps |
| CPU time | 7.37 seconds |
| Started | Aug 27 06:23:14 PM UTC 24 |
| Finished | Aug 27 06:23:23 PM UTC 24 |
| Peak memory | 227456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3332283994 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_all.3332283994 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/30.spi_device_tpm_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/30.spi_device_tpm_read_hw_reg.1909852049 |
| Short name | T643 |
| Test name | |
| Test status | |
| Simulation time | 2623164966 ps |
| CPU time | 5.6 seconds |
| Started | Aug 27 06:23:12 PM UTC 24 |
| Finished | Aug 27 06:23:18 PM UTC 24 |
| Peak memory | 227552 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1909852049 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_26/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_read_hw_reg.1909852049 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/30.spi_device_tpm_read_hw_reg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/30.spi_device_tpm_rw.1778025351 |
| Short name | T644 |
| Test name | |
| Test status | |
| Simulation time | 118428891 ps |
| CPU time | 1.64 seconds |
| Started | Aug 27 06:23:17 PM UTC 24 |
| Finished | Aug 27 06:23:20 PM UTC 24 |
| Peak memory | 226384 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1778025351 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_rw.1778025351 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/30.spi_device_tpm_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/30.spi_device_tpm_sts_read.3712434882 |
| Short name | T642 |
| Test name | |
| Test status | |
| Simulation time | 25128612 ps |
| CPU time | 1.03 seconds |
| Started | Aug 27 06:23:14 PM UTC 24 |
| Finished | Aug 27 06:23:16 PM UTC 24 |
| Peak memory | 215872 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3712434882 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_2 6/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_sts_read.3712434882 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/30.spi_device_tpm_sts_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/30.spi_device_upload.1635891379 |
| Short name | T223 |
| Test name | |
| Test status | |
| Simulation time | 3761911646 ps |
| CPU time | 23.73 seconds |
| Started | Aug 27 06:23:25 PM UTC 24 |
| Finished | Aug 27 06:23:50 PM UTC 24 |
| Peak memory | 261788 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1635891379 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_upload.1635891379 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/30.spi_device_upload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/31.spi_device_alert_test.2087752164 |
| Short name | T672 |
| Test name | |
| Test status | |
| Simulation time | 46409824 ps |
| CPU time | 1.07 seconds |
| Started | Aug 27 06:24:11 PM UTC 24 |
| Finished | Aug 27 06:24:13 PM UTC 24 |
| Peak memory | 215680 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2087752164 -assert nopostproc +UVM_TES TNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_alert_test.2087752164 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/31.spi_device_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/31.spi_device_cfg_cmd.4199237291 |
| Short name | T671 |
| Test name | |
| Test status | |
| Simulation time | 2155623511 ps |
| CPU time | 14.94 seconds |
| Started | Aug 27 06:23:56 PM UTC 24 |
| Finished | Aug 27 06:24:12 PM UTC 24 |
| Peak memory | 245216 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4199237291 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_cfg_cmd.4199237291 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/31.spi_device_cfg_cmd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/31.spi_device_csb_read.423068936 |
| Short name | T656 |
| Test name | |
| Test status | |
| Simulation time | 12780945 ps |
| CPU time | 1.12 seconds |
| Started | Aug 27 06:23:46 PM UTC 24 |
| Finished | Aug 27 06:23:48 PM UTC 24 |
| Peak memory | 215808 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=423068936 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_csb_read.423068936 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/31.spi_device_csb_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/31.spi_device_flash_all.3376921448 |
| Short name | T793 |
| Test name | |
| Test status | |
| Simulation time | 87432648796 ps |
| CPU time | 164.11 seconds |
| Started | Aug 27 06:24:03 PM UTC 24 |
| Finished | Aug 27 06:26:50 PM UTC 24 |
| Peak memory | 263768 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3376921448 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/s pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_all.3376921448 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/31.spi_device_flash_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/31.spi_device_flash_and_tpm.1572129746 |
| Short name | T344 |
| Test name | |
| Test status | |
| Simulation time | 88730019314 ps |
| CPU time | 233.09 seconds |
| Started | Aug 27 06:24:08 PM UTC 24 |
| Finished | Aug 27 06:28:04 PM UTC 24 |
| Peak memory | 265884 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1572129746 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_ 26/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_and_tpm.1572129746 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/31.spi_device_flash_and_tpm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/31.spi_device_flash_and_tpm_min_idle.1538971064 |
| Short name | T992 |
| Test name | |
| Test status | |
| Simulation time | 875497392787 ps |
| CPU time | 463.61 seconds |
| Started | Aug 27 06:24:09 PM UTC 24 |
| Finished | Aug 27 06:31:58 PM UTC 24 |
| Peak memory | 282188 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1538971064 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_26/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_and_tpm_min_idle.1538971064 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/31.spi_device_flash_and_tpm_min_idle/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/31.spi_device_flash_mode.2268560926 |
| Short name | T674 |
| Test name | |
| Test status | |
| Simulation time | 620679833 ps |
| CPU time | 17.21 seconds |
| Started | Aug 27 06:23:56 PM UTC 24 |
| Finished | Aug 27 06:24:14 PM UTC 24 |
| Peak memory | 261712 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2268560926 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/ spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_mode.2268560926 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/31.spi_device_flash_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/31.spi_device_flash_mode_ignore_cmds.2086657424 |
| Short name | T342 |
| Test name | |
| Test status | |
| Simulation time | 15242120980 ps |
| CPU time | 38.59 seconds |
| Started | Aug 27 06:23:57 PM UTC 24 |
| Finished | Aug 27 06:24:37 PM UTC 24 |
| Peak memory | 261716 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2086657424 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_26/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_mode_ignore_cmds.2086657424 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/31.spi_device_flash_mode_ignore_cmds/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/31.spi_device_intercept.3085414119 |
| Short name | T667 |
| Test name | |
| Test status | |
| Simulation time | 5771318965 ps |
| CPU time | 12.65 seconds |
| Started | Aug 27 06:23:53 PM UTC 24 |
| Finished | Aug 27 06:24:07 PM UTC 24 |
| Peak memory | 243960 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3085414119 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/s pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_intercept.3085414119 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/31.spi_device_intercept/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/31.spi_device_mailbox.1055132777 |
| Short name | T737 |
| Test name | |
| Test status | |
| Simulation time | 66336339277 ps |
| CPU time | 124.52 seconds |
| Started | Aug 27 06:23:53 PM UTC 24 |
| Finished | Aug 27 06:26:00 PM UTC 24 |
| Peak memory | 267852 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1055132777 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_mailbox.1055132777 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/31.spi_device_mailbox/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/31.spi_device_pass_addr_payload_swap.1682245024 |
| Short name | T333 |
| Test name | |
| Test status | |
| Simulation time | 73814400513 ps |
| CPU time | 20.32 seconds |
| Started | Aug 27 06:23:51 PM UTC 24 |
| Finished | Aug 27 06:24:13 PM UTC 24 |
| Peak memory | 235096 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1682245024 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_26/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_pass_addr_payload_swap.1682245024 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/31.spi_device_pass_addr_payload_swap/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/31.spi_device_pass_cmd_filtering.4094893379 |
| Short name | T664 |
| Test name | |
| Test status | |
| Simulation time | 255177936 ps |
| CPU time | 3.51 seconds |
| Started | Aug 27 06:23:50 PM UTC 24 |
| Finished | Aug 27 06:23:55 PM UTC 24 |
| Peak memory | 234904 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4094893379 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_08_26/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_pass_cmd_filtering.4094893379 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/31.spi_device_pass_cmd_filtering/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/31.spi_device_read_buffer_direct.1384135071 |
| Short name | T677 |
| Test name | |
| Test status | |
| Simulation time | 1756853021 ps |
| CPU time | 15.07 seconds |
| Started | Aug 27 06:24:02 PM UTC 24 |
| Finished | Aug 27 06:24:18 PM UTC 24 |
| Peak memory | 233596 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1384135071 -assert nopostproc +UVM_TESTNAME=spi_device _base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_read_buffer_direct.1384135071 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/31.spi_device_read_buffer_direct/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/31.spi_device_stress_all.2259458127 |
| Short name | T711 |
| Test name | |
| Test status | |
| Simulation time | 8237559079 ps |
| CPU time | 75.79 seconds |
| Started | Aug 27 06:24:09 PM UTC 24 |
| Finished | Aug 27 06:25:27 PM UTC 24 |
| Peak memory | 249476 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2259458127 -assert nopostproc +UVM_ TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_stress_all.2259458127 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/31.spi_device_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/31.spi_device_tpm_all.2079428101 |
| Short name | T685 |
| Test name | |
| Test status | |
| Simulation time | 31363812115 ps |
| CPU time | 43.35 seconds |
| Started | Aug 27 06:23:50 PM UTC 24 |
| Finished | Aug 27 06:24:35 PM UTC 24 |
| Peak memory | 227692 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2079428101 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_all.2079428101 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/31.spi_device_tpm_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/31.spi_device_tpm_read_hw_reg.2258737881 |
| Short name | T665 |
| Test name | |
| Test status | |
| Simulation time | 487059978 ps |
| CPU time | 6.17 seconds |
| Started | Aug 27 06:23:48 PM UTC 24 |
| Finished | Aug 27 06:23:55 PM UTC 24 |
| Peak memory | 227448 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2258737881 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_26/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_read_hw_reg.2258737881 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/31.spi_device_tpm_read_hw_reg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/31.spi_device_tpm_rw.4117010166 |
| Short name | T662 |
| Test name | |
| Test status | |
| Simulation time | 213836892 ps |
| CPU time | 1.97 seconds |
| Started | Aug 27 06:23:50 PM UTC 24 |
| Finished | Aug 27 06:23:53 PM UTC 24 |
| Peak memory | 226700 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4117010166 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_rw.4117010166 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/31.spi_device_tpm_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/31.spi_device_tpm_sts_read.2554606431 |
| Short name | T661 |
| Test name | |
| Test status | |
| Simulation time | 16860064 ps |
| CPU time | 1.12 seconds |
| Started | Aug 27 06:23:50 PM UTC 24 |
| Finished | Aug 27 06:23:52 PM UTC 24 |
| Peak memory | 215872 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2554606431 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_2 6/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_sts_read.2554606431 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/31.spi_device_tpm_sts_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/31.spi_device_upload.131437316 |
| Short name | T670 |
| Test name | |
| Test status | |
| Simulation time | 22945368434 ps |
| CPU time | 14.84 seconds |
| Started | Aug 27 06:23:54 PM UTC 24 |
| Finished | Aug 27 06:24:10 PM UTC 24 |
| Peak memory | 235112 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=131437316 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/spi_d evice_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_upload.131437316 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/31.spi_device_upload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/32.spi_device_alert_test.178949802 |
| Short name | T687 |
| Test name | |
| Test status | |
| Simulation time | 13019023 ps |
| CPU time | 1.08 seconds |
| Started | Aug 27 06:24:36 PM UTC 24 |
| Finished | Aug 27 06:24:38 PM UTC 24 |
| Peak memory | 215744 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=178949802 -assert nopostproc +UVM_TEST NAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_alert_test.178949802 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/32.spi_device_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/32.spi_device_cfg_cmd.3826186070 |
| Short name | T682 |
| Test name | |
| Test status | |
| Simulation time | 36889576 ps |
| CPU time | 3.19 seconds |
| Started | Aug 27 06:24:20 PM UTC 24 |
| Finished | Aug 27 06:24:25 PM UTC 24 |
| Peak memory | 245200 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3826186070 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_cfg_cmd.3826186070 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/32.spi_device_cfg_cmd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/32.spi_device_csb_read.763337690 |
| Short name | T673 |
| Test name | |
| Test status | |
| Simulation time | 96082941 ps |
| CPU time | 1.16 seconds |
| Started | Aug 27 06:24:11 PM UTC 24 |
| Finished | Aug 27 06:24:13 PM UTC 24 |
| Peak memory | 215520 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=763337690 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_csb_read.763337690 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/32.spi_device_csb_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/32.spi_device_flash_all.2337641631 |
| Short name | T702 |
| Test name | |
| Test status | |
| Simulation time | 22798768215 ps |
| CPU time | 54.97 seconds |
| Started | Aug 27 06:24:22 PM UTC 24 |
| Finished | Aug 27 06:25:18 PM UTC 24 |
| Peak memory | 251472 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2337641631 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/s pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_all.2337641631 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/32.spi_device_flash_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/32.spi_device_flash_and_tpm.2054703537 |
| Short name | T328 |
| Test name | |
| Test status | |
| Simulation time | 3005439985 ps |
| CPU time | 99.25 seconds |
| Started | Aug 27 06:24:25 PM UTC 24 |
| Finished | Aug 27 06:26:07 PM UTC 24 |
| Peak memory | 265860 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2054703537 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_ 26/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_and_tpm.2054703537 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/32.spi_device_flash_and_tpm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/32.spi_device_flash_and_tpm_min_idle.1356463621 |
| Short name | T754 |
| Test name | |
| Test status | |
| Simulation time | 4190675283 ps |
| CPU time | 97.92 seconds |
| Started | Aug 27 06:24:29 PM UTC 24 |
| Finished | Aug 27 06:26:10 PM UTC 24 |
| Peak memory | 267988 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1356463621 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_26/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_and_tpm_min_idle.1356463621 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/32.spi_device_flash_and_tpm_min_idle/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/32.spi_device_flash_mode.2894156153 |
| Short name | T684 |
| Test name | |
| Test status | |
| Simulation time | 429273942 ps |
| CPU time | 7.42 seconds |
| Started | Aug 27 06:24:20 PM UTC 24 |
| Finished | Aug 27 06:24:29 PM UTC 24 |
| Peak memory | 235024 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2894156153 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/ spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_mode.2894156153 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/32.spi_device_flash_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/32.spi_device_flash_mode_ignore_cmds.4242639798 |
| Short name | T343 |
| Test name | |
| Test status | |
| Simulation time | 210193654962 ps |
| CPU time | 290.1 seconds |
| Started | Aug 27 06:24:21 PM UTC 24 |
| Finished | Aug 27 06:29:15 PM UTC 24 |
| Peak memory | 267988 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4242639798 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_26/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_mode_ignore_cmds.4242639798 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/32.spi_device_flash_mode_ignore_cmds/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/32.spi_device_intercept.3898419603 |
| Short name | T691 |
| Test name | |
| Test status | |
| Simulation time | 12679347744 ps |
| CPU time | 32.53 seconds |
| Started | Aug 27 06:24:17 PM UTC 24 |
| Finished | Aug 27 06:24:51 PM UTC 24 |
| Peak memory | 245332 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3898419603 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/s pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_intercept.3898419603 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/32.spi_device_intercept/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/32.spi_device_mailbox.1351814532 |
| Short name | T690 |
| Test name | |
| Test status | |
| Simulation time | 2115715267 ps |
| CPU time | 28.74 seconds |
| Started | Aug 27 06:24:17 PM UTC 24 |
| Finished | Aug 27 06:24:47 PM UTC 24 |
| Peak memory | 249300 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1351814532 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_mailbox.1351814532 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/32.spi_device_mailbox/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/32.spi_device_pass_addr_payload_swap.2029085424 |
| Short name | T681 |
| Test name | |
| Test status | |
| Simulation time | 32761458 ps |
| CPU time | 2.73 seconds |
| Started | Aug 27 06:24:17 PM UTC 24 |
| Finished | Aug 27 06:24:21 PM UTC 24 |
| Peak memory | 234168 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2029085424 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_26/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_pass_addr_payload_swap.2029085424 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/32.spi_device_pass_addr_payload_swap/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/32.spi_device_pass_cmd_filtering.496332360 |
| Short name | T680 |
| Test name | |
| Test status | |
| Simulation time | 685175160 ps |
| CPU time | 2.86 seconds |
| Started | Aug 27 06:24:15 PM UTC 24 |
| Finished | Aug 27 06:24:19 PM UTC 24 |
| Peak memory | 245216 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=496332360 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _08_26/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_pass_cmd_filtering.496332360 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/32.spi_device_pass_cmd_filtering/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/32.spi_device_read_buffer_direct.1653551455 |
| Short name | T683 |
| Test name | |
| Test status | |
| Simulation time | 438802149 ps |
| CPU time | 5.79 seconds |
| Started | Aug 27 06:24:21 PM UTC 24 |
| Finished | Aug 27 06:24:27 PM UTC 24 |
| Peak memory | 233360 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1653551455 -assert nopostproc +UVM_TESTNAME=spi_device _base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_read_buffer_direct.1653551455 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/32.spi_device_read_buffer_direct/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/32.spi_device_stress_all.2522777300 |
| Short name | T764 |
| Test name | |
| Test status | |
| Simulation time | 68739404683 ps |
| CPU time | 107.42 seconds |
| Started | Aug 27 06:24:30 PM UTC 24 |
| Finished | Aug 27 06:26:19 PM UTC 24 |
| Peak memory | 265860 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2522777300 -assert nopostproc +UVM_ TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_stress_all.2522777300 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/32.spi_device_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/32.spi_device_tpm_all.1021474967 |
| Short name | T700 |
| Test name | |
| Test status | |
| Simulation time | 28363954297 ps |
| CPU time | 55.8 seconds |
| Started | Aug 27 06:24:15 PM UTC 24 |
| Finished | Aug 27 06:25:13 PM UTC 24 |
| Peak memory | 231664 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1021474967 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_all.1021474967 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/32.spi_device_tpm_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/32.spi_device_tpm_read_hw_reg.1604272088 |
| Short name | T678 |
| Test name | |
| Test status | |
| Simulation time | 933762256 ps |
| CPU time | 4.38 seconds |
| Started | Aug 27 06:24:13 PM UTC 24 |
| Finished | Aug 27 06:24:19 PM UTC 24 |
| Peak memory | 227428 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1604272088 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_26/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_read_hw_reg.1604272088 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/32.spi_device_tpm_read_hw_reg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/32.spi_device_tpm_rw.2141196894 |
| Short name | T679 |
| Test name | |
| Test status | |
| Simulation time | 208119758 ps |
| CPU time | 2.83 seconds |
| Started | Aug 27 06:24:15 PM UTC 24 |
| Finished | Aug 27 06:24:19 PM UTC 24 |
| Peak memory | 227544 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2141196894 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_rw.2141196894 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/32.spi_device_tpm_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/32.spi_device_tpm_sts_read.2400859007 |
| Short name | T676 |
| Test name | |
| Test status | |
| Simulation time | 40783258 ps |
| CPU time | 1.09 seconds |
| Started | Aug 27 06:24:15 PM UTC 24 |
| Finished | Aug 27 06:24:17 PM UTC 24 |
| Peak memory | 215872 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2400859007 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_2 6/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_sts_read.2400859007 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/32.spi_device_tpm_sts_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/32.spi_device_upload.1737691539 |
| Short name | T686 |
| Test name | |
| Test status | |
| Simulation time | 20393277529 ps |
| CPU time | 18.42 seconds |
| Started | Aug 27 06:24:18 PM UTC 24 |
| Finished | Aug 27 06:24:38 PM UTC 24 |
| Peak memory | 249380 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1737691539 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_upload.1737691539 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/32.spi_device_upload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/33.spi_device_alert_test.3670447147 |
| Short name | T704 |
| Test name | |
| Test status | |
| Simulation time | 40644752 ps |
| CPU time | 0.94 seconds |
| Started | Aug 27 06:25:20 PM UTC 24 |
| Finished | Aug 27 06:25:22 PM UTC 24 |
| Peak memory | 215804 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3670447147 -assert nopostproc +UVM_TES TNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_alert_test.3670447147 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/33.spi_device_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/33.spi_device_cfg_cmd.2223223596 |
| Short name | T707 |
| Test name | |
| Test status | |
| Simulation time | 1553378098 ps |
| CPU time | 22.46 seconds |
| Started | Aug 27 06:25:00 PM UTC 24 |
| Finished | Aug 27 06:25:24 PM UTC 24 |
| Peak memory | 245216 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2223223596 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_cfg_cmd.2223223596 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/33.spi_device_cfg_cmd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/33.spi_device_csb_read.3566803713 |
| Short name | T688 |
| Test name | |
| Test status | |
| Simulation time | 14962704 ps |
| CPU time | 1.14 seconds |
| Started | Aug 27 06:24:38 PM UTC 24 |
| Finished | Aug 27 06:24:41 PM UTC 24 |
| Peak memory | 215808 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3566803713 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/sp i_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_csb_read.3566803713 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/33.spi_device_csb_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/33.spi_device_flash_all.211935102 |
| Short name | T248 |
| Test name | |
| Test status | |
| Simulation time | 2541771958 ps |
| CPU time | 56.6 seconds |
| Started | Aug 27 06:25:09 PM UTC 24 |
| Finished | Aug 27 06:26:07 PM UTC 24 |
| Peak memory | 251548 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=211935102 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/sp i_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_all.211935102 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/33.spi_device_flash_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/33.spi_device_flash_and_tpm.1046980080 |
| Short name | T712 |
| Test name | |
| Test status | |
| Simulation time | 1872057678 ps |
| CPU time | 15.63 seconds |
| Started | Aug 27 06:25:11 PM UTC 24 |
| Finished | Aug 27 06:25:28 PM UTC 24 |
| Peak memory | 231548 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1046980080 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_ 26/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_and_tpm.1046980080 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/33.spi_device_flash_and_tpm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/33.spi_device_flash_and_tpm_min_idle.3752829759 |
| Short name | T716 |
| Test name | |
| Test status | |
| Simulation time | 2951275479 ps |
| CPU time | 21.73 seconds |
| Started | Aug 27 06:25:11 PM UTC 24 |
| Finished | Aug 27 06:25:34 PM UTC 24 |
| Peak memory | 247348 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3752829759 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_26/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_and_tpm_min_idle.3752829759 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/33.spi_device_flash_and_tpm_min_idle/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/33.spi_device_flash_mode.856740079 |
| Short name | T698 |
| Test name | |
| Test status | |
| Simulation time | 1522348212 ps |
| CPU time | 5.82 seconds |
| Started | Aug 27 06:25:02 PM UTC 24 |
| Finished | Aug 27 06:25:09 PM UTC 24 |
| Peak memory | 245216 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=856740079 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/s pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_mode.856740079 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/33.spi_device_flash_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/33.spi_device_flash_mode_ignore_cmds.1908373625 |
| Short name | T696 |
| Test name | |
| Test status | |
| Simulation time | 43686673 ps |
| CPU time | 1.19 seconds |
| Started | Aug 27 06:25:03 PM UTC 24 |
| Finished | Aug 27 06:25:06 PM UTC 24 |
| Peak memory | 225740 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1908373625 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_26/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_mode_ignore_cmds.1908373625 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/33.spi_device_flash_mode_ignore_cmds/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/33.spi_device_intercept.1217866376 |
| Short name | T694 |
| Test name | |
| Test status | |
| Simulation time | 1718395317 ps |
| CPU time | 6.02 seconds |
| Started | Aug 27 06:24:54 PM UTC 24 |
| Finished | Aug 27 06:25:01 PM UTC 24 |
| Peak memory | 234980 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1217866376 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/s pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_intercept.1217866376 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/33.spi_device_intercept/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/33.spi_device_mailbox.3344731191 |
| Short name | T722 |
| Test name | |
| Test status | |
| Simulation time | 33315925782 ps |
| CPU time | 44.42 seconds |
| Started | Aug 27 06:24:54 PM UTC 24 |
| Finished | Aug 27 06:25:40 PM UTC 24 |
| Peak memory | 261724 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3344731191 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_mailbox.3344731191 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/33.spi_device_mailbox/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/33.spi_device_pass_addr_payload_swap.2900884219 |
| Short name | T699 |
| Test name | |
| Test status | |
| Simulation time | 2767042313 ps |
| CPU time | 16.03 seconds |
| Started | Aug 27 06:24:52 PM UTC 24 |
| Finished | Aug 27 06:25:09 PM UTC 24 |
| Peak memory | 235028 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2900884219 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_26/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_pass_addr_payload_swap.2900884219 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/33.spi_device_pass_addr_payload_swap/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/33.spi_device_pass_cmd_filtering.932753409 |
| Short name | T705 |
| Test name | |
| Test status | |
| Simulation time | 4367201188 ps |
| CPU time | 31.61 seconds |
| Started | Aug 27 06:24:49 PM UTC 24 |
| Finished | Aug 27 06:25:22 PM UTC 24 |
| Peak memory | 251556 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=932753409 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _08_26/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_pass_cmd_filtering.932753409 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/33.spi_device_pass_cmd_filtering/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/33.spi_device_read_buffer_direct.1539159825 |
| Short name | T708 |
| Test name | |
| Test status | |
| Simulation time | 2299982216 ps |
| CPU time | 15.94 seconds |
| Started | Aug 27 06:25:07 PM UTC 24 |
| Finished | Aug 27 06:25:24 PM UTC 24 |
| Peak memory | 231384 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1539159825 -assert nopostproc +UVM_TESTNAME=spi_device _base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_read_buffer_direct.1539159825 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/33.spi_device_read_buffer_direct/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/33.spi_device_stress_all.2743622243 |
| Short name | T741 |
| Test name | |
| Test status | |
| Simulation time | 5581908338 ps |
| CPU time | 47.18 seconds |
| Started | Aug 27 06:25:14 PM UTC 24 |
| Finished | Aug 27 06:26:03 PM UTC 24 |
| Peak memory | 247460 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2743622243 -assert nopostproc +UVM_ TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_stress_all.2743622243 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/33.spi_device_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/33.spi_device_tpm_all.3247560096 |
| Short name | T697 |
| Test name | |
| Test status | |
| Simulation time | 2094395329 ps |
| CPU time | 26.58 seconds |
| Started | Aug 27 06:24:40 PM UTC 24 |
| Finished | Aug 27 06:25:08 PM UTC 24 |
| Peak memory | 227440 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3247560096 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_all.3247560096 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/33.spi_device_tpm_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/33.spi_device_tpm_read_hw_reg.1609459815 |
| Short name | T695 |
| Test name | |
| Test status | |
| Simulation time | 17212047445 ps |
| CPU time | 21.48 seconds |
| Started | Aug 27 06:24:40 PM UTC 24 |
| Finished | Aug 27 06:25:02 PM UTC 24 |
| Peak memory | 227612 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1609459815 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_26/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_read_hw_reg.1609459815 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/33.spi_device_tpm_read_hw_reg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/33.spi_device_tpm_rw.2334984365 |
| Short name | T692 |
| Test name | |
| Test status | |
| Simulation time | 138717441 ps |
| CPU time | 6.22 seconds |
| Started | Aug 27 06:24:45 PM UTC 24 |
| Finished | Aug 27 06:24:53 PM UTC 24 |
| Peak memory | 227424 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2334984365 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_rw.2334984365 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/33.spi_device_tpm_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/33.spi_device_tpm_sts_read.754611657 |
| Short name | T689 |
| Test name | |
| Test status | |
| Simulation time | 168875493 ps |
| CPU time | 1.52 seconds |
| Started | Aug 27 06:24:42 PM UTC 24 |
| Finished | Aug 27 06:24:45 PM UTC 24 |
| Peak memory | 215868 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=754611657 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26 /spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_sts_read.754611657 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/33.spi_device_tpm_sts_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/33.spi_device_upload.3477833269 |
| Short name | T701 |
| Test name | |
| Test status | |
| Simulation time | 2674518614 ps |
| CPU time | 19.28 seconds |
| Started | Aug 27 06:24:58 PM UTC 24 |
| Finished | Aug 27 06:25:18 PM UTC 24 |
| Peak memory | 245288 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3477833269 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_upload.3477833269 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/33.spi_device_upload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/34.spi_device_alert_test.3770630133 |
| Short name | T719 |
| Test name | |
| Test status | |
| Simulation time | 21293439 ps |
| CPU time | 1.13 seconds |
| Started | Aug 27 06:25:36 PM UTC 24 |
| Finished | Aug 27 06:25:38 PM UTC 24 |
| Peak memory | 215744 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3770630133 -assert nopostproc +UVM_TES TNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_alert_test.3770630133 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/34.spi_device_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/34.spi_device_cfg_cmd.2805921667 |
| Short name | T713 |
| Test name | |
| Test status | |
| Simulation time | 370519572 ps |
| CPU time | 2.85 seconds |
| Started | Aug 27 06:25:28 PM UTC 24 |
| Finished | Aug 27 06:25:32 PM UTC 24 |
| Peak memory | 245216 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2805921667 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_cfg_cmd.2805921667 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/34.spi_device_cfg_cmd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/34.spi_device_csb_read.4221466596 |
| Short name | T706 |
| Test name | |
| Test status | |
| Simulation time | 59693732 ps |
| CPU time | 1.17 seconds |
| Started | Aug 27 06:25:20 PM UTC 24 |
| Finished | Aug 27 06:25:22 PM UTC 24 |
| Peak memory | 215520 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4221466596 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/sp i_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_csb_read.4221466596 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/34.spi_device_csb_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/34.spi_device_flash_all.3461017528 |
| Short name | T335 |
| Test name | |
| Test status | |
| Simulation time | 5190729547 ps |
| CPU time | 58.32 seconds |
| Started | Aug 27 06:25:33 PM UTC 24 |
| Finished | Aug 27 06:26:33 PM UTC 24 |
| Peak memory | 267860 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3461017528 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/s pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_all.3461017528 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/34.spi_device_flash_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/34.spi_device_flash_and_tpm.1762196591 |
| Short name | T75 |
| Test name | |
| Test status | |
| Simulation time | 191926502423 ps |
| CPU time | 342.81 seconds |
| Started | Aug 27 06:25:35 PM UTC 24 |
| Finished | Aug 27 06:31:22 PM UTC 24 |
| Peak memory | 284272 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1762196591 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_ 26/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_and_tpm.1762196591 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/34.spi_device_flash_and_tpm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/34.spi_device_flash_and_tpm_min_idle.3196816610 |
| Short name | T782 |
| Test name | |
| Test status | |
| Simulation time | 9321726046 ps |
| CPU time | 61.97 seconds |
| Started | Aug 27 06:25:35 PM UTC 24 |
| Finished | Aug 27 06:26:39 PM UTC 24 |
| Peak memory | 251508 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3196816610 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_26/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_and_tpm_min_idle.3196816610 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/34.spi_device_flash_and_tpm_min_idle/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/34.spi_device_flash_mode_ignore_cmds.4088195564 |
| Short name | T873 |
| Test name | |
| Test status | |
| Simulation time | 19613268342 ps |
| CPU time | 159.91 seconds |
| Started | Aug 27 06:25:33 PM UTC 24 |
| Finished | Aug 27 06:28:16 PM UTC 24 |
| Peak memory | 249440 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4088195564 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_26/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_mode_ignore_cmds.4088195564 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/34.spi_device_flash_mode_ignore_cmds/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/34.spi_device_intercept.4079271084 |
| Short name | T718 |
| Test name | |
| Test status | |
| Simulation time | 5373535321 ps |
| CPU time | 11.43 seconds |
| Started | Aug 27 06:25:25 PM UTC 24 |
| Finished | Aug 27 06:25:38 PM UTC 24 |
| Peak memory | 235032 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4079271084 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/s pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_intercept.4079271084 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/34.spi_device_intercept/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/34.spi_device_mailbox.2568190184 |
| Short name | T727 |
| Test name | |
| Test status | |
| Simulation time | 1769969532 ps |
| CPU time | 19.81 seconds |
| Started | Aug 27 06:25:27 PM UTC 24 |
| Finished | Aug 27 06:25:48 PM UTC 24 |
| Peak memory | 245216 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2568190184 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_mailbox.2568190184 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/34.spi_device_mailbox/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/34.spi_device_pass_addr_payload_swap.908744277 |
| Short name | T349 |
| Test name | |
| Test status | |
| Simulation time | 45272659218 ps |
| CPU time | 32.92 seconds |
| Started | Aug 27 06:25:25 PM UTC 24 |
| Finished | Aug 27 06:26:00 PM UTC 24 |
| Peak memory | 245332 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=908744277 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_26/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_pass_addr_payload_swap.908744277 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/34.spi_device_pass_addr_payload_swap/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/34.spi_device_pass_cmd_filtering.1540954095 |
| Short name | T728 |
| Test name | |
| Test status | |
| Simulation time | 8968460974 ps |
| CPU time | 23.24 seconds |
| Started | Aug 27 06:25:25 PM UTC 24 |
| Finished | Aug 27 06:25:50 PM UTC 24 |
| Peak memory | 245336 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1540954095 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_08_26/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_pass_cmd_filtering.1540954095 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/34.spi_device_pass_cmd_filtering/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/34.spi_device_read_buffer_direct.1238844029 |
| Short name | T720 |
| Test name | |
| Test status | |
| Simulation time | 624411379 ps |
| CPU time | 4.44 seconds |
| Started | Aug 27 06:25:33 PM UTC 24 |
| Finished | Aug 27 06:25:39 PM UTC 24 |
| Peak memory | 231448 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1238844029 -assert nopostproc +UVM_TESTNAME=spi_device _base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_read_buffer_direct.1238844029 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/34.spi_device_read_buffer_direct/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/34.spi_device_stress_all.863474829 |
| Short name | T76 |
| Test name | |
| Test status | |
| Simulation time | 24979471721 ps |
| CPU time | 373.95 seconds |
| Started | Aug 27 06:25:35 PM UTC 24 |
| Finished | Aug 27 06:31:54 PM UTC 24 |
| Peak memory | 282252 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=863474829 -assert nopostproc +UVM_T ESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_stress_all.863474829 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/34.spi_device_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/34.spi_device_tpm_all.828507715 |
| Short name | T714 |
| Test name | |
| Test status | |
| Simulation time | 1168848343 ps |
| CPU time | 8.29 seconds |
| Started | Aug 27 06:25:23 PM UTC 24 |
| Finished | Aug 27 06:25:33 PM UTC 24 |
| Peak memory | 227216 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=828507715 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_all.828507715 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/34.spi_device_tpm_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/34.spi_device_tpm_read_hw_reg.642080705 |
| Short name | T717 |
| Test name | |
| Test status | |
| Simulation time | 93373188126 ps |
| CPU time | 14 seconds |
| Started | Aug 27 06:25:20 PM UTC 24 |
| Finished | Aug 27 06:25:35 PM UTC 24 |
| Peak memory | 227552 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=642080705 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08 _26/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_read_hw_reg.642080705 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/34.spi_device_tpm_read_hw_reg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/34.spi_device_tpm_rw.2571005522 |
| Short name | T709 |
| Test name | |
| Test status | |
| Simulation time | 37922610 ps |
| CPU time | 1.05 seconds |
| Started | Aug 27 06:25:23 PM UTC 24 |
| Finished | Aug 27 06:25:26 PM UTC 24 |
| Peak memory | 215740 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2571005522 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_rw.2571005522 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/34.spi_device_tpm_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/34.spi_device_tpm_sts_read.1509779688 |
| Short name | T710 |
| Test name | |
| Test status | |
| Simulation time | 239380945 ps |
| CPU time | 1.39 seconds |
| Started | Aug 27 06:25:23 PM UTC 24 |
| Finished | Aug 27 06:25:26 PM UTC 24 |
| Peak memory | 215448 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1509779688 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_2 6/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_sts_read.1509779688 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/34.spi_device_tpm_sts_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/34.spi_device_upload.1673379189 |
| Short name | T734 |
| Test name | |
| Test status | |
| Simulation time | 44193016628 ps |
| CPU time | 29.06 seconds |
| Started | Aug 27 06:25:27 PM UTC 24 |
| Finished | Aug 27 06:25:57 PM UTC 24 |
| Peak memory | 235156 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1673379189 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_upload.1673379189 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/34.spi_device_upload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/35.spi_device_alert_test.214985601 |
| Short name | T733 |
| Test name | |
| Test status | |
| Simulation time | 18009455 ps |
| CPU time | 1.09 seconds |
| Started | Aug 27 06:25:55 PM UTC 24 |
| Finished | Aug 27 06:25:57 PM UTC 24 |
| Peak memory | 215684 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=214985601 -assert nopostproc +UVM_TEST NAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_alert_test.214985601 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/35.spi_device_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/35.spi_device_cfg_cmd.709422949 |
| Short name | T729 |
| Test name | |
| Test status | |
| Simulation time | 1125720099 ps |
| CPU time | 5.53 seconds |
| Started | Aug 27 06:25:46 PM UTC 24 |
| Finished | Aug 27 06:25:52 PM UTC 24 |
| Peak memory | 234956 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=709422949 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_cfg_cmd.709422949 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/35.spi_device_cfg_cmd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/35.spi_device_csb_read.1030968404 |
| Short name | T721 |
| Test name | |
| Test status | |
| Simulation time | 22364007 ps |
| CPU time | 1.17 seconds |
| Started | Aug 27 06:25:38 PM UTC 24 |
| Finished | Aug 27 06:25:40 PM UTC 24 |
| Peak memory | 215812 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1030968404 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/sp i_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_csb_read.1030968404 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/35.spi_device_csb_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/35.spi_device_flash_all.1581412900 |
| Short name | T773 |
| Test name | |
| Test status | |
| Simulation time | 3064466885 ps |
| CPU time | 37.59 seconds |
| Started | Aug 27 06:25:50 PM UTC 24 |
| Finished | Aug 27 06:26:29 PM UTC 24 |
| Peak memory | 249432 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1581412900 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/s pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_all.1581412900 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/35.spi_device_flash_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/35.spi_device_flash_and_tpm.3469188025 |
| Short name | T800 |
| Test name | |
| Test status | |
| Simulation time | 8666379125 ps |
| CPU time | 63.48 seconds |
| Started | Aug 27 06:25:51 PM UTC 24 |
| Finished | Aug 27 06:26:56 PM UTC 24 |
| Peak memory | 261788 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3469188025 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_ 26/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_and_tpm.3469188025 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/35.spi_device_flash_and_tpm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/35.spi_device_flash_and_tpm_min_idle.16463717 |
| Short name | T825 |
| Test name | |
| Test status | |
| Simulation time | 4779683278 ps |
| CPU time | 79.13 seconds |
| Started | Aug 27 06:25:53 PM UTC 24 |
| Finished | Aug 27 06:27:14 PM UTC 24 |
| Peak memory | 261784 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=16463717 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_26/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_and_tpm_min_idle.16463717 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/35.spi_device_flash_and_tpm_min_idle/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/35.spi_device_flash_mode.1524087324 |
| Short name | T751 |
| Test name | |
| Test status | |
| Simulation time | 5529428991 ps |
| CPU time | 20.53 seconds |
| Started | Aug 27 06:25:47 PM UTC 24 |
| Finished | Aug 27 06:26:08 PM UTC 24 |
| Peak memory | 235236 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1524087324 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/ spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_mode.1524087324 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/35.spi_device_flash_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/35.spi_device_flash_mode_ignore_cmds.3682444302 |
| Short name | T792 |
| Test name | |
| Test status | |
| Simulation time | 16545581222 ps |
| CPU time | 58.83 seconds |
| Started | Aug 27 06:25:48 PM UTC 24 |
| Finished | Aug 27 06:26:48 PM UTC 24 |
| Peak memory | 267924 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3682444302 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_26/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_mode_ignore_cmds.3682444302 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/35.spi_device_flash_mode_ignore_cmds/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/35.spi_device_intercept.2305896807 |
| Short name | T730 |
| Test name | |
| Test status | |
| Simulation time | 705739470 ps |
| CPU time | 8.81 seconds |
| Started | Aug 27 06:25:43 PM UTC 24 |
| Finished | Aug 27 06:25:53 PM UTC 24 |
| Peak memory | 234964 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2305896807 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/s pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_intercept.2305896807 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/35.spi_device_intercept/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/35.spi_device_mailbox.4286711108 |
| Short name | T736 |
| Test name | |
| Test status | |
| Simulation time | 1936532373 ps |
| CPU time | 14.87 seconds |
| Started | Aug 27 06:25:43 PM UTC 24 |
| Finished | Aug 27 06:25:59 PM UTC 24 |
| Peak memory | 245144 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4286711108 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_mailbox.4286711108 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/35.spi_device_mailbox/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/35.spi_device_pass_addr_payload_swap.2994829366 |
| Short name | T731 |
| Test name | |
| Test status | |
| Simulation time | 1138081472 ps |
| CPU time | 9.79 seconds |
| Started | Aug 27 06:25:43 PM UTC 24 |
| Finished | Aug 27 06:25:54 PM UTC 24 |
| Peak memory | 245160 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2994829366 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_26/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_pass_addr_payload_swap.2994829366 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/35.spi_device_pass_addr_payload_swap/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/35.spi_device_pass_cmd_filtering.1861691829 |
| Short name | T744 |
| Test name | |
| Test status | |
| Simulation time | 4135921699 ps |
| CPU time | 20.6 seconds |
| Started | Aug 27 06:25:41 PM UTC 24 |
| Finished | Aug 27 06:26:03 PM UTC 24 |
| Peak memory | 234968 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1861691829 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_08_26/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_pass_cmd_filtering.1861691829 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/35.spi_device_pass_cmd_filtering/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/35.spi_device_read_buffer_direct.1427619794 |
| Short name | T732 |
| Test name | |
| Test status | |
| Simulation time | 264767574 ps |
| CPU time | 6.16 seconds |
| Started | Aug 27 06:25:50 PM UTC 24 |
| Finished | Aug 27 06:25:57 PM UTC 24 |
| Peak memory | 233368 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1427619794 -assert nopostproc +UVM_TESTNAME=spi_device _base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_read_buffer_direct.1427619794 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/35.spi_device_read_buffer_direct/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/35.spi_device_stress_all.2461572424 |
| Short name | T735 |
| Test name | |
| Test status | |
| Simulation time | 59842991 ps |
| CPU time | 1.63 seconds |
| Started | Aug 27 06:25:55 PM UTC 24 |
| Finished | Aug 27 06:25:57 PM UTC 24 |
| Peak memory | 216292 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2461572424 -assert nopostproc +UVM_ TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_stress_all.2461572424 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/35.spi_device_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/35.spi_device_tpm_all.1007086917 |
| Short name | T746 |
| Test name | |
| Test status | |
| Simulation time | 3951688058 ps |
| CPU time | 24.14 seconds |
| Started | Aug 27 06:25:40 PM UTC 24 |
| Finished | Aug 27 06:26:05 PM UTC 24 |
| Peak memory | 227612 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1007086917 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_all.1007086917 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/35.spi_device_tpm_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/35.spi_device_tpm_read_hw_reg.3675708624 |
| Short name | T726 |
| Test name | |
| Test status | |
| Simulation time | 1647910050 ps |
| CPU time | 7.19 seconds |
| Started | Aug 27 06:25:40 PM UTC 24 |
| Finished | Aug 27 06:25:48 PM UTC 24 |
| Peak memory | 227484 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3675708624 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_26/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_read_hw_reg.3675708624 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/35.spi_device_tpm_read_hw_reg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/35.spi_device_tpm_rw.1250077285 |
| Short name | T725 |
| Test name | |
| Test status | |
| Simulation time | 392990823 ps |
| CPU time | 2.41 seconds |
| Started | Aug 27 06:25:41 PM UTC 24 |
| Finished | Aug 27 06:25:45 PM UTC 24 |
| Peak memory | 227480 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1250077285 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_rw.1250077285 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/35.spi_device_tpm_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/35.spi_device_tpm_sts_read.3414178138 |
| Short name | T723 |
| Test name | |
| Test status | |
| Simulation time | 285734959 ps |
| CPU time | 1.24 seconds |
| Started | Aug 27 06:25:40 PM UTC 24 |
| Finished | Aug 27 06:25:42 PM UTC 24 |
| Peak memory | 215872 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3414178138 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_2 6/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_sts_read.3414178138 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/35.spi_device_tpm_sts_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/35.spi_device_upload.3532715683 |
| Short name | T742 |
| Test name | |
| Test status | |
| Simulation time | 3101077848 ps |
| CPU time | 17.19 seconds |
| Started | Aug 27 06:25:44 PM UTC 24 |
| Finished | Aug 27 06:26:03 PM UTC 24 |
| Peak memory | 251492 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3532715683 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_upload.3532715683 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/35.spi_device_upload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/36.spi_device_alert_test.3197045007 |
| Short name | T755 |
| Test name | |
| Test status | |
| Simulation time | 108936960 ps |
| CPU time | 0.97 seconds |
| Started | Aug 27 06:26:08 PM UTC 24 |
| Finished | Aug 27 06:26:10 PM UTC 24 |
| Peak memory | 215804 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3197045007 -assert nopostproc +UVM_TES TNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_alert_test.3197045007 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/36.spi_device_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/36.spi_device_cfg_cmd.1946855006 |
| Short name | T750 |
| Test name | |
| Test status | |
| Simulation time | 309173196 ps |
| CPU time | 2.63 seconds |
| Started | Aug 27 06:26:05 PM UTC 24 |
| Finished | Aug 27 06:26:08 PM UTC 24 |
| Peak memory | 234324 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1946855006 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_cfg_cmd.1946855006 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/36.spi_device_cfg_cmd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/36.spi_device_csb_read.1772988339 |
| Short name | T738 |
| Test name | |
| Test status | |
| Simulation time | 128547377 ps |
| CPU time | 1.2 seconds |
| Started | Aug 27 06:25:59 PM UTC 24 |
| Finished | Aug 27 06:26:01 PM UTC 24 |
| Peak memory | 215580 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1772988339 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/sp i_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_csb_read.1772988339 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/36.spi_device_csb_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/36.spi_device_flash_all.3848002717 |
| Short name | T256 |
| Test name | |
| Test status | |
| Simulation time | 3624126052 ps |
| CPU time | 43.34 seconds |
| Started | Aug 27 06:26:05 PM UTC 24 |
| Finished | Aug 27 06:26:50 PM UTC 24 |
| Peak memory | 265828 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3848002717 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/s pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_all.3848002717 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/36.spi_device_flash_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/36.spi_device_flash_and_tpm.3623827047 |
| Short name | T1005 |
| Test name | |
| Test status | |
| Simulation time | 101058032391 ps |
| CPU time | 489.69 seconds |
| Started | Aug 27 06:26:06 PM UTC 24 |
| Finished | Aug 27 06:34:22 PM UTC 24 |
| Peak memory | 267892 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3623827047 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_ 26/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_and_tpm.3623827047 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/36.spi_device_flash_and_tpm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/36.spi_device_flash_and_tpm_min_idle.1147280237 |
| Short name | T875 |
| Test name | |
| Test status | |
| Simulation time | 16266541234 ps |
| CPU time | 126.36 seconds |
| Started | Aug 27 06:26:08 PM UTC 24 |
| Finished | Aug 27 06:28:17 PM UTC 24 |
| Peak memory | 263292 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1147280237 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_26/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_and_tpm_min_idle.1147280237 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/36.spi_device_flash_and_tpm_min_idle/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/36.spi_device_flash_mode.2282945151 |
| Short name | T774 |
| Test name | |
| Test status | |
| Simulation time | 4692524969 ps |
| CPU time | 23.02 seconds |
| Started | Aug 27 06:26:05 PM UTC 24 |
| Finished | Aug 27 06:26:29 PM UTC 24 |
| Peak memory | 234932 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2282945151 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/ spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_mode.2282945151 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/36.spi_device_flash_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/36.spi_device_flash_mode_ignore_cmds.1521473366 |
| Short name | T249 |
| Test name | |
| Test status | |
| Simulation time | 5477170783 ps |
| CPU time | 74.74 seconds |
| Started | Aug 27 06:26:05 PM UTC 24 |
| Finished | Aug 27 06:27:21 PM UTC 24 |
| Peak memory | 263828 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1521473366 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_26/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_mode_ignore_cmds.1521473366 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/36.spi_device_flash_mode_ignore_cmds/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/36.spi_device_intercept.976429349 |
| Short name | T749 |
| Test name | |
| Test status | |
| Simulation time | 1156600032 ps |
| CPU time | 5.58 seconds |
| Started | Aug 27 06:26:01 PM UTC 24 |
| Finished | Aug 27 06:26:07 PM UTC 24 |
| Peak memory | 245156 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=976429349 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/sp i_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_intercept.976429349 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/36.spi_device_intercept/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/36.spi_device_mailbox.212815978 |
| Short name | T765 |
| Test name | |
| Test status | |
| Simulation time | 1535586944 ps |
| CPU time | 17.69 seconds |
| Started | Aug 27 06:26:02 PM UTC 24 |
| Finished | Aug 27 06:26:21 PM UTC 24 |
| Peak memory | 251428 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=212815978 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_mailbox.212815978 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/36.spi_device_mailbox/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/36.spi_device_pass_addr_payload_swap.1167796383 |
| Short name | T753 |
| Test name | |
| Test status | |
| Simulation time | 22944959357 ps |
| CPU time | 7.72 seconds |
| Started | Aug 27 06:26:01 PM UTC 24 |
| Finished | Aug 27 06:26:09 PM UTC 24 |
| Peak memory | 245328 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1167796383 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_26/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_pass_addr_payload_swap.1167796383 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/36.spi_device_pass_addr_payload_swap/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/36.spi_device_pass_cmd_filtering.2976651631 |
| Short name | T747 |
| Test name | |
| Test status | |
| Simulation time | 2320400857 ps |
| CPU time | 4.78 seconds |
| Started | Aug 27 06:26:01 PM UTC 24 |
| Finished | Aug 27 06:26:06 PM UTC 24 |
| Peak memory | 235092 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2976651631 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_08_26/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_pass_cmd_filtering.2976651631 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/36.spi_device_pass_cmd_filtering/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/36.spi_device_read_buffer_direct.3364188789 |
| Short name | T760 |
| Test name | |
| Test status | |
| Simulation time | 1186162129 ps |
| CPU time | 7.81 seconds |
| Started | Aug 27 06:26:05 PM UTC 24 |
| Finished | Aug 27 06:26:14 PM UTC 24 |
| Peak memory | 233384 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3364188789 -assert nopostproc +UVM_TESTNAME=spi_device _base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_read_buffer_direct.3364188789 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/36.spi_device_read_buffer_direct/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/36.spi_device_stress_all.28831477 |
| Short name | T78 |
| Test name | |
| Test status | |
| Simulation time | 87631974375 ps |
| CPU time | 478.39 seconds |
| Started | Aug 27 06:26:08 PM UTC 24 |
| Finished | Aug 27 06:34:12 PM UTC 24 |
| Peak memory | 277768 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=28831477 -assert nopostproc +UVM_TE STNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_stress_all.28831477 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/36.spi_device_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/36.spi_device_tpm_all.2719399069 |
| Short name | T756 |
| Test name | |
| Test status | |
| Simulation time | 2251066453 ps |
| CPU time | 12.93 seconds |
| Started | Aug 27 06:25:59 PM UTC 24 |
| Finished | Aug 27 06:26:13 PM UTC 24 |
| Peak memory | 231644 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2719399069 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_all.2719399069 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/36.spi_device_tpm_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/36.spi_device_tpm_read_hw_reg.1407380474 |
| Short name | T743 |
| Test name | |
| Test status | |
| Simulation time | 649540835 ps |
| CPU time | 2.93 seconds |
| Started | Aug 27 06:25:59 PM UTC 24 |
| Finished | Aug 27 06:26:03 PM UTC 24 |
| Peak memory | 217092 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1407380474 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_26/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_read_hw_reg.1407380474 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/36.spi_device_tpm_read_hw_reg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/36.spi_device_tpm_rw.2770603430 |
| Short name | T745 |
| Test name | |
| Test status | |
| Simulation time | 53875933 ps |
| CPU time | 2.53 seconds |
| Started | Aug 27 06:26:01 PM UTC 24 |
| Finished | Aug 27 06:26:04 PM UTC 24 |
| Peak memory | 227440 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2770603430 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_rw.2770603430 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/36.spi_device_tpm_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/36.spi_device_tpm_sts_read.4198746776 |
| Short name | T739 |
| Test name | |
| Test status | |
| Simulation time | 20521526 ps |
| CPU time | 1.09 seconds |
| Started | Aug 27 06:25:59 PM UTC 24 |
| Finished | Aug 27 06:26:01 PM UTC 24 |
| Peak memory | 215872 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4198746776 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_2 6/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_sts_read.4198746776 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/36.spi_device_tpm_sts_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/36.spi_device_upload.1396794402 |
| Short name | T762 |
| Test name | |
| Test status | |
| Simulation time | 2607032035 ps |
| CPU time | 11.86 seconds |
| Started | Aug 27 06:26:02 PM UTC 24 |
| Finished | Aug 27 06:26:15 PM UTC 24 |
| Peak memory | 241972 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1396794402 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_upload.1396794402 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/36.spi_device_upload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/37.spi_device_alert_test.2960482146 |
| Short name | T770 |
| Test name | |
| Test status | |
| Simulation time | 13340371 ps |
| CPU time | 1.09 seconds |
| Started | Aug 27 06:26:24 PM UTC 24 |
| Finished | Aug 27 06:26:26 PM UTC 24 |
| Peak memory | 215744 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2960482146 -assert nopostproc +UVM_TES TNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_alert_test.2960482146 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/37.spi_device_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/37.spi_device_cfg_cmd.3510327483 |
| Short name | T783 |
| Test name | |
| Test status | |
| Simulation time | 8957748926 ps |
| CPU time | 23.13 seconds |
| Started | Aug 27 06:26:14 PM UTC 24 |
| Finished | Aug 27 06:26:39 PM UTC 24 |
| Peak memory | 251428 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3510327483 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_cfg_cmd.3510327483 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/37.spi_device_cfg_cmd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/37.spi_device_csb_read.1280329835 |
| Short name | T758 |
| Test name | |
| Test status | |
| Simulation time | 19218932 ps |
| CPU time | 1.13 seconds |
| Started | Aug 27 06:26:11 PM UTC 24 |
| Finished | Aug 27 06:26:13 PM UTC 24 |
| Peak memory | 215812 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1280329835 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/sp i_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_csb_read.1280329835 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/37.spi_device_csb_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/37.spi_device_flash_all.972932759 |
| Short name | T884 |
| Test name | |
| Test status | |
| Simulation time | 15397711136 ps |
| CPU time | 131.69 seconds |
| Started | Aug 27 06:26:16 PM UTC 24 |
| Finished | Aug 27 06:28:31 PM UTC 24 |
| Peak memory | 261712 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=972932759 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/sp i_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_all.972932759 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/37.spi_device_flash_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/37.spi_device_flash_and_tpm.1286477387 |
| Short name | T795 |
| Test name | |
| Test status | |
| Simulation time | 18920581484 ps |
| CPU time | 30.21 seconds |
| Started | Aug 27 06:26:19 PM UTC 24 |
| Finished | Aug 27 06:26:52 PM UTC 24 |
| Peak memory | 229736 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1286477387 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_ 26/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_and_tpm.1286477387 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/37.spi_device_flash_and_tpm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/37.spi_device_flash_and_tpm_min_idle.2326141962 |
| Short name | T768 |
| Test name | |
| Test status | |
| Simulation time | 18980221 ps |
| CPU time | 1.25 seconds |
| Started | Aug 27 06:26:21 PM UTC 24 |
| Finished | Aug 27 06:26:23 PM UTC 24 |
| Peak memory | 228028 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2326141962 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_26/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_and_tpm_min_idle.2326141962 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/37.spi_device_flash_and_tpm_min_idle/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/37.spi_device_flash_mode.392754717 |
| Short name | T766 |
| Test name | |
| Test status | |
| Simulation time | 244330499 ps |
| CPU time | 6.78 seconds |
| Started | Aug 27 06:26:15 PM UTC 24 |
| Finished | Aug 27 06:26:22 PM UTC 24 |
| Peak memory | 234964 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=392754717 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/s pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_mode.392754717 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/37.spi_device_flash_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/37.spi_device_flash_mode_ignore_cmds.2629469220 |
| Short name | T789 |
| Test name | |
| Test status | |
| Simulation time | 1093903106 ps |
| CPU time | 28.96 seconds |
| Started | Aug 27 06:26:15 PM UTC 24 |
| Finished | Aug 27 06:26:45 PM UTC 24 |
| Peak memory | 249300 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2629469220 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_26/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_mode_ignore_cmds.2629469220 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/37.spi_device_flash_mode_ignore_cmds/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/37.spi_device_intercept.2048836276 |
| Short name | T779 |
| Test name | |
| Test status | |
| Simulation time | 4014762471 ps |
| CPU time | 20.32 seconds |
| Started | Aug 27 06:26:12 PM UTC 24 |
| Finished | Aug 27 06:26:34 PM UTC 24 |
| Peak memory | 245348 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2048836276 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/s pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_intercept.2048836276 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/37.spi_device_intercept/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/37.spi_device_mailbox.1948745126 |
| Short name | T784 |
| Test name | |
| Test status | |
| Simulation time | 33580168373 ps |
| CPU time | 24.3 seconds |
| Started | Aug 27 06:26:14 PM UTC 24 |
| Finished | Aug 27 06:26:40 PM UTC 24 |
| Peak memory | 245344 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1948745126 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_mailbox.1948745126 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/37.spi_device_mailbox/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/37.spi_device_pass_addr_payload_swap.4183555803 |
| Short name | T757 |
| Test name | |
| Test status | |
| Simulation time | 10573853921 ps |
| CPU time | 16.23 seconds |
| Started | Aug 27 06:26:11 PM UTC 24 |
| Finished | Aug 27 06:26:28 PM UTC 24 |
| Peak memory | 245332 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4183555803 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_26/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_pass_addr_payload_swap.4183555803 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/37.spi_device_pass_addr_payload_swap/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/37.spi_device_pass_cmd_filtering.2030766585 |
| Short name | T769 |
| Test name | |
| Test status | |
| Simulation time | 33133579332 ps |
| CPU time | 12.26 seconds |
| Started | Aug 27 06:26:11 PM UTC 24 |
| Finished | Aug 27 06:26:24 PM UTC 24 |
| Peak memory | 251416 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2030766585 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_08_26/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_pass_cmd_filtering.2030766585 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/37.spi_device_pass_cmd_filtering/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/37.spi_device_read_buffer_direct.1895676833 |
| Short name | T767 |
| Test name | |
| Test status | |
| Simulation time | 173120446 ps |
| CPU time | 4.86 seconds |
| Started | Aug 27 06:26:16 PM UTC 24 |
| Finished | Aug 27 06:26:22 PM UTC 24 |
| Peak memory | 233648 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1895676833 -assert nopostproc +UVM_TESTNAME=spi_device _base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_read_buffer_direct.1895676833 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/37.spi_device_read_buffer_direct/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/37.spi_device_stress_all.2846922303 |
| Short name | T1008 |
| Test name | |
| Test status | |
| Simulation time | 228977655012 ps |
| CPU time | 548.92 seconds |
| Started | Aug 27 06:26:22 PM UTC 24 |
| Finished | Aug 27 06:35:38 PM UTC 24 |
| Peak memory | 261852 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2846922303 -assert nopostproc +UVM_ TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_stress_all.2846922303 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/37.spi_device_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/37.spi_device_tpm_all.2961719720 |
| Short name | T794 |
| Test name | |
| Test status | |
| Simulation time | 5055816980 ps |
| CPU time | 38.98 seconds |
| Started | Aug 27 06:26:11 PM UTC 24 |
| Finished | Aug 27 06:26:51 PM UTC 24 |
| Peak memory | 227552 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2961719720 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_all.2961719720 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/37.spi_device_tpm_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/37.spi_device_tpm_read_hw_reg.4132169100 |
| Short name | T775 |
| Test name | |
| Test status | |
| Simulation time | 3642952501 ps |
| CPU time | 17.47 seconds |
| Started | Aug 27 06:26:11 PM UTC 24 |
| Finished | Aug 27 06:26:30 PM UTC 24 |
| Peak memory | 227616 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4132169100 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_26/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_read_hw_reg.4132169100 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/37.spi_device_tpm_read_hw_reg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/37.spi_device_tpm_rw.174918356 |
| Short name | T761 |
| Test name | |
| Test status | |
| Simulation time | 204886036 ps |
| CPU time | 1.73 seconds |
| Started | Aug 27 06:26:11 PM UTC 24 |
| Finished | Aug 27 06:26:14 PM UTC 24 |
| Peak memory | 226480 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=174918356 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/spi_d evice_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_rw.174918356 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/37.spi_device_tpm_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/37.spi_device_tpm_sts_read.2090812584 |
| Short name | T759 |
| Test name | |
| Test status | |
| Simulation time | 98472850 ps |
| CPU time | 1.21 seconds |
| Started | Aug 27 06:26:11 PM UTC 24 |
| Finished | Aug 27 06:26:13 PM UTC 24 |
| Peak memory | 215872 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2090812584 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_2 6/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_sts_read.2090812584 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/37.spi_device_tpm_sts_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/37.spi_device_upload.370800976 |
| Short name | T763 |
| Test name | |
| Test status | |
| Simulation time | 1004795794 ps |
| CPU time | 3.18 seconds |
| Started | Aug 27 06:26:14 PM UTC 24 |
| Finished | Aug 27 06:26:19 PM UTC 24 |
| Peak memory | 234700 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=370800976 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/spi_d evice_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_upload.370800976 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/37.spi_device_upload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/38.spi_device_alert_test.646856782 |
| Short name | T785 |
| Test name | |
| Test status | |
| Simulation time | 27639902 ps |
| CPU time | 1.04 seconds |
| Started | Aug 27 06:26:38 PM UTC 24 |
| Finished | Aug 27 06:26:40 PM UTC 24 |
| Peak memory | 215808 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=646856782 -assert nopostproc +UVM_TEST NAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_alert_test.646856782 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/38.spi_device_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/38.spi_device_cfg_cmd.1089696751 |
| Short name | T780 |
| Test name | |
| Test status | |
| Simulation time | 152568610 ps |
| CPU time | 3.43 seconds |
| Started | Aug 27 06:26:31 PM UTC 24 |
| Finished | Aug 27 06:26:36 PM UTC 24 |
| Peak memory | 245132 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1089696751 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_cfg_cmd.1089696751 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/38.spi_device_cfg_cmd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/38.spi_device_csb_read.380475650 |
| Short name | T771 |
| Test name | |
| Test status | |
| Simulation time | 34006293 ps |
| CPU time | 1.15 seconds |
| Started | Aug 27 06:26:24 PM UTC 24 |
| Finished | Aug 27 06:26:26 PM UTC 24 |
| Peak memory | 215812 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=380475650 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_csb_read.380475650 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/38.spi_device_csb_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/38.spi_device_flash_all.748229173 |
| Short name | T838 |
| Test name | |
| Test status | |
| Simulation time | 17215504055 ps |
| CPU time | 53.4 seconds |
| Started | Aug 27 06:26:34 PM UTC 24 |
| Finished | Aug 27 06:27:29 PM UTC 24 |
| Peak memory | 263776 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=748229173 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/sp i_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_all.748229173 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/38.spi_device_flash_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/38.spi_device_flash_and_tpm.1038598084 |
| Short name | T854 |
| Test name | |
| Test status | |
| Simulation time | 2878125331 ps |
| CPU time | 71.27 seconds |
| Started | Aug 27 06:26:34 PM UTC 24 |
| Finished | Aug 27 06:27:47 PM UTC 24 |
| Peak memory | 265904 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1038598084 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_ 26/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_and_tpm.1038598084 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/38.spi_device_flash_and_tpm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/38.spi_device_flash_and_tpm_min_idle.2566589194 |
| Short name | T923 |
| Test name | |
| Test status | |
| Simulation time | 13245992095 ps |
| CPU time | 159.14 seconds |
| Started | Aug 27 06:26:36 PM UTC 24 |
| Finished | Aug 27 06:29:18 PM UTC 24 |
| Peak memory | 284296 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2566589194 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_26/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_and_tpm_min_idle.2566589194 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/38.spi_device_flash_and_tpm_min_idle/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/38.spi_device_flash_mode.1026350819 |
| Short name | T806 |
| Test name | |
| Test status | |
| Simulation time | 7739383858 ps |
| CPU time | 27.79 seconds |
| Started | Aug 27 06:26:31 PM UTC 24 |
| Finished | Aug 27 06:27:00 PM UTC 24 |
| Peak memory | 245328 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1026350819 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/ spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_mode.1026350819 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/38.spi_device_flash_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/38.spi_device_flash_mode_ignore_cmds.3467256146 |
| Short name | T908 |
| Test name | |
| Test status | |
| Simulation time | 15247671805 ps |
| CPU time | 148.81 seconds |
| Started | Aug 27 06:26:32 PM UTC 24 |
| Finished | Aug 27 06:29:03 PM UTC 24 |
| Peak memory | 267880 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3467256146 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_26/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_mode_ignore_cmds.3467256146 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/38.spi_device_flash_mode_ignore_cmds/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/38.spi_device_intercept.1427377828 |
| Short name | T797 |
| Test name | |
| Test status | |
| Simulation time | 2274840262 ps |
| CPU time | 21.49 seconds |
| Started | Aug 27 06:26:30 PM UTC 24 |
| Finished | Aug 27 06:26:53 PM UTC 24 |
| Peak memory | 245268 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1427377828 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/s pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_intercept.1427377828 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/38.spi_device_intercept/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/38.spi_device_mailbox.482245586 |
| Short name | T813 |
| Test name | |
| Test status | |
| Simulation time | 3169524811 ps |
| CPU time | 34.74 seconds |
| Started | Aug 27 06:26:30 PM UTC 24 |
| Finished | Aug 27 06:27:06 PM UTC 24 |
| Peak memory | 241888 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=482245586 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_mailbox.482245586 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/38.spi_device_mailbox/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/38.spi_device_pass_addr_payload_swap.2930490799 |
| Short name | T812 |
| Test name | |
| Test status | |
| Simulation time | 6906881860 ps |
| CPU time | 33.7 seconds |
| Started | Aug 27 06:26:28 PM UTC 24 |
| Finished | Aug 27 06:27:03 PM UTC 24 |
| Peak memory | 251432 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2930490799 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_26/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_pass_addr_payload_swap.2930490799 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/38.spi_device_pass_addr_payload_swap/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/38.spi_device_pass_cmd_filtering.1096979050 |
| Short name | T776 |
| Test name | |
| Test status | |
| Simulation time | 36012416 ps |
| CPU time | 2.59 seconds |
| Started | Aug 27 06:26:27 PM UTC 24 |
| Finished | Aug 27 06:26:30 PM UTC 24 |
| Peak memory | 244952 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1096979050 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_08_26/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_pass_cmd_filtering.1096979050 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/38.spi_device_pass_cmd_filtering/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/38.spi_device_read_buffer_direct.1519023820 |
| Short name | T791 |
| Test name | |
| Test status | |
| Simulation time | 1399505950 ps |
| CPU time | 13.69 seconds |
| Started | Aug 27 06:26:33 PM UTC 24 |
| Finished | Aug 27 06:26:48 PM UTC 24 |
| Peak memory | 231320 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1519023820 -assert nopostproc +UVM_TESTNAME=spi_device _base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_read_buffer_direct.1519023820 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/38.spi_device_read_buffer_direct/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/38.spi_device_stress_all.497705394 |
| Short name | T878 |
| Test name | |
| Test status | |
| Simulation time | 16248876242 ps |
| CPU time | 101.93 seconds |
| Started | Aug 27 06:26:37 PM UTC 24 |
| Finished | Aug 27 06:28:21 PM UTC 24 |
| Peak memory | 276172 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=497705394 -assert nopostproc +UVM_T ESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_stress_all.497705394 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/38.spi_device_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/38.spi_device_tpm_all.1874076331 |
| Short name | T804 |
| Test name | |
| Test status | |
| Simulation time | 11649046837 ps |
| CPU time | 31.47 seconds |
| Started | Aug 27 06:26:25 PM UTC 24 |
| Finished | Aug 27 06:26:58 PM UTC 24 |
| Peak memory | 233772 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1874076331 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_all.1874076331 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/38.spi_device_tpm_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/38.spi_device_tpm_read_hw_reg.2067392226 |
| Short name | T778 |
| Test name | |
| Test status | |
| Simulation time | 13274325380 ps |
| CPU time | 8.14 seconds |
| Started | Aug 27 06:26:24 PM UTC 24 |
| Finished | Aug 27 06:26:33 PM UTC 24 |
| Peak memory | 227636 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2067392226 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_26/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_read_hw_reg.2067392226 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/38.spi_device_tpm_read_hw_reg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/38.spi_device_tpm_rw.2122260694 |
| Short name | T740 |
| Test name | |
| Test status | |
| Simulation time | 115081817 ps |
| CPU time | 1.33 seconds |
| Started | Aug 27 06:26:27 PM UTC 24 |
| Finished | Aug 27 06:26:29 PM UTC 24 |
| Peak memory | 215696 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2122260694 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_rw.2122260694 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/38.spi_device_tpm_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/38.spi_device_tpm_sts_read.2021934524 |
| Short name | T772 |
| Test name | |
| Test status | |
| Simulation time | 28129217 ps |
| CPU time | 0.95 seconds |
| Started | Aug 27 06:26:25 PM UTC 24 |
| Finished | Aug 27 06:26:27 PM UTC 24 |
| Peak memory | 215872 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2021934524 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_2 6/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_sts_read.2021934524 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/38.spi_device_tpm_sts_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/38.spi_device_upload.291082358 |
| Short name | T781 |
| Test name | |
| Test status | |
| Simulation time | 1225147290 ps |
| CPU time | 6 seconds |
| Started | Aug 27 06:26:30 PM UTC 24 |
| Finished | Aug 27 06:26:37 PM UTC 24 |
| Peak memory | 245164 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=291082358 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/spi_d evice_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_upload.291082358 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/38.spi_device_upload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/39.spi_device_alert_test.422052964 |
| Short name | T801 |
| Test name | |
| Test status | |
| Simulation time | 82312554 ps |
| CPU time | 1.09 seconds |
| Started | Aug 27 06:26:55 PM UTC 24 |
| Finished | Aug 27 06:26:57 PM UTC 24 |
| Peak memory | 215684 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=422052964 -assert nopostproc +UVM_TEST NAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_alert_test.422052964 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/39.spi_device_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/39.spi_device_cfg_cmd.3988776605 |
| Short name | T799 |
| Test name | |
| Test status | |
| Simulation time | 103437447 ps |
| CPU time | 3.58 seconds |
| Started | Aug 27 06:26:49 PM UTC 24 |
| Finished | Aug 27 06:26:54 PM UTC 24 |
| Peak memory | 234900 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3988776605 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_cfg_cmd.3988776605 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/39.spi_device_cfg_cmd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/39.spi_device_csb_read.2598479062 |
| Short name | T786 |
| Test name | |
| Test status | |
| Simulation time | 99111879 ps |
| CPU time | 1.11 seconds |
| Started | Aug 27 06:26:40 PM UTC 24 |
| Finished | Aug 27 06:26:42 PM UTC 24 |
| Peak memory | 215580 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2598479062 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/sp i_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_csb_read.2598479062 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/39.spi_device_csb_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/39.spi_device_flash_all.3164646662 |
| Short name | T348 |
| Test name | |
| Test status | |
| Simulation time | 60163659807 ps |
| CPU time | 495.06 seconds |
| Started | Aug 27 06:26:52 PM UTC 24 |
| Finished | Aug 27 06:35:13 PM UTC 24 |
| Peak memory | 278112 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3164646662 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/s pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_all.3164646662 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/39.spi_device_flash_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/39.spi_device_flash_and_tpm.2365976941 |
| Short name | T937 |
| Test name | |
| Test status | |
| Simulation time | 59592805349 ps |
| CPU time | 161.78 seconds |
| Started | Aug 27 06:26:52 PM UTC 24 |
| Finished | Aug 27 06:29:37 PM UTC 24 |
| Peak memory | 249500 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2365976941 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_ 26/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_and_tpm.2365976941 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/39.spi_device_flash_and_tpm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/39.spi_device_flash_and_tpm_min_idle.1497210994 |
| Short name | T995 |
| Test name | |
| Test status | |
| Simulation time | 67061664906 ps |
| CPU time | 329.03 seconds |
| Started | Aug 27 06:26:54 PM UTC 24 |
| Finished | Aug 27 06:32:27 PM UTC 24 |
| Peak memory | 280176 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1497210994 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_26/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_and_tpm_min_idle.1497210994 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/39.spi_device_flash_and_tpm_min_idle/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/39.spi_device_flash_mode.380055987 |
| Short name | T355 |
| Test name | |
| Test status | |
| Simulation time | 990131017 ps |
| CPU time | 13.74 seconds |
| Started | Aug 27 06:26:49 PM UTC 24 |
| Finished | Aug 27 06:27:04 PM UTC 24 |
| Peak memory | 245204 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=380055987 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/s pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_mode.380055987 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/39.spi_device_flash_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/39.spi_device_flash_mode_ignore_cmds.4199578618 |
| Short name | T336 |
| Test name | |
| Test status | |
| Simulation time | 4034372989 ps |
| CPU time | 58.72 seconds |
| Started | Aug 27 06:26:50 PM UTC 24 |
| Finished | Aug 27 06:27:51 PM UTC 24 |
| Peak memory | 267864 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4199578618 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_26/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_mode_ignore_cmds.4199578618 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/39.spi_device_flash_mode_ignore_cmds/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/39.spi_device_intercept.1448688288 |
| Short name | T798 |
| Test name | |
| Test status | |
| Simulation time | 658382488 ps |
| CPU time | 6.15 seconds |
| Started | Aug 27 06:26:46 PM UTC 24 |
| Finished | Aug 27 06:26:54 PM UTC 24 |
| Peak memory | 245220 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1448688288 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/s pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_intercept.1448688288 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/39.spi_device_intercept/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/39.spi_device_mailbox.3330012038 |
| Short name | T828 |
| Test name | |
| Test status | |
| Simulation time | 3467536172 ps |
| CPU time | 30.42 seconds |
| Started | Aug 27 06:26:46 PM UTC 24 |
| Finished | Aug 27 06:27:18 PM UTC 24 |
| Peak memory | 251428 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3330012038 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_mailbox.3330012038 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/39.spi_device_mailbox/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/39.spi_device_pass_addr_payload_swap.3475471660 |
| Short name | T803 |
| Test name | |
| Test status | |
| Simulation time | 15790690126 ps |
| CPU time | 11.37 seconds |
| Started | Aug 27 06:26:45 PM UTC 24 |
| Finished | Aug 27 06:26:57 PM UTC 24 |
| Peak memory | 235092 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3475471660 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_26/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_pass_addr_payload_swap.3475471660 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/39.spi_device_pass_addr_payload_swap/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/39.spi_device_pass_cmd_filtering.3230532018 |
| Short name | T796 |
| Test name | |
| Test status | |
| Simulation time | 317664922 ps |
| CPU time | 8.33 seconds |
| Started | Aug 27 06:26:43 PM UTC 24 |
| Finished | Aug 27 06:26:52 PM UTC 24 |
| Peak memory | 245164 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3230532018 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_08_26/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_pass_cmd_filtering.3230532018 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/39.spi_device_pass_cmd_filtering/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/39.spi_device_read_buffer_direct.1471268764 |
| Short name | T807 |
| Test name | |
| Test status | |
| Simulation time | 2420745116 ps |
| CPU time | 7.34 seconds |
| Started | Aug 27 06:26:52 PM UTC 24 |
| Finished | Aug 27 06:27:00 PM UTC 24 |
| Peak memory | 233452 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1471268764 -assert nopostproc +UVM_TESTNAME=spi_device _base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_read_buffer_direct.1471268764 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/39.spi_device_read_buffer_direct/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/39.spi_device_stress_all.1651736834 |
| Short name | T996 |
| Test name | |
| Test status | |
| Simulation time | 134242448670 ps |
| CPU time | 356.14 seconds |
| Started | Aug 27 06:26:54 PM UTC 24 |
| Finished | Aug 27 06:32:55 PM UTC 24 |
| Peak memory | 265956 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1651736834 -assert nopostproc +UVM_ TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_stress_all.1651736834 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/39.spi_device_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/39.spi_device_tpm_all.175082701 |
| Short name | T819 |
| Test name | |
| Test status | |
| Simulation time | 62071045100 ps |
| CPU time | 28.5 seconds |
| Started | Aug 27 06:26:41 PM UTC 24 |
| Finished | Aug 27 06:27:11 PM UTC 24 |
| Peak memory | 227612 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=175082701 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_all.175082701 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/39.spi_device_tpm_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/39.spi_device_tpm_read_hw_reg.961753070 |
| Short name | T790 |
| Test name | |
| Test status | |
| Simulation time | 982675600 ps |
| CPU time | 5.25 seconds |
| Started | Aug 27 06:26:40 PM UTC 24 |
| Finished | Aug 27 06:26:46 PM UTC 24 |
| Peak memory | 227488 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=961753070 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08 _26/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_read_hw_reg.961753070 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/39.spi_device_tpm_read_hw_reg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/39.spi_device_tpm_rw.506151073 |
| Short name | T788 |
| Test name | |
| Test status | |
| Simulation time | 73189731 ps |
| CPU time | 1.27 seconds |
| Started | Aug 27 06:26:43 PM UTC 24 |
| Finished | Aug 27 06:26:45 PM UTC 24 |
| Peak memory | 215868 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=506151073 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/spi_d evice_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_rw.506151073 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/39.spi_device_tpm_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/39.spi_device_tpm_sts_read.1866286939 |
| Short name | T787 |
| Test name | |
| Test status | |
| Simulation time | 100159733 ps |
| CPU time | 1.34 seconds |
| Started | Aug 27 06:26:41 PM UTC 24 |
| Finished | Aug 27 06:26:44 PM UTC 24 |
| Peak memory | 215872 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1866286939 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_2 6/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_sts_read.1866286939 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/39.spi_device_tpm_sts_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/39.spi_device_upload.2882598809 |
| Short name | T809 |
| Test name | |
| Test status | |
| Simulation time | 10214239721 ps |
| CPU time | 12.98 seconds |
| Started | Aug 27 06:26:48 PM UTC 24 |
| Finished | Aug 27 06:27:02 PM UTC 24 |
| Peak memory | 249444 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2882598809 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_upload.2882598809 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/39.spi_device_upload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/4.spi_device_alert_test.498082580 |
| Short name | T384 |
| Test name | |
| Test status | |
| Simulation time | 13618692 ps |
| CPU time | 1.07 seconds |
| Started | Aug 27 06:12:10 PM UTC 24 |
| Finished | Aug 27 06:12:12 PM UTC 24 |
| Peak memory | 215744 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=498082580 -assert nopostproc +UVM_TEST NAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_alert_test.498082580 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/4.spi_device_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/4.spi_device_cfg_cmd.1503988692 |
| Short name | T211 |
| Test name | |
| Test status | |
| Simulation time | 623177588 ps |
| CPU time | 7.28 seconds |
| Started | Aug 27 06:11:54 PM UTC 24 |
| Finished | Aug 27 06:12:02 PM UTC 24 |
| Peak memory | 245160 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1503988692 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_cfg_cmd.1503988692 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/4.spi_device_cfg_cmd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/4.spi_device_csb_read.2421815215 |
| Short name | T380 |
| Test name | |
| Test status | |
| Simulation time | 15201464 ps |
| CPU time | 1.15 seconds |
| Started | Aug 27 06:11:36 PM UTC 24 |
| Finished | Aug 27 06:11:38 PM UTC 24 |
| Peak memory | 215748 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2421815215 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/sp i_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_csb_read.2421815215 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/4.spi_device_csb_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/4.spi_device_flash_all.1574949848 |
| Short name | T104 |
| Test name | |
| Test status | |
| Simulation time | 21014954038 ps |
| CPU time | 69.84 seconds |
| Started | Aug 27 06:12:03 PM UTC 24 |
| Finished | Aug 27 06:13:15 PM UTC 24 |
| Peak memory | 261796 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1574949848 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/s pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_all.1574949848 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/4.spi_device_flash_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/4.spi_device_flash_and_tpm.3933097734 |
| Short name | T264 |
| Test name | |
| Test status | |
| Simulation time | 8396465719 ps |
| CPU time | 105.27 seconds |
| Started | Aug 27 06:12:03 PM UTC 24 |
| Finished | Aug 27 06:13:51 PM UTC 24 |
| Peak memory | 267920 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3933097734 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_ 26/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_and_tpm.3933097734 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/4.spi_device_flash_and_tpm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/4.spi_device_flash_and_tpm_min_idle.4018753823 |
| Short name | T100 |
| Test name | |
| Test status | |
| Simulation time | 22356761512 ps |
| CPU time | 276.67 seconds |
| Started | Aug 27 06:12:03 PM UTC 24 |
| Finished | Aug 27 06:16:44 PM UTC 24 |
| Peak memory | 284296 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4018753823 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_26/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_and_tpm_min_idle.4018753823 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/4.spi_device_flash_and_tpm_min_idle/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/4.spi_device_flash_mode.1781308486 |
| Short name | T52 |
| Test name | |
| Test status | |
| Simulation time | 959441894 ps |
| CPU time | 13.35 seconds |
| Started | Aug 27 06:11:54 PM UTC 24 |
| Finished | Aug 27 06:12:08 PM UTC 24 |
| Peak memory | 247244 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1781308486 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/ spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_mode.1781308486 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/4.spi_device_flash_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/4.spi_device_intercept.3564918166 |
| Short name | T226 |
| Test name | |
| Test status | |
| Simulation time | 2760734172 ps |
| CPU time | 29.03 seconds |
| Started | Aug 27 06:11:49 PM UTC 24 |
| Finished | Aug 27 06:12:20 PM UTC 24 |
| Peak memory | 235108 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3564918166 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/s pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_intercept.3564918166 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/4.spi_device_intercept/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/4.spi_device_mailbox.2682490404 |
| Short name | T268 |
| Test name | |
| Test status | |
| Simulation time | 19427434026 ps |
| CPU time | 50.73 seconds |
| Started | Aug 27 06:11:53 PM UTC 24 |
| Finished | Aug 27 06:12:45 PM UTC 24 |
| Peak memory | 235112 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2682490404 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_mailbox.2682490404 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/4.spi_device_mailbox/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/4.spi_device_pass_addr_payload_swap.4026185024 |
| Short name | T382 |
| Test name | |
| Test status | |
| Simulation time | 51731028 ps |
| CPU time | 2.85 seconds |
| Started | Aug 27 06:11:49 PM UTC 24 |
| Finished | Aug 27 06:11:53 PM UTC 24 |
| Peak memory | 233576 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4026185024 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_26/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_pass_addr_payload_swap.4026185024 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/4.spi_device_pass_addr_payload_swap/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/4.spi_device_pass_cmd_filtering.1024700394 |
| Short name | T60 |
| Test name | |
| Test status | |
| Simulation time | 2971899460 ps |
| CPU time | 14.16 seconds |
| Started | Aug 27 06:11:47 PM UTC 24 |
| Finished | Aug 27 06:12:03 PM UTC 24 |
| Peak memory | 245328 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1024700394 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_08_26/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_pass_cmd_filtering.1024700394 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/4.spi_device_pass_cmd_filtering/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/4.spi_device_read_buffer_direct.1069272196 |
| Short name | T111 |
| Test name | |
| Test status | |
| Simulation time | 337542977 ps |
| CPU time | 5.47 seconds |
| Started | Aug 27 06:12:02 PM UTC 24 |
| Finished | Aug 27 06:12:09 PM UTC 24 |
| Peak memory | 234068 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1069272196 -assert nopostproc +UVM_TESTNAME=spi_device _base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_read_buffer_direct.1069272196 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/4.spi_device_read_buffer_direct/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/4.spi_device_sec_cm.395952853 |
| Short name | T2 |
| Test name | |
| Test status | |
| Simulation time | 312756247 ps |
| CPU time | 1.89 seconds |
| Started | Aug 27 06:12:10 PM UTC 24 |
| Finished | Aug 27 06:12:13 PM UTC 24 |
| Peak memory | 258040 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=395952853 -assert nopostproc +UVM_TESTN AME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_sec_cm.395952853 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/4.spi_device_sec_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/4.spi_device_stress_all.3090633435 |
| Short name | T260 |
| Test name | |
| Test status | |
| Simulation time | 569328160467 ps |
| CPU time | 435.57 seconds |
| Started | Aug 27 06:12:09 PM UTC 24 |
| Finished | Aug 27 06:19:30 PM UTC 24 |
| Peak memory | 276112 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3090633435 -assert nopostproc +UVM_ TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_stress_all.3090633435 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/4.spi_device_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/4.spi_device_tpm_all.1530201398 |
| Short name | T368 |
| Test name | |
| Test status | |
| Simulation time | 72955368851 ps |
| CPU time | 45.52 seconds |
| Started | Aug 27 06:11:40 PM UTC 24 |
| Finished | Aug 27 06:12:27 PM UTC 24 |
| Peak memory | 231716 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1530201398 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_all.1530201398 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/4.spi_device_tpm_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/4.spi_device_tpm_read_hw_reg.3467073252 |
| Short name | T383 |
| Test name | |
| Test status | |
| Simulation time | 7143300314 ps |
| CPU time | 22.04 seconds |
| Started | Aug 27 06:11:39 PM UTC 24 |
| Finished | Aug 27 06:12:02 PM UTC 24 |
| Peak memory | 227684 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3467073252 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_26/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_read_hw_reg.3467073252 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/4.spi_device_tpm_read_hw_reg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/4.spi_device_tpm_rw.2723670228 |
| Short name | T68 |
| Test name | |
| Test status | |
| Simulation time | 146575190 ps |
| CPU time | 2.8 seconds |
| Started | Aug 27 06:11:45 PM UTC 24 |
| Finished | Aug 27 06:11:49 PM UTC 24 |
| Peak memory | 227484 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2723670228 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_rw.2723670228 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/4.spi_device_tpm_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/4.spi_device_tpm_sts_read.3292129218 |
| Short name | T381 |
| Test name | |
| Test status | |
| Simulation time | 185652374 ps |
| CPU time | 1.29 seconds |
| Started | Aug 27 06:11:44 PM UTC 24 |
| Finished | Aug 27 06:11:46 PM UTC 24 |
| Peak memory | 215868 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3292129218 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_2 6/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_sts_read.3292129218 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/4.spi_device_tpm_sts_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/4.spi_device_upload.1337853986 |
| Short name | T251 |
| Test name | |
| Test status | |
| Simulation time | 11749766560 ps |
| CPU time | 30.12 seconds |
| Started | Aug 27 06:11:53 PM UTC 24 |
| Finished | Aug 27 06:12:24 PM UTC 24 |
| Peak memory | 235096 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1337853986 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_upload.1337853986 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/4.spi_device_upload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/40.spi_device_alert_test.1673286619 |
| Short name | T816 |
| Test name | |
| Test status | |
| Simulation time | 35626460 ps |
| CPU time | 1.09 seconds |
| Started | Aug 27 06:27:08 PM UTC 24 |
| Finished | Aug 27 06:27:10 PM UTC 24 |
| Peak memory | 215744 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1673286619 -assert nopostproc +UVM_TES TNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_alert_test.1673286619 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/40.spi_device_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/40.spi_device_cfg_cmd.2832483711 |
| Short name | T820 |
| Test name | |
| Test status | |
| Simulation time | 233737071 ps |
| CPU time | 6.78 seconds |
| Started | Aug 27 06:27:03 PM UTC 24 |
| Finished | Aug 27 06:27:11 PM UTC 24 |
| Peak memory | 245216 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2832483711 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_cfg_cmd.2832483711 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/40.spi_device_cfg_cmd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/40.spi_device_csb_read.717895044 |
| Short name | T802 |
| Test name | |
| Test status | |
| Simulation time | 16817441 ps |
| CPU time | 1.15 seconds |
| Started | Aug 27 06:26:55 PM UTC 24 |
| Finished | Aug 27 06:26:57 PM UTC 24 |
| Peak memory | 215808 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=717895044 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_csb_read.717895044 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/40.spi_device_csb_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/40.spi_device_flash_all.2116613969 |
| Short name | T862 |
| Test name | |
| Test status | |
| Simulation time | 10543383354 ps |
| CPU time | 55.12 seconds |
| Started | Aug 27 06:27:06 PM UTC 24 |
| Finished | Aug 27 06:28:02 PM UTC 24 |
| Peak memory | 251320 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2116613969 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/s pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_all.2116613969 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/40.spi_device_flash_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/40.spi_device_flash_and_tpm.1557855050 |
| Short name | T867 |
| Test name | |
| Test status | |
| Simulation time | 4163699232 ps |
| CPU time | 62.11 seconds |
| Started | Aug 27 06:27:06 PM UTC 24 |
| Finished | Aug 27 06:28:09 PM UTC 24 |
| Peak memory | 267916 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1557855050 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_ 26/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_and_tpm.1557855050 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/40.spi_device_flash_and_tpm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/40.spi_device_flash_and_tpm_min_idle.3223203807 |
| Short name | T73 |
| Test name | |
| Test status | |
| Simulation time | 100244723809 ps |
| CPU time | 245.03 seconds |
| Started | Aug 27 06:27:06 PM UTC 24 |
| Finished | Aug 27 06:31:14 PM UTC 24 |
| Peak memory | 251472 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3223203807 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_26/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_and_tpm_min_idle.3223203807 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/40.spi_device_flash_and_tpm_min_idle/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/40.spi_device_flash_mode.1832738843 |
| Short name | T850 |
| Test name | |
| Test status | |
| Simulation time | 7427741726 ps |
| CPU time | 40.47 seconds |
| Started | Aug 27 06:27:03 PM UTC 24 |
| Finished | Aug 27 06:27:45 PM UTC 24 |
| Peak memory | 251556 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1832738843 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/ spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_mode.1832738843 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/40.spi_device_flash_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/40.spi_device_flash_mode_ignore_cmds.3531532379 |
| Short name | T980 |
| Test name | |
| Test status | |
| Simulation time | 22440037992 ps |
| CPU time | 198.49 seconds |
| Started | Aug 27 06:27:04 PM UTC 24 |
| Finished | Aug 27 06:30:25 PM UTC 24 |
| Peak memory | 263760 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3531532379 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_26/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_mode_ignore_cmds.3531532379 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/40.spi_device_flash_mode_ignore_cmds/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/40.spi_device_intercept.1231105614 |
| Short name | T814 |
| Test name | |
| Test status | |
| Simulation time | 344163014 ps |
| CPU time | 3.91 seconds |
| Started | Aug 27 06:27:01 PM UTC 24 |
| Finished | Aug 27 06:27:06 PM UTC 24 |
| Peak memory | 245156 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1231105614 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/s pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_intercept.1231105614 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/40.spi_device_intercept/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/40.spi_device_mailbox.2982906312 |
| Short name | T964 |
| Test name | |
| Test status | |
| Simulation time | 48659359127 ps |
| CPU time | 176 seconds |
| Started | Aug 27 06:27:02 PM UTC 24 |
| Finished | Aug 27 06:30:00 PM UTC 24 |
| Peak memory | 251468 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2982906312 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_mailbox.2982906312 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/40.spi_device_mailbox/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/40.spi_device_pass_addr_payload_swap.1034575295 |
| Short name | T836 |
| Test name | |
| Test status | |
| Simulation time | 17778266858 ps |
| CPU time | 24.51 seconds |
| Started | Aug 27 06:27:00 PM UTC 24 |
| Finished | Aug 27 06:27:25 PM UTC 24 |
| Peak memory | 235032 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1034575295 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_26/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_pass_addr_payload_swap.1034575295 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/40.spi_device_pass_addr_payload_swap/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/40.spi_device_pass_cmd_filtering.394488804 |
| Short name | T818 |
| Test name | |
| Test status | |
| Simulation time | 6895146081 ps |
| CPU time | 9.53 seconds |
| Started | Aug 27 06:27:00 PM UTC 24 |
| Finished | Aug 27 06:27:10 PM UTC 24 |
| Peak memory | 235056 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=394488804 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _08_26/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_pass_cmd_filtering.394488804 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/40.spi_device_pass_cmd_filtering/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/40.spi_device_read_buffer_direct.2832494187 |
| Short name | T830 |
| Test name | |
| Test status | |
| Simulation time | 3785465053 ps |
| CPU time | 13.95 seconds |
| Started | Aug 27 06:27:04 PM UTC 24 |
| Finished | Aug 27 06:27:19 PM UTC 24 |
| Peak memory | 233512 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2832494187 -assert nopostproc +UVM_TESTNAME=spi_device _base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_read_buffer_direct.2832494187 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/40.spi_device_read_buffer_direct/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/40.spi_device_stress_all.482274693 |
| Short name | T815 |
| Test name | |
| Test status | |
| Simulation time | 49358833 ps |
| CPU time | 1.46 seconds |
| Started | Aug 27 06:27:06 PM UTC 24 |
| Finished | Aug 27 06:27:08 PM UTC 24 |
| Peak memory | 215744 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=482274693 -assert nopostproc +UVM_T ESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_stress_all.482274693 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/40.spi_device_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/40.spi_device_tpm_all.2254184910 |
| Short name | T810 |
| Test name | |
| Test status | |
| Simulation time | 465797975 ps |
| CPU time | 2.94 seconds |
| Started | Aug 27 06:26:58 PM UTC 24 |
| Finished | Aug 27 06:27:02 PM UTC 24 |
| Peak memory | 227452 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2254184910 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_all.2254184910 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/40.spi_device_tpm_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/40.spi_device_tpm_read_hw_reg.728491138 |
| Short name | T808 |
| Test name | |
| Test status | |
| Simulation time | 868197776 ps |
| CPU time | 4.08 seconds |
| Started | Aug 27 06:26:57 PM UTC 24 |
| Finished | Aug 27 06:27:02 PM UTC 24 |
| Peak memory | 227488 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=728491138 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08 _26/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_read_hw_reg.728491138 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/40.spi_device_tpm_read_hw_reg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/40.spi_device_tpm_rw.847182788 |
| Short name | T811 |
| Test name | |
| Test status | |
| Simulation time | 157776597 ps |
| CPU time | 2.07 seconds |
| Started | Aug 27 06:27:00 PM UTC 24 |
| Finished | Aug 27 06:27:03 PM UTC 24 |
| Peak memory | 227480 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=847182788 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/spi_d evice_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_rw.847182788 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/40.spi_device_tpm_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/40.spi_device_tpm_sts_read.151889233 |
| Short name | T805 |
| Test name | |
| Test status | |
| Simulation time | 51212321 ps |
| CPU time | 1.26 seconds |
| Started | Aug 27 06:26:58 PM UTC 24 |
| Finished | Aug 27 06:27:00 PM UTC 24 |
| Peak memory | 215868 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=151889233 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26 /spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_sts_read.151889233 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/40.spi_device_tpm_sts_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/40.spi_device_upload.2035770096 |
| Short name | T824 |
| Test name | |
| Test status | |
| Simulation time | 25873543441 ps |
| CPU time | 10.76 seconds |
| Started | Aug 27 06:27:02 PM UTC 24 |
| Finished | Aug 27 06:27:13 PM UTC 24 |
| Peak memory | 235032 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2035770096 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_upload.2035770096 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/40.spi_device_upload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/41.spi_device_alert_test.1253508177 |
| Short name | T832 |
| Test name | |
| Test status | |
| Simulation time | 28276819 ps |
| CPU time | 1.11 seconds |
| Started | Aug 27 06:27:21 PM UTC 24 |
| Finished | Aug 27 06:27:23 PM UTC 24 |
| Peak memory | 215804 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1253508177 -assert nopostproc +UVM_TES TNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_alert_test.1253508177 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/41.spi_device_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/41.spi_device_cfg_cmd.3047761692 |
| Short name | T829 |
| Test name | |
| Test status | |
| Simulation time | 31797823 ps |
| CPU time | 2.85 seconds |
| Started | Aug 27 06:27:15 PM UTC 24 |
| Finished | Aug 27 06:27:19 PM UTC 24 |
| Peak memory | 234668 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3047761692 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_cfg_cmd.3047761692 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/41.spi_device_cfg_cmd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/41.spi_device_csb_read.1963784409 |
| Short name | T817 |
| Test name | |
| Test status | |
| Simulation time | 50796849 ps |
| CPU time | 1.17 seconds |
| Started | Aug 27 06:27:08 PM UTC 24 |
| Finished | Aug 27 06:27:10 PM UTC 24 |
| Peak memory | 215812 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1963784409 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/sp i_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_csb_read.1963784409 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/41.spi_device_csb_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/41.spi_device_flash_all.3182873374 |
| Short name | T865 |
| Test name | |
| Test status | |
| Simulation time | 1703206715 ps |
| CPU time | 46.24 seconds |
| Started | Aug 27 06:27:18 PM UTC 24 |
| Finished | Aug 27 06:28:05 PM UTC 24 |
| Peak memory | 263828 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3182873374 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/s pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_all.3182873374 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/41.spi_device_flash_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/41.spi_device_flash_and_tpm.387763037 |
| Short name | T993 |
| Test name | |
| Test status | |
| Simulation time | 154161430181 ps |
| CPU time | 292.75 seconds |
| Started | Aug 27 06:27:19 PM UTC 24 |
| Finished | Aug 27 06:32:16 PM UTC 24 |
| Peak memory | 263884 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=387763037 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_2 6/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_and_tpm.387763037 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/41.spi_device_flash_and_tpm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/41.spi_device_flash_and_tpm_min_idle.442551437 |
| Short name | T998 |
| Test name | |
| Test status | |
| Simulation time | 101509938215 ps |
| CPU time | 339.48 seconds |
| Started | Aug 27 06:27:19 PM UTC 24 |
| Finished | Aug 27 06:33:03 PM UTC 24 |
| Peak memory | 265844 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=442551437 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_26/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_and_tpm_min_idle.442551437 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/41.spi_device_flash_and_tpm_min_idle/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/41.spi_device_flash_mode.3201816562 |
| Short name | T834 |
| Test name | |
| Test status | |
| Simulation time | 549288586 ps |
| CPU time | 8.16 seconds |
| Started | Aug 27 06:27:15 PM UTC 24 |
| Finished | Aug 27 06:27:24 PM UTC 24 |
| Peak memory | 245140 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3201816562 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/ spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_mode.3201816562 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/41.spi_device_flash_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/41.spi_device_flash_mode_ignore_cmds.3620449081 |
| Short name | T856 |
| Test name | |
| Test status | |
| Simulation time | 3888662098 ps |
| CPU time | 30.76 seconds |
| Started | Aug 27 06:27:16 PM UTC 24 |
| Finished | Aug 27 06:27:48 PM UTC 24 |
| Peak memory | 247336 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3620449081 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_26/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_mode_ignore_cmds.3620449081 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/41.spi_device_flash_mode_ignore_cmds/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/41.spi_device_intercept.1686957772 |
| Short name | T831 |
| Test name | |
| Test status | |
| Simulation time | 187157553 ps |
| CPU time | 5.57 seconds |
| Started | Aug 27 06:27:13 PM UTC 24 |
| Finished | Aug 27 06:27:20 PM UTC 24 |
| Peak memory | 234968 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1686957772 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/s pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_intercept.1686957772 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/41.spi_device_intercept/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/41.spi_device_mailbox.3559285707 |
| Short name | T826 |
| Test name | |
| Test status | |
| Simulation time | 33743454 ps |
| CPU time | 2.43 seconds |
| Started | Aug 27 06:27:13 PM UTC 24 |
| Finished | Aug 27 06:27:16 PM UTC 24 |
| Peak memory | 244944 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3559285707 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_mailbox.3559285707 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/41.spi_device_mailbox/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/41.spi_device_pass_addr_payload_swap.3561935876 |
| Short name | T827 |
| Test name | |
| Test status | |
| Simulation time | 116127405 ps |
| CPU time | 2.84 seconds |
| Started | Aug 27 06:27:13 PM UTC 24 |
| Finished | Aug 27 06:27:17 PM UTC 24 |
| Peak memory | 234904 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3561935876 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_26/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_pass_addr_payload_swap.3561935876 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/41.spi_device_pass_addr_payload_swap/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/41.spi_device_pass_cmd_filtering.3871772293 |
| Short name | T833 |
| Test name | |
| Test status | |
| Simulation time | 1650635586 ps |
| CPU time | 9.86 seconds |
| Started | Aug 27 06:27:13 PM UTC 24 |
| Finished | Aug 27 06:27:24 PM UTC 24 |
| Peak memory | 245208 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3871772293 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_08_26/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_pass_cmd_filtering.3871772293 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/41.spi_device_pass_cmd_filtering/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/41.spi_device_read_buffer_direct.3533074282 |
| Short name | T841 |
| Test name | |
| Test status | |
| Simulation time | 700086431 ps |
| CPU time | 13.3 seconds |
| Started | Aug 27 06:27:18 PM UTC 24 |
| Finished | Aug 27 06:27:32 PM UTC 24 |
| Peak memory | 231324 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3533074282 -assert nopostproc +UVM_TESTNAME=spi_device _base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_read_buffer_direct.3533074282 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/41.spi_device_read_buffer_direct/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/41.spi_device_stress_all.739296169 |
| Short name | T1014 |
| Test name | |
| Test status | |
| Simulation time | 127217337873 ps |
| CPU time | 1157.58 seconds |
| Started | Aug 27 06:27:21 PM UTC 24 |
| Finished | Aug 27 06:46:51 PM UTC 24 |
| Peak memory | 327316 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=739296169 -assert nopostproc +UVM_T ESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_stress_all.739296169 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/41.spi_device_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/41.spi_device_tpm_all.197967685 |
| Short name | T851 |
| Test name | |
| Test status | |
| Simulation time | 4749387891 ps |
| CPU time | 35.55 seconds |
| Started | Aug 27 06:27:09 PM UTC 24 |
| Finished | Aug 27 06:27:46 PM UTC 24 |
| Peak memory | 227680 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=197967685 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_all.197967685 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/41.spi_device_tpm_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/41.spi_device_tpm_read_hw_reg.2872103367 |
| Short name | T821 |
| Test name | |
| Test status | |
| Simulation time | 414313719 ps |
| CPU time | 2.85 seconds |
| Started | Aug 27 06:27:08 PM UTC 24 |
| Finished | Aug 27 06:27:12 PM UTC 24 |
| Peak memory | 227396 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2872103367 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_26/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_read_hw_reg.2872103367 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/41.spi_device_tpm_read_hw_reg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/41.spi_device_tpm_rw.2874330862 |
| Short name | T822 |
| Test name | |
| Test status | |
| Simulation time | 33551766 ps |
| CPU time | 1.04 seconds |
| Started | Aug 27 06:27:11 PM UTC 24 |
| Finished | Aug 27 06:27:13 PM UTC 24 |
| Peak memory | 215744 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2874330862 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_rw.2874330862 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/41.spi_device_tpm_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/41.spi_device_tpm_sts_read.2065025443 |
| Short name | T823 |
| Test name | |
| Test status | |
| Simulation time | 22090235 ps |
| CPU time | 1.21 seconds |
| Started | Aug 27 06:27:11 PM UTC 24 |
| Finished | Aug 27 06:27:13 PM UTC 24 |
| Peak memory | 215872 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2065025443 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_2 6/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_sts_read.2065025443 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/41.spi_device_tpm_sts_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/41.spi_device_upload.249405917 |
| Short name | T840 |
| Test name | |
| Test status | |
| Simulation time | 8590154150 ps |
| CPU time | 15.02 seconds |
| Started | Aug 27 06:27:15 PM UTC 24 |
| Finished | Aug 27 06:27:31 PM UTC 24 |
| Peak memory | 245336 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=249405917 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/spi_d evice_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_upload.249405917 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/41.spi_device_upload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/42.spi_device_alert_test.2619337389 |
| Short name | T853 |
| Test name | |
| Test status | |
| Simulation time | 12811895 ps |
| CPU time | 1.1 seconds |
| Started | Aug 27 06:27:45 PM UTC 24 |
| Finished | Aug 27 06:27:47 PM UTC 24 |
| Peak memory | 215744 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2619337389 -assert nopostproc +UVM_TES TNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_alert_test.2619337389 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/42.spi_device_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/42.spi_device_cfg_cmd.2350877632 |
| Short name | T846 |
| Test name | |
| Test status | |
| Simulation time | 190579117 ps |
| CPU time | 5.94 seconds |
| Started | Aug 27 06:27:34 PM UTC 24 |
| Finished | Aug 27 06:27:41 PM UTC 24 |
| Peak memory | 245220 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2350877632 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_cfg_cmd.2350877632 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/42.spi_device_cfg_cmd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/42.spi_device_csb_read.3752799770 |
| Short name | T835 |
| Test name | |
| Test status | |
| Simulation time | 48231020 ps |
| CPU time | 1.14 seconds |
| Started | Aug 27 06:27:22 PM UTC 24 |
| Finished | Aug 27 06:27:24 PM UTC 24 |
| Peak memory | 215580 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3752799770 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/sp i_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_csb_read.3752799770 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/42.spi_device_csb_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/42.spi_device_flash_all.2243152335 |
| Short name | T858 |
| Test name | |
| Test status | |
| Simulation time | 2448941479 ps |
| CPU time | 11.7 seconds |
| Started | Aug 27 06:27:40 PM UTC 24 |
| Finished | Aug 27 06:27:52 PM UTC 24 |
| Peak memory | 231720 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2243152335 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/s pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_all.2243152335 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/42.spi_device_flash_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/42.spi_device_flash_and_tpm.2302872840 |
| Short name | T893 |
| Test name | |
| Test status | |
| Simulation time | 14200527526 ps |
| CPU time | 55.66 seconds |
| Started | Aug 27 06:27:42 PM UTC 24 |
| Finished | Aug 27 06:28:39 PM UTC 24 |
| Peak memory | 261784 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2302872840 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_ 26/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_and_tpm.2302872840 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/42.spi_device_flash_and_tpm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/42.spi_device_flash_and_tpm_min_idle.1070161253 |
| Short name | T330 |
| Test name | |
| Test status | |
| Simulation time | 13943440911 ps |
| CPU time | 136.24 seconds |
| Started | Aug 27 06:27:42 PM UTC 24 |
| Finished | Aug 27 06:30:01 PM UTC 24 |
| Peak memory | 280292 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1070161253 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_26/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_and_tpm_min_idle.1070161253 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/42.spi_device_flash_and_tpm_min_idle/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/42.spi_device_flash_mode.3885728713 |
| Short name | T868 |
| Test name | |
| Test status | |
| Simulation time | 6705144042 ps |
| CPU time | 36.17 seconds |
| Started | Aug 27 06:27:35 PM UTC 24 |
| Finished | Aug 27 06:28:13 PM UTC 24 |
| Peak memory | 251488 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3885728713 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/ spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_mode.3885728713 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/42.spi_device_flash_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/42.spi_device_flash_mode_ignore_cmds.107147242 |
| Short name | T930 |
| Test name | |
| Test status | |
| Simulation time | 45643865978 ps |
| CPU time | 106.14 seconds |
| Started | Aug 27 06:27:35 PM UTC 24 |
| Finished | Aug 27 06:29:23 PM UTC 24 |
| Peak memory | 261732 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=107147242 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_26/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_mode_ignore_cmds.107147242 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/42.spi_device_flash_mode_ignore_cmds/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/42.spi_device_intercept.3180811876 |
| Short name | T847 |
| Test name | |
| Test status | |
| Simulation time | 266415967 ps |
| CPU time | 8.38 seconds |
| Started | Aug 27 06:27:31 PM UTC 24 |
| Finished | Aug 27 06:27:41 PM UTC 24 |
| Peak memory | 229480 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3180811876 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/s pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_intercept.3180811876 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/42.spi_device_intercept/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/42.spi_device_mailbox.3576850287 |
| Short name | T849 |
| Test name | |
| Test status | |
| Simulation time | 472362276 ps |
| CPU time | 11.2 seconds |
| Started | Aug 27 06:27:31 PM UTC 24 |
| Finished | Aug 27 06:27:44 PM UTC 24 |
| Peak memory | 245160 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3576850287 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_mailbox.3576850287 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/42.spi_device_mailbox/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/42.spi_device_pass_addr_payload_swap.3924987236 |
| Short name | T843 |
| Test name | |
| Test status | |
| Simulation time | 478152900 ps |
| CPU time | 3.35 seconds |
| Started | Aug 27 06:27:30 PM UTC 24 |
| Finished | Aug 27 06:27:34 PM UTC 24 |
| Peak memory | 245204 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3924987236 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_26/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_pass_addr_payload_swap.3924987236 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/42.spi_device_pass_addr_payload_swap/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/42.spi_device_pass_cmd_filtering.3791237611 |
| Short name | T848 |
| Test name | |
| Test status | |
| Simulation time | 10315864480 ps |
| CPU time | 13.48 seconds |
| Started | Aug 27 06:27:27 PM UTC 24 |
| Finished | Aug 27 06:27:42 PM UTC 24 |
| Peak memory | 245396 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3791237611 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_08_26/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_pass_cmd_filtering.3791237611 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/42.spi_device_pass_cmd_filtering/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/42.spi_device_read_buffer_direct.708480500 |
| Short name | T852 |
| Test name | |
| Test status | |
| Simulation time | 715726541 ps |
| CPU time | 7.52 seconds |
| Started | Aug 27 06:27:38 PM UTC 24 |
| Finished | Aug 27 06:27:47 PM UTC 24 |
| Peak memory | 231332 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=708480500 -assert nopostproc +UVM_TESTNAME=spi_device_ base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_read_buffer_direct.708480500 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/42.spi_device_read_buffer_direct/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/42.spi_device_stress_all.1886053943 |
| Short name | T1000 |
| Test name | |
| Test status | |
| Simulation time | 30999159699 ps |
| CPU time | 357.92 seconds |
| Started | Aug 27 06:27:43 PM UTC 24 |
| Finished | Aug 27 06:33:46 PM UTC 24 |
| Peak memory | 265872 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1886053943 -assert nopostproc +UVM_ TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_stress_all.1886053943 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/42.spi_device_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/42.spi_device_tpm_all.2641912494 |
| Short name | T879 |
| Test name | |
| Test status | |
| Simulation time | 97272594798 ps |
| CPU time | 53.96 seconds |
| Started | Aug 27 06:27:26 PM UTC 24 |
| Finished | Aug 27 06:28:22 PM UTC 24 |
| Peak memory | 227276 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2641912494 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_all.2641912494 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/42.spi_device_tpm_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/42.spi_device_tpm_read_hw_reg.3644183171 |
| Short name | T845 |
| Test name | |
| Test status | |
| Simulation time | 2036695447 ps |
| CPU time | 12.64 seconds |
| Started | Aug 27 06:27:24 PM UTC 24 |
| Finished | Aug 27 06:27:38 PM UTC 24 |
| Peak memory | 227420 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3644183171 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_26/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_read_hw_reg.3644183171 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/42.spi_device_tpm_read_hw_reg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/42.spi_device_tpm_rw.3814995030 |
| Short name | T839 |
| Test name | |
| Test status | |
| Simulation time | 559358133 ps |
| CPU time | 3.04 seconds |
| Started | Aug 27 06:27:26 PM UTC 24 |
| Finished | Aug 27 06:27:30 PM UTC 24 |
| Peak memory | 227484 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3814995030 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_rw.3814995030 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/42.spi_device_tpm_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/42.spi_device_tpm_sts_read.2006216047 |
| Short name | T837 |
| Test name | |
| Test status | |
| Simulation time | 46207422 ps |
| CPU time | 1.33 seconds |
| Started | Aug 27 06:27:26 PM UTC 24 |
| Finished | Aug 27 06:27:28 PM UTC 24 |
| Peak memory | 215696 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2006216047 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_2 6/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_sts_read.2006216047 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/42.spi_device_tpm_sts_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/42.spi_device_upload.1888621077 |
| Short name | T844 |
| Test name | |
| Test status | |
| Simulation time | 85911629 ps |
| CPU time | 3.9 seconds |
| Started | Aug 27 06:27:32 PM UTC 24 |
| Finished | Aug 27 06:27:37 PM UTC 24 |
| Peak memory | 245220 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1888621077 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_upload.1888621077 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/42.spi_device_upload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/43.spi_device_alert_test.1552294516 |
| Short name | T869 |
| Test name | |
| Test status | |
| Simulation time | 14659983 ps |
| CPU time | 1.11 seconds |
| Started | Aug 27 06:28:10 PM UTC 24 |
| Finished | Aug 27 06:28:13 PM UTC 24 |
| Peak memory | 215744 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1552294516 -assert nopostproc +UVM_TES TNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_alert_test.1552294516 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/43.spi_device_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/43.spi_device_cfg_cmd.2432715396 |
| Short name | T864 |
| Test name | |
| Test status | |
| Simulation time | 1659149647 ps |
| CPU time | 8.57 seconds |
| Started | Aug 27 06:27:55 PM UTC 24 |
| Finished | Aug 27 06:28:04 PM UTC 24 |
| Peak memory | 245284 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2432715396 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_cfg_cmd.2432715396 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/43.spi_device_cfg_cmd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/43.spi_device_csb_read.2712981288 |
| Short name | T855 |
| Test name | |
| Test status | |
| Simulation time | 52371709 ps |
| CPU time | 1.16 seconds |
| Started | Aug 27 06:27:46 PM UTC 24 |
| Finished | Aug 27 06:27:48 PM UTC 24 |
| Peak memory | 215808 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2712981288 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/sp i_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_csb_read.2712981288 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/43.spi_device_csb_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/43.spi_device_flash_all.1037645587 |
| Short name | T892 |
| Test name | |
| Test status | |
| Simulation time | 6075749938 ps |
| CPU time | 32.45 seconds |
| Started | Aug 27 06:28:05 PM UTC 24 |
| Finished | Aug 27 06:28:39 PM UTC 24 |
| Peak memory | 249448 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1037645587 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/s pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_all.1037645587 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/43.spi_device_flash_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/43.spi_device_flash_and_tpm.240350668 |
| Short name | T74 |
| Test name | |
| Test status | |
| Simulation time | 20486337466 ps |
| CPU time | 187.41 seconds |
| Started | Aug 27 06:28:05 PM UTC 24 |
| Finished | Aug 27 06:31:16 PM UTC 24 |
| Peak memory | 261780 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=240350668 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_2 6/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_and_tpm.240350668 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/43.spi_device_flash_and_tpm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/43.spi_device_flash_and_tpm_min_idle.278108073 |
| Short name | T977 |
| Test name | |
| Test status | |
| Simulation time | 5913852903 ps |
| CPU time | 128.6 seconds |
| Started | Aug 27 06:28:05 PM UTC 24 |
| Finished | Aug 27 06:30:16 PM UTC 24 |
| Peak memory | 267916 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=278108073 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_26/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_and_tpm_min_idle.278108073 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/43.spi_device_flash_and_tpm_min_idle/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/43.spi_device_flash_mode.931472956 |
| Short name | T874 |
| Test name | |
| Test status | |
| Simulation time | 17026813762 ps |
| CPU time | 15.73 seconds |
| Started | Aug 27 06:27:59 PM UTC 24 |
| Finished | Aug 27 06:28:16 PM UTC 24 |
| Peak memory | 235216 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=931472956 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/s pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_mode.931472956 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/43.spi_device_flash_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/43.spi_device_flash_mode_ignore_cmds.1363620825 |
| Short name | T1003 |
| Test name | |
| Test status | |
| Simulation time | 155926060233 ps |
| CPU time | 353.23 seconds |
| Started | Aug 27 06:28:00 PM UTC 24 |
| Finished | Aug 27 06:33:58 PM UTC 24 |
| Peak memory | 265828 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1363620825 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_26/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_mode_ignore_cmds.1363620825 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/43.spi_device_flash_mode_ignore_cmds/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/43.spi_device_intercept.3601005982 |
| Short name | T860 |
| Test name | |
| Test status | |
| Simulation time | 95874513 ps |
| CPU time | 5.06 seconds |
| Started | Aug 27 06:27:52 PM UTC 24 |
| Finished | Aug 27 06:27:58 PM UTC 24 |
| Peak memory | 245160 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3601005982 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/s pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_intercept.3601005982 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/43.spi_device_intercept/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/43.spi_device_mailbox.872058695 |
| Short name | T863 |
| Test name | |
| Test status | |
| Simulation time | 307635598 ps |
| CPU time | 11.02 seconds |
| Started | Aug 27 06:27:52 PM UTC 24 |
| Finished | Aug 27 06:28:04 PM UTC 24 |
| Peak memory | 245264 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=872058695 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_mailbox.872058695 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/43.spi_device_mailbox/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/43.spi_device_pass_addr_payload_swap.3320333311 |
| Short name | T870 |
| Test name | |
| Test status | |
| Simulation time | 4679502226 ps |
| CPU time | 22.05 seconds |
| Started | Aug 27 06:27:50 PM UTC 24 |
| Finished | Aug 27 06:28:13 PM UTC 24 |
| Peak memory | 251476 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3320333311 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_26/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_pass_addr_payload_swap.3320333311 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/43.spi_device_pass_addr_payload_swap/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/43.spi_device_pass_cmd_filtering.676727209 |
| Short name | T861 |
| Test name | |
| Test status | |
| Simulation time | 749552990 ps |
| CPU time | 8.2 seconds |
| Started | Aug 27 06:27:50 PM UTC 24 |
| Finished | Aug 27 06:27:59 PM UTC 24 |
| Peak memory | 251344 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=676727209 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _08_26/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_pass_cmd_filtering.676727209 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/43.spi_device_pass_cmd_filtering/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/43.spi_device_read_buffer_direct.3085311437 |
| Short name | T883 |
| Test name | |
| Test status | |
| Simulation time | 2816828798 ps |
| CPU time | 20.27 seconds |
| Started | Aug 27 06:28:04 PM UTC 24 |
| Finished | Aug 27 06:28:25 PM UTC 24 |
| Peak memory | 231448 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3085311437 -assert nopostproc +UVM_TESTNAME=spi_device _base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_read_buffer_direct.3085311437 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/43.spi_device_read_buffer_direct/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/43.spi_device_stress_all.3463639566 |
| Short name | T345 |
| Test name | |
| Test status | |
| Simulation time | 98419102644 ps |
| CPU time | 413.68 seconds |
| Started | Aug 27 06:28:07 PM UTC 24 |
| Finished | Aug 27 06:35:05 PM UTC 24 |
| Peak memory | 278220 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3463639566 -assert nopostproc +UVM_ TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_stress_all.3463639566 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/43.spi_device_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/43.spi_device_tpm_all.4205085708 |
| Short name | T866 |
| Test name | |
| Test status | |
| Simulation time | 4381576998 ps |
| CPU time | 19.87 seconds |
| Started | Aug 27 06:27:48 PM UTC 24 |
| Finished | Aug 27 06:28:09 PM UTC 24 |
| Peak memory | 231720 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4205085708 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_all.4205085708 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/43.spi_device_tpm_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/43.spi_device_tpm_read_hw_reg.926037009 |
| Short name | T880 |
| Test name | |
| Test status | |
| Simulation time | 30427329758 ps |
| CPU time | 33.09 seconds |
| Started | Aug 27 06:27:48 PM UTC 24 |
| Finished | Aug 27 06:28:22 PM UTC 24 |
| Peak memory | 227556 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=926037009 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08 _26/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_read_hw_reg.926037009 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/43.spi_device_tpm_read_hw_reg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/43.spi_device_tpm_rw.3087026012 |
| Short name | T859 |
| Test name | |
| Test status | |
| Simulation time | 67496306 ps |
| CPU time | 3.21 seconds |
| Started | Aug 27 06:27:50 PM UTC 24 |
| Finished | Aug 27 06:27:54 PM UTC 24 |
| Peak memory | 227500 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3087026012 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_rw.3087026012 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/43.spi_device_tpm_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/43.spi_device_tpm_sts_read.433505208 |
| Short name | T857 |
| Test name | |
| Test status | |
| Simulation time | 569778018 ps |
| CPU time | 1.63 seconds |
| Started | Aug 27 06:27:48 PM UTC 24 |
| Finished | Aug 27 06:27:51 PM UTC 24 |
| Peak memory | 215868 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=433505208 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26 /spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_sts_read.433505208 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/43.spi_device_tpm_sts_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/43.spi_device_upload.895438695 |
| Short name | T872 |
| Test name | |
| Test status | |
| Simulation time | 2442611878 ps |
| CPU time | 20.17 seconds |
| Started | Aug 27 06:27:54 PM UTC 24 |
| Finished | Aug 27 06:28:15 PM UTC 24 |
| Peak memory | 245356 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=895438695 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/spi_d evice_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_upload.895438695 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/43.spi_device_upload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/44.spi_device_alert_test.3182450091 |
| Short name | T888 |
| Test name | |
| Test status | |
| Simulation time | 15650551 ps |
| CPU time | 1.11 seconds |
| Started | Aug 27 06:28:32 PM UTC 24 |
| Finished | Aug 27 06:28:35 PM UTC 24 |
| Peak memory | 215744 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3182450091 -assert nopostproc +UVM_TES TNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_alert_test.3182450091 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/44.spi_device_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/44.spi_device_cfg_cmd.1341018316 |
| Short name | T886 |
| Test name | |
| Test status | |
| Simulation time | 2210787468 ps |
| CPU time | 9.9 seconds |
| Started | Aug 27 06:28:21 PM UTC 24 |
| Finished | Aug 27 06:28:32 PM UTC 24 |
| Peak memory | 234964 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1341018316 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_cfg_cmd.1341018316 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/44.spi_device_cfg_cmd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/44.spi_device_csb_read.2249680878 |
| Short name | T871 |
| Test name | |
| Test status | |
| Simulation time | 15814024 ps |
| CPU time | 1.17 seconds |
| Started | Aug 27 06:28:11 PM UTC 24 |
| Finished | Aug 27 06:28:13 PM UTC 24 |
| Peak memory | 215812 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2249680878 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/sp i_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_csb_read.2249680878 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/44.spi_device_csb_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/44.spi_device_flash_all.4226439070 |
| Short name | T948 |
| Test name | |
| Test status | |
| Simulation time | 3726221489 ps |
| CPU time | 78.04 seconds |
| Started | Aug 27 06:28:24 PM UTC 24 |
| Finished | Aug 27 06:29:44 PM UTC 24 |
| Peak memory | 273996 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4226439070 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/s pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_all.4226439070 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/44.spi_device_flash_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/44.spi_device_flash_and_tpm.287473759 |
| Short name | T913 |
| Test name | |
| Test status | |
| Simulation time | 2983715910 ps |
| CPU time | 41.93 seconds |
| Started | Aug 27 06:28:24 PM UTC 24 |
| Finished | Aug 27 06:29:08 PM UTC 24 |
| Peak memory | 261808 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=287473759 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_2 6/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_and_tpm.287473759 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/44.spi_device_flash_and_tpm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/44.spi_device_flash_and_tpm_min_idle.1056395115 |
| Short name | T904 |
| Test name | |
| Test status | |
| Simulation time | 5794944754 ps |
| CPU time | 32.15 seconds |
| Started | Aug 27 06:28:26 PM UTC 24 |
| Finished | Aug 27 06:29:00 PM UTC 24 |
| Peak memory | 229576 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1056395115 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_26/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_and_tpm_min_idle.1056395115 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/44.spi_device_flash_and_tpm_min_idle/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/44.spi_device_flash_mode.856239860 |
| Short name | T909 |
| Test name | |
| Test status | |
| Simulation time | 2245571691 ps |
| CPU time | 39.75 seconds |
| Started | Aug 27 06:28:23 PM UTC 24 |
| Finished | Aug 27 06:29:04 PM UTC 24 |
| Peak memory | 251408 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=856239860 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/s pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_mode.856239860 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/44.spi_device_flash_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/44.spi_device_flash_mode_ignore_cmds.2421603076 |
| Short name | T940 |
| Test name | |
| Test status | |
| Simulation time | 6723148599 ps |
| CPU time | 73.6 seconds |
| Started | Aug 27 06:28:23 PM UTC 24 |
| Finished | Aug 27 06:29:38 PM UTC 24 |
| Peak memory | 261780 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2421603076 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_26/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_mode_ignore_cmds.2421603076 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/44.spi_device_flash_mode_ignore_cmds/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/44.spi_device_intercept.841811959 |
| Short name | T881 |
| Test name | |
| Test status | |
| Simulation time | 301339803 ps |
| CPU time | 4.15 seconds |
| Started | Aug 27 06:28:17 PM UTC 24 |
| Finished | Aug 27 06:28:22 PM UTC 24 |
| Peak memory | 234832 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=841811959 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/sp i_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_intercept.841811959 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/44.spi_device_intercept/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/44.spi_device_mailbox.3441729190 |
| Short name | T935 |
| Test name | |
| Test status | |
| Simulation time | 37601311263 ps |
| CPU time | 69.81 seconds |
| Started | Aug 27 06:28:19 PM UTC 24 |
| Finished | Aug 27 06:29:30 PM UTC 24 |
| Peak memory | 261844 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3441729190 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_mailbox.3441729190 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/44.spi_device_mailbox/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/44.spi_device_pass_addr_payload_swap.1051565417 |
| Short name | T901 |
| Test name | |
| Test status | |
| Simulation time | 18714158094 ps |
| CPU time | 32.92 seconds |
| Started | Aug 27 06:28:17 PM UTC 24 |
| Finished | Aug 27 06:28:52 PM UTC 24 |
| Peak memory | 249360 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1051565417 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_26/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_pass_addr_payload_swap.1051565417 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/44.spi_device_pass_addr_payload_swap/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/44.spi_device_pass_cmd_filtering.648823622 |
| Short name | T898 |
| Test name | |
| Test status | |
| Simulation time | 8079787700 ps |
| CPU time | 29.93 seconds |
| Started | Aug 27 06:28:16 PM UTC 24 |
| Finished | Aug 27 06:28:47 PM UTC 24 |
| Peak memory | 251532 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=648823622 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _08_26/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_pass_cmd_filtering.648823622 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/44.spi_device_pass_cmd_filtering/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/44.spi_device_read_buffer_direct.294615059 |
| Short name | T902 |
| Test name | |
| Test status | |
| Simulation time | 2120716740 ps |
| CPU time | 28.25 seconds |
| Started | Aug 27 06:28:23 PM UTC 24 |
| Finished | Aug 27 06:28:53 PM UTC 24 |
| Peak memory | 233376 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=294615059 -assert nopostproc +UVM_TESTNAME=spi_device_ base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_read_buffer_direct.294615059 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/44.spi_device_read_buffer_direct/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/44.spi_device_stress_all.317529455 |
| Short name | T1011 |
| Test name | |
| Test status | |
| Simulation time | 33499816856 ps |
| CPU time | 556.38 seconds |
| Started | Aug 27 06:28:32 PM UTC 24 |
| Finished | Aug 27 06:37:56 PM UTC 24 |
| Peak memory | 296608 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=317529455 -assert nopostproc +UVM_T ESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_stress_all.317529455 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/44.spi_device_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/44.spi_device_tpm_all.1255719844 |
| Short name | T889 |
| Test name | |
| Test status | |
| Simulation time | 4240984668 ps |
| CPU time | 19.34 seconds |
| Started | Aug 27 06:28:14 PM UTC 24 |
| Finished | Aug 27 06:28:35 PM UTC 24 |
| Peak memory | 227612 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1255719844 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_all.1255719844 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/44.spi_device_tpm_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/44.spi_device_tpm_read_hw_reg.3871092598 |
| Short name | T882 |
| Test name | |
| Test status | |
| Simulation time | 519271458 ps |
| CPU time | 7.38 seconds |
| Started | Aug 27 06:28:14 PM UTC 24 |
| Finished | Aug 27 06:28:23 PM UTC 24 |
| Peak memory | 227424 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3871092598 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_26/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_read_hw_reg.3871092598 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/44.spi_device_tpm_read_hw_reg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/44.spi_device_tpm_rw.1482014477 |
| Short name | T877 |
| Test name | |
| Test status | |
| Simulation time | 743153019 ps |
| CPU time | 3.95 seconds |
| Started | Aug 27 06:28:14 PM UTC 24 |
| Finished | Aug 27 06:28:20 PM UTC 24 |
| Peak memory | 227568 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1482014477 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_rw.1482014477 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/44.spi_device_tpm_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/44.spi_device_tpm_sts_read.2641480791 |
| Short name | T876 |
| Test name | |
| Test status | |
| Simulation time | 70609960 ps |
| CPU time | 1.23 seconds |
| Started | Aug 27 06:28:14 PM UTC 24 |
| Finished | Aug 27 06:28:17 PM UTC 24 |
| Peak memory | 215872 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2641480791 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_2 6/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_sts_read.2641480791 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/44.spi_device_tpm_sts_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/44.spi_device_upload.2788319023 |
| Short name | T887 |
| Test name | |
| Test status | |
| Simulation time | 4049149865 ps |
| CPU time | 12.85 seconds |
| Started | Aug 27 06:28:19 PM UTC 24 |
| Finished | Aug 27 06:28:33 PM UTC 24 |
| Peak memory | 235092 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2788319023 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_upload.2788319023 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/44.spi_device_upload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/45.spi_device_alert_test.1912911582 |
| Short name | T905 |
| Test name | |
| Test status | |
| Simulation time | 24519631 ps |
| CPU time | 1.13 seconds |
| Started | Aug 27 06:28:58 PM UTC 24 |
| Finished | Aug 27 06:29:01 PM UTC 24 |
| Peak memory | 215744 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1912911582 -assert nopostproc +UVM_TES TNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_alert_test.1912911582 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/45.spi_device_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/45.spi_device_cfg_cmd.3198157730 |
| Short name | T899 |
| Test name | |
| Test status | |
| Simulation time | 218180871 ps |
| CPU time | 5.25 seconds |
| Started | Aug 27 06:28:42 PM UTC 24 |
| Finished | Aug 27 06:28:48 PM UTC 24 |
| Peak memory | 245140 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3198157730 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_cfg_cmd.3198157730 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/45.spi_device_cfg_cmd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/45.spi_device_csb_read.934498858 |
| Short name | T890 |
| Test name | |
| Test status | |
| Simulation time | 15442093 ps |
| CPU time | 1.14 seconds |
| Started | Aug 27 06:28:34 PM UTC 24 |
| Finished | Aug 27 06:28:36 PM UTC 24 |
| Peak memory | 215404 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=934498858 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_csb_read.934498858 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/45.spi_device_csb_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/45.spi_device_flash_all.1554453464 |
| Short name | T958 |
| Test name | |
| Test status | |
| Simulation time | 43455395724 ps |
| CPU time | 64.07 seconds |
| Started | Aug 27 06:28:49 PM UTC 24 |
| Finished | Aug 27 06:29:55 PM UTC 24 |
| Peak memory | 245336 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1554453464 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/s pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_all.1554453464 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/45.spi_device_flash_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/45.spi_device_flash_and_tpm.327609198 |
| Short name | T943 |
| Test name | |
| Test status | |
| Simulation time | 1987879627 ps |
| CPU time | 47.86 seconds |
| Started | Aug 27 06:28:52 PM UTC 24 |
| Finished | Aug 27 06:29:41 PM UTC 24 |
| Peak memory | 249264 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=327609198 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_2 6/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_and_tpm.327609198 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/45.spi_device_flash_and_tpm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/45.spi_device_flash_and_tpm_min_idle.2518803158 |
| Short name | T994 |
| Test name | |
| Test status | |
| Simulation time | 290052989019 ps |
| CPU time | 203.62 seconds |
| Started | Aug 27 06:28:53 PM UTC 24 |
| Finished | Aug 27 06:32:20 PM UTC 24 |
| Peak memory | 261756 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2518803158 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_26/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_and_tpm_min_idle.2518803158 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/45.spi_device_flash_and_tpm_min_idle/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/45.spi_device_flash_mode.2580913502 |
| Short name | T919 |
| Test name | |
| Test status | |
| Simulation time | 1114522675 ps |
| CPU time | 26.1 seconds |
| Started | Aug 27 06:28:48 PM UTC 24 |
| Finished | Aug 27 06:29:15 PM UTC 24 |
| Peak memory | 249296 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2580913502 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/ spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_mode.2580913502 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/45.spi_device_flash_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/45.spi_device_flash_mode_ignore_cmds.450763771 |
| Short name | T920 |
| Test name | |
| Test status | |
| Simulation time | 809681173 ps |
| CPU time | 26.79 seconds |
| Started | Aug 27 06:28:48 PM UTC 24 |
| Finished | Aug 27 06:29:16 PM UTC 24 |
| Peak memory | 261588 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=450763771 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_26/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_mode_ignore_cmds.450763771 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/45.spi_device_flash_mode_ignore_cmds/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/45.spi_device_intercept.769029501 |
| Short name | T897 |
| Test name | |
| Test status | |
| Simulation time | 149154856 ps |
| CPU time | 4.19 seconds |
| Started | Aug 27 06:28:41 PM UTC 24 |
| Finished | Aug 27 06:28:46 PM UTC 24 |
| Peak memory | 245200 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=769029501 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/sp i_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_intercept.769029501 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/45.spi_device_intercept/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/45.spi_device_mailbox.3164502168 |
| Short name | T915 |
| Test name | |
| Test status | |
| Simulation time | 5134101319 ps |
| CPU time | 27.9 seconds |
| Started | Aug 27 06:28:41 PM UTC 24 |
| Finished | Aug 27 06:29:10 PM UTC 24 |
| Peak memory | 245388 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3164502168 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_mailbox.3164502168 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/45.spi_device_mailbox/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/45.spi_device_pass_addr_payload_swap.644537881 |
| Short name | T896 |
| Test name | |
| Test status | |
| Simulation time | 825076212 ps |
| CPU time | 5.98 seconds |
| Started | Aug 27 06:28:39 PM UTC 24 |
| Finished | Aug 27 06:28:46 PM UTC 24 |
| Peak memory | 245160 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=644537881 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_26/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_pass_addr_payload_swap.644537881 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/45.spi_device_pass_addr_payload_swap/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/45.spi_device_pass_cmd_filtering.2901187352 |
| Short name | T895 |
| Test name | |
| Test status | |
| Simulation time | 311872186 ps |
| CPU time | 3.55 seconds |
| Started | Aug 27 06:28:37 PM UTC 24 |
| Finished | Aug 27 06:28:41 PM UTC 24 |
| Peak memory | 234892 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2901187352 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_08_26/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_pass_cmd_filtering.2901187352 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/45.spi_device_pass_cmd_filtering/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/45.spi_device_read_buffer_direct.221879854 |
| Short name | T903 |
| Test name | |
| Test status | |
| Simulation time | 271556839 ps |
| CPU time | 7.04 seconds |
| Started | Aug 27 06:28:49 PM UTC 24 |
| Finished | Aug 27 06:28:57 PM UTC 24 |
| Peak memory | 231328 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=221879854 -assert nopostproc +UVM_TESTNAME=spi_device_ base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_read_buffer_direct.221879854 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/45.spi_device_read_buffer_direct/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/45.spi_device_stress_all.3254481539 |
| Short name | T997 |
| Test name | |
| Test status | |
| Simulation time | 58158868265 ps |
| CPU time | 241.88 seconds |
| Started | Aug 27 06:28:54 PM UTC 24 |
| Finished | Aug 27 06:33:00 PM UTC 24 |
| Peak memory | 280220 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3254481539 -assert nopostproc +UVM_ TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_stress_all.3254481539 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/45.spi_device_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/45.spi_device_tpm_all.2119572002 |
| Short name | T910 |
| Test name | |
| Test status | |
| Simulation time | 1865330225 ps |
| CPU time | 28.57 seconds |
| Started | Aug 27 06:28:35 PM UTC 24 |
| Finished | Aug 27 06:29:05 PM UTC 24 |
| Peak memory | 227488 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2119572002 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_all.2119572002 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/45.spi_device_tpm_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/45.spi_device_tpm_read_hw_reg.2376386372 |
| Short name | T906 |
| Test name | |
| Test status | |
| Simulation time | 8150479839 ps |
| CPU time | 25.98 seconds |
| Started | Aug 27 06:28:34 PM UTC 24 |
| Finished | Aug 27 06:29:01 PM UTC 24 |
| Peak memory | 227404 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2376386372 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_26/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_read_hw_reg.2376386372 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/45.spi_device_tpm_read_hw_reg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/45.spi_device_tpm_rw.3983893373 |
| Short name | T894 |
| Test name | |
| Test status | |
| Simulation time | 224701275 ps |
| CPU time | 1.96 seconds |
| Started | Aug 27 06:28:37 PM UTC 24 |
| Finished | Aug 27 06:28:40 PM UTC 24 |
| Peak memory | 226756 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3983893373 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_rw.3983893373 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/45.spi_device_tpm_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/45.spi_device_tpm_sts_read.3079570459 |
| Short name | T891 |
| Test name | |
| Test status | |
| Simulation time | 80652710 ps |
| CPU time | 1.2 seconds |
| Started | Aug 27 06:28:35 PM UTC 24 |
| Finished | Aug 27 06:28:38 PM UTC 24 |
| Peak memory | 215872 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3079570459 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_2 6/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_sts_read.3079570459 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/45.spi_device_tpm_sts_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/45.spi_device_upload.2590595002 |
| Short name | T900 |
| Test name | |
| Test status | |
| Simulation time | 1159572602 ps |
| CPU time | 8.54 seconds |
| Started | Aug 27 06:28:41 PM UTC 24 |
| Finished | Aug 27 06:28:51 PM UTC 24 |
| Peak memory | 245200 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2590595002 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_upload.2590595002 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/45.spi_device_upload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/46.spi_device_alert_test.381694693 |
| Short name | T924 |
| Test name | |
| Test status | |
| Simulation time | 56487185 ps |
| CPU time | 1.13 seconds |
| Started | Aug 27 06:29:17 PM UTC 24 |
| Finished | Aug 27 06:29:19 PM UTC 24 |
| Peak memory | 215684 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=381694693 -assert nopostproc +UVM_TEST NAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_alert_test.381694693 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/46.spi_device_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/46.spi_device_cfg_cmd.2433943807 |
| Short name | T918 |
| Test name | |
| Test status | |
| Simulation time | 135895371 ps |
| CPU time | 3.19 seconds |
| Started | Aug 27 06:29:09 PM UTC 24 |
| Finished | Aug 27 06:29:14 PM UTC 24 |
| Peak memory | 245152 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2433943807 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_cfg_cmd.2433943807 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/46.spi_device_cfg_cmd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/46.spi_device_csb_read.1546427400 |
| Short name | T907 |
| Test name | |
| Test status | |
| Simulation time | 57279017 ps |
| CPU time | 1.13 seconds |
| Started | Aug 27 06:29:01 PM UTC 24 |
| Finished | Aug 27 06:29:03 PM UTC 24 |
| Peak memory | 215520 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1546427400 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/sp i_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_csb_read.1546427400 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/46.spi_device_csb_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/46.spi_device_flash_all.1090087338 |
| Short name | T1006 |
| Test name | |
| Test status | |
| Simulation time | 144550200335 ps |
| CPU time | 303.57 seconds |
| Started | Aug 27 06:29:15 PM UTC 24 |
| Finished | Aug 27 06:34:22 PM UTC 24 |
| Peak memory | 276072 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1090087338 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/s pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_all.1090087338 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/46.spi_device_flash_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/46.spi_device_flash_and_tpm.605770936 |
| Short name | T1004 |
| Test name | |
| Test status | |
| Simulation time | 590951874875 ps |
| CPU time | 283.25 seconds |
| Started | Aug 27 06:29:15 PM UTC 24 |
| Finished | Aug 27 06:34:02 PM UTC 24 |
| Peak memory | 261764 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=605770936 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_2 6/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_and_tpm.605770936 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/46.spi_device_flash_and_tpm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/46.spi_device_flash_and_tpm_min_idle.468599319 |
| Short name | T973 |
| Test name | |
| Test status | |
| Simulation time | 23804485806 ps |
| CPU time | 51.47 seconds |
| Started | Aug 27 06:29:17 PM UTC 24 |
| Finished | Aug 27 06:30:10 PM UTC 24 |
| Peak memory | 247460 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=468599319 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_26/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_and_tpm_min_idle.468599319 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/46.spi_device_flash_and_tpm_min_idle/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/46.spi_device_flash_mode.847110608 |
| Short name | T922 |
| Test name | |
| Test status | |
| Simulation time | 200195655 ps |
| CPU time | 4.53 seconds |
| Started | Aug 27 06:29:11 PM UTC 24 |
| Finished | Aug 27 06:29:17 PM UTC 24 |
| Peak memory | 234960 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=847110608 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/s pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_mode.847110608 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/46.spi_device_flash_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/46.spi_device_flash_mode_ignore_cmds.2355851574 |
| Short name | T985 |
| Test name | |
| Test status | |
| Simulation time | 29508119721 ps |
| CPU time | 115.74 seconds |
| Started | Aug 27 06:29:11 PM UTC 24 |
| Finished | Aug 27 06:31:09 PM UTC 24 |
| Peak memory | 265812 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2355851574 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_26/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_mode_ignore_cmds.2355851574 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/46.spi_device_flash_mode_ignore_cmds/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/46.spi_device_intercept.2811111943 |
| Short name | T916 |
| Test name | |
| Test status | |
| Simulation time | 344027382 ps |
| CPU time | 4.45 seconds |
| Started | Aug 27 06:29:07 PM UTC 24 |
| Finished | Aug 27 06:29:12 PM UTC 24 |
| Peak memory | 234968 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2811111943 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/s pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_intercept.2811111943 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/46.spi_device_intercept/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/46.spi_device_mailbox.1560024795 |
| Short name | T957 |
| Test name | |
| Test status | |
| Simulation time | 35545319634 ps |
| CPU time | 45.05 seconds |
| Started | Aug 27 06:29:08 PM UTC 24 |
| Finished | Aug 27 06:29:55 PM UTC 24 |
| Peak memory | 247320 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1560024795 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_mailbox.1560024795 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/46.spi_device_mailbox/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/46.spi_device_pass_addr_payload_swap.1662624703 |
| Short name | T927 |
| Test name | |
| Test status | |
| Simulation time | 2018529605 ps |
| CPU time | 14.35 seconds |
| Started | Aug 27 06:29:07 PM UTC 24 |
| Finished | Aug 27 06:29:22 PM UTC 24 |
| Peak memory | 251364 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1662624703 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_26/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_pass_addr_payload_swap.1662624703 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/46.spi_device_pass_addr_payload_swap/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/46.spi_device_pass_cmd_filtering.2311635343 |
| Short name | T914 |
| Test name | |
| Test status | |
| Simulation time | 144072356 ps |
| CPU time | 3.19 seconds |
| Started | Aug 27 06:29:05 PM UTC 24 |
| Finished | Aug 27 06:29:09 PM UTC 24 |
| Peak memory | 245200 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2311635343 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_08_26/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_pass_cmd_filtering.2311635343 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/46.spi_device_pass_cmd_filtering/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/46.spi_device_read_buffer_direct.4145822397 |
| Short name | T932 |
| Test name | |
| Test status | |
| Simulation time | 407350498 ps |
| CPU time | 9.96 seconds |
| Started | Aug 27 06:29:13 PM UTC 24 |
| Finished | Aug 27 06:29:24 PM UTC 24 |
| Peak memory | 231260 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4145822397 -assert nopostproc +UVM_TESTNAME=spi_device _base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_read_buffer_direct.4145822397 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/46.spi_device_read_buffer_direct/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/46.spi_device_stress_all.458696863 |
| Short name | T1012 |
| Test name | |
| Test status | |
| Simulation time | 214768899640 ps |
| CPU time | 575.65 seconds |
| Started | Aug 27 06:29:17 PM UTC 24 |
| Finished | Aug 27 06:38:59 PM UTC 24 |
| Peak memory | 276188 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=458696863 -assert nopostproc +UVM_T ESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_stress_all.458696863 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/46.spi_device_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/46.spi_device_tpm_all.2815185413 |
| Short name | T921 |
| Test name | |
| Test status | |
| Simulation time | 12293546705 ps |
| CPU time | 12.43 seconds |
| Started | Aug 27 06:29:02 PM UTC 24 |
| Finished | Aug 27 06:29:16 PM UTC 24 |
| Peak memory | 227624 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2815185413 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_all.2815185413 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/46.spi_device_tpm_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/46.spi_device_tpm_read_hw_reg.2319475422 |
| Short name | T917 |
| Test name | |
| Test status | |
| Simulation time | 1091365817 ps |
| CPU time | 9.97 seconds |
| Started | Aug 27 06:29:02 PM UTC 24 |
| Finished | Aug 27 06:29:13 PM UTC 24 |
| Peak memory | 227452 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2319475422 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_26/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_read_hw_reg.2319475422 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/46.spi_device_tpm_read_hw_reg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/46.spi_device_tpm_rw.3864268144 |
| Short name | T912 |
| Test name | |
| Test status | |
| Simulation time | 218787501 ps |
| CPU time | 1.93 seconds |
| Started | Aug 27 06:29:04 PM UTC 24 |
| Finished | Aug 27 06:29:07 PM UTC 24 |
| Peak memory | 226700 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3864268144 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_rw.3864268144 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/46.spi_device_tpm_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/46.spi_device_tpm_sts_read.1555853671 |
| Short name | T911 |
| Test name | |
| Test status | |
| Simulation time | 57479393 ps |
| CPU time | 1.27 seconds |
| Started | Aug 27 06:29:04 PM UTC 24 |
| Finished | Aug 27 06:29:06 PM UTC 24 |
| Peak memory | 215704 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1555853671 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_2 6/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_sts_read.1555853671 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/46.spi_device_tpm_sts_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/46.spi_device_upload.2141873318 |
| Short name | T949 |
| Test name | |
| Test status | |
| Simulation time | 25542885835 ps |
| CPU time | 35.5 seconds |
| Started | Aug 27 06:29:08 PM UTC 24 |
| Finished | Aug 27 06:29:45 PM UTC 24 |
| Peak memory | 245280 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2141873318 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_upload.2141873318 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/46.spi_device_upload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/47.spi_device_alert_test.909126975 |
| Short name | T941 |
| Test name | |
| Test status | |
| Simulation time | 22364766 ps |
| CPU time | 0.93 seconds |
| Started | Aug 27 06:29:38 PM UTC 24 |
| Finished | Aug 27 06:29:39 PM UTC 24 |
| Peak memory | 215744 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=909126975 -assert nopostproc +UVM_TEST NAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_alert_test.909126975 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/47.spi_device_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/47.spi_device_cfg_cmd.4293242046 |
| Short name | T939 |
| Test name | |
| Test status | |
| Simulation time | 5054803190 ps |
| CPU time | 11.95 seconds |
| Started | Aug 27 06:29:25 PM UTC 24 |
| Finished | Aug 27 06:29:38 PM UTC 24 |
| Peak memory | 245344 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4293242046 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_cfg_cmd.4293242046 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/47.spi_device_cfg_cmd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/47.spi_device_csb_read.1807214613 |
| Short name | T925 |
| Test name | |
| Test status | |
| Simulation time | 34887020 ps |
| CPU time | 1.2 seconds |
| Started | Aug 27 06:29:17 PM UTC 24 |
| Finished | Aug 27 06:29:19 PM UTC 24 |
| Peak memory | 215812 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1807214613 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/sp i_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_csb_read.1807214613 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/47.spi_device_csb_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/47.spi_device_flash_all.2715659163 |
| Short name | T1002 |
| Test name | |
| Test status | |
| Simulation time | 72142005574 ps |
| CPU time | 265.7 seconds |
| Started | Aug 27 06:29:28 PM UTC 24 |
| Finished | Aug 27 06:33:58 PM UTC 24 |
| Peak memory | 278232 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2715659163 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/s pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_all.2715659163 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/47.spi_device_flash_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/47.spi_device_flash_and_tpm.468383726 |
| Short name | T39 |
| Test name | |
| Test status | |
| Simulation time | 194877741927 ps |
| CPU time | 623.01 seconds |
| Started | Aug 27 06:29:32 PM UTC 24 |
| Finished | Aug 27 06:40:03 PM UTC 24 |
| Peak memory | 267932 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=468383726 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_2 6/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_and_tpm.468383726 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/47.spi_device_flash_and_tpm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/47.spi_device_flash_and_tpm_min_idle.313719656 |
| Short name | T986 |
| Test name | |
| Test status | |
| Simulation time | 6383562903 ps |
| CPU time | 101.17 seconds |
| Started | Aug 27 06:29:32 PM UTC 24 |
| Finished | Aug 27 06:31:15 PM UTC 24 |
| Peak memory | 261908 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=313719656 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_26/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_and_tpm_min_idle.313719656 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/47.spi_device_flash_and_tpm_min_idle/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/47.spi_device_flash_mode.1359070391 |
| Short name | T954 |
| Test name | |
| Test status | |
| Simulation time | 1181083534 ps |
| CPU time | 24.46 seconds |
| Started | Aug 27 06:29:25 PM UTC 24 |
| Finished | Aug 27 06:29:50 PM UTC 24 |
| Peak memory | 245200 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1359070391 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/ spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_mode.1359070391 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/47.spi_device_flash_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/47.spi_device_flash_mode_ignore_cmds.386735475 |
| Short name | T1009 |
| Test name | |
| Test status | |
| Simulation time | 148083418289 ps |
| CPU time | 373.34 seconds |
| Started | Aug 27 06:29:26 PM UTC 24 |
| Finished | Aug 27 06:35:44 PM UTC 24 |
| Peak memory | 276052 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=386735475 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_26/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_mode_ignore_cmds.386735475 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/47.spi_device_flash_mode_ignore_cmds/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/47.spi_device_intercept.3048568419 |
| Short name | T933 |
| Test name | |
| Test status | |
| Simulation time | 169848822 ps |
| CPU time | 3.54 seconds |
| Started | Aug 27 06:29:23 PM UTC 24 |
| Finished | Aug 27 06:29:27 PM UTC 24 |
| Peak memory | 234904 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3048568419 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/s pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_intercept.3048568419 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/47.spi_device_intercept/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/47.spi_device_mailbox.712875767 |
| Short name | T956 |
| Test name | |
| Test status | |
| Simulation time | 1624780121 ps |
| CPU time | 29.18 seconds |
| Started | Aug 27 06:29:23 PM UTC 24 |
| Finished | Aug 27 06:29:53 PM UTC 24 |
| Peak memory | 235092 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=712875767 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_mailbox.712875767 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/47.spi_device_mailbox/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/47.spi_device_pass_addr_payload_swap.2797179052 |
| Short name | T934 |
| Test name | |
| Test status | |
| Simulation time | 500036040 ps |
| CPU time | 7.8 seconds |
| Started | Aug 27 06:29:21 PM UTC 24 |
| Finished | Aug 27 06:29:30 PM UTC 24 |
| Peak memory | 249360 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2797179052 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_26/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_pass_addr_payload_swap.2797179052 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/47.spi_device_pass_addr_payload_swap/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/47.spi_device_pass_cmd_filtering.2702086754 |
| Short name | T931 |
| Test name | |
| Test status | |
| Simulation time | 101722885 ps |
| CPU time | 2.72 seconds |
| Started | Aug 27 06:29:20 PM UTC 24 |
| Finished | Aug 27 06:29:24 PM UTC 24 |
| Peak memory | 234916 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2702086754 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_08_26/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_pass_cmd_filtering.2702086754 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/47.spi_device_pass_cmd_filtering/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/47.spi_device_read_buffer_direct.932181207 |
| Short name | T938 |
| Test name | |
| Test status | |
| Simulation time | 311562312 ps |
| CPU time | 8.72 seconds |
| Started | Aug 27 06:29:27 PM UTC 24 |
| Finished | Aug 27 06:29:37 PM UTC 24 |
| Peak memory | 233392 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=932181207 -assert nopostproc +UVM_TESTNAME=spi_device_ base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_read_buffer_direct.932181207 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/47.spi_device_read_buffer_direct/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/47.spi_device_stress_all.1445760566 |
| Short name | T942 |
| Test name | |
| Test status | |
| Simulation time | 58543846 ps |
| CPU time | 1.58 seconds |
| Started | Aug 27 06:29:37 PM UTC 24 |
| Finished | Aug 27 06:29:40 PM UTC 24 |
| Peak memory | 215604 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1445760566 -assert nopostproc +UVM_ TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_stress_all.1445760566 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/47.spi_device_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/47.spi_device_tpm_all.3966358544 |
| Short name | T936 |
| Test name | |
| Test status | |
| Simulation time | 5800682393 ps |
| CPU time | 14.85 seconds |
| Started | Aug 27 06:29:20 PM UTC 24 |
| Finished | Aug 27 06:29:36 PM UTC 24 |
| Peak memory | 231708 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3966358544 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_all.3966358544 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/47.spi_device_tpm_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/47.spi_device_tpm_read_hw_reg.2613937758 |
| Short name | T926 |
| Test name | |
| Test status | |
| Simulation time | 16070826 ps |
| CPU time | 0.95 seconds |
| Started | Aug 27 06:29:18 PM UTC 24 |
| Finished | Aug 27 06:29:20 PM UTC 24 |
| Peak memory | 215864 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2613937758 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_26/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_read_hw_reg.2613937758 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/47.spi_device_tpm_read_hw_reg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/47.spi_device_tpm_rw.1015874510 |
| Short name | T929 |
| Test name | |
| Test status | |
| Simulation time | 165822343 ps |
| CPU time | 2.1 seconds |
| Started | Aug 27 06:29:20 PM UTC 24 |
| Finished | Aug 27 06:29:23 PM UTC 24 |
| Peak memory | 227484 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1015874510 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_rw.1015874510 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/47.spi_device_tpm_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/47.spi_device_tpm_sts_read.3710432451 |
| Short name | T928 |
| Test name | |
| Test status | |
| Simulation time | 87425141 ps |
| CPU time | 1.22 seconds |
| Started | Aug 27 06:29:20 PM UTC 24 |
| Finished | Aug 27 06:29:22 PM UTC 24 |
| Peak memory | 215872 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3710432451 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_2 6/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_sts_read.3710432451 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/47.spi_device_tpm_sts_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/47.spi_device_upload.2901617100 |
| Short name | T953 |
| Test name | |
| Test status | |
| Simulation time | 5115720720 ps |
| CPU time | 23.83 seconds |
| Started | Aug 27 06:29:24 PM UTC 24 |
| Finished | Aug 27 06:29:49 PM UTC 24 |
| Peak memory | 247524 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2901617100 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_upload.2901617100 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/47.spi_device_upload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/48.spi_device_alert_test.3800850758 |
| Short name | T960 |
| Test name | |
| Test status | |
| Simulation time | 27034789 ps |
| CPU time | 1.13 seconds |
| Started | Aug 27 06:29:55 PM UTC 24 |
| Finished | Aug 27 06:29:57 PM UTC 24 |
| Peak memory | 215804 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3800850758 -assert nopostproc +UVM_TES TNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_alert_test.3800850758 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/48.spi_device_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/48.spi_device_cfg_cmd.443345025 |
| Short name | T961 |
| Test name | |
| Test status | |
| Simulation time | 3491380154 ps |
| CPU time | 12.03 seconds |
| Started | Aug 27 06:29:46 PM UTC 24 |
| Finished | Aug 27 06:29:59 PM UTC 24 |
| Peak memory | 245408 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=443345025 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_cfg_cmd.443345025 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/48.spi_device_cfg_cmd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/48.spi_device_csb_read.150413098 |
| Short name | T945 |
| Test name | |
| Test status | |
| Simulation time | 17468460 ps |
| CPU time | 1.15 seconds |
| Started | Aug 27 06:29:39 PM UTC 24 |
| Finished | Aug 27 06:29:41 PM UTC 24 |
| Peak memory | 215812 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=150413098 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_csb_read.150413098 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/48.spi_device_csb_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/48.spi_device_flash_all.1006749277 |
| Short name | T974 |
| Test name | |
| Test status | |
| Simulation time | 2584706697 ps |
| CPU time | 19.02 seconds |
| Started | Aug 27 06:29:50 PM UTC 24 |
| Finished | Aug 27 06:30:10 PM UTC 24 |
| Peak memory | 249424 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1006749277 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/s pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_all.1006749277 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/48.spi_device_flash_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/48.spi_device_flash_and_tpm.1482593153 |
| Short name | T1007 |
| Test name | |
| Test status | |
| Simulation time | 36273871881 ps |
| CPU time | 291.22 seconds |
| Started | Aug 27 06:29:51 PM UTC 24 |
| Finished | Aug 27 06:34:46 PM UTC 24 |
| Peak memory | 261788 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1482593153 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_ 26/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_and_tpm.1482593153 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/48.spi_device_flash_and_tpm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/48.spi_device_flash_and_tpm_min_idle.1679675992 |
| Short name | T1013 |
| Test name | |
| Test status | |
| Simulation time | 205706333876 ps |
| CPU time | 544.39 seconds |
| Started | Aug 27 06:29:51 PM UTC 24 |
| Finished | Aug 27 06:39:02 PM UTC 24 |
| Peak memory | 276180 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1679675992 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_26/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_and_tpm_min_idle.1679675992 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/48.spi_device_flash_and_tpm_min_idle/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/48.spi_device_flash_mode.164104625 |
| Short name | T970 |
| Test name | |
| Test status | |
| Simulation time | 1086324163 ps |
| CPU time | 20.54 seconds |
| Started | Aug 27 06:29:46 PM UTC 24 |
| Finished | Aug 27 06:30:08 PM UTC 24 |
| Peak memory | 251360 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=164104625 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/s pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_mode.164104625 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/48.spi_device_flash_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/48.spi_device_flash_mode_ignore_cmds.3102525935 |
| Short name | T989 |
| Test name | |
| Test status | |
| Simulation time | 26176901861 ps |
| CPU time | 90.18 seconds |
| Started | Aug 27 06:29:48 PM UTC 24 |
| Finished | Aug 27 06:31:20 PM UTC 24 |
| Peak memory | 267876 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3102525935 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_26/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_mode_ignore_cmds.3102525935 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/48.spi_device_flash_mode_ignore_cmds/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/48.spi_device_intercept.3525403043 |
| Short name | T951 |
| Test name | |
| Test status | |
| Simulation time | 220600818 ps |
| CPU time | 4.04 seconds |
| Started | Aug 27 06:29:43 PM UTC 24 |
| Finished | Aug 27 06:29:48 PM UTC 24 |
| Peak memory | 245224 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3525403043 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/s pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_intercept.3525403043 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/48.spi_device_intercept/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/48.spi_device_mailbox.2021648615 |
| Short name | T984 |
| Test name | |
| Test status | |
| Simulation time | 10318199605 ps |
| CPU time | 71.57 seconds |
| Started | Aug 27 06:29:44 PM UTC 24 |
| Finished | Aug 27 06:30:58 PM UTC 24 |
| Peak memory | 245396 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2021648615 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_mailbox.2021648615 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/48.spi_device_mailbox/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/48.spi_device_pass_addr_payload_swap.2000519467 |
| Short name | T950 |
| Test name | |
| Test status | |
| Simulation time | 282022406 ps |
| CPU time | 2.92 seconds |
| Started | Aug 27 06:29:43 PM UTC 24 |
| Finished | Aug 27 06:29:47 PM UTC 24 |
| Peak memory | 229284 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2000519467 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_26/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_pass_addr_payload_swap.2000519467 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/48.spi_device_pass_addr_payload_swap/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/48.spi_device_pass_cmd_filtering.4294618353 |
| Short name | T955 |
| Test name | |
| Test status | |
| Simulation time | 396937669 ps |
| CPU time | 8.54 seconds |
| Started | Aug 27 06:29:43 PM UTC 24 |
| Finished | Aug 27 06:29:52 PM UTC 24 |
| Peak memory | 245200 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4294618353 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_08_26/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_pass_cmd_filtering.4294618353 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/48.spi_device_pass_cmd_filtering/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/48.spi_device_read_buffer_direct.1095225048 |
| Short name | T959 |
| Test name | |
| Test status | |
| Simulation time | 2921708185 ps |
| CPU time | 6.96 seconds |
| Started | Aug 27 06:29:48 PM UTC 24 |
| Finished | Aug 27 06:29:56 PM UTC 24 |
| Peak memory | 233576 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1095225048 -assert nopostproc +UVM_TESTNAME=spi_device _base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_read_buffer_direct.1095225048 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/48.spi_device_read_buffer_direct/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/48.spi_device_stress_all.3442084557 |
| Short name | T988 |
| Test name | |
| Test status | |
| Simulation time | 8037871903 ps |
| CPU time | 82.82 seconds |
| Started | Aug 27 06:29:54 PM UTC 24 |
| Finished | Aug 27 06:31:18 PM UTC 24 |
| Peak memory | 261844 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3442084557 -assert nopostproc +UVM_ TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_stress_all.3442084557 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/48.spi_device_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/48.spi_device_tpm_all.2944479132 |
| Short name | T967 |
| Test name | |
| Test status | |
| Simulation time | 8948376479 ps |
| CPU time | 24.95 seconds |
| Started | Aug 27 06:29:39 PM UTC 24 |
| Finished | Aug 27 06:30:06 PM UTC 24 |
| Peak memory | 231708 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2944479132 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_all.2944479132 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/48.spi_device_tpm_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/48.spi_device_tpm_read_hw_reg.2044430483 |
| Short name | T944 |
| Test name | |
| Test status | |
| Simulation time | 38032902 ps |
| CPU time | 1.07 seconds |
| Started | Aug 27 06:29:39 PM UTC 24 |
| Finished | Aug 27 06:29:41 PM UTC 24 |
| Peak memory | 215864 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2044430483 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_26/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_read_hw_reg.2044430483 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/48.spi_device_tpm_read_hw_reg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/48.spi_device_tpm_rw.2911231956 |
| Short name | T947 |
| Test name | |
| Test status | |
| Simulation time | 52075233 ps |
| CPU time | 1.9 seconds |
| Started | Aug 27 06:29:41 PM UTC 24 |
| Finished | Aug 27 06:29:44 PM UTC 24 |
| Peak memory | 226404 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2911231956 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_rw.2911231956 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/48.spi_device_tpm_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/48.spi_device_tpm_sts_read.3245119530 |
| Short name | T946 |
| Test name | |
| Test status | |
| Simulation time | 220652094 ps |
| CPU time | 1.27 seconds |
| Started | Aug 27 06:29:41 PM UTC 24 |
| Finished | Aug 27 06:29:43 PM UTC 24 |
| Peak memory | 215872 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3245119530 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_2 6/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_sts_read.3245119530 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/48.spi_device_tpm_sts_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/48.spi_device_upload.3310831201 |
| Short name | T952 |
| Test name | |
| Test status | |
| Simulation time | 628527144 ps |
| CPU time | 3.32 seconds |
| Started | Aug 27 06:29:44 PM UTC 24 |
| Finished | Aug 27 06:29:49 PM UTC 24 |
| Peak memory | 229348 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3310831201 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_upload.3310831201 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/48.spi_device_upload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/49.spi_device_alert_test.4188725051 |
| Short name | T976 |
| Test name | |
| Test status | |
| Simulation time | 19789074 ps |
| CPU time | 1.06 seconds |
| Started | Aug 27 06:30:11 PM UTC 24 |
| Finished | Aug 27 06:30:14 PM UTC 24 |
| Peak memory | 215864 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4188725051 -assert nopostproc +UVM_TES TNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_alert_test.4188725051 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/49.spi_device_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/49.spi_device_cfg_cmd.606979591 |
| Short name | T975 |
| Test name | |
| Test status | |
| Simulation time | 472720975 ps |
| CPU time | 4.35 seconds |
| Started | Aug 27 06:30:05 PM UTC 24 |
| Finished | Aug 27 06:30:10 PM UTC 24 |
| Peak memory | 245156 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=606979591 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_cfg_cmd.606979591 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/49.spi_device_cfg_cmd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/49.spi_device_csb_read.2999102072 |
| Short name | T962 |
| Test name | |
| Test status | |
| Simulation time | 26822268 ps |
| CPU time | 1.13 seconds |
| Started | Aug 27 06:29:56 PM UTC 24 |
| Finished | Aug 27 06:29:59 PM UTC 24 |
| Peak memory | 215812 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2999102072 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/sp i_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_csb_read.2999102072 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/49.spi_device_csb_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/49.spi_device_flash_all.3634932725 |
| Short name | T987 |
| Test name | |
| Test status | |
| Simulation time | 21526531893 ps |
| CPU time | 64.8 seconds |
| Started | Aug 27 06:30:10 PM UTC 24 |
| Finished | Aug 27 06:31:16 PM UTC 24 |
| Peak memory | 261712 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3634932725 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/s pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_all.3634932725 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/49.spi_device_flash_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/49.spi_device_flash_and_tpm.1541209361 |
| Short name | T1001 |
| Test name | |
| Test status | |
| Simulation time | 23398728027 ps |
| CPU time | 221.8 seconds |
| Started | Aug 27 06:30:10 PM UTC 24 |
| Finished | Aug 27 06:33:55 PM UTC 24 |
| Peak memory | 263820 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1541209361 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_ 26/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_and_tpm.1541209361 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/49.spi_device_flash_and_tpm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/49.spi_device_flash_and_tpm_min_idle.4235996416 |
| Short name | T991 |
| Test name | |
| Test status | |
| Simulation time | 10844896485 ps |
| CPU time | 93.76 seconds |
| Started | Aug 27 06:30:10 PM UTC 24 |
| Finished | Aug 27 06:31:46 PM UTC 24 |
| Peak memory | 261816 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4235996416 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_26/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_and_tpm_min_idle.4235996416 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/49.spi_device_flash_and_tpm_min_idle/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/49.spi_device_flash_mode.3357682633 |
| Short name | T982 |
| Test name | |
| Test status | |
| Simulation time | 2235810452 ps |
| CPU time | 23.52 seconds |
| Started | Aug 27 06:30:06 PM UTC 24 |
| Finished | Aug 27 06:30:31 PM UTC 24 |
| Peak memory | 235020 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3357682633 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/ spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_mode.3357682633 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/49.spi_device_flash_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/49.spi_device_flash_mode_ignore_cmds.654621323 |
| Short name | T983 |
| Test name | |
| Test status | |
| Simulation time | 1279071176 ps |
| CPU time | 40.98 seconds |
| Started | Aug 27 06:30:08 PM UTC 24 |
| Finished | Aug 27 06:30:50 PM UTC 24 |
| Peak memory | 247252 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=654621323 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_26/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_mode_ignore_cmds.654621323 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/49.spi_device_flash_mode_ignore_cmds/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/49.spi_device_intercept.526743916 |
| Short name | T978 |
| Test name | |
| Test status | |
| Simulation time | 6143633705 ps |
| CPU time | 13.83 seconds |
| Started | Aug 27 06:30:02 PM UTC 24 |
| Finished | Aug 27 06:30:17 PM UTC 24 |
| Peak memory | 245328 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=526743916 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/sp i_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_intercept.526743916 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/49.spi_device_intercept/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/49.spi_device_mailbox.2272896690 |
| Short name | T990 |
| Test name | |
| Test status | |
| Simulation time | 39690930603 ps |
| CPU time | 82.35 seconds |
| Started | Aug 27 06:30:03 PM UTC 24 |
| Finished | Aug 27 06:31:27 PM UTC 24 |
| Peak memory | 245336 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2272896690 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_mailbox.2272896690 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/49.spi_device_mailbox/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/49.spi_device_pass_addr_payload_swap.250638296 |
| Short name | T969 |
| Test name | |
| Test status | |
| Simulation time | 448440438 ps |
| CPU time | 5.47 seconds |
| Started | Aug 27 06:30:01 PM UTC 24 |
| Finished | Aug 27 06:30:08 PM UTC 24 |
| Peak memory | 245164 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=250638296 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_26/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_pass_addr_payload_swap.250638296 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/49.spi_device_pass_addr_payload_swap/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/49.spi_device_pass_cmd_filtering.3857871803 |
| Short name | T971 |
| Test name | |
| Test status | |
| Simulation time | 602244068 ps |
| CPU time | 5.75 seconds |
| Started | Aug 27 06:30:01 PM UTC 24 |
| Finished | Aug 27 06:30:08 PM UTC 24 |
| Peak memory | 234936 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3857871803 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_08_26/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_pass_cmd_filtering.3857871803 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/49.spi_device_pass_cmd_filtering/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/49.spi_device_read_buffer_direct.4175538689 |
| Short name | T979 |
| Test name | |
| Test status | |
| Simulation time | 2068589994 ps |
| CPU time | 10.76 seconds |
| Started | Aug 27 06:30:10 PM UTC 24 |
| Finished | Aug 27 06:30:22 PM UTC 24 |
| Peak memory | 233612 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4175538689 -assert nopostproc +UVM_TESTNAME=spi_device _base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_read_buffer_direct.4175538689 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/49.spi_device_read_buffer_direct/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/49.spi_device_stress_all.1384842492 |
| Short name | T1010 |
| Test name | |
| Test status | |
| Simulation time | 232232205656 ps |
| CPU time | 351.92 seconds |
| Started | Aug 27 06:30:10 PM UTC 24 |
| Finished | Aug 27 06:36:06 PM UTC 24 |
| Peak memory | 261832 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1384842492 -assert nopostproc +UVM_ TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_stress_all.1384842492 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/49.spi_device_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/49.spi_device_tpm_all.2695477112 |
| Short name | T981 |
| Test name | |
| Test status | |
| Simulation time | 5727494219 ps |
| CPU time | 30.1 seconds |
| Started | Aug 27 06:29:58 PM UTC 24 |
| Finished | Aug 27 06:30:30 PM UTC 24 |
| Peak memory | 231664 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2695477112 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_all.2695477112 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/49.spi_device_tpm_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/49.spi_device_tpm_read_hw_reg.2998176457 |
| Short name | T963 |
| Test name | |
| Test status | |
| Simulation time | 17103130 ps |
| CPU time | 1.02 seconds |
| Started | Aug 27 06:29:56 PM UTC 24 |
| Finished | Aug 27 06:29:59 PM UTC 24 |
| Peak memory | 215804 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2998176457 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_26/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_read_hw_reg.2998176457 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/49.spi_device_tpm_read_hw_reg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/49.spi_device_tpm_rw.336762896 |
| Short name | T966 |
| Test name | |
| Test status | |
| Simulation time | 119761461 ps |
| CPU time | 1.59 seconds |
| Started | Aug 27 06:30:01 PM UTC 24 |
| Finished | Aug 27 06:30:04 PM UTC 24 |
| Peak memory | 215960 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=336762896 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/spi_d evice_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_rw.336762896 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/49.spi_device_tpm_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/49.spi_device_tpm_sts_read.3562660113 |
| Short name | T965 |
| Test name | |
| Test status | |
| Simulation time | 180359899 ps |
| CPU time | 1.1 seconds |
| Started | Aug 27 06:29:58 PM UTC 24 |
| Finished | Aug 27 06:30:01 PM UTC 24 |
| Peak memory | 215872 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3562660113 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_2 6/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_sts_read.3562660113 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/49.spi_device_tpm_sts_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/49.spi_device_upload.1849895592 |
| Short name | T972 |
| Test name | |
| Test status | |
| Simulation time | 674008488 ps |
| CPU time | 4.82 seconds |
| Started | Aug 27 06:30:03 PM UTC 24 |
| Finished | Aug 27 06:30:08 PM UTC 24 |
| Peak memory | 243940 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1849895592 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_upload.1849895592 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/49.spi_device_upload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/5.spi_device_alert_test.2464667761 |
| Short name | T390 |
| Test name | |
| Test status | |
| Simulation time | 15563244 ps |
| CPU time | 1.12 seconds |
| Started | Aug 27 06:12:39 PM UTC 24 |
| Finished | Aug 27 06:12:41 PM UTC 24 |
| Peak memory | 215684 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2464667761 -assert nopostproc +UVM_TES TNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_alert_test.2464667761 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/5.spi_device_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/5.spi_device_cfg_cmd.3650646700 |
| Short name | T212 |
| Test name | |
| Test status | |
| Simulation time | 75397868 ps |
| CPU time | 3.21 seconds |
| Started | Aug 27 06:12:27 PM UTC 24 |
| Finished | Aug 27 06:12:31 PM UTC 24 |
| Peak memory | 234904 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3650646700 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_cfg_cmd.3650646700 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/5.spi_device_cfg_cmd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/5.spi_device_csb_read.1520447606 |
| Short name | T386 |
| Test name | |
| Test status | |
| Simulation time | 47452938 ps |
| CPU time | 1.12 seconds |
| Started | Aug 27 06:12:13 PM UTC 24 |
| Finished | Aug 27 06:12:15 PM UTC 24 |
| Peak memory | 215808 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1520447606 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/sp i_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_csb_read.1520447606 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/5.spi_device_csb_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/5.spi_device_flash_all.2200861083 |
| Short name | T97 |
| Test name | |
| Test status | |
| Simulation time | 41743252938 ps |
| CPU time | 103.72 seconds |
| Started | Aug 27 06:12:32 PM UTC 24 |
| Finished | Aug 27 06:14:18 PM UTC 24 |
| Peak memory | 265816 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2200861083 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/s pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_all.2200861083 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/5.spi_device_flash_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/5.spi_device_flash_and_tpm.2910150813 |
| Short name | T245 |
| Test name | |
| Test status | |
| Simulation time | 9026312131 ps |
| CPU time | 59.82 seconds |
| Started | Aug 27 06:12:33 PM UTC 24 |
| Finished | Aug 27 06:13:34 PM UTC 24 |
| Peak memory | 251672 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2910150813 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_ 26/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_and_tpm.2910150813 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/5.spi_device_flash_and_tpm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/5.spi_device_flash_and_tpm_min_idle.4132771928 |
| Short name | T191 |
| Test name | |
| Test status | |
| Simulation time | 16843973808 ps |
| CPU time | 53.08 seconds |
| Started | Aug 27 06:12:38 PM UTC 24 |
| Finished | Aug 27 06:13:32 PM UTC 24 |
| Peak memory | 265844 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4132771928 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_26/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_and_tpm_min_idle.4132771928 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/5.spi_device_flash_and_tpm_min_idle/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/5.spi_device_flash_mode.64840563 |
| Short name | T164 |
| Test name | |
| Test status | |
| Simulation time | 4602945801 ps |
| CPU time | 18.98 seconds |
| Started | Aug 27 06:12:28 PM UTC 24 |
| Finished | Aug 27 06:12:48 PM UTC 24 |
| Peak memory | 251476 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=64840563 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/sp i_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_mode.64840563 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/5.spi_device_flash_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/5.spi_device_intercept.3808665199 |
| Short name | T120 |
| Test name | |
| Test status | |
| Simulation time | 14896248904 ps |
| CPU time | 35.54 seconds |
| Started | Aug 27 06:12:21 PM UTC 24 |
| Finished | Aug 27 06:12:58 PM UTC 24 |
| Peak memory | 235108 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3808665199 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/s pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_intercept.3808665199 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/5.spi_device_intercept/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/5.spi_device_mailbox.2910011090 |
| Short name | T388 |
| Test name | |
| Test status | |
| Simulation time | 994332292 ps |
| CPU time | 14.45 seconds |
| Started | Aug 27 06:12:21 PM UTC 24 |
| Finished | Aug 27 06:12:36 PM UTC 24 |
| Peak memory | 251308 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2910011090 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_mailbox.2910011090 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/5.spi_device_mailbox/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/5.spi_device_pass_addr_payload_swap.541591535 |
| Short name | T62 |
| Test name | |
| Test status | |
| Simulation time | 1464904725 ps |
| CPU time | 5.92 seconds |
| Started | Aug 27 06:12:20 PM UTC 24 |
| Finished | Aug 27 06:12:27 PM UTC 24 |
| Peak memory | 245208 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=541591535 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_26/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_pass_addr_payload_swap.541591535 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/5.spi_device_pass_addr_payload_swap/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/5.spi_device_pass_cmd_filtering.1918245376 |
| Short name | T263 |
| Test name | |
| Test status | |
| Simulation time | 417108630 ps |
| CPU time | 7.92 seconds |
| Started | Aug 27 06:12:20 PM UTC 24 |
| Finished | Aug 27 06:12:29 PM UTC 24 |
| Peak memory | 245160 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1918245376 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_08_26/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_pass_cmd_filtering.1918245376 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/5.spi_device_pass_cmd_filtering/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/5.spi_device_read_buffer_direct.2715938596 |
| Short name | T163 |
| Test name | |
| Test status | |
| Simulation time | 2603186003 ps |
| CPU time | 15.12 seconds |
| Started | Aug 27 06:12:29 PM UTC 24 |
| Finished | Aug 27 06:12:46 PM UTC 24 |
| Peak memory | 233504 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2715938596 -assert nopostproc +UVM_TESTNAME=spi_device _base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_read_buffer_direct.2715938596 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/5.spi_device_read_buffer_direct/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/5.spi_device_stress_all.2151062809 |
| Short name | T999 |
| Test name | |
| Test status | |
| Simulation time | 111025638747 ps |
| CPU time | 1219.37 seconds |
| Started | Aug 27 06:12:38 PM UTC 24 |
| Finished | Aug 27 06:33:11 PM UTC 24 |
| Peak memory | 294532 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2151062809 -assert nopostproc +UVM_ TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_stress_all.2151062809 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/5.spi_device_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/5.spi_device_tpm_all.2006260452 |
| Short name | T360 |
| Test name | |
| Test status | |
| Simulation time | 40201676899 ps |
| CPU time | 30.42 seconds |
| Started | Aug 27 06:12:14 PM UTC 24 |
| Finished | Aug 27 06:12:46 PM UTC 24 |
| Peak memory | 227616 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2006260452 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_all.2006260452 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/5.spi_device_tpm_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/5.spi_device_tpm_read_hw_reg.2465525895 |
| Short name | T389 |
| Test name | |
| Test status | |
| Simulation time | 4019271126 ps |
| CPU time | 21.18 seconds |
| Started | Aug 27 06:12:14 PM UTC 24 |
| Finished | Aug 27 06:12:37 PM UTC 24 |
| Peak memory | 227548 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2465525895 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_26/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_read_hw_reg.2465525895 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/5.spi_device_tpm_read_hw_reg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/5.spi_device_tpm_rw.649655720 |
| Short name | T369 |
| Test name | |
| Test status | |
| Simulation time | 184249732 ps |
| CPU time | 2.54 seconds |
| Started | Aug 27 06:12:16 PM UTC 24 |
| Finished | Aug 27 06:12:20 PM UTC 24 |
| Peak memory | 227456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=649655720 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/spi_d evice_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_rw.649655720 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/5.spi_device_tpm_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/5.spi_device_tpm_sts_read.3758157127 |
| Short name | T387 |
| Test name | |
| Test status | |
| Simulation time | 91739334 ps |
| CPU time | 1.24 seconds |
| Started | Aug 27 06:12:16 PM UTC 24 |
| Finished | Aug 27 06:12:19 PM UTC 24 |
| Peak memory | 215868 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3758157127 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_2 6/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_sts_read.3758157127 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/5.spi_device_tpm_sts_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/5.spi_device_upload.4085308857 |
| Short name | T61 |
| Test name | |
| Test status | |
| Simulation time | 1053365368 ps |
| CPU time | 12.47 seconds |
| Started | Aug 27 06:12:25 PM UTC 24 |
| Finished | Aug 27 06:12:39 PM UTC 24 |
| Peak memory | 235024 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4085308857 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_upload.4085308857 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/5.spi_device_upload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/6.spi_device_alert_test.1197122239 |
| Short name | T397 |
| Test name | |
| Test status | |
| Simulation time | 46653228 ps |
| CPU time | 1.12 seconds |
| Started | Aug 27 06:13:02 PM UTC 24 |
| Finished | Aug 27 06:13:04 PM UTC 24 |
| Peak memory | 215680 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1197122239 -assert nopostproc +UVM_TES TNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_alert_test.1197122239 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/6.spi_device_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/6.spi_device_cfg_cmd.1226138451 |
| Short name | T317 |
| Test name | |
| Test status | |
| Simulation time | 1042331986 ps |
| CPU time | 8.43 seconds |
| Started | Aug 27 06:12:49 PM UTC 24 |
| Finished | Aug 27 06:12:59 PM UTC 24 |
| Peak memory | 245156 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1226138451 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_cfg_cmd.1226138451 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/6.spi_device_cfg_cmd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/6.spi_device_csb_read.1385903985 |
| Short name | T391 |
| Test name | |
| Test status | |
| Simulation time | 27183649 ps |
| CPU time | 1.12 seconds |
| Started | Aug 27 06:12:40 PM UTC 24 |
| Finished | Aug 27 06:12:42 PM UTC 24 |
| Peak memory | 215456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1385903985 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/sp i_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_csb_read.1385903985 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/6.spi_device_csb_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/6.spi_device_flash_all.3376287669 |
| Short name | T396 |
| Test name | |
| Test status | |
| Simulation time | 48408975 ps |
| CPU time | 1.17 seconds |
| Started | Aug 27 06:12:59 PM UTC 24 |
| Finished | Aug 27 06:13:01 PM UTC 24 |
| Peak memory | 225680 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3376287669 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/s pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_all.3376287669 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/6.spi_device_flash_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/6.spi_device_flash_and_tpm_min_idle.3703940758 |
| Short name | T197 |
| Test name | |
| Test status | |
| Simulation time | 1878696150 ps |
| CPU time | 40.25 seconds |
| Started | Aug 27 06:13:01 PM UTC 24 |
| Finished | Aug 27 06:13:43 PM UTC 24 |
| Peak memory | 261576 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3703940758 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_26/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_and_tpm_min_idle.3703940758 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/6.spi_device_flash_and_tpm_min_idle/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/6.spi_device_flash_mode.2034665940 |
| Short name | T350 |
| Test name | |
| Test status | |
| Simulation time | 2965159230 ps |
| CPU time | 65.11 seconds |
| Started | Aug 27 06:12:52 PM UTC 24 |
| Finished | Aug 27 06:13:59 PM UTC 24 |
| Peak memory | 235108 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2034665940 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/ spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_mode.2034665940 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/6.spi_device_flash_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/6.spi_device_flash_mode_ignore_cmds.4192022475 |
| Short name | T210 |
| Test name | |
| Test status | |
| Simulation time | 9001318090 ps |
| CPU time | 48.17 seconds |
| Started | Aug 27 06:12:57 PM UTC 24 |
| Finished | Aug 27 06:13:46 PM UTC 24 |
| Peak memory | 251416 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4192022475 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_26/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_mode_ignore_cmds.4192022475 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/6.spi_device_flash_mode_ignore_cmds/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/6.spi_device_intercept.867217142 |
| Short name | T269 |
| Test name | |
| Test status | |
| Simulation time | 1376867983 ps |
| CPU time | 12.16 seconds |
| Started | Aug 27 06:12:48 PM UTC 24 |
| Finished | Aug 27 06:13:02 PM UTC 24 |
| Peak memory | 245164 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=867217142 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/sp i_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_intercept.867217142 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/6.spi_device_intercept/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/6.spi_device_mailbox.184865148 |
| Short name | T283 |
| Test name | |
| Test status | |
| Simulation time | 4923773738 ps |
| CPU time | 40.57 seconds |
| Started | Aug 27 06:12:49 PM UTC 24 |
| Finished | Aug 27 06:13:31 PM UTC 24 |
| Peak memory | 245360 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=184865148 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_mailbox.184865148 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/6.spi_device_mailbox/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/6.spi_device_pass_addr_payload_swap.3711761430 |
| Short name | T394 |
| Test name | |
| Test status | |
| Simulation time | 34755697 ps |
| CPU time | 3.17 seconds |
| Started | Aug 27 06:12:47 PM UTC 24 |
| Finished | Aug 27 06:12:51 PM UTC 24 |
| Peak memory | 244948 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3711761430 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_26/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_pass_addr_payload_swap.3711761430 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/6.spi_device_pass_addr_payload_swap/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/6.spi_device_pass_cmd_filtering.1992112414 |
| Short name | T198 |
| Test name | |
| Test status | |
| Simulation time | 8020866043 ps |
| CPU time | 7.91 seconds |
| Started | Aug 27 06:12:47 PM UTC 24 |
| Finished | Aug 27 06:12:56 PM UTC 24 |
| Peak memory | 235028 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1992112414 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_08_26/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_pass_cmd_filtering.1992112414 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/6.spi_device_pass_cmd_filtering/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/6.spi_device_read_buffer_direct.2234773894 |
| Short name | T165 |
| Test name | |
| Test status | |
| Simulation time | 316212483 ps |
| CPU time | 3.51 seconds |
| Started | Aug 27 06:12:59 PM UTC 24 |
| Finished | Aug 27 06:13:03 PM UTC 24 |
| Peak memory | 233332 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2234773894 -assert nopostproc +UVM_TESTNAME=spi_device _base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_read_buffer_direct.2234773894 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/6.spi_device_read_buffer_direct/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/6.spi_device_stress_all.376748866 |
| Short name | T72 |
| Test name | |
| Test status | |
| Simulation time | 169623368578 ps |
| CPU time | 740.54 seconds |
| Started | Aug 27 06:13:02 PM UTC 24 |
| Finished | Aug 27 06:25:31 PM UTC 24 |
| Peak memory | 296576 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=376748866 -assert nopostproc +UVM_T ESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_stress_all.376748866 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/6.spi_device_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/6.spi_device_tpm_all.2630824280 |
| Short name | T359 |
| Test name | |
| Test status | |
| Simulation time | 1242610367 ps |
| CPU time | 16 seconds |
| Started | Aug 27 06:12:43 PM UTC 24 |
| Finished | Aug 27 06:13:01 PM UTC 24 |
| Peak memory | 227504 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2630824280 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_all.2630824280 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/6.spi_device_tpm_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/6.spi_device_tpm_read_hw_reg.8860325 |
| Short name | T395 |
| Test name | |
| Test status | |
| Simulation time | 1232500709 ps |
| CPU time | 14.04 seconds |
| Started | Aug 27 06:12:42 PM UTC 24 |
| Finished | Aug 27 06:12:58 PM UTC 24 |
| Peak memory | 227408 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=8860325 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U VM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_2 6/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_read_hw_reg.8860325 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/6.spi_device_tpm_read_hw_reg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/6.spi_device_tpm_rw.2943633710 |
| Short name | T393 |
| Test name | |
| Test status | |
| Simulation time | 46564943 ps |
| CPU time | 1.04 seconds |
| Started | Aug 27 06:12:46 PM UTC 24 |
| Finished | Aug 27 06:12:48 PM UTC 24 |
| Peak memory | 215740 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2943633710 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_rw.2943633710 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/6.spi_device_tpm_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/6.spi_device_tpm_sts_read.873039829 |
| Short name | T392 |
| Test name | |
| Test status | |
| Simulation time | 73287192 ps |
| CPU time | 1.06 seconds |
| Started | Aug 27 06:12:45 PM UTC 24 |
| Finished | Aug 27 06:12:48 PM UTC 24 |
| Peak memory | 215804 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=873039829 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26 /spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_sts_read.873039829 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/6.spi_device_tpm_sts_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/6.spi_device_upload.632125241 |
| Short name | T220 |
| Test name | |
| Test status | |
| Simulation time | 3492733878 ps |
| CPU time | 11.03 seconds |
| Started | Aug 27 06:12:49 PM UTC 24 |
| Finished | Aug 27 06:13:01 PM UTC 24 |
| Peak memory | 245288 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=632125241 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/spi_d evice_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_upload.632125241 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/6.spi_device_upload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/7.spi_device_alert_test.365917339 |
| Short name | T402 |
| Test name | |
| Test status | |
| Simulation time | 13385674 ps |
| CPU time | 0.96 seconds |
| Started | Aug 27 06:13:28 PM UTC 24 |
| Finished | Aug 27 06:13:30 PM UTC 24 |
| Peak memory | 215684 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=365917339 -assert nopostproc +UVM_TEST NAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_alert_test.365917339 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/7.spi_device_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/7.spi_device_cfg_cmd.2631709984 |
| Short name | T273 |
| Test name | |
| Test status | |
| Simulation time | 1130247546 ps |
| CPU time | 10.09 seconds |
| Started | Aug 27 06:13:13 PM UTC 24 |
| Finished | Aug 27 06:13:24 PM UTC 24 |
| Peak memory | 234900 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2631709984 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_cfg_cmd.2631709984 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/7.spi_device_cfg_cmd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/7.spi_device_csb_read.162041693 |
| Short name | T398 |
| Test name | |
| Test status | |
| Simulation time | 15522312 ps |
| CPU time | 1.2 seconds |
| Started | Aug 27 06:13:02 PM UTC 24 |
| Finished | Aug 27 06:13:05 PM UTC 24 |
| Peak memory | 215744 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=162041693 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_csb_read.162041693 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/7.spi_device_csb_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/7.spi_device_flash_all.2697936515 |
| Short name | T227 |
| Test name | |
| Test status | |
| Simulation time | 5285738780 ps |
| CPU time | 41.71 seconds |
| Started | Aug 27 06:13:20 PM UTC 24 |
| Finished | Aug 27 06:14:03 PM UTC 24 |
| Peak memory | 261732 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2697936515 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/s pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_all.2697936515 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/7.spi_device_flash_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/7.spi_device_flash_and_tpm.3965456434 |
| Short name | T254 |
| Test name | |
| Test status | |
| Simulation time | 6176887728 ps |
| CPU time | 98.07 seconds |
| Started | Aug 27 06:13:21 PM UTC 24 |
| Finished | Aug 27 06:15:01 PM UTC 24 |
| Peak memory | 267904 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3965456434 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_ 26/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_and_tpm.3965456434 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/7.spi_device_flash_and_tpm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/7.spi_device_flash_mode_ignore_cmds.750873007 |
| Short name | T82 |
| Test name | |
| Test status | |
| Simulation time | 81533962730 ps |
| CPU time | 155.19 seconds |
| Started | Aug 27 06:13:19 PM UTC 24 |
| Finished | Aug 27 06:15:57 PM UTC 24 |
| Peak memory | 249012 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=750873007 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_26/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_mode_ignore_cmds.750873007 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/7.spi_device_flash_mode_ignore_cmds/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/7.spi_device_intercept.1036992603 |
| Short name | T50 |
| Test name | |
| Test status | |
| Simulation time | 222905150 ps |
| CPU time | 8.17 seconds |
| Started | Aug 27 06:13:09 PM UTC 24 |
| Finished | Aug 27 06:13:19 PM UTC 24 |
| Peak memory | 245288 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1036992603 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/s pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_intercept.1036992603 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/7.spi_device_intercept/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/7.spi_device_mailbox.3974887042 |
| Short name | T275 |
| Test name | |
| Test status | |
| Simulation time | 1605015024 ps |
| CPU time | 28.46 seconds |
| Started | Aug 27 06:13:10 PM UTC 24 |
| Finished | Aug 27 06:13:40 PM UTC 24 |
| Peak memory | 234936 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3974887042 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_mailbox.3974887042 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/7.spi_device_mailbox/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/7.spi_device_pass_addr_payload_swap.3745322290 |
| Short name | T401 |
| Test name | |
| Test status | |
| Simulation time | 125119546 ps |
| CPU time | 3.12 seconds |
| Started | Aug 27 06:13:07 PM UTC 24 |
| Finished | Aug 27 06:13:11 PM UTC 24 |
| Peak memory | 244948 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3745322290 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_26/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_pass_addr_payload_swap.3745322290 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/7.spi_device_pass_addr_payload_swap/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/7.spi_device_pass_cmd_filtering.2224367225 |
| Short name | T266 |
| Test name | |
| Test status | |
| Simulation time | 3013901303 ps |
| CPU time | 19.43 seconds |
| Started | Aug 27 06:13:06 PM UTC 24 |
| Finished | Aug 27 06:13:26 PM UTC 24 |
| Peak memory | 245204 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2224367225 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_08_26/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_pass_cmd_filtering.2224367225 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/7.spi_device_pass_cmd_filtering/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/7.spi_device_read_buffer_direct.722588558 |
| Short name | T167 |
| Test name | |
| Test status | |
| Simulation time | 999821807 ps |
| CPU time | 9.53 seconds |
| Started | Aug 27 06:13:19 PM UTC 24 |
| Finished | Aug 27 06:13:30 PM UTC 24 |
| Peak memory | 228604 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=722588558 -assert nopostproc +UVM_TESTNAME=spi_device_ base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_read_buffer_direct.722588558 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/7.spi_device_read_buffer_direct/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/7.spi_device_stress_all.1532472842 |
| Short name | T35 |
| Test name | |
| Test status | |
| Simulation time | 6733499663 ps |
| CPU time | 106.62 seconds |
| Started | Aug 27 06:13:28 PM UTC 24 |
| Finished | Aug 27 06:15:16 PM UTC 24 |
| Peak memory | 261724 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1532472842 -assert nopostproc +UVM_ TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_stress_all.1532472842 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/7.spi_device_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/7.spi_device_tpm_all.732751145 |
| Short name | T370 |
| Test name | |
| Test status | |
| Simulation time | 1781571457 ps |
| CPU time | 27.16 seconds |
| Started | Aug 27 06:13:05 PM UTC 24 |
| Finished | Aug 27 06:13:33 PM UTC 24 |
| Peak memory | 227576 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=732751145 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_all.732751145 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/7.spi_device_tpm_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/7.spi_device_tpm_read_hw_reg.3523996086 |
| Short name | T400 |
| Test name | |
| Test status | |
| Simulation time | 382769588 ps |
| CPU time | 6.26 seconds |
| Started | Aug 27 06:13:02 PM UTC 24 |
| Finished | Aug 27 06:13:10 PM UTC 24 |
| Peak memory | 227492 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3523996086 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_26/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_read_hw_reg.3523996086 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/7.spi_device_tpm_read_hw_reg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/7.spi_device_tpm_rw.2576641828 |
| Short name | T374 |
| Test name | |
| Test status | |
| Simulation time | 509445129 ps |
| CPU time | 2.89 seconds |
| Started | Aug 27 06:13:06 PM UTC 24 |
| Finished | Aug 27 06:13:10 PM UTC 24 |
| Peak memory | 227424 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2576641828 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_rw.2576641828 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/7.spi_device_tpm_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/7.spi_device_tpm_sts_read.533558031 |
| Short name | T399 |
| Test name | |
| Test status | |
| Simulation time | 58875024 ps |
| CPU time | 1.32 seconds |
| Started | Aug 27 06:13:06 PM UTC 24 |
| Finished | Aug 27 06:13:08 PM UTC 24 |
| Peak memory | 215864 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=533558031 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26 /spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_sts_read.533558031 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/7.spi_device_tpm_sts_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/7.spi_device_upload.3789029735 |
| Short name | T219 |
| Test name | |
| Test status | |
| Simulation time | 315557236 ps |
| CPU time | 6.05 seconds |
| Started | Aug 27 06:13:10 PM UTC 24 |
| Finished | Aug 27 06:13:18 PM UTC 24 |
| Peak memory | 249244 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3789029735 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_upload.3789029735 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/7.spi_device_upload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/8.spi_device_alert_test.4224782270 |
| Short name | T408 |
| Test name | |
| Test status | |
| Simulation time | 14476703 ps |
| CPU time | 1.12 seconds |
| Started | Aug 27 06:13:50 PM UTC 24 |
| Finished | Aug 27 06:13:52 PM UTC 24 |
| Peak memory | 215684 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4224782270 -assert nopostproc +UVM_TES TNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_alert_test.4224782270 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/8.spi_device_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/8.spi_device_cfg_cmd.675191507 |
| Short name | T276 |
| Test name | |
| Test status | |
| Simulation time | 33788555 ps |
| CPU time | 3.26 seconds |
| Started | Aug 27 06:13:36 PM UTC 24 |
| Finished | Aug 27 06:13:40 PM UTC 24 |
| Peak memory | 234908 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=675191507 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_cfg_cmd.675191507 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/8.spi_device_cfg_cmd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/8.spi_device_csb_read.409514402 |
| Short name | T403 |
| Test name | |
| Test status | |
| Simulation time | 63513689 ps |
| CPU time | 1.15 seconds |
| Started | Aug 27 06:13:29 PM UTC 24 |
| Finished | Aug 27 06:13:31 PM UTC 24 |
| Peak memory | 215744 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=409514402 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_csb_read.409514402 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/8.spi_device_csb_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/8.spi_device_flash_all.3615602554 |
| Short name | T64 |
| Test name | |
| Test status | |
| Simulation time | 6379888903 ps |
| CPU time | 86.42 seconds |
| Started | Aug 27 06:13:44 PM UTC 24 |
| Finished | Aug 27 06:15:12 PM UTC 24 |
| Peak memory | 265828 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3615602554 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/s pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_all.3615602554 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/8.spi_device_flash_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/8.spi_device_flash_and_tpm.1206838631 |
| Short name | T188 |
| Test name | |
| Test status | |
| Simulation time | 3738643681 ps |
| CPU time | 40.94 seconds |
| Started | Aug 27 06:13:44 PM UTC 24 |
| Finished | Aug 27 06:14:27 PM UTC 24 |
| Peak memory | 235100 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1206838631 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_ 26/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_and_tpm.1206838631 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/8.spi_device_flash_and_tpm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/8.spi_device_flash_and_tpm_min_idle.3617023331 |
| Short name | T236 |
| Test name | |
| Test status | |
| Simulation time | 241441364364 ps |
| CPU time | 576.72 seconds |
| Started | Aug 27 06:13:47 PM UTC 24 |
| Finished | Aug 27 06:23:31 PM UTC 24 |
| Peak memory | 276192 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3617023331 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_26/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_and_tpm_min_idle.3617023331 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/8.spi_device_flash_and_tpm_min_idle/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/8.spi_device_flash_mode.3642663711 |
| Short name | T168 |
| Test name | |
| Test status | |
| Simulation time | 511134940 ps |
| CPU time | 17.73 seconds |
| Started | Aug 27 06:13:41 PM UTC 24 |
| Finished | Aug 27 06:14:00 PM UTC 24 |
| Peak memory | 245208 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3642663711 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/ spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_mode.3642663711 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/8.spi_device_flash_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/8.spi_device_flash_mode_ignore_cmds.2416148872 |
| Short name | T208 |
| Test name | |
| Test status | |
| Simulation time | 2341139997 ps |
| CPU time | 7.21 seconds |
| Started | Aug 27 06:13:41 PM UTC 24 |
| Finished | Aug 27 06:13:49 PM UTC 24 |
| Peak memory | 235156 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2416148872 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_26/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_mode_ignore_cmds.2416148872 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/8.spi_device_flash_mode_ignore_cmds/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/8.spi_device_intercept.1799502096 |
| Short name | T237 |
| Test name | |
| Test status | |
| Simulation time | 114373103 ps |
| CPU time | 4.25 seconds |
| Started | Aug 27 06:13:36 PM UTC 24 |
| Finished | Aug 27 06:13:41 PM UTC 24 |
| Peak memory | 234964 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1799502096 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/s pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_intercept.1799502096 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/8.spi_device_intercept/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/8.spi_device_mailbox.3346145354 |
| Short name | T278 |
| Test name | |
| Test status | |
| Simulation time | 5705348999 ps |
| CPU time | 72.31 seconds |
| Started | Aug 27 06:13:36 PM UTC 24 |
| Finished | Aug 27 06:14:50 PM UTC 24 |
| Peak memory | 249380 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3346145354 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_mailbox.3346145354 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/8.spi_device_mailbox/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/8.spi_device_pass_addr_payload_swap.946637623 |
| Short name | T253 |
| Test name | |
| Test status | |
| Simulation time | 517783715 ps |
| CPU time | 7.7 seconds |
| Started | Aug 27 06:13:34 PM UTC 24 |
| Finished | Aug 27 06:13:43 PM UTC 24 |
| Peak memory | 245168 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=946637623 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_26/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_pass_addr_payload_swap.946637623 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/8.spi_device_pass_addr_payload_swap/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/8.spi_device_pass_cmd_filtering.1665201227 |
| Short name | T194 |
| Test name | |
| Test status | |
| Simulation time | 10890406128 ps |
| CPU time | 67.4 seconds |
| Started | Aug 27 06:13:34 PM UTC 24 |
| Finished | Aug 27 06:14:43 PM UTC 24 |
| Peak memory | 245392 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1665201227 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_08_26/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_pass_cmd_filtering.1665201227 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/8.spi_device_pass_cmd_filtering/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/8.spi_device_read_buffer_direct.4286144608 |
| Short name | T407 |
| Test name | |
| Test status | |
| Simulation time | 76042234 ps |
| CPU time | 5.25 seconds |
| Started | Aug 27 06:13:42 PM UTC 24 |
| Finished | Aug 27 06:13:48 PM UTC 24 |
| Peak memory | 231392 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4286144608 -assert nopostproc +UVM_TESTNAME=spi_device _base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_read_buffer_direct.4286144608 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/8.spi_device_read_buffer_direct/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/8.spi_device_stress_all.2243648345 |
| Short name | T179 |
| Test name | |
| Test status | |
| Simulation time | 232663438963 ps |
| CPU time | 617.33 seconds |
| Started | Aug 27 06:13:50 PM UTC 24 |
| Finished | Aug 27 06:24:14 PM UTC 24 |
| Peak memory | 294544 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2243648345 -assert nopostproc +UVM_ TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_stress_all.2243648345 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/8.spi_device_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/8.spi_device_tpm_all.2104629123 |
| Short name | T361 |
| Test name | |
| Test status | |
| Simulation time | 9477133360 ps |
| CPU time | 22.14 seconds |
| Started | Aug 27 06:13:32 PM UTC 24 |
| Finished | Aug 27 06:13:55 PM UTC 24 |
| Peak memory | 227616 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2104629123 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_all.2104629123 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/8.spi_device_tpm_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/8.spi_device_tpm_read_hw_reg.4214466171 |
| Short name | T404 |
| Test name | |
| Test status | |
| Simulation time | 772900323 ps |
| CPU time | 2.22 seconds |
| Started | Aug 27 06:13:31 PM UTC 24 |
| Finished | Aug 27 06:13:34 PM UTC 24 |
| Peak memory | 216464 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4214466171 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_26/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_read_hw_reg.4214466171 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/8.spi_device_tpm_read_hw_reg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/8.spi_device_tpm_rw.2883191844 |
| Short name | T406 |
| Test name | |
| Test status | |
| Simulation time | 11392580 ps |
| CPU time | 1.07 seconds |
| Started | Aug 27 06:13:33 PM UTC 24 |
| Finished | Aug 27 06:13:35 PM UTC 24 |
| Peak memory | 215740 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2883191844 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_rw.2883191844 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/8.spi_device_tpm_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/8.spi_device_tpm_sts_read.2586361658 |
| Short name | T405 |
| Test name | |
| Test status | |
| Simulation time | 75996645 ps |
| CPU time | 1.37 seconds |
| Started | Aug 27 06:13:32 PM UTC 24 |
| Finished | Aug 27 06:13:34 PM UTC 24 |
| Peak memory | 215864 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2586361658 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_2 6/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_sts_read.2586361658 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/8.spi_device_tpm_sts_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/8.spi_device_upload.3216219116 |
| Short name | T243 |
| Test name | |
| Test status | |
| Simulation time | 2186147746 ps |
| CPU time | 11.6 seconds |
| Started | Aug 27 06:13:36 PM UTC 24 |
| Finished | Aug 27 06:13:48 PM UTC 24 |
| Peak memory | 245268 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3216219116 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_upload.3216219116 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/8.spi_device_upload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/9.spi_device_alert_test.4010691534 |
| Short name | T182 |
| Test name | |
| Test status | |
| Simulation time | 11752631 ps |
| CPU time | 1.09 seconds |
| Started | Aug 27 06:14:18 PM UTC 24 |
| Finished | Aug 27 06:14:20 PM UTC 24 |
| Peak memory | 215684 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4010691534 -assert nopostproc +UVM_TES TNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_alert_test.4010691534 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/9.spi_device_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/9.spi_device_cfg_cmd.854175974 |
| Short name | T285 |
| Test name | |
| Test status | |
| Simulation time | 71094138 ps |
| CPU time | 3.38 seconds |
| Started | Aug 27 06:14:04 PM UTC 24 |
| Finished | Aug 27 06:14:08 PM UTC 24 |
| Peak memory | 245156 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=854175974 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_cfg_cmd.854175974 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/9.spi_device_cfg_cmd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/9.spi_device_csb_read.1502037638 |
| Short name | T409 |
| Test name | |
| Test status | |
| Simulation time | 38085699 ps |
| CPU time | 1.2 seconds |
| Started | Aug 27 06:13:50 PM UTC 24 |
| Finished | Aug 27 06:13:52 PM UTC 24 |
| Peak memory | 215812 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1502037638 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/sp i_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_csb_read.1502037638 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/9.spi_device_csb_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/9.spi_device_flash_all.83825871 |
| Short name | T410 |
| Test name | |
| Test status | |
| Simulation time | 17554766 ps |
| CPU time | 1.15 seconds |
| Started | Aug 27 06:14:10 PM UTC 24 |
| Finished | Aug 27 06:14:12 PM UTC 24 |
| Peak memory | 225676 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=83825871 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_all.83825871 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/9.spi_device_flash_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/9.spi_device_flash_and_tpm_min_idle.2902603803 |
| Short name | T363 |
| Test name | |
| Test status | |
| Simulation time | 60702669132 ps |
| CPU time | 125.91 seconds |
| Started | Aug 27 06:14:13 PM UTC 24 |
| Finished | Aug 27 06:16:22 PM UTC 24 |
| Peak memory | 261768 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2902603803 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_26/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_and_tpm_min_idle.2902603803 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/9.spi_device_flash_and_tpm_min_idle/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/9.spi_device_flash_mode.287310379 |
| Short name | T411 |
| Test name | |
| Test status | |
| Simulation time | 1089687110 ps |
| CPU time | 7.64 seconds |
| Started | Aug 27 06:14:04 PM UTC 24 |
| Finished | Aug 27 06:14:12 PM UTC 24 |
| Peak memory | 245224 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=287310379 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/s pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_mode.287310379 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/9.spi_device_flash_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/9.spi_device_flash_mode_ignore_cmds.1247701432 |
| Short name | T98 |
| Test name | |
| Test status | |
| Simulation time | 15801309038 ps |
| CPU time | 71.79 seconds |
| Started | Aug 27 06:14:08 PM UTC 24 |
| Finished | Aug 27 06:15:21 PM UTC 24 |
| Peak memory | 265804 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1247701432 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_26/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_mode_ignore_cmds.1247701432 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/9.spi_device_flash_mode_ignore_cmds/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/9.spi_device_intercept.2364765985 |
| Short name | T277 |
| Test name | |
| Test status | |
| Simulation time | 1349005160 ps |
| CPU time | 13.36 seconds |
| Started | Aug 27 06:13:57 PM UTC 24 |
| Finished | Aug 27 06:14:12 PM UTC 24 |
| Peak memory | 245220 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2364765985 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/s pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_intercept.2364765985 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/9.spi_device_intercept/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/9.spi_device_mailbox.2797885737 |
| Short name | T185 |
| Test name | |
| Test status | |
| Simulation time | 1828313271 ps |
| CPU time | 18.86 seconds |
| Started | Aug 27 06:14:01 PM UTC 24 |
| Finished | Aug 27 06:14:21 PM UTC 24 |
| Peak memory | 251372 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2797885737 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_mailbox.2797885737 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/9.spi_device_mailbox/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/9.spi_device_pass_addr_payload_swap.2002568425 |
| Short name | T299 |
| Test name | |
| Test status | |
| Simulation time | 426057653 ps |
| CPU time | 4.18 seconds |
| Started | Aug 27 06:13:57 PM UTC 24 |
| Finished | Aug 27 06:14:03 PM UTC 24 |
| Peak memory | 245268 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2002568425 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_26/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_pass_addr_payload_swap.2002568425 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/9.spi_device_pass_addr_payload_swap/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/9.spi_device_pass_cmd_filtering.4187643616 |
| Short name | T186 |
| Test name | |
| Test status | |
| Simulation time | 46773466763 ps |
| CPU time | 24.45 seconds |
| Started | Aug 27 06:13:56 PM UTC 24 |
| Finished | Aug 27 06:14:22 PM UTC 24 |
| Peak memory | 251472 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4187643616 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_08_26/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_pass_cmd_filtering.4187643616 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/9.spi_device_pass_cmd_filtering/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/9.spi_device_read_buffer_direct.2812067955 |
| Short name | T184 |
| Test name | |
| Test status | |
| Simulation time | 1690129228 ps |
| CPU time | 9.79 seconds |
| Started | Aug 27 06:14:09 PM UTC 24 |
| Finished | Aug 27 06:14:20 PM UTC 24 |
| Peak memory | 233376 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2812067955 -assert nopostproc +UVM_TESTNAME=spi_device _base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_read_buffer_direct.2812067955 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/9.spi_device_read_buffer_direct/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/9.spi_device_stress_all.3266607715 |
| Short name | T33 |
| Test name | |
| Test status | |
| Simulation time | 66963974 ps |
| CPU time | 1.59 seconds |
| Started | Aug 27 06:14:13 PM UTC 24 |
| Finished | Aug 27 06:14:16 PM UTC 24 |
| Peak memory | 215764 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3266607715 -assert nopostproc +UVM_ TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_stress_all.3266607715 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/9.spi_device_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/9.spi_device_tpm_all.2201124956 |
| Short name | T365 |
| Test name | |
| Test status | |
| Simulation time | 1214809521 ps |
| CPU time | 15.2 seconds |
| Started | Aug 27 06:13:53 PM UTC 24 |
| Finished | Aug 27 06:14:09 PM UTC 24 |
| Peak memory | 229316 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2201124956 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_all.2201124956 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/9.spi_device_tpm_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/9.spi_device_tpm_read_hw_reg.1526978130 |
| Short name | T412 |
| Test name | |
| Test status | |
| Simulation time | 16418210939 ps |
| CPU time | 22.21 seconds |
| Started | Aug 27 06:13:53 PM UTC 24 |
| Finished | Aug 27 06:14:16 PM UTC 24 |
| Peak memory | 227448 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1526978130 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_26/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_read_hw_reg.1526978130 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/9.spi_device_tpm_read_hw_reg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/9.spi_device_tpm_rw.2771867660 |
| Short name | T371 |
| Test name | |
| Test status | |
| Simulation time | 206957145 ps |
| CPU time | 1.4 seconds |
| Started | Aug 27 06:13:54 PM UTC 24 |
| Finished | Aug 27 06:13:56 PM UTC 24 |
| Peak memory | 215864 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2771867660 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_rw.2771867660 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/9.spi_device_tpm_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/9.spi_device_tpm_sts_read.1221255630 |
| Short name | T385 |
| Test name | |
| Test status | |
| Simulation time | 32484466 ps |
| CPU time | 1.07 seconds |
| Started | Aug 27 06:13:54 PM UTC 24 |
| Finished | Aug 27 06:13:56 PM UTC 24 |
| Peak memory | 215868 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1221255630 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_2 6/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_sts_read.1221255630 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/9.spi_device_tpm_sts_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/coverage/default/9.spi_device_upload.3341071685 |
| Short name | T240 |
| Test name | |
| Test status | |
| Simulation time | 288057113 ps |
| CPU time | 5.03 seconds |
| Started | Aug 27 06:14:01 PM UTC 24 |
| Finished | Aug 27 06:14:07 PM UTC 24 |
| Peak memory | 245144 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3341071685 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_upload.3341071685 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/spi_device_1r1w-sim-vcs/9.spi_device_upload/latest |
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