| T305 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/14.spi_device_mailbox.3518048791 |
|
|
Sep 01 02:52:15 PM UTC 24 |
Sep 01 02:52:33 PM UTC 24 |
2387583568 ps |
| T467 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/14.spi_device_read_buffer_direct.79066407 |
|
|
Sep 01 02:52:27 PM UTC 24 |
Sep 01 02:52:33 PM UTC 24 |
86383783 ps |
| T379 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/14.spi_device_flash_mode.2789315461 |
|
|
Sep 01 02:52:25 PM UTC 24 |
Sep 01 02:52:34 PM UTC 24 |
943404948 ps |
| T381 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/14.spi_device_tpm_all.236720078 |
|
|
Sep 01 02:52:09 PM UTC 24 |
Sep 01 02:52:37 PM UTC 24 |
1410074846 ps |
| T233 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/4.spi_device_flash_and_tpm.1761945572 |
|
|
Sep 01 02:47:35 PM UTC 24 |
Sep 01 02:52:37 PM UTC 24 |
112997809894 ps |
| T468 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/14.spi_device_alert_test.538523764 |
|
|
Sep 01 02:52:38 PM UTC 24 |
Sep 01 02:52:40 PM UTC 24 |
13576971 ps |
| T469 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/15.spi_device_csb_read.3255342859 |
|
|
Sep 01 02:52:38 PM UTC 24 |
Sep 01 02:52:41 PM UTC 24 |
19797934 ps |
| T37 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/3.spi_device_stress_all.1613413405 |
|
|
Sep 01 02:47:09 PM UTC 24 |
Sep 01 02:52:42 PM UTC 24 |
26747836527 ps |
| T329 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/14.spi_device_pass_addr_payload_swap.3632686016 |
|
|
Sep 01 02:52:14 PM UTC 24 |
Sep 01 02:52:42 PM UTC 24 |
7845483703 ps |
| T470 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/15.spi_device_tpm_sts_read.1505577313 |
|
|
Sep 01 02:52:43 PM UTC 24 |
Sep 01 02:52:45 PM UTC 24 |
723042700 ps |
| T471 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/15.spi_device_tpm_read_hw_reg.2183362537 |
|
|
Sep 01 02:52:42 PM UTC 24 |
Sep 01 02:52:48 PM UTC 24 |
925312821 ps |
| T472 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/15.spi_device_tpm_rw.1023506496 |
|
|
Sep 01 02:52:45 PM UTC 24 |
Sep 01 02:52:55 PM UTC 24 |
1090897257 ps |
| T38 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/4.spi_device_stress_all.2494182469 |
|
|
Sep 01 02:47:35 PM UTC 24 |
Sep 01 02:53:00 PM UTC 24 |
15977431319 ps |
| T473 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/17.spi_device_alert_test.3989605536 |
|
|
Sep 01 02:54:17 PM UTC 24 |
Sep 01 02:54:19 PM UTC 24 |
15530550 ps |
| T307 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/13.spi_device_mailbox.1814707453 |
|
|
Sep 01 02:51:48 PM UTC 24 |
Sep 01 02:53:02 PM UTC 24 |
14506244305 ps |
| T322 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/15.spi_device_pass_addr_payload_swap.100759870 |
|
|
Sep 01 02:52:48 PM UTC 24 |
Sep 01 02:53:04 PM UTC 24 |
1073019132 ps |
| T269 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/11.spi_device_stress_all.1315578988 |
|
|
Sep 01 02:51:07 PM UTC 24 |
Sep 01 02:53:07 PM UTC 24 |
82068822735 ps |
| T474 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/15.spi_device_intercept.3999328927 |
|
|
Sep 01 02:52:56 PM UTC 24 |
Sep 01 02:53:07 PM UTC 24 |
3249553460 ps |
| T268 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/13.spi_device_flash_all.1063010400 |
|
|
Sep 01 02:51:53 PM UTC 24 |
Sep 01 02:53:08 PM UTC 24 |
23347061903 ps |
| T347 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/15.spi_device_cfg_cmd.3754133537 |
|
|
Sep 01 02:53:05 PM UTC 24 |
Sep 01 02:53:09 PM UTC 24 |
120915627 ps |
| T251 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/9.spi_device_flash_and_tpm_min_idle.125226379 |
|
|
Sep 01 02:50:06 PM UTC 24 |
Sep 01 02:53:10 PM UTC 24 |
15693624564 ps |
| T475 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/15.spi_device_flash_mode_ignore_cmds.319284796 |
|
|
Sep 01 02:53:09 PM UTC 24 |
Sep 01 02:53:11 PM UTC 24 |
12027308 ps |
| T254 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/15.spi_device_upload.1871565652 |
|
|
Sep 01 02:53:03 PM UTC 24 |
Sep 01 02:53:12 PM UTC 24 |
10370977396 ps |
| T476 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/15.spi_device_flash_mode.2847427037 |
|
|
Sep 01 02:53:07 PM UTC 24 |
Sep 01 02:53:14 PM UTC 24 |
1284467441 ps |
| T196 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/15.spi_device_stress_all.3949021402 |
|
|
Sep 01 02:53:13 PM UTC 24 |
Sep 01 02:53:15 PM UTC 24 |
28619005 ps |
| T477 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/15.spi_device_alert_test.3453985603 |
|
|
Sep 01 02:53:15 PM UTC 24 |
Sep 01 02:53:17 PM UTC 24 |
30172360 ps |
| T478 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/16.spi_device_csb_read.993802912 |
|
|
Sep 01 02:53:16 PM UTC 24 |
Sep 01 02:53:18 PM UTC 24 |
14473585 ps |
| T479 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/15.spi_device_read_buffer_direct.1215624964 |
|
|
Sep 01 02:53:09 PM UTC 24 |
Sep 01 02:53:24 PM UTC 24 |
4199485173 ps |
| T480 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/16.spi_device_tpm_sts_read.2698159834 |
|
|
Sep 01 02:53:24 PM UTC 24 |
Sep 01 02:53:27 PM UTC 24 |
119180020 ps |
| T481 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/15.spi_device_tpm_all.3955045425 |
|
|
Sep 01 02:52:43 PM UTC 24 |
Sep 01 02:53:28 PM UTC 24 |
7848890976 ps |
| T264 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/15.spi_device_pass_cmd_filtering.2558648836 |
|
|
Sep 01 02:52:46 PM UTC 24 |
Sep 01 02:53:31 PM UTC 24 |
37994088167 ps |
| T482 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/16.spi_device_tpm_rw.3412750295 |
|
|
Sep 01 02:53:28 PM UTC 24 |
Sep 01 02:53:32 PM UTC 24 |
1976029879 ps |
| T197 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/7.spi_device_stress_all.2348335628 |
|
|
Sep 01 02:48:58 PM UTC 24 |
Sep 01 02:53:33 PM UTC 24 |
97787899493 ps |
| T483 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/16.spi_device_pass_cmd_filtering.3609116641 |
|
|
Sep 01 02:53:28 PM UTC 24 |
Sep 01 02:53:35 PM UTC 24 |
160238776 ps |
| T256 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/14.spi_device_flash_mode_ignore_cmds.3841887028 |
|
|
Sep 01 02:52:26 PM UTC 24 |
Sep 01 02:53:37 PM UTC 24 |
4252772747 ps |
| T336 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/15.spi_device_mailbox.1809894145 |
|
|
Sep 01 02:53:00 PM UTC 24 |
Sep 01 02:53:39 PM UTC 24 |
4103566022 ps |
| T335 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/16.spi_device_mailbox.4265442166 |
|
|
Sep 01 02:53:33 PM UTC 24 |
Sep 01 02:53:40 PM UTC 24 |
356126602 ps |
| T484 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/16.spi_device_intercept.2983463894 |
|
|
Sep 01 02:53:32 PM UTC 24 |
Sep 01 02:53:41 PM UTC 24 |
135648695 ps |
| T296 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/16.spi_device_cfg_cmd.4223495195 |
|
|
Sep 01 02:53:36 PM UTC 24 |
Sep 01 02:53:42 PM UTC 24 |
282648747 ps |
| T179 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/5.spi_device_stress_all.2714002774 |
|
|
Sep 01 02:47:57 PM UTC 24 |
Sep 01 02:53:42 PM UTC 24 |
18145757842 ps |
| T187 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/16.spi_device_tpm_read_hw_reg.3162248168 |
|
|
Sep 01 02:53:19 PM UTC 24 |
Sep 01 02:53:44 PM UTC 24 |
25451841168 ps |
| T188 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/12.spi_device_flash_and_tpm.354710542 |
|
|
Sep 01 02:51:31 PM UTC 24 |
Sep 01 02:53:45 PM UTC 24 |
15627645772 ps |
| T189 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/16.spi_device_alert_test.1252482101 |
|
|
Sep 01 02:53:46 PM UTC 24 |
Sep 01 02:53:48 PM UTC 24 |
14418550 ps |
| T190 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/16.spi_device_tpm_all.4258042121 |
|
|
Sep 01 02:53:21 PM UTC 24 |
Sep 01 02:53:51 PM UTC 24 |
1793375285 ps |
| T191 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/17.spi_device_csb_read.3650539244 |
|
|
Sep 01 02:53:49 PM UTC 24 |
Sep 01 02:53:51 PM UTC 24 |
179429920 ps |
| T192 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/16.spi_device_read_buffer_direct.2401344705 |
|
|
Sep 01 02:53:40 PM UTC 24 |
Sep 01 02:53:52 PM UTC 24 |
835364539 ps |
| T193 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/16.spi_device_upload.23603386 |
|
|
Sep 01 02:53:34 PM UTC 24 |
Sep 01 02:54:20 PM UTC 24 |
16032795849 ps |
| T194 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/0.spi_device_flash_and_tpm_min_idle.1931245502 |
|
|
Sep 01 02:46:00 PM UTC 24 |
Sep 01 02:53:54 PM UTC 24 |
497882948067 ps |
| T195 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/16.spi_device_pass_addr_payload_swap.828478753 |
|
|
Sep 01 02:53:29 PM UTC 24 |
Sep 01 02:53:56 PM UTC 24 |
21625188081 ps |
| T239 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/2.spi_device_flash_and_tpm.1157747797 |
|
|
Sep 01 02:46:36 PM UTC 24 |
Sep 01 02:53:56 PM UTC 24 |
197687271288 ps |
| T485 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/17.spi_device_tpm_sts_read.4151353564 |
|
|
Sep 01 02:53:54 PM UTC 24 |
Sep 01 02:53:56 PM UTC 24 |
31344868 ps |
| T270 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/16.spi_device_flash_mode.2163844375 |
|
|
Sep 01 02:53:38 PM UTC 24 |
Sep 01 02:53:57 PM UTC 24 |
2081081624 ps |
| T486 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/17.spi_device_tpm_rw.795007694 |
|
|
Sep 01 02:53:54 PM UTC 24 |
Sep 01 02:54:00 PM UTC 24 |
331213618 ps |
| T487 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/17.spi_device_pass_addr_payload_swap.1448699802 |
|
|
Sep 01 02:53:58 PM UTC 24 |
Sep 01 02:54:01 PM UTC 24 |
32007871 ps |
| T488 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/17.spi_device_tpm_read_hw_reg.2116250293 |
|
|
Sep 01 02:53:52 PM UTC 24 |
Sep 01 02:54:03 PM UTC 24 |
6367433099 ps |
| T489 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/17.spi_device_upload.16458162 |
|
|
Sep 01 02:54:01 PM UTC 24 |
Sep 01 02:54:05 PM UTC 24 |
90460948 ps |
| T490 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/17.spi_device_intercept.3358683794 |
|
|
Sep 01 02:53:58 PM UTC 24 |
Sep 01 02:54:08 PM UTC 24 |
2484663540 ps |
| T491 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/17.spi_device_pass_cmd_filtering.733483655 |
|
|
Sep 01 02:53:58 PM UTC 24 |
Sep 01 02:54:08 PM UTC 24 |
1516813352 ps |
| T492 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/17.spi_device_flash_mode.1997810423 |
|
|
Sep 01 02:54:04 PM UTC 24 |
Sep 01 02:54:13 PM UTC 24 |
1762263216 ps |
| T493 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/17.spi_device_read_buffer_direct.576774227 |
|
|
Sep 01 02:54:08 PM UTC 24 |
Sep 01 02:54:14 PM UTC 24 |
143939277 ps |
| T40 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/13.spi_device_flash_and_tpm_min_idle.2430568032 |
|
|
Sep 01 02:52:03 PM UTC 24 |
Sep 01 02:54:17 PM UTC 24 |
29030367888 ps |
| T83 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/18.spi_device_csb_read.2060703034 |
|
|
Sep 01 02:54:18 PM UTC 24 |
Sep 01 02:54:20 PM UTC 24 |
27733553 ps |
| T84 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/17.spi_device_cfg_cmd.2498221778 |
|
|
Sep 01 02:54:02 PM UTC 24 |
Sep 01 02:54:21 PM UTC 24 |
18010896903 ps |
| T85 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/13.spi_device_flash_and_tpm.121937171 |
|
|
Sep 01 02:51:59 PM UTC 24 |
Sep 01 02:54:22 PM UTC 24 |
20534766350 ps |
| T86 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/18.spi_device_tpm_rw.4283293535 |
|
|
Sep 01 02:54:22 PM UTC 24 |
Sep 01 02:54:25 PM UTC 24 |
303134184 ps |
| T87 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/18.spi_device_tpm_sts_read.1626287857 |
|
|
Sep 01 02:54:22 PM UTC 24 |
Sep 01 02:54:25 PM UTC 24 |
459271629 ps |
| T88 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/15.spi_device_flash_and_tpm.1866863343 |
|
|
Sep 01 02:53:11 PM UTC 24 |
Sep 01 02:54:26 PM UTC 24 |
27442906572 ps |
| T89 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/18.spi_device_pass_cmd_filtering.3974438280 |
|
|
Sep 01 02:54:23 PM UTC 24 |
Sep 01 02:54:30 PM UTC 24 |
1921872092 ps |
| T90 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/6.spi_device_flash_and_tpm_min_idle.1406580232 |
|
|
Sep 01 02:48:24 PM UTC 24 |
Sep 01 02:54:32 PM UTC 24 |
109322523211 ps |
| T91 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/15.spi_device_flash_and_tpm_min_idle.3724416117 |
|
|
Sep 01 02:53:12 PM UTC 24 |
Sep 01 02:54:33 PM UTC 24 |
4890873122 ps |
| T494 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/18.spi_device_intercept.1627953076 |
|
|
Sep 01 02:54:26 PM UTC 24 |
Sep 01 02:54:33 PM UTC 24 |
367776612 ps |
| T495 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/17.spi_device_tpm_all.1258296872 |
|
|
Sep 01 02:53:53 PM UTC 24 |
Sep 01 02:54:37 PM UTC 24 |
4480331048 ps |
| T496 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/18.spi_device_mailbox.189137567 |
|
|
Sep 01 02:54:27 PM UTC 24 |
Sep 01 02:54:38 PM UTC 24 |
2946717192 ps |
| T497 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/18.spi_device_pass_addr_payload_swap.193585 |
|
|
Sep 01 02:54:26 PM UTC 24 |
Sep 01 02:54:38 PM UTC 24 |
686992536 ps |
| T498 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/18.spi_device_read_buffer_direct.1176347741 |
|
|
Sep 01 02:54:38 PM UTC 24 |
Sep 01 02:54:43 PM UTC 24 |
151087791 ps |
| T499 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/18.spi_device_alert_test.1897958926 |
|
|
Sep 01 02:54:44 PM UTC 24 |
Sep 01 02:54:46 PM UTC 24 |
37803685 ps |
| T500 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/18.spi_device_flash_mode.3999442419 |
|
|
Sep 01 02:54:34 PM UTC 24 |
Sep 01 02:54:47 PM UTC 24 |
586750501 ps |
| T501 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/18.spi_device_cfg_cmd.1318408037 |
|
|
Sep 01 02:54:33 PM UTC 24 |
Sep 01 02:54:49 PM UTC 24 |
1626003366 ps |
| T502 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/18.spi_device_upload.304874863 |
|
|
Sep 01 02:54:31 PM UTC 24 |
Sep 01 02:54:49 PM UTC 24 |
3504836960 ps |
| T503 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/19.spi_device_csb_read.3998478565 |
|
|
Sep 01 02:54:48 PM UTC 24 |
Sep 01 02:54:50 PM UTC 24 |
192515321 ps |
| T504 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/18.spi_device_flash_and_tpm.2441245334 |
|
|
Sep 01 02:54:38 PM UTC 24 |
Sep 01 02:54:51 PM UTC 24 |
409363033 ps |
| T262 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/17.spi_device_flash_all.3100971931 |
|
|
Sep 01 02:54:09 PM UTC 24 |
Sep 01 02:54:53 PM UTC 24 |
14352861314 ps |
| T505 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/19.spi_device_tpm_sts_read.1899716718 |
|
|
Sep 01 02:54:51 PM UTC 24 |
Sep 01 02:54:54 PM UTC 24 |
28029116 ps |
| T506 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/19.spi_device_tpm_rw.274919034 |
|
|
Sep 01 02:54:51 PM UTC 24 |
Sep 01 02:54:56 PM UTC 24 |
566912647 ps |
| T507 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/19.spi_device_tpm_all.3942591122 |
|
|
Sep 01 02:54:51 PM UTC 24 |
Sep 01 02:54:59 PM UTC 24 |
289056448 ps |
| T345 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/19.spi_device_intercept.2472118826 |
|
|
Sep 01 02:54:54 PM UTC 24 |
Sep 01 02:55:00 PM UTC 24 |
389494907 ps |
| T303 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/19.spi_device_pass_cmd_filtering.1331086354 |
|
|
Sep 01 02:54:52 PM UTC 24 |
Sep 01 02:55:00 PM UTC 24 |
478348200 ps |
| T508 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/18.spi_device_tpm_read_hw_reg.3618928352 |
|
|
Sep 01 02:54:21 PM UTC 24 |
Sep 01 02:55:03 PM UTC 24 |
7145315387 ps |
| T509 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/19.spi_device_cfg_cmd.1145524223 |
|
|
Sep 01 02:55:01 PM UTC 24 |
Sep 01 02:55:06 PM UTC 24 |
54045215 ps |
| T271 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/16.spi_device_flash_and_tpm.805273292 |
|
|
Sep 01 02:53:43 PM UTC 24 |
Sep 01 02:55:06 PM UTC 24 |
23855663978 ps |
| T510 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/13.spi_device_flash_mode_ignore_cmds.1379519066 |
|
|
Sep 01 02:51:53 PM UTC 24 |
Sep 01 02:55:08 PM UTC 24 |
105962969742 ps |
| T511 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/18.spi_device_tpm_all.3645955120 |
|
|
Sep 01 02:54:21 PM UTC 24 |
Sep 01 02:55:08 PM UTC 24 |
4625927709 ps |
| T512 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/19.spi_device_tpm_read_hw_reg.1180215189 |
|
|
Sep 01 02:54:50 PM UTC 24 |
Sep 01 02:55:11 PM UTC 24 |
22628073532 ps |
| T339 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/19.spi_device_upload.89551171 |
|
|
Sep 01 02:55:00 PM UTC 24 |
Sep 01 02:55:13 PM UTC 24 |
2283475948 ps |
| T314 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/19.spi_device_mailbox.56524835 |
|
|
Sep 01 02:54:57 PM UTC 24 |
Sep 01 02:55:13 PM UTC 24 |
742336476 ps |
| T344 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/19.spi_device_pass_addr_payload_swap.1778445787 |
|
|
Sep 01 02:54:54 PM UTC 24 |
Sep 01 02:55:13 PM UTC 24 |
26647704392 ps |
| T513 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/19.spi_device_alert_test.1183655339 |
|
|
Sep 01 02:55:12 PM UTC 24 |
Sep 01 02:55:14 PM UTC 24 |
30828120 ps |
| T514 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/19.spi_device_read_buffer_direct.1556196763 |
|
|
Sep 01 02:55:05 PM UTC 24 |
Sep 01 02:55:15 PM UTC 24 |
782311156 ps |
| T515 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/20.spi_device_csb_read.573229888 |
|
|
Sep 01 02:55:14 PM UTC 24 |
Sep 01 02:55:16 PM UTC 24 |
70647299 ps |
| T516 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/20.spi_device_tpm_sts_read.1252275948 |
|
|
Sep 01 02:55:15 PM UTC 24 |
Sep 01 02:55:17 PM UTC 24 |
371695326 ps |
| T517 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/20.spi_device_tpm_rw.1515159036 |
|
|
Sep 01 02:55:16 PM UTC 24 |
Sep 01 02:55:19 PM UTC 24 |
138915548 ps |
| T278 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/12.spi_device_flash_all.3213034225 |
|
|
Sep 01 02:51:31 PM UTC 24 |
Sep 01 02:55:20 PM UTC 24 |
21635705491 ps |
| T265 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/15.spi_device_flash_all.3030024743 |
|
|
Sep 01 02:53:11 PM UTC 24 |
Sep 01 02:55:23 PM UTC 24 |
7175107910 ps |
| T518 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/20.spi_device_pass_cmd_filtering.788592250 |
|
|
Sep 01 02:55:17 PM UTC 24 |
Sep 01 02:55:25 PM UTC 24 |
1435928449 ps |
| T41 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/3.spi_device_flash_and_tpm_min_idle.454765527 |
|
|
Sep 01 02:47:08 PM UTC 24 |
Sep 01 02:55:27 PM UTC 24 |
861682329717 ps |
| T292 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/11.spi_device_flash_and_tpm_min_idle.162362613 |
|
|
Sep 01 02:51:05 PM UTC 24 |
Sep 01 02:55:27 PM UTC 24 |
25849353831 ps |
| T376 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/19.spi_device_flash_mode.1682265281 |
|
|
Sep 01 02:55:02 PM UTC 24 |
Sep 01 02:55:28 PM UTC 24 |
6748553388 ps |
| T342 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/20.spi_device_intercept.2582286695 |
|
|
Sep 01 02:55:19 PM UTC 24 |
Sep 01 02:55:30 PM UTC 24 |
398166871 ps |
| T325 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/20.spi_device_pass_addr_payload_swap.958627850 |
|
|
Sep 01 02:55:18 PM UTC 24 |
Sep 01 02:55:31 PM UTC 24 |
6233011115 ps |
| T221 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/20.spi_device_upload.2155365740 |
|
|
Sep 01 02:55:25 PM UTC 24 |
Sep 01 02:55:33 PM UTC 24 |
562370015 ps |
| T519 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/20.spi_device_flash_all.3827832198 |
|
|
Sep 01 02:55:31 PM UTC 24 |
Sep 01 02:55:33 PM UTC 24 |
19285919 ps |
| T520 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/20.spi_device_alert_test.2691317700 |
|
|
Sep 01 02:55:34 PM UTC 24 |
Sep 01 02:55:37 PM UTC 24 |
16280286 ps |
| T521 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/20.spi_device_read_buffer_direct.2768509700 |
|
|
Sep 01 02:55:29 PM UTC 24 |
Sep 01 02:55:37 PM UTC 24 |
220847955 ps |
| T522 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/20.spi_device_tpm_read_hw_reg.3433536290 |
|
|
Sep 01 02:55:14 PM UTC 24 |
Sep 01 02:55:37 PM UTC 24 |
89586019684 ps |
| T523 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/20.spi_device_tpm_all.1280037742 |
|
|
Sep 01 02:55:15 PM UTC 24 |
Sep 01 02:55:38 PM UTC 24 |
1722309008 ps |
| T524 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/21.spi_device_csb_read.2730643501 |
|
|
Sep 01 02:55:38 PM UTC 24 |
Sep 01 02:55:40 PM UTC 24 |
155924106 ps |
| T525 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/21.spi_device_tpm_sts_read.1269746791 |
|
|
Sep 01 02:55:39 PM UTC 24 |
Sep 01 02:55:41 PM UTC 24 |
104066018 ps |
| T526 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/21.spi_device_tpm_rw.526768132 |
|
|
Sep 01 02:55:41 PM UTC 24 |
Sep 01 02:55:43 PM UTC 24 |
12178355 ps |
| T527 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/21.spi_device_tpm_read_hw_reg.3923989360 |
|
|
Sep 01 02:55:38 PM UTC 24 |
Sep 01 02:55:44 PM UTC 24 |
1398041003 ps |
| T263 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/9.spi_device_stress_all.1111446854 |
|
|
Sep 01 02:50:10 PM UTC 24 |
Sep 01 02:55:45 PM UTC 24 |
437456949336 ps |
| T299 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/20.spi_device_cfg_cmd.2514899665 |
|
|
Sep 01 02:55:26 PM UTC 24 |
Sep 01 02:55:47 PM UTC 24 |
2125098952 ps |
| T373 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/20.spi_device_flash_mode.2938056467 |
|
|
Sep 01 02:55:28 PM UTC 24 |
Sep 01 02:55:51 PM UTC 24 |
2277561329 ps |
| T528 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/21.spi_device_intercept.2177662120 |
|
|
Sep 01 02:55:45 PM UTC 24 |
Sep 01 02:55:56 PM UTC 24 |
2308490714 ps |
| T529 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/11.spi_device_flash_all.1867485878 |
|
|
Sep 01 02:51:04 PM UTC 24 |
Sep 01 02:55:56 PM UTC 24 |
117048908822 ps |
| T530 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/21.spi_device_cfg_cmd.119560962 |
|
|
Sep 01 02:55:52 PM UTC 24 |
Sep 01 02:55:57 PM UTC 24 |
127893523 ps |
| T531 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/21.spi_device_pass_addr_payload_swap.428456746 |
|
|
Sep 01 02:55:44 PM UTC 24 |
Sep 01 02:56:00 PM UTC 24 |
1152537129 ps |
| T532 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/21.spi_device_upload.3614258828 |
|
|
Sep 01 02:55:48 PM UTC 24 |
Sep 01 02:56:01 PM UTC 24 |
1122590369 ps |
| T282 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/18.spi_device_flash_all.4122224931 |
|
|
Sep 01 02:54:38 PM UTC 24 |
Sep 01 02:56:07 PM UTC 24 |
8573687330 ps |
| T533 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/21.spi_device_read_buffer_direct.1155090858 |
|
|
Sep 01 02:55:58 PM UTC 24 |
Sep 01 02:56:09 PM UTC 24 |
2489469550 ps |
| T534 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/20.spi_device_mailbox.1264874784 |
|
|
Sep 01 02:55:20 PM UTC 24 |
Sep 01 02:56:10 PM UTC 24 |
9761677911 ps |
| T535 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/21.spi_device_flash_mode.1868531890 |
|
|
Sep 01 02:55:57 PM UTC 24 |
Sep 01 02:56:11 PM UTC 24 |
519095659 ps |
| T536 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/21.spi_device_alert_test.299900482 |
|
|
Sep 01 02:56:11 PM UTC 24 |
Sep 01 02:56:13 PM UTC 24 |
23348507 ps |
| T537 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/22.spi_device_csb_read.2858960665 |
|
|
Sep 01 02:56:12 PM UTC 24 |
Sep 01 02:56:15 PM UTC 24 |
20613719 ps |
| T538 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/21.spi_device_tpm_all.3010356561 |
|
|
Sep 01 02:55:38 PM UTC 24 |
Sep 01 02:56:17 PM UTC 24 |
5449643504 ps |
| T539 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/22.spi_device_tpm_read_hw_reg.122677693 |
|
|
Sep 01 02:56:14 PM UTC 24 |
Sep 01 02:56:18 PM UTC 24 |
90037974 ps |
| T540 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/22.spi_device_tpm_sts_read.754708310 |
|
|
Sep 01 02:56:19 PM UTC 24 |
Sep 01 02:56:21 PM UTC 24 |
30113518 ps |
| T541 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/22.spi_device_tpm_rw.1633732124 |
|
|
Sep 01 02:56:20 PM UTC 24 |
Sep 01 02:56:22 PM UTC 24 |
61843804 ps |
| T231 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/6.spi_device_flash_and_tpm.2965458465 |
|
|
Sep 01 02:48:24 PM UTC 24 |
Sep 01 02:56:24 PM UTC 24 |
373819907884 ps |
| T542 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/21.spi_device_flash_and_tpm_min_idle.4262174847 |
|
|
Sep 01 02:56:08 PM UTC 24 |
Sep 01 02:56:27 PM UTC 24 |
1521539589 ps |
| T543 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/21.spi_device_pass_cmd_filtering.4211521002 |
|
|
Sep 01 02:55:42 PM UTC 24 |
Sep 01 02:56:31 PM UTC 24 |
18518662387 ps |
| T360 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/22.spi_device_pass_addr_payload_swap.2067613381 |
|
|
Sep 01 02:56:23 PM UTC 24 |
Sep 01 02:56:31 PM UTC 24 |
712519642 ps |
| T247 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/16.spi_device_flash_mode_ignore_cmds.3363670062 |
|
|
Sep 01 02:53:39 PM UTC 24 |
Sep 01 02:56:35 PM UTC 24 |
14803353309 ps |
| T544 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/14.spi_device_flash_and_tpm.164563526 |
|
|
Sep 01 02:52:34 PM UTC 24 |
Sep 01 02:56:35 PM UTC 24 |
28476443048 ps |
| T286 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/22.spi_device_cfg_cmd.2510284156 |
|
|
Sep 01 02:56:32 PM UTC 24 |
Sep 01 02:56:42 PM UTC 24 |
641842688 ps |
| T243 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/21.spi_device_mailbox.3450351585 |
|
|
Sep 01 02:55:46 PM UTC 24 |
Sep 01 02:56:42 PM UTC 24 |
20400156124 ps |
| T545 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/22.spi_device_flash_all.1610590460 |
|
|
Sep 01 02:56:43 PM UTC 24 |
Sep 01 02:56:45 PM UTC 24 |
227822846 ps |
| T546 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/22.spi_device_intercept.3207190774 |
|
|
Sep 01 02:56:25 PM UTC 24 |
Sep 01 02:56:45 PM UTC 24 |
3160224577 ps |
| T547 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/22.spi_device_flash_mode.289001951 |
|
|
Sep 01 02:56:36 PM UTC 24 |
Sep 01 02:56:47 PM UTC 24 |
2271605911 ps |
| T548 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/22.spi_device_tpm_all.2476087032 |
|
|
Sep 01 02:56:15 PM UTC 24 |
Sep 01 02:56:49 PM UTC 24 |
5760509752 ps |
| T549 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/22.spi_device_upload.3261805587 |
|
|
Sep 01 02:56:31 PM UTC 24 |
Sep 01 02:56:50 PM UTC 24 |
1168286650 ps |
| T550 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/22.spi_device_stress_all.1030996559 |
|
|
Sep 01 02:56:48 PM UTC 24 |
Sep 01 02:56:51 PM UTC 24 |
46137573 ps |
| T551 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/22.spi_device_alert_test.2374887893 |
|
|
Sep 01 02:56:50 PM UTC 24 |
Sep 01 02:56:53 PM UTC 24 |
21972515 ps |
| T552 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/23.spi_device_csb_read.3752961218 |
|
|
Sep 01 02:56:50 PM UTC 24 |
Sep 01 02:56:53 PM UTC 24 |
19591993 ps |
| T330 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/4.spi_device_flash_mode_ignore_cmds.3757222160 |
|
|
Sep 01 02:47:33 PM UTC 24 |
Sep 01 02:56:53 PM UTC 24 |
213475455976 ps |
| T553 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/23.spi_device_tpm_sts_read.1949133016 |
|
|
Sep 01 02:56:54 PM UTC 24 |
Sep 01 02:56:56 PM UTC 24 |
15084501 ps |
| T554 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/23.spi_device_tpm_all.294753462 |
|
|
Sep 01 02:56:54 PM UTC 24 |
Sep 01 02:56:56 PM UTC 24 |
31378555 ps |
| T555 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/21.spi_device_flash_mode_ignore_cmds.3789373230 |
|
|
Sep 01 02:55:57 PM UTC 24 |
Sep 01 02:56:57 PM UTC 24 |
4783243077 ps |
| T556 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/19.spi_device_flash_all.3627717936 |
|
|
Sep 01 02:55:06 PM UTC 24 |
Sep 01 02:56:57 PM UTC 24 |
10265639979 ps |
| T557 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/23.spi_device_tpm_rw.130046420 |
|
|
Sep 01 02:56:54 PM UTC 24 |
Sep 01 02:56:57 PM UTC 24 |
56621688 ps |
| T150 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/17.spi_device_stress_all.965849428 |
|
|
Sep 01 02:54:17 PM UTC 24 |
Sep 01 02:57:01 PM UTC 24 |
35276150174 ps |
| T151 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/1.spi_device_stress_all.971232676 |
|
|
Sep 01 02:46:15 PM UTC 24 |
Sep 01 02:57:03 PM UTC 24 |
91686787985 ps |
| T152 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/23.spi_device_upload.3941883350 |
|
|
Sep 01 02:56:58 PM UTC 24 |
Sep 01 02:57:03 PM UTC 24 |
80540453 ps |
| T153 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/22.spi_device_read_buffer_direct.744315088 |
|
|
Sep 01 02:56:43 PM UTC 24 |
Sep 01 02:57:04 PM UTC 24 |
5545116380 ps |
| T154 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/23.spi_device_pass_cmd_filtering.1572114619 |
|
|
Sep 01 02:56:57 PM UTC 24 |
Sep 01 02:57:04 PM UTC 24 |
304112566 ps |
| T155 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/21.spi_device_stress_all.3063946038 |
|
|
Sep 01 02:56:10 PM UTC 24 |
Sep 01 02:57:06 PM UTC 24 |
10586749386 ps |
| T156 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/18.spi_device_flash_mode_ignore_cmds.711373890 |
|
|
Sep 01 02:54:34 PM UTC 24 |
Sep 01 02:57:07 PM UTC 24 |
10379363406 ps |
| T157 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/23.spi_device_read_buffer_direct.2591529928 |
|
|
Sep 01 02:57:04 PM UTC 24 |
Sep 01 02:57:10 PM UTC 24 |
313946830 ps |
| T158 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/23.spi_device_cfg_cmd.3642294767 |
|
|
Sep 01 02:57:01 PM UTC 24 |
Sep 01 02:57:11 PM UTC 24 |
2052640717 ps |
| T159 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/14.spi_device_flash_and_tpm_min_idle.151415179 |
|
|
Sep 01 02:52:34 PM UTC 24 |
Sep 01 02:57:11 PM UTC 24 |
72532855740 ps |
| T558 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/23.spi_device_alert_test.3647496895 |
|
|
Sep 01 02:57:10 PM UTC 24 |
Sep 01 02:57:12 PM UTC 24 |
15744507 ps |
| T224 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/20.spi_device_flash_mode_ignore_cmds.2836088430 |
|
|
Sep 01 02:55:28 PM UTC 24 |
Sep 01 02:57:13 PM UTC 24 |
26386543885 ps |
| T266 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/17.spi_device_flash_and_tpm.891296700 |
|
|
Sep 01 02:54:13 PM UTC 24 |
Sep 01 02:57:13 PM UTC 24 |
28400761330 ps |
| T559 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/24.spi_device_csb_read.1332623879 |
|
|
Sep 01 02:57:11 PM UTC 24 |
Sep 01 02:57:13 PM UTC 24 |
15143850 ps |
| T560 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/23.spi_device_pass_addr_payload_swap.1631357121 |
|
|
Sep 01 02:56:57 PM UTC 24 |
Sep 01 02:57:15 PM UTC 24 |
5717859891 ps |
| T561 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/24.spi_device_tpm_sts_read.522874766 |
|
|
Sep 01 02:57:12 PM UTC 24 |
Sep 01 02:57:15 PM UTC 24 |
120413991 ps |
| T374 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/23.spi_device_flash_mode.1978919746 |
|
|
Sep 01 02:57:02 PM UTC 24 |
Sep 01 02:57:15 PM UTC 24 |
338494458 ps |
| T562 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/24.spi_device_tpm_rw.2702309786 |
|
|
Sep 01 02:57:14 PM UTC 24 |
Sep 01 02:57:16 PM UTC 24 |
24965778 ps |
| T180 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/12.spi_device_stress_all.3999568209 |
|
|
Sep 01 02:51:32 PM UTC 24 |
Sep 01 02:57:17 PM UTC 24 |
19670632657 ps |
| T563 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/23.spi_device_tpm_read_hw_reg.4105009171 |
|
|
Sep 01 02:56:52 PM UTC 24 |
Sep 01 02:57:18 PM UTC 24 |
5975328843 ps |
| T564 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/24.spi_device_pass_addr_payload_swap.3575768360 |
|
|
Sep 01 02:57:14 PM UTC 24 |
Sep 01 02:57:18 PM UTC 24 |
31760208 ps |
| T288 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/23.spi_device_intercept.2989207188 |
|
|
Sep 01 02:56:58 PM UTC 24 |
Sep 01 02:57:19 PM UTC 24 |
5118999171 ps |
| T565 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/24.spi_device_tpm_read_hw_reg.2788432876 |
|
|
Sep 01 02:57:12 PM UTC 24 |
Sep 01 02:57:22 PM UTC 24 |
2193063649 ps |
| T566 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/24.spi_device_flash_mode.111093590 |
|
|
Sep 01 02:57:18 PM UTC 24 |
Sep 01 02:57:23 PM UTC 24 |
78219929 ps |
| T337 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/22.spi_device_mailbox.3445599340 |
|
|
Sep 01 02:56:28 PM UTC 24 |
Sep 01 02:57:23 PM UTC 24 |
6193813369 ps |
| T567 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/24.spi_device_cfg_cmd.2813703960 |
|
|
Sep 01 02:57:18 PM UTC 24 |
Sep 01 02:57:24 PM UTC 24 |
73255107 ps |
| T568 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/22.spi_device_pass_cmd_filtering.4083070997 |
|
|
Sep 01 02:56:22 PM UTC 24 |
Sep 01 02:57:24 PM UTC 24 |
23431569479 ps |
| T569 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/24.spi_device_alert_test.2139518612 |
|
|
Sep 01 02:57:25 PM UTC 24 |
Sep 01 02:57:27 PM UTC 24 |
56081807 ps |
| T570 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/25.spi_device_csb_read.4110517926 |
|
|
Sep 01 02:57:25 PM UTC 24 |
Sep 01 02:57:27 PM UTC 24 |
23704908 ps |
| T571 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/24.spi_device_stress_all.1611304657 |
|
|
Sep 01 02:57:25 PM UTC 24 |
Sep 01 02:57:27 PM UTC 24 |
343863809 ps |
| T572 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/24.spi_device_upload.3146717794 |
|
|
Sep 01 02:57:16 PM UTC 24 |
Sep 01 02:57:31 PM UTC 24 |
1263189226 ps |
| T573 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/25.spi_device_tpm_sts_read.3222535157 |
|
|
Sep 01 02:57:28 PM UTC 24 |
Sep 01 02:57:31 PM UTC 24 |
262221499 ps |
| T574 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/24.spi_device_pass_cmd_filtering.3478617902 |
|
|
Sep 01 02:57:14 PM UTC 24 |
Sep 01 02:57:31 PM UTC 24 |
4319839539 ps |
| T575 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/24.spi_device_intercept.843793414 |
|
|
Sep 01 02:57:16 PM UTC 24 |
Sep 01 02:57:34 PM UTC 24 |
1877101147 ps |
| T576 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/25.spi_device_tpm_rw.2912232060 |
|
|
Sep 01 02:57:32 PM UTC 24 |
Sep 01 02:57:34 PM UTC 24 |
23305401 ps |
| T577 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/25.spi_device_pass_cmd_filtering.2835946018 |
|
|
Sep 01 02:57:32 PM UTC 24 |
Sep 01 02:57:35 PM UTC 24 |
202874275 ps |
| T578 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/24.spi_device_read_buffer_direct.2564922917 |
|
|
Sep 01 02:57:19 PM UTC 24 |
Sep 01 02:57:36 PM UTC 24 |
10534976607 ps |
| T310 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/25.spi_device_cfg_cmd.3711734585 |
|
|
Sep 01 02:57:38 PM UTC 24 |
Sep 01 02:57:42 PM UTC 24 |
78002639 ps |
| T318 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/25.spi_device_upload.1413200330 |
|
|
Sep 01 02:57:36 PM UTC 24 |
Sep 01 02:57:44 PM UTC 24 |
203037915 ps |
| T579 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/25.spi_device_tpm_all.509449356 |
|
|
Sep 01 02:57:28 PM UTC 24 |
Sep 01 02:57:44 PM UTC 24 |
4588937898 ps |
| T580 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/25.spi_device_pass_addr_payload_swap.1174103705 |
|
|
Sep 01 02:57:32 PM UTC 24 |
Sep 01 02:57:45 PM UTC 24 |
7500843112 ps |
| T581 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/25.spi_device_tpm_read_hw_reg.768950925 |
|
|
Sep 01 02:57:28 PM UTC 24 |
Sep 01 02:57:46 PM UTC 24 |
2494556878 ps |
| T327 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/22.spi_device_flash_mode_ignore_cmds.4137307844 |
|
|
Sep 01 02:56:36 PM UTC 24 |
Sep 01 02:57:53 PM UTC 24 |
3243203163 ps |
| T582 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/24.spi_device_tpm_all.665641297 |
|
|
Sep 01 02:57:12 PM UTC 24 |
Sep 01 02:57:53 PM UTC 24 |
20511709975 ps |
| T583 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/25.spi_device_intercept.378463609 |
|
|
Sep 01 02:57:35 PM UTC 24 |
Sep 01 02:57:54 PM UTC 24 |
16557528627 ps |
| T584 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/19.spi_device_flash_and_tpm_min_idle.1426207330 |
|
|
Sep 01 02:55:08 PM UTC 24 |
Sep 01 02:57:56 PM UTC 24 |
26516348665 ps |
| T585 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/25.spi_device_alert_test.4155356115 |
|
|
Sep 01 02:57:54 PM UTC 24 |
Sep 01 02:57:56 PM UTC 24 |
11856289 ps |
| T586 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/26.spi_device_csb_read.3796701565 |
|
|
Sep 01 02:57:54 PM UTC 24 |
Sep 01 02:57:56 PM UTC 24 |
67188918 ps |
| T587 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/25.spi_device_read_buffer_direct.2367277062 |
|
|
Sep 01 02:57:45 PM UTC 24 |
Sep 01 02:57:57 PM UTC 24 |
612448356 ps |
| T588 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/24.spi_device_flash_and_tpm_min_idle.1510477432 |
|
|
Sep 01 02:57:23 PM UTC 24 |
Sep 01 02:57:57 PM UTC 24 |
1414100644 ps |
| T394 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/21.spi_device_flash_and_tpm.3732534665 |
|
|
Sep 01 02:56:02 PM UTC 24 |
Sep 01 02:57:59 PM UTC 24 |
37937697417 ps |
| T589 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/26.spi_device_tpm_rw.1139862184 |
|
|
Sep 01 02:57:57 PM UTC 24 |
Sep 01 02:57:59 PM UTC 24 |
115593280 ps |
| T590 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/26.spi_device_tpm_sts_read.3006658566 |
|
|
Sep 01 02:57:57 PM UTC 24 |
Sep 01 02:58:00 PM UTC 24 |
186557284 ps |
| T338 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/25.spi_device_mailbox.3812669406 |
|
|
Sep 01 02:57:35 PM UTC 24 |
Sep 01 02:58:01 PM UTC 24 |
610868339 ps |
| T181 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/20.spi_device_stress_all.2553269196 |
|
|
Sep 01 02:55:33 PM UTC 24 |
Sep 01 02:58:02 PM UTC 24 |
15439778646 ps |
| T591 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/26.spi_device_tpm_read_hw_reg.1084084092 |
|
|
Sep 01 02:57:55 PM UTC 24 |
Sep 01 02:58:04 PM UTC 24 |
562085210 ps |
| T592 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/23.spi_device_mailbox.951060035 |
|
|
Sep 01 02:56:58 PM UTC 24 |
Sep 01 02:58:05 PM UTC 24 |
28983998306 ps |
| T593 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/26.spi_device_intercept.2201980082 |
|
|
Sep 01 02:58:00 PM UTC 24 |
Sep 01 02:58:05 PM UTC 24 |
133666688 ps |
| T594 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/26.spi_device_upload.696258466 |
|
|
Sep 01 02:58:01 PM UTC 24 |
Sep 01 02:58:07 PM UTC 24 |
2612965515 ps |
| T595 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/26.spi_device_flash_mode_ignore_cmds.1764356810 |
|
|
Sep 01 02:58:05 PM UTC 24 |
Sep 01 02:58:07 PM UTC 24 |
34940581 ps |
| T596 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/21.spi_device_flash_all.2814718989 |
|
|
Sep 01 02:56:01 PM UTC 24 |
Sep 01 02:58:07 PM UTC 24 |
23097160905 ps |
| T597 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/26.spi_device_pass_addr_payload_swap.4048434558 |
|
|
Sep 01 02:57:59 PM UTC 24 |
Sep 01 02:58:09 PM UTC 24 |
284138589 ps |
| T598 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/22.spi_device_flash_and_tpm_min_idle.2640784069 |
|
|
Sep 01 02:56:46 PM UTC 24 |
Sep 01 02:58:10 PM UTC 24 |
10969558552 ps |
| T599 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/26.spi_device_read_buffer_direct.1173854318 |
|
|
Sep 01 02:58:06 PM UTC 24 |
Sep 01 02:58:12 PM UTC 24 |
583733890 ps |
| T600 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/20.spi_device_flash_and_tpm_min_idle.1981857107 |
|
|
Sep 01 02:55:33 PM UTC 24 |
Sep 01 02:58:12 PM UTC 24 |
52476549933 ps |
| T601 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/26.spi_device_alert_test.3224635399 |
|
|
Sep 01 02:58:11 PM UTC 24 |
Sep 01 02:58:13 PM UTC 24 |
48529461 ps |
| T602 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/27.spi_device_csb_read.3035167919 |
|
|
Sep 01 02:58:11 PM UTC 24 |
Sep 01 02:58:13 PM UTC 24 |
22687458 ps |
| T603 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/26.spi_device_cfg_cmd.3657934004 |
|
|
Sep 01 02:58:01 PM UTC 24 |
Sep 01 02:58:15 PM UTC 24 |
1825779765 ps |
| T604 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/26.spi_device_mailbox.1279543164 |
|
|
Sep 01 02:58:00 PM UTC 24 |
Sep 01 02:58:15 PM UTC 24 |
621705328 ps |
| T605 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/27.spi_device_tpm_rw.3311903532 |
|
|
Sep 01 02:58:14 PM UTC 24 |
Sep 01 02:58:16 PM UTC 24 |
26001013 ps |
| T606 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/19.spi_device_flash_mode_ignore_cmds.1891695386 |
|
|
Sep 01 02:55:04 PM UTC 24 |
Sep 01 02:58:16 PM UTC 24 |
265811879264 ps |
| T607 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/27.spi_device_tpm_sts_read.1056111407 |
|
|
Sep 01 02:58:14 PM UTC 24 |
Sep 01 02:58:16 PM UTC 24 |
34074800 ps |
| T608 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/25.spi_device_flash_all.1699794223 |
|
|
Sep 01 02:57:46 PM UTC 24 |
Sep 01 02:58:17 PM UTC 24 |
1187550966 ps |
| T609 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/27.spi_device_tpm_read_hw_reg.396758052 |
|
|
Sep 01 02:58:13 PM UTC 24 |
Sep 01 02:58:20 PM UTC 24 |
648225037 ps |
| T610 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/23.spi_device_flash_and_tpm.524120592 |
|
|
Sep 01 02:57:05 PM UTC 24 |
Sep 01 02:58:23 PM UTC 24 |
22263909426 ps |
| T611 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/26.spi_device_flash_mode.1318801645 |
|
|
Sep 01 02:58:03 PM UTC 24 |
Sep 01 02:58:23 PM UTC 24 |
1143556745 ps |
| T612 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/27.spi_device_cfg_cmd.275547568 |
|
|
Sep 01 02:58:18 PM UTC 24 |
Sep 01 02:58:24 PM UTC 24 |
224106050 ps |
| T613 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/27.spi_device_tpm_all.1709068465 |
|
|
Sep 01 02:58:13 PM UTC 24 |
Sep 01 02:58:25 PM UTC 24 |
1735187617 ps |
| T294 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/27.spi_device_pass_cmd_filtering.628795730 |
|
|
Sep 01 02:58:16 PM UTC 24 |
Sep 01 02:58:25 PM UTC 24 |
423501611 ps |
| T614 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/25.spi_device_flash_mode.434129686 |
|
|
Sep 01 02:57:44 PM UTC 24 |
Sep 01 02:58:26 PM UTC 24 |
8806418742 ps |
| T615 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/27.spi_device_intercept.3083938319 |
|
|
Sep 01 02:58:17 PM UTC 24 |
Sep 01 02:58:26 PM UTC 24 |
634421969 ps |
| T616 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/27.spi_device_alert_test.3103180482 |
|
|
Sep 01 02:58:26 PM UTC 24 |
Sep 01 02:58:29 PM UTC 24 |
22609521 ps |
| T617 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/28.spi_device_csb_read.2821481195 |
|
|
Sep 01 02:58:30 PM UTC 24 |
Sep 01 02:58:32 PM UTC 24 |
15930510 ps |
| T328 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/27.spi_device_pass_addr_payload_swap.2129259140 |
|
|
Sep 01 02:58:16 PM UTC 24 |
Sep 01 02:58:33 PM UTC 24 |
944667440 ps |
| T618 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/27.spi_device_read_buffer_direct.2490768622 |
|
|
Sep 01 02:58:24 PM UTC 24 |
Sep 01 02:58:34 PM UTC 24 |
635447608 ps |
| T619 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/26.spi_device_tpm_all.101567593 |
|
|
Sep 01 02:57:56 PM UTC 24 |
Sep 01 02:58:34 PM UTC 24 |
10602442737 ps |
| T620 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/28.spi_device_tpm_sts_read.3646268457 |
|
|
Sep 01 02:58:34 PM UTC 24 |
Sep 01 02:58:36 PM UTC 24 |
235965639 ps |
| T621 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/18.spi_device_flash_and_tpm_min_idle.4052886825 |
|
|
Sep 01 02:54:39 PM UTC 24 |
Sep 01 02:58:37 PM UTC 24 |
45412107039 ps |
| T395 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/12.spi_device_flash_and_tpm_min_idle.2800060828 |
|
|
Sep 01 02:51:32 PM UTC 24 |
Sep 01 02:58:39 PM UTC 24 |
50069936879 ps |
| T622 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/28.spi_device_pass_cmd_filtering.3698001025 |
|
|
Sep 01 02:58:35 PM UTC 24 |
Sep 01 02:58:39 PM UTC 24 |
34996742 ps |
| T623 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/28.spi_device_tpm_rw.3211839336 |
|
|
Sep 01 02:58:35 PM UTC 24 |
Sep 01 02:58:40 PM UTC 24 |
220911505 ps |