| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
| 96.04 | 98.38 | 93.99 | 98.62 | 89.36 | 97.19 | 95.45 | 99.26 |
| T146 | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/2.spi_device_csr_bit_bash.4044489692 | Sep 01 02:44:58 PM UTC 24 | Sep 01 02:45:12 PM UTC 24 | 1082801338 ps | ||
| T127 | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/4.spi_device_tl_errors.2003305126 | Sep 01 02:45:05 PM UTC 24 | Sep 01 02:45:12 PM UTC 24 | 1649861124 ps | ||
| T147 | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/4.spi_device_csr_rw.1018579437 | Sep 01 02:45:09 PM UTC 24 | Sep 01 02:45:14 PM UTC 24 | 142942679 ps | ||
| T1028 | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/4.spi_device_same_csr_outstanding.301750142 | Sep 01 02:45:11 PM UTC 24 | Sep 01 02:45:15 PM UTC 24 | 103695429 ps | ||
| T133 | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/4.spi_device_csr_mem_rw_with_rand_reset.1656882920 | Sep 01 02:45:11 PM UTC 24 | Sep 01 02:45:15 PM UTC 24 | 105695813 ps | ||
| T209 | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/1.spi_device_tl_intg_err.437053927 | Sep 01 02:44:51 PM UTC 24 | Sep 01 02:45:15 PM UTC 24 | 824718154 ps | ||
| T1029 | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/5.spi_device_intr_test.3238315435 | Sep 01 02:45:14 PM UTC 24 | Sep 01 02:45:17 PM UTC 24 | 23338028 ps | ||
| T172 | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/2.spi_device_tl_intg_err.2922239148 | Sep 01 02:44:54 PM UTC 24 | Sep 01 02:45:19 PM UTC 24 | 12627361913 ps | ||
| T131 | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/5.spi_device_tl_errors.4040299537 | Sep 01 02:45:13 PM UTC 24 | Sep 01 02:45:19 PM UTC 24 | 101956766 ps | ||
| T148 | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/5.spi_device_csr_rw.3556967713 | Sep 01 02:45:16 PM UTC 24 | Sep 01 02:45:20 PM UTC 24 | 301448731 ps | ||
| T1030 | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/6.spi_device_intr_test.3694557558 | Sep 01 02:45:18 PM UTC 24 | Sep 01 02:45:20 PM UTC 24 | 55430229 ps | ||
| T177 | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/6.spi_device_tl_errors.2534556034 | Sep 01 02:45:17 PM UTC 24 | Sep 01 02:45:20 PM UTC 24 | 414075195 ps | ||
| T1031 | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/3.spi_device_csr_bit_bash.308859551 | Sep 01 02:45:03 PM UTC 24 | Sep 01 02:45:21 PM UTC 24 | 638638621 ps | ||
| T149 | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/0.spi_device_csr_aliasing.1021305903 | Sep 01 02:44:50 PM UTC 24 | Sep 01 02:45:21 PM UTC 24 | 310708019 ps | ||
| T1032 | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/1.spi_device_csr_aliasing.740943897 | Sep 01 02:44:53 PM UTC 24 | Sep 01 02:45:21 PM UTC 24 | 949661280 ps | ||
| T1033 | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/5.spi_device_csr_mem_rw_with_rand_reset.3140899952 | Sep 01 02:45:17 PM UTC 24 | Sep 01 02:45:21 PM UTC 24 | 139590463 ps | ||
| T1034 | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/5.spi_device_same_csr_outstanding.3718135346 | Sep 01 02:45:16 PM UTC 24 | Sep 01 02:45:21 PM UTC 24 | 165063393 ps | ||
| T1035 | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/6.spi_device_csr_rw.3592264328 | Sep 01 02:45:20 PM UTC 24 | Sep 01 02:45:24 PM UTC 24 | 62513824 ps | ||
| T1036 | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/7.spi_device_intr_test.1037062541 | Sep 01 02:45:22 PM UTC 24 | Sep 01 02:45:24 PM UTC 24 | 14857758 ps | ||
| T210 | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/4.spi_device_tl_intg_err.628065238 | Sep 01 02:45:05 PM UTC 24 | Sep 01 02:45:25 PM UTC 24 | 2474958486 ps | ||
| T173 | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/5.spi_device_tl_intg_err.2261215805 | Sep 01 02:45:13 PM UTC 24 | Sep 01 02:45:26 PM UTC 24 | 380682670 ps | ||
| T1037 | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/7.spi_device_same_csr_outstanding.3959552247 | Sep 01 02:45:22 PM UTC 24 | Sep 01 02:45:26 PM UTC 24 | 217348934 ps | ||
| T1038 | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/6.spi_device_csr_mem_rw_with_rand_reset.3063509569 | Sep 01 02:45:21 PM UTC 24 | Sep 01 02:45:27 PM UTC 24 | 655810716 ps | ||
| T174 | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/6.spi_device_same_csr_outstanding.700794197 | Sep 01 02:45:20 PM UTC 24 | Sep 01 02:45:27 PM UTC 24 | 765433715 ps | ||
| T128 | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/8.spi_device_tl_errors.3569486088 | Sep 01 02:45:23 PM UTC 24 | Sep 01 02:45:27 PM UTC 24 | 64639121 ps | ||
| T175 | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/6.spi_device_tl_intg_err.1875727906 | Sep 01 02:45:17 PM UTC 24 | Sep 01 02:45:27 PM UTC 24 | 360440447 ps | ||
| T124 | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/7.spi_device_tl_errors.3434677732 | Sep 01 02:45:21 PM UTC 24 | Sep 01 02:45:28 PM UTC 24 | 161956242 ps | ||
| T1039 | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/1.spi_device_csr_bit_bash.1165102152 | Sep 01 02:44:53 PM UTC 24 | Sep 01 02:45:28 PM UTC 24 | 1397239046 ps | ||
| T1040 | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/8.spi_device_intr_test.3075033319 | Sep 01 02:45:26 PM UTC 24 | Sep 01 02:45:28 PM UTC 24 | 87966213 ps | ||
| T176 | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/2.spi_device_csr_aliasing.3739537346 | Sep 01 02:44:59 PM UTC 24 | Sep 01 02:45:30 PM UTC 24 | 4627108064 ps | ||
| T1041 | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/9.spi_device_intr_test.1610603059 | Sep 01 02:45:28 PM UTC 24 | Sep 01 02:45:30 PM UTC 24 | 39813400 ps | ||
| T1042 | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/8.spi_device_csr_rw.79427414 | Sep 01 02:45:26 PM UTC 24 | Sep 01 02:45:30 PM UTC 24 | 35128334 ps | ||
| T1043 | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/8.spi_device_same_csr_outstanding.3420065670 | Sep 01 02:45:27 PM UTC 24 | Sep 01 02:45:30 PM UTC 24 | 94906245 ps | ||
| T1044 | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/10.spi_device_intr_test.1911789755 | Sep 01 02:45:28 PM UTC 24 | Sep 01 02:45:30 PM UTC 24 | 41678492 ps | ||
| T1045 | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/9.spi_device_csr_mem_rw_with_rand_reset.2216140865 | Sep 01 02:45:28 PM UTC 24 | Sep 01 02:45:32 PM UTC 24 | 25542622 ps | ||
| T178 | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/8.spi_device_csr_mem_rw_with_rand_reset.2871986926 | Sep 01 02:45:27 PM UTC 24 | Sep 01 02:45:32 PM UTC 24 | 106667940 ps | ||
| T1046 | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/10.spi_device_csr_rw.1593919575 | Sep 01 02:45:28 PM UTC 24 | Sep 01 02:45:32 PM UTC 24 | 30601361 ps | ||
| T1047 | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/9.spi_device_same_csr_outstanding.4264573406 | Sep 01 02:45:28 PM UTC 24 | Sep 01 02:45:33 PM UTC 24 | 46151699 ps | ||
| T1048 | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/11.spi_device_intr_test.1882149280 | Sep 01 02:45:32 PM UTC 24 | Sep 01 02:45:34 PM UTC 24 | 150931683 ps | ||
| T1049 | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/10.spi_device_csr_mem_rw_with_rand_reset.4047914105 | Sep 01 02:45:31 PM UTC 24 | Sep 01 02:45:34 PM UTC 24 | 48441563 ps | ||
| T1050 | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/3.spi_device_csr_aliasing.681603968 | Sep 01 02:45:03 PM UTC 24 | Sep 01 02:45:35 PM UTC 24 | 5071790456 ps | ||
| T1051 | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/11.spi_device_csr_rw.2552002378 | Sep 01 02:45:32 PM UTC 24 | Sep 01 02:45:35 PM UTC 24 | 182051244 ps | ||
| T132 | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/10.spi_device_tl_errors.1916768083 | Sep 01 02:45:28 PM UTC 24 | Sep 01 02:45:35 PM UTC 24 | 91116265 ps | ||
| T1052 | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/10.spi_device_same_csr_outstanding.1349067794 | Sep 01 02:45:30 PM UTC 24 | Sep 01 02:45:35 PM UTC 24 | 131713891 ps | ||
| T1053 | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/12.spi_device_intr_test.3890380524 | Sep 01 02:45:33 PM UTC 24 | Sep 01 02:45:35 PM UTC 24 | 15605162 ps | ||
| T125 | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/11.spi_device_tl_errors.643661665 | Sep 01 02:45:31 PM UTC 24 | Sep 01 02:45:35 PM UTC 24 | 70240647 ps | ||
| T1054 | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/12.spi_device_csr_rw.3724652122 | Sep 01 02:45:33 PM UTC 24 | Sep 01 02:45:36 PM UTC 24 | 38260197 ps | ||
| T215 | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/10.spi_device_tl_intg_err.3522812677 | Sep 01 02:45:28 PM UTC 24 | Sep 01 02:45:37 PM UTC 24 | 365115027 ps | ||
| T1055 | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/11.spi_device_same_csr_outstanding.727533164 | Sep 01 02:45:32 PM UTC 24 | Sep 01 02:45:37 PM UTC 24 | 328679364 ps | ||
| T1056 | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/4.spi_device_csr_bit_bash.3827098898 | Sep 01 02:45:11 PM UTC 24 | Sep 01 02:45:38 PM UTC 24 | 1258116455 ps | ||
| T1057 | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/13.spi_device_intr_test.1763450082 | Sep 01 02:45:36 PM UTC 24 | Sep 01 02:45:38 PM UTC 24 | 15995417 ps | ||
| T1058 | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/11.spi_device_csr_mem_rw_with_rand_reset.3349620299 | Sep 01 02:45:33 PM UTC 24 | Sep 01 02:45:38 PM UTC 24 | 148507056 ps | ||
| T1059 | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/12.spi_device_same_csr_outstanding.3545434328 | Sep 01 02:45:34 PM UTC 24 | Sep 01 02:45:38 PM UTC 24 | 28205397 ps | ||
| T134 | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/12.spi_device_tl_errors.1145333640 | Sep 01 02:45:33 PM UTC 24 | Sep 01 02:45:39 PM UTC 24 | 134774410 ps | ||
| T1060 | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/14.spi_device_intr_test.2185404480 | Sep 01 02:45:37 PM UTC 24 | Sep 01 02:45:39 PM UTC 24 | 25339879 ps | ||
| T1061 | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/13.spi_device_csr_rw.4278286373 | Sep 01 02:45:36 PM UTC 24 | Sep 01 02:45:39 PM UTC 24 | 76125290 ps | ||
| T1062 | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/13.spi_device_same_csr_outstanding.3073001254 | Sep 01 02:45:36 PM UTC 24 | Sep 01 02:45:40 PM UTC 24 | 269013871 ps | ||
| T1063 | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/12.spi_device_csr_mem_rw_with_rand_reset.3983912662 | Sep 01 02:45:34 PM UTC 24 | Sep 01 02:45:41 PM UTC 24 | 157192228 ps | ||
| T1064 | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/14.spi_device_tl_errors.2137533516 | Sep 01 02:45:37 PM UTC 24 | Sep 01 02:45:41 PM UTC 24 | 172621254 ps | ||
| T1065 | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/15.spi_device_intr_test.2573936807 | Sep 01 02:45:39 PM UTC 24 | Sep 01 02:45:41 PM UTC 24 | 12599080 ps | ||
| T1066 | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/13.spi_device_csr_mem_rw_with_rand_reset.311434931 | Sep 01 02:45:37 PM UTC 24 | Sep 01 02:45:42 PM UTC 24 | 43634970 ps | ||
| T1067 | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/4.spi_device_csr_aliasing.1405724311 | Sep 01 02:45:11 PM UTC 24 | Sep 01 02:45:42 PM UTC 24 | 5639150499 ps | ||
| T1068 | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/14.spi_device_csr_mem_rw_with_rand_reset.1016008982 | Sep 01 02:45:38 PM UTC 24 | Sep 01 02:45:42 PM UTC 24 | 41226941 ps | ||
| T1069 | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/11.spi_device_tl_intg_err.3832153149 | Sep 01 02:45:32 PM UTC 24 | Sep 01 02:45:42 PM UTC 24 | 1453754548 ps | ||
| T1070 | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/14.spi_device_csr_rw.3274220923 | Sep 01 02:45:38 PM UTC 24 | Sep 01 02:45:43 PM UTC 24 | 355589880 ps | ||
| T1071 | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/12.spi_device_tl_intg_err.3516083068 | Sep 01 02:45:33 PM UTC 24 | Sep 01 02:45:43 PM UTC 24 | 109918860 ps | ||
| T1072 | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/13.spi_device_tl_errors.2671612099 | Sep 01 02:45:35 PM UTC 24 | Sep 01 02:45:44 PM UTC 24 | 1991986944 ps | ||
| T1073 | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/15.spi_device_csr_rw.503667128 | Sep 01 02:45:40 PM UTC 24 | Sep 01 02:45:44 PM UTC 24 | 71947555 ps | ||
| T1074 | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/15.spi_device_same_csr_outstanding.748322715 | Sep 01 02:45:40 PM UTC 24 | Sep 01 02:45:44 PM UTC 24 | 196957135 ps | ||
| T208 | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/8.spi_device_tl_intg_err.4083208709 | Sep 01 02:45:25 PM UTC 24 | Sep 01 02:45:44 PM UTC 24 | 792005796 ps | ||
| T1075 | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/14.spi_device_same_csr_outstanding.2423354519 | Sep 01 02:45:38 PM UTC 24 | Sep 01 02:45:45 PM UTC 24 | 832003408 ps | ||
| T1076 | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/15.spi_device_csr_mem_rw_with_rand_reset.1214984585 | Sep 01 02:45:40 PM UTC 24 | Sep 01 02:45:45 PM UTC 24 | 334539508 ps | ||
| T1077 | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/16.spi_device_intr_test.2970461930 | Sep 01 02:45:43 PM UTC 24 | Sep 01 02:45:45 PM UTC 24 | 29172113 ps | ||
| T1078 | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/16.spi_device_csr_rw.1425244987 | Sep 01 02:45:43 PM UTC 24 | Sep 01 02:45:46 PM UTC 24 | 59354453 ps | ||
| T1079 | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/17.spi_device_intr_test.2383750118 | Sep 01 02:45:44 PM UTC 24 | Sep 01 02:45:46 PM UTC 24 | 103679793 ps | ||
| T1080 | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/16.spi_device_tl_errors.848262188 | Sep 01 02:45:41 PM UTC 24 | Sep 01 02:45:47 PM UTC 24 | 189746393 ps | ||
| T1081 | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/16.spi_device_csr_mem_rw_with_rand_reset.205072868 | Sep 01 02:45:43 PM UTC 24 | Sep 01 02:45:48 PM UTC 24 | 70103642 ps | ||
| T1082 | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/17.spi_device_csr_rw.1253834104 | Sep 01 02:45:44 PM UTC 24 | Sep 01 02:45:48 PM UTC 24 | 119012997 ps | ||
| T1083 | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/15.spi_device_tl_errors.310296255 | Sep 01 02:45:39 PM UTC 24 | Sep 01 02:45:48 PM UTC 24 | 390398369 ps | ||
| T1084 | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/18.spi_device_intr_test.3465970014 | Sep 01 02:45:46 PM UTC 24 | Sep 01 02:45:49 PM UTC 24 | 42941899 ps | ||
| T1085 | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/17.spi_device_csr_mem_rw_with_rand_reset.3019343557 | Sep 01 02:45:45 PM UTC 24 | Sep 01 02:45:49 PM UTC 24 | 52448681 ps | ||
| T1086 | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/16.spi_device_same_csr_outstanding.2171597573 | Sep 01 02:45:43 PM UTC 24 | Sep 01 02:45:49 PM UTC 24 | 600529696 ps | ||
| T1087 | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/17.spi_device_same_csr_outstanding.1581565162 | Sep 01 02:45:44 PM UTC 24 | Sep 01 02:45:49 PM UTC 24 | 120198376 ps | ||
| T212 | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/14.spi_device_tl_intg_err.1408206312 | Sep 01 02:45:37 PM UTC 24 | Sep 01 02:45:50 PM UTC 24 | 324875788 ps | ||
| T1088 | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/17.spi_device_tl_errors.4294414283 | Sep 01 02:45:43 PM UTC 24 | Sep 01 02:45:50 PM UTC 24 | 713929745 ps | ||
| T1089 | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/18.spi_device_csr_rw.2985748485 | Sep 01 02:45:46 PM UTC 24 | Sep 01 02:45:51 PM UTC 24 | 158089149 ps | ||
| T1090 | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/19.spi_device_intr_test.2467991110 | Sep 01 02:45:49 PM UTC 24 | Sep 01 02:45:51 PM UTC 24 | 48180231 ps | ||
| T214 | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/15.spi_device_tl_intg_err.865664752 | Sep 01 02:45:39 PM UTC 24 | Sep 01 02:45:52 PM UTC 24 | 407603696 ps | ||
| T213 | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/9.spi_device_tl_intg_err.1133238391 | Sep 01 02:45:28 PM UTC 24 | Sep 01 02:45:52 PM UTC 24 | 790366800 ps | ||
| T1091 | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/19.spi_device_tl_errors.330733982 | Sep 01 02:45:48 PM UTC 24 | Sep 01 02:45:52 PM UTC 24 | 96529261 ps | ||
| T1092 | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/19.spi_device_csr_rw.3748051994 | Sep 01 02:45:49 PM UTC 24 | Sep 01 02:45:52 PM UTC 24 | 47679137 ps | ||
| T1093 | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/20.spi_device_intr_test.427795470 | Sep 01 02:45:50 PM UTC 24 | Sep 01 02:45:52 PM UTC 24 | 37466234 ps | ||
| T1094 | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/21.spi_device_intr_test.412201496 | Sep 01 02:45:50 PM UTC 24 | Sep 01 02:45:52 PM UTC 24 | 32081216 ps | ||
| T1095 | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/18.spi_device_same_csr_outstanding.3877438399 | Sep 01 02:45:47 PM UTC 24 | Sep 01 02:45:53 PM UTC 24 | 228501535 ps | ||
| T1096 | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/18.spi_device_tl_errors.1318157015 | Sep 01 02:45:45 PM UTC 24 | Sep 01 02:45:53 PM UTC 24 | 259974854 ps | ||
| T1097 | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/18.spi_device_csr_mem_rw_with_rand_reset.1422957127 | Sep 01 02:45:47 PM UTC 24 | Sep 01 02:45:53 PM UTC 24 | 127170617 ps | ||
| T1098 | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/22.spi_device_intr_test.2653772503 | Sep 01 02:45:51 PM UTC 24 | Sep 01 02:45:53 PM UTC 24 | 49027272 ps | ||
| T1099 | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/23.spi_device_intr_test.1603053260 | Sep 01 02:45:51 PM UTC 24 | Sep 01 02:45:53 PM UTC 24 | 30142431 ps | ||
| T1100 | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/25.spi_device_intr_test.2950715852 | Sep 01 02:45:51 PM UTC 24 | Sep 01 02:45:53 PM UTC 24 | 14181974 ps | ||
| T1101 | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/24.spi_device_intr_test.1622080906 | Sep 01 02:45:51 PM UTC 24 | Sep 01 02:45:54 PM UTC 24 | 27231185 ps | ||
| T1102 | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/19.spi_device_csr_mem_rw_with_rand_reset.3072428813 | Sep 01 02:45:50 PM UTC 24 | Sep 01 02:45:54 PM UTC 24 | 51964574 ps | ||
| T1103 | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/19.spi_device_same_csr_outstanding.1775290522 | Sep 01 02:45:49 PM UTC 24 | Sep 01 02:45:54 PM UTC 24 | 44143829 ps | ||
| T1104 | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/26.spi_device_intr_test.3359134173 | Sep 01 02:45:52 PM UTC 24 | Sep 01 02:45:55 PM UTC 24 | 31099583 ps | ||
| T1105 | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/27.spi_device_intr_test.1594989329 | Sep 01 02:45:52 PM UTC 24 | Sep 01 02:45:55 PM UTC 24 | 10367116 ps | ||
| T1106 | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/28.spi_device_intr_test.3083495369 | Sep 01 02:45:52 PM UTC 24 | Sep 01 02:45:55 PM UTC 24 | 54267638 ps | ||
| T1107 | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/30.spi_device_intr_test.151297951 | Sep 01 02:45:54 PM UTC 24 | Sep 01 02:45:56 PM UTC 24 | 12854689 ps | ||
| T1108 | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/29.spi_device_intr_test.2923248978 | Sep 01 02:45:54 PM UTC 24 | Sep 01 02:45:56 PM UTC 24 | 22092438 ps | ||
| T1109 | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/32.spi_device_intr_test.3704994346 | Sep 01 02:45:54 PM UTC 24 | Sep 01 02:45:56 PM UTC 24 | 37749224 ps | ||
| T1110 | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/33.spi_device_intr_test.3604522537 | Sep 01 02:45:54 PM UTC 24 | Sep 01 02:45:56 PM UTC 24 | 14283816 ps | ||
| T1111 | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/31.spi_device_intr_test.2466008318 | Sep 01 02:45:54 PM UTC 24 | Sep 01 02:45:56 PM UTC 24 | 15655867 ps | ||
| T1112 | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/35.spi_device_intr_test.3693502120 | Sep 01 02:45:54 PM UTC 24 | Sep 01 02:45:56 PM UTC 24 | 34153115 ps | ||
| T1113 | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/34.spi_device_intr_test.1540223166 | Sep 01 02:45:54 PM UTC 24 | Sep 01 02:45:56 PM UTC 24 | 13126979 ps | ||
| T1114 | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/36.spi_device_intr_test.3667176939 | Sep 01 02:45:55 PM UTC 24 | Sep 01 02:45:57 PM UTC 24 | 39533075 ps | ||
| T1115 | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/37.spi_device_intr_test.401348003 | Sep 01 02:45:55 PM UTC 24 | Sep 01 02:45:57 PM UTC 24 | 31532266 ps | ||
| T1116 | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/38.spi_device_intr_test.1015643940 | Sep 01 02:45:55 PM UTC 24 | Sep 01 02:45:57 PM UTC 24 | 12530487 ps | ||
| T1117 | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/41.spi_device_intr_test.182081263 | Sep 01 02:45:55 PM UTC 24 | Sep 01 02:45:57 PM UTC 24 | 58599310 ps | ||
| T1118 | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/39.spi_device_intr_test.2974049617 | Sep 01 02:45:55 PM UTC 24 | Sep 01 02:45:57 PM UTC 24 | 16645449 ps | ||
| T1119 | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/40.spi_device_intr_test.694667940 | Sep 01 02:45:55 PM UTC 24 | Sep 01 02:45:57 PM UTC 24 | 32814551 ps | ||
| T1120 | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/42.spi_device_intr_test.72869607 | Sep 01 02:45:55 PM UTC 24 | Sep 01 02:45:57 PM UTC 24 | 13451254 ps | ||
| T1121 | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/43.spi_device_intr_test.3874450070 | Sep 01 02:45:55 PM UTC 24 | Sep 01 02:45:58 PM UTC 24 | 74639644 ps | ||
| T1122 | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/44.spi_device_intr_test.2884646365 | Sep 01 02:45:55 PM UTC 24 | Sep 01 02:45:58 PM UTC 24 | 58907418 ps | ||
| T211 | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/16.spi_device_tl_intg_err.1448319004 | Sep 01 02:45:42 PM UTC 24 | Sep 01 02:45:58 PM UTC 24 | 698062962 ps | ||
| T1123 | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/13.spi_device_tl_intg_err.2988070319 | Sep 01 02:45:35 PM UTC 24 | Sep 01 02:45:58 PM UTC 24 | 8965963573 ps | ||
| T1124 | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/45.spi_device_intr_test.2354079969 | Sep 01 02:45:57 PM UTC 24 | Sep 01 02:45:59 PM UTC 24 | 12165963 ps | ||
| T1125 | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/19.spi_device_tl_intg_err.3825319297 | Sep 01 02:45:49 PM UTC 24 | Sep 01 02:45:59 PM UTC 24 | 2542827409 ps | ||
| T1126 | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/46.spi_device_intr_test.2551155666 | Sep 01 02:45:57 PM UTC 24 | Sep 01 02:45:59 PM UTC 24 | 41181688 ps | ||
| T1127 | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/47.spi_device_intr_test.3687401010 | Sep 01 02:45:57 PM UTC 24 | Sep 01 02:45:59 PM UTC 24 | 86189686 ps | ||
| T1128 | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/48.spi_device_intr_test.1511416527 | Sep 01 02:45:57 PM UTC 24 | Sep 01 02:45:59 PM UTC 24 | 31939831 ps | ||
| T1129 | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/49.spi_device_intr_test.3284412412 | Sep 01 02:45:57 PM UTC 24 | Sep 01 02:45:59 PM UTC 24 | 11237757 ps | ||
| T1130 | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/17.spi_device_tl_intg_err.3247596821 | Sep 01 02:45:43 PM UTC 24 | Sep 01 02:46:01 PM UTC 24 | 2328705839 ps | ||
| T1131 | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/18.spi_device_tl_intg_err.597387852 | Sep 01 02:45:45 PM UTC 24 | Sep 01 02:46:02 PM UTC 24 | 1722657303 ps |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/0.spi_device_upload.296832309 |
| Short name | T10 |
| Test name | |
| Test status | |
| Simulation time | 973286109 ps |
| CPU time | 4.88 seconds |
| Started | Sep 01 02:46:00 PM UTC 24 |
| Finished | Sep 01 02:46:06 PM UTC 24 |
| Peak memory | 234900 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=296832309 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/spi_d evice_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_upload.296832309 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/0.spi_device_upload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/1.spi_device_flash_and_tpm_min_idle.1450363895 |
| Short name | T49 |
| Test name | |
| Test status | |
| Simulation time | 3218750995 ps |
| CPU time | 69.18 seconds |
| Started | Sep 01 02:46:15 PM UTC 24 |
| Finished | Sep 01 02:47:26 PM UTC 24 |
| Peak memory | 267988 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1450363895 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_31/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_and_tpm_min_idle.1450363895 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/1.spi_device_flash_and_tpm_min_idle/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/0.spi_device_tpm_all.3535898173 |
| Short name | T13 |
| Test name | |
| Test status | |
| Simulation time | 2698729120 ps |
| CPU time | 10.54 seconds |
| Started | Sep 01 02:45:58 PM UTC 24 |
| Finished | Sep 01 02:46:10 PM UTC 24 |
| Peak memory | 227612 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3535898173 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_all.3535898173 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/0.spi_device_tpm_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/0.spi_device_stress_all.2188472031 |
| Short name | T36 |
| Test name | |
| Test status | |
| Simulation time | 61439424220 ps |
| CPU time | 269.42 seconds |
| Started | Sep 01 02:46:00 PM UTC 24 |
| Finished | Sep 01 02:50:33 PM UTC 24 |
| Peak memory | 284300 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2188472031 -assert nopostproc +UVM_ TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_stress_all.2188472031 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/0.spi_device_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/2.spi_device_flash_mode_ignore_cmds.662863083 |
| Short name | T63 |
| Test name | |
| Test status | |
| Simulation time | 2705441678 ps |
| CPU time | 72.57 seconds |
| Started | Sep 01 02:46:30 PM UTC 24 |
| Finished | Sep 01 02:47:45 PM UTC 24 |
| Peak memory | 261776 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=662863083 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_31/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_mode_ignore_cmds.662863083 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/2.spi_device_flash_mode_ignore_cmds/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/5.spi_device_stress_all.2714002774 |
| Short name | T179 |
| Test name | |
| Test status | |
| Simulation time | 18145757842 ps |
| CPU time | 340.4 seconds |
| Started | Sep 01 02:47:57 PM UTC 24 |
| Finished | Sep 01 02:53:42 PM UTC 24 |
| Peak memory | 290436 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2714002774 -assert nopostproc +UVM_ TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_stress_all.2714002774 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/5.spi_device_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/2.spi_device_tl_intg_err.2922239148 |
| Short name | T172 |
| Test name | |
| Test status | |
| Simulation time | 12627361913 ps |
| CPU time | 23.16 seconds |
| Started | Sep 01 02:44:54 PM UTC 24 |
| Finished | Sep 01 02:45:19 PM UTC 24 |
| Peak memory | 227320 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2922239148 -assert nopostproc + UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_tl_intg_err.2922239148 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/2.spi_device_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/0.spi_device_ram_cfg.1245827071 |
| Short name | T2 |
| Test name | |
| Test status | |
| Simulation time | 20928158 ps |
| CPU time | 1.15 seconds |
| Started | Sep 01 02:45:58 PM UTC 24 |
| Finished | Sep 01 02:46:00 PM UTC 24 |
| Peak memory | 225732 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1245827071 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_ram_cfg.1245827071 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/0.spi_device_ram_cfg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/2.spi_device_flash_and_tpm_min_idle.2090953992 |
| Short name | T48 |
| Test name | |
| Test status | |
| Simulation time | 6005348586 ps |
| CPU time | 47.78 seconds |
| Started | Sep 01 02:46:37 PM UTC 24 |
| Finished | Sep 01 02:47:26 PM UTC 24 |
| Peak memory | 247460 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2090953992 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_31/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_and_tpm_min_idle.2090953992 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/2.spi_device_flash_and_tpm_min_idle/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/0.spi_device_tl_errors.1422750187 |
| Short name | T117 |
| Test name | |
| Test status | |
| Simulation time | 406416053 ps |
| CPU time | 7.44 seconds |
| Started | Sep 01 02:44:49 PM UTC 24 |
| Finished | Sep 01 02:44:57 PM UTC 24 |
| Peak memory | 227180 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1422750187 -assert nopostproc +UVM_TESTNAME =spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_08_31/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_tl_errors.1422750187 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/0.spi_device_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/4.spi_device_stress_all.2494182469 |
| Short name | T38 |
| Test name | |
| Test status | |
| Simulation time | 15977431319 ps |
| CPU time | 319.31 seconds |
| Started | Sep 01 02:47:35 PM UTC 24 |
| Finished | Sep 01 02:53:00 PM UTC 24 |
| Peak memory | 294544 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2494182469 -assert nopostproc +UVM_ TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_stress_all.2494182469 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/4.spi_device_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/4.spi_device_flash_mode.2120769103 |
| Short name | T7 |
| Test name | |
| Test status | |
| Simulation time | 4457947589 ps |
| CPU time | 7.69 seconds |
| Started | Sep 01 02:47:32 PM UTC 24 |
| Finished | Sep 01 02:47:41 PM UTC 24 |
| Peak memory | 235152 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2120769103 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/ spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_mode.2120769103 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/4.spi_device_flash_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/4.spi_device_flash_and_tpm_min_idle.1201641319 |
| Short name | T201 |
| Test name | |
| Test status | |
| Simulation time | 45052015759 ps |
| CPU time | 234.82 seconds |
| Started | Sep 01 02:47:35 PM UTC 24 |
| Finished | Sep 01 02:51:34 PM UTC 24 |
| Peak memory | 276108 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1201641319 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_31/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_and_tpm_min_idle.1201641319 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/4.spi_device_flash_and_tpm_min_idle/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/6.spi_device_stress_all.1055994020 |
| Short name | T332 |
| Test name | |
| Test status | |
| Simulation time | 237806064447 ps |
| CPU time | 685.71 seconds |
| Started | Sep 01 02:48:26 PM UTC 24 |
| Finished | Sep 01 03:00:00 PM UTC 24 |
| Peak memory | 278176 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1055994020 -assert nopostproc +UVM_ TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_stress_all.1055994020 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/6.spi_device_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/0.spi_device_sec_cm.2456451374 |
| Short name | T6 |
| Test name | |
| Test status | |
| Simulation time | 458196741 ps |
| CPU time | 1.98 seconds |
| Started | Sep 01 02:46:00 PM UTC 24 |
| Finished | Sep 01 02:46:03 PM UTC 24 |
| Peak memory | 260072 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2456451374 -assert nopostproc +UVM_TEST NAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_sec_cm.2456451374 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/0.spi_device_sec_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/5.spi_device_flash_and_tpm.4217204166 |
| Short name | T72 |
| Test name | |
| Test status | |
| Simulation time | 4305864779 ps |
| CPU time | 94.38 seconds |
| Started | Sep 01 02:47:54 PM UTC 24 |
| Finished | Sep 01 02:49:30 PM UTC 24 |
| Peak memory | 263876 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4217204166 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_ 31/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_and_tpm.4217204166 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/5.spi_device_flash_and_tpm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/12.spi_device_stress_all.3999568209 |
| Short name | T180 |
| Test name | |
| Test status | |
| Simulation time | 19670632657 ps |
| CPU time | 339.52 seconds |
| Started | Sep 01 02:51:32 PM UTC 24 |
| Finished | Sep 01 02:57:17 PM UTC 24 |
| Peak memory | 265888 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3999568209 -assert nopostproc +UVM_ TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_stress_all.3999568209 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/12.spi_device_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/1.spi_device_stress_all.971232676 |
| Short name | T151 |
| Test name | |
| Test status | |
| Simulation time | 91686787985 ps |
| CPU time | 639.64 seconds |
| Started | Sep 01 02:46:15 PM UTC 24 |
| Finished | Sep 01 02:57:03 PM UTC 24 |
| Peak memory | 278224 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=971232676 -assert nopostproc +UVM_T ESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_stress_all.971232676 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/1.spi_device_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/1.spi_device_flash_mode_ignore_cmds.4168563257 |
| Short name | T44 |
| Test name | |
| Test status | |
| Simulation time | 1603153610 ps |
| CPU time | 47.13 seconds |
| Started | Sep 01 02:46:11 PM UTC 24 |
| Finished | Sep 01 02:47:00 PM UTC 24 |
| Peak memory | 261732 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4168563257 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_31/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_mode_ignore_cmds.4168563257 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/1.spi_device_flash_mode_ignore_cmds/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/0.spi_device_csr_hw_reset.4261873489 |
| Short name | T106 |
| Test name | |
| Test status | |
| Simulation time | 321930464 ps |
| CPU time | 1.83 seconds |
| Started | Sep 01 02:44:49 PM UTC 24 |
| Finished | Sep 01 02:44:52 PM UTC 24 |
| Peak memory | 223952 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4261873489 -assert nopostproc +UVM _TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_csr_hw_reset.4261873489 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/0.spi_device_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/15.spi_device_flash_all.3030024743 |
| Short name | T265 |
| Test name | |
| Test status | |
| Simulation time | 7175107910 ps |
| CPU time | 130.14 seconds |
| Started | Sep 01 02:53:11 PM UTC 24 |
| Finished | Sep 01 02:55:23 PM UTC 24 |
| Peak memory | 278048 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3030024743 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/s pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_all.3030024743 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/15.spi_device_flash_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/10.spi_device_stress_all.2537783353 |
| Short name | T79 |
| Test name | |
| Test status | |
| Simulation time | 306157238542 ps |
| CPU time | 688.39 seconds |
| Started | Sep 01 02:50:38 PM UTC 24 |
| Finished | Sep 01 03:02:15 PM UTC 24 |
| Peak memory | 284312 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2537783353 -assert nopostproc +UVM_ TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_stress_all.2537783353 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/10.spi_device_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/0.spi_device_pass_cmd_filtering.1314876878 |
| Short name | T5 |
| Test name | |
| Test status | |
| Simulation time | 244339261 ps |
| CPU time | 3.17 seconds |
| Started | Sep 01 02:45:58 PM UTC 24 |
| Finished | Sep 01 02:46:03 PM UTC 24 |
| Peak memory | 234960 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1314876878 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_08_31/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_pass_cmd_filtering.1314876878 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/0.spi_device_pass_cmd_filtering/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/10.spi_device_flash_mode_ignore_cmds.2385789804 |
| Short name | T272 |
| Test name | |
| Test status | |
| Simulation time | 61430635653 ps |
| CPU time | 580.22 seconds |
| Started | Sep 01 02:50:28 PM UTC 24 |
| Finished | Sep 01 03:00:15 PM UTC 24 |
| Peak memory | 278092 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2385789804 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_31/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_mode_ignore_cmds.2385789804 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/10.spi_device_flash_mode_ignore_cmds/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/0.spi_device_tpm_read_hw_reg.3353224194 |
| Short name | T25 |
| Test name | |
| Test status | |
| Simulation time | 1856291276 ps |
| CPU time | 15.86 seconds |
| Started | Sep 01 02:45:58 PM UTC 24 |
| Finished | Sep 01 02:46:15 PM UTC 24 |
| Peak memory | 227540 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3353224194 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_31/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_read_hw_reg.3353224194 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/0.spi_device_tpm_read_hw_reg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/17.spi_device_flash_and_tpm_min_idle.2797925940 |
| Short name | T244 |
| Test name | |
| Test status | |
| Simulation time | 79543456246 ps |
| CPU time | 412.7 seconds |
| Started | Sep 01 02:54:15 PM UTC 24 |
| Finished | Sep 01 03:01:13 PM UTC 24 |
| Peak memory | 278160 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2797925940 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_31/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_and_tpm_min_idle.2797925940 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/17.spi_device_flash_and_tpm_min_idle/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/40.spi_device_stress_all.3400909077 |
| Short name | T162 |
| Test name | |
| Test status | |
| Simulation time | 11270397870 ps |
| CPU time | 387.75 seconds |
| Started | Sep 01 03:03:07 PM UTC 24 |
| Finished | Sep 01 03:09:42 PM UTC 24 |
| Peak memory | 308888 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3400909077 -assert nopostproc +UVM_ TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_stress_all.3400909077 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/40.spi_device_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/12.spi_device_flash_and_tpm.354710542 |
| Short name | T188 |
| Test name | |
| Test status | |
| Simulation time | 15627645772 ps |
| CPU time | 131.55 seconds |
| Started | Sep 01 02:51:31 PM UTC 24 |
| Finished | Sep 01 02:53:45 PM UTC 24 |
| Peak memory | 276076 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=354710542 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_3 1/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_and_tpm.354710542 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/12.spi_device_flash_and_tpm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/35.spi_device_flash_all.570980436 |
| Short name | T290 |
| Test name | |
| Test status | |
| Simulation time | 4228905044 ps |
| CPU time | 111.74 seconds |
| Started | Sep 01 03:01:22 PM UTC 24 |
| Finished | Sep 01 03:03:16 PM UTC 24 |
| Peak memory | 267864 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=570980436 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/sp i_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_all.570980436 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/35.spi_device_flash_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/2.spi_device_stress_all.1876364407 |
| Short name | T34 |
| Test name | |
| Test status | |
| Simulation time | 5833541957 ps |
| CPU time | 64.09 seconds |
| Started | Sep 01 02:46:38 PM UTC 24 |
| Finished | Sep 01 02:47:44 PM UTC 24 |
| Peak memory | 261836 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1876364407 -assert nopostproc +UVM_ TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_stress_all.1876364407 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/2.spi_device_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/0.spi_device_alert_test.2951614903 |
| Short name | T9 |
| Test name | |
| Test status | |
| Simulation time | 15326779 ps |
| CPU time | 1.14 seconds |
| Started | Sep 01 02:46:01 PM UTC 24 |
| Finished | Sep 01 02:46:03 PM UTC 24 |
| Peak memory | 215680 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2951614903 -assert nopostproc +UVM_TES TNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_alert_test.2951614903 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/0.spi_device_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/48.spi_device_flash_all.2007583938 |
| Short name | T356 |
| Test name | |
| Test status | |
| Simulation time | 4455084351 ps |
| CPU time | 102.91 seconds |
| Started | Sep 01 03:05:57 PM UTC 24 |
| Finished | Sep 01 03:07:42 PM UTC 24 |
| Peak memory | 277560 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2007583938 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/s pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_all.2007583938 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/48.spi_device_flash_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/10.spi_device_tl_errors.1916768083 |
| Short name | T132 |
| Test name | |
| Test status | |
| Simulation time | 91116265 ps |
| CPU time | 5.52 seconds |
| Started | Sep 01 02:45:28 PM UTC 24 |
| Finished | Sep 01 02:45:35 PM UTC 24 |
| Peak memory | 227232 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1916768083 -assert nopostproc +UVM_TESTNAME =spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_08_31/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_tl_errors.1916768083 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/10.spi_device_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/0.spi_device_flash_mode.306394332 |
| Short name | T165 |
| Test name | |
| Test status | |
| Simulation time | 2360001142 ps |
| CPU time | 42.15 seconds |
| Started | Sep 01 02:46:00 PM UTC 24 |
| Finished | Sep 01 02:46:43 PM UTC 24 |
| Peak memory | 245224 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=306394332 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/s pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_mode.306394332 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/0.spi_device_flash_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/1.spi_device_tl_intg_err.437053927 |
| Short name | T209 |
| Test name | |
| Test status | |
| Simulation time | 824718154 ps |
| CPU time | 23.37 seconds |
| Started | Sep 01 02:44:51 PM UTC 24 |
| Finished | Sep 01 02:45:15 PM UTC 24 |
| Peak memory | 227060 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=437053927 -assert nopostproc +U VM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_tl_intg_err.437053927 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/1.spi_device_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/16.spi_device_flash_mode_ignore_cmds.3363670062 |
| Short name | T247 |
| Test name | |
| Test status | |
| Simulation time | 14803353309 ps |
| CPU time | 172.75 seconds |
| Started | Sep 01 02:53:39 PM UTC 24 |
| Finished | Sep 01 02:56:35 PM UTC 24 |
| Peak memory | 267856 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3363670062 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_31/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_mode_ignore_cmds.3363670062 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/16.spi_device_flash_mode_ignore_cmds/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/3.spi_device_flash_and_tpm_min_idle.454765527 |
| Short name | T41 |
| Test name | |
| Test status | |
| Simulation time | 861682329717 ps |
| CPU time | 491.44 seconds |
| Started | Sep 01 02:47:08 PM UTC 24 |
| Finished | Sep 01 02:55:27 PM UTC 24 |
| Peak memory | 267988 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=454765527 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_31/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_and_tpm_min_idle.454765527 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/3.spi_device_flash_and_tpm_min_idle/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/1.spi_device_intercept.583680337 |
| Short name | T20 |
| Test name | |
| Test status | |
| Simulation time | 3571911228 ps |
| CPU time | 11.21 seconds |
| Started | Sep 01 02:46:05 PM UTC 24 |
| Finished | Sep 01 02:46:17 PM UTC 24 |
| Peak memory | 235096 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=583680337 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/sp i_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_intercept.583680337 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/1.spi_device_intercept/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/12.spi_device_flash_mode.763701984 |
| Short name | T371 |
| Test name | |
| Test status | |
| Simulation time | 265959990 ps |
| CPU time | 9.32 seconds |
| Started | Sep 01 02:51:27 PM UTC 24 |
| Finished | Sep 01 02:51:38 PM UTC 24 |
| Peak memory | 234952 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=763701984 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/s pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_mode.763701984 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/12.spi_device_flash_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/20.spi_device_flash_mode_ignore_cmds.2836088430 |
| Short name | T224 |
| Test name | |
| Test status | |
| Simulation time | 26386543885 ps |
| CPU time | 102.52 seconds |
| Started | Sep 01 02:55:28 PM UTC 24 |
| Finished | Sep 01 02:57:13 PM UTC 24 |
| Peak memory | 265804 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2836088430 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_31/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_mode_ignore_cmds.2836088430 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/20.spi_device_flash_mode_ignore_cmds/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/24.spi_device_flash_mode_ignore_cmds.2152470944 |
| Short name | T986 |
| Test name | |
| Test status | |
| Simulation time | 147137622935 ps |
| CPU time | 608.54 seconds |
| Started | Sep 01 02:57:19 PM UTC 24 |
| Finished | Sep 01 03:07:35 PM UTC 24 |
| Peak memory | 267856 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2152470944 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_31/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_mode_ignore_cmds.2152470944 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/24.spi_device_flash_mode_ignore_cmds/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/3.spi_device_stress_all.1613413405 |
| Short name | T37 |
| Test name | |
| Test status | |
| Simulation time | 26747836527 ps |
| CPU time | 327.8 seconds |
| Started | Sep 01 02:47:09 PM UTC 24 |
| Finished | Sep 01 02:52:42 PM UTC 24 |
| Peak memory | 261764 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1613413405 -assert nopostproc +UVM_ TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_stress_all.1613413405 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/3.spi_device_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/38.spi_device_flash_and_tpm.2639667440 |
| Short name | T161 |
| Test name | |
| Test status | |
| Simulation time | 91084988243 ps |
| CPU time | 244.46 seconds |
| Started | Sep 01 03:02:22 PM UTC 24 |
| Finished | Sep 01 03:06:30 PM UTC 24 |
| Peak memory | 284324 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2639667440 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_ 31/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_and_tpm.2639667440 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/38.spi_device_flash_and_tpm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/14.spi_device_tl_errors.2137533516 |
| Short name | T1064 |
| Test name | |
| Test status | |
| Simulation time | 172621254 ps |
| CPU time | 3.59 seconds |
| Started | Sep 01 02:45:37 PM UTC 24 |
| Finished | Sep 01 02:45:41 PM UTC 24 |
| Peak memory | 227340 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2137533516 -assert nopostproc +UVM_TESTNAME =spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_08_31/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_tl_errors.2137533516 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/14.spi_device_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/14.spi_device_tl_intg_err.1408206312 |
| Short name | T212 |
| Test name | |
| Test status | |
| Simulation time | 324875788 ps |
| CPU time | 11.61 seconds |
| Started | Sep 01 02:45:37 PM UTC 24 |
| Finished | Sep 01 02:45:50 PM UTC 24 |
| Peak memory | 225068 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1408206312 -assert nopostproc + UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_tl_intg_err.1408206312 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/14.spi_device_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/8.spi_device_tl_intg_err.4083208709 |
| Short name | T208 |
| Test name | |
| Test status | |
| Simulation time | 792005796 ps |
| CPU time | 18.32 seconds |
| Started | Sep 01 02:45:25 PM UTC 24 |
| Finished | Sep 01 02:45:44 PM UTC 24 |
| Peak memory | 227132 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4083208709 -assert nopostproc + UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_tl_intg_err.4083208709 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/8.spi_device_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/10.spi_device_flash_and_tpm.3927801901 |
| Short name | T241 |
| Test name | |
| Test status | |
| Simulation time | 66628108211 ps |
| CPU time | 868.2 seconds |
| Started | Sep 01 02:50:34 PM UTC 24 |
| Finished | Sep 01 03:05:14 PM UTC 24 |
| Peak memory | 278244 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3927801901 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_ 31/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_and_tpm.3927801901 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/10.spi_device_flash_and_tpm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/11.spi_device_flash_mode.1848624409 |
| Short name | T370 |
| Test name | |
| Test status | |
| Simulation time | 3979924133 ps |
| CPU time | 19.27 seconds |
| Started | Sep 01 02:51:00 PM UTC 24 |
| Finished | Sep 01 02:51:20 PM UTC 24 |
| Peak memory | 249436 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1848624409 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/ spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_mode.1848624409 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/11.spi_device_flash_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/11.spi_device_tpm_all.943399112 |
| Short name | T388 |
| Test name | |
| Test status | |
| Simulation time | 1790669694 ps |
| CPU time | 33.14 seconds |
| Started | Sep 01 02:50:46 PM UTC 24 |
| Finished | Sep 01 02:51:20 PM UTC 24 |
| Peak memory | 231576 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=943399112 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_all.943399112 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/11.spi_device_tpm_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/12.spi_device_flash_and_tpm_min_idle.2800060828 |
| Short name | T395 |
| Test name | |
| Test status | |
| Simulation time | 50069936879 ps |
| CPU time | 421.1 seconds |
| Started | Sep 01 02:51:32 PM UTC 24 |
| Finished | Sep 01 02:58:39 PM UTC 24 |
| Peak memory | 268000 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2800060828 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_31/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_and_tpm_min_idle.2800060828 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/12.spi_device_flash_and_tpm_min_idle/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/13.spi_device_flash_and_tpm.121937171 |
| Short name | T85 |
| Test name | |
| Test status | |
| Simulation time | 20534766350 ps |
| CPU time | 138.98 seconds |
| Started | Sep 01 02:51:59 PM UTC 24 |
| Finished | Sep 01 02:54:22 PM UTC 24 |
| Peak memory | 261820 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=121937171 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_3 1/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_and_tpm.121937171 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/13.spi_device_flash_and_tpm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/25.spi_device_flash_and_tpm.1216603501 |
| Short name | T349 |
| Test name | |
| Test status | |
| Simulation time | 260220245147 ps |
| CPU time | 621.58 seconds |
| Started | Sep 01 02:57:47 PM UTC 24 |
| Finished | Sep 01 03:08:17 PM UTC 24 |
| Peak memory | 282240 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1216603501 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_ 31/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_and_tpm.1216603501 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/25.spi_device_flash_and_tpm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/42.spi_device_flash_mode.1887116534 |
| Short name | T378 |
| Test name | |
| Test status | |
| Simulation time | 2553341340 ps |
| CPU time | 28.86 seconds |
| Started | Sep 01 03:03:30 PM UTC 24 |
| Finished | Sep 01 03:04:01 PM UTC 24 |
| Peak memory | 235084 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1887116534 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/ spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_mode.1887116534 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/42.spi_device_flash_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/42.spi_device_upload.2907528168 |
| Short name | T217 |
| Test name | |
| Test status | |
| Simulation time | 1661534721 ps |
| CPU time | 3.19 seconds |
| Started | Sep 01 03:03:29 PM UTC 24 |
| Finished | Sep 01 03:03:33 PM UTC 24 |
| Peak memory | 234848 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2907528168 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_upload.2907528168 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/42.spi_device_upload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/1.spi_device_mailbox.3680198403 |
| Short name | T114 |
| Test name | |
| Test status | |
| Simulation time | 4195009579 ps |
| CPU time | 42.53 seconds |
| Started | Sep 01 02:46:05 PM UTC 24 |
| Finished | Sep 01 02:46:49 PM UTC 24 |
| Peak memory | 247436 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3680198403 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_mailbox.3680198403 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/1.spi_device_mailbox/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/11.spi_device_tl_errors.643661665 |
| Short name | T125 |
| Test name | |
| Test status | |
| Simulation time | 70240647 ps |
| CPU time | 3.66 seconds |
| Started | Sep 01 02:45:31 PM UTC 24 |
| Finished | Sep 01 02:45:35 PM UTC 24 |
| Peak memory | 227440 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=643661665 -assert nopostproc +UVM_TESTNAME= spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_08_31/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_tl_errors.643661665 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/11.spi_device_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/0.spi_device_csr_aliasing.1021305903 |
| Short name | T149 |
| Test name | |
| Test status | |
| Simulation time | 310708019 ps |
| CPU time | 29.02 seconds |
| Started | Sep 01 02:44:50 PM UTC 24 |
| Finished | Sep 01 02:45:21 PM UTC 24 |
| Peak memory | 225124 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1021305903 -assert nopostproc +UVM _TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_csr_aliasing.1021305903 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/0.spi_device_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/0.spi_device_csr_bit_bash.1634144237 |
| Short name | T1023 |
| Test name | |
| Test status | |
| Simulation time | 194647261 ps |
| CPU time | 12.02 seconds |
| Started | Sep 01 02:44:50 PM UTC 24 |
| Finished | Sep 01 02:45:03 PM UTC 24 |
| Peak memory | 214952 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1634144237 -assert nopostproc +UVM _TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_csr_bit_bash.1634144237 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/0.spi_device_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/0.spi_device_csr_mem_rw_with_rand_reset.4195149766 |
| Short name | T101 |
| Test name | |
| Test status | |
| Simulation time | 37008953 ps |
| CPU time | 3.49 seconds |
| Started | Sep 01 02:44:51 PM UTC 24 |
| Finished | Sep 01 02:44:55 PM UTC 24 |
| Peak memory | 229428 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000 000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb _random_seed=4195149766 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_ name 0.spi_device_csr_mem_rw_with_rand_reset.4195149766 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/0.spi_device_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/0.spi_device_csr_rw.4292893942 |
| Short name | T164 |
| Test name | |
| Test status | |
| Simulation time | 42957486 ps |
| CPU time | 2.01 seconds |
| Started | Sep 01 02:44:49 PM UTC 24 |
| Finished | Sep 01 02:44:52 PM UTC 24 |
| Peak memory | 215140 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4292893942 -assert nopostproc +UVM_TESTN AME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_csr_rw.4292893942 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/0.spi_device_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/0.spi_device_intr_test.2969132724 |
| Short name | T1012 |
| Test name | |
| Test status | |
| Simulation time | 12219646 ps |
| CPU time | 1.09 seconds |
| Started | Sep 01 02:44:49 PM UTC 24 |
| Finished | Sep 01 02:44:51 PM UTC 24 |
| Peak memory | 212740 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2969132724 -assert nopostproc +UVM_TESTNAME =spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_08_31/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_intr_test.2969132724 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/0.spi_device_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/0.spi_device_mem_partial_access.3201051664 |
| Short name | T138 |
| Test name | |
| Test status | |
| Simulation time | 27021220 ps |
| CPU time | 2.93 seconds |
| Started | Sep 01 02:44:49 PM UTC 24 |
| Finished | Sep 01 02:44:53 PM UTC 24 |
| Peak memory | 225052 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3201051664 -assert nopos tproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re po/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_mem_partial_access.3201051664 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/0.spi_device_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/0.spi_device_mem_walk.634722969 |
| Short name | T1013 |
| Test name | |
| Test status | |
| Simulation time | 13052801 ps |
| CPU time | 1.06 seconds |
| Started | Sep 01 02:44:49 PM UTC 24 |
| Finished | Sep 01 02:44:51 PM UTC 24 |
| Peak memory | 211752 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=634722969 -assert nopostproc +UVM_ TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_mem_walk.634722969 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/0.spi_device_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/0.spi_device_same_csr_outstanding.990749277 |
| Short name | T1017 |
| Test name | |
| Test status | |
| Simulation time | 113814235 ps |
| CPU time | 4.11 seconds |
| Started | Sep 01 02:44:50 PM UTC 24 |
| Finished | Sep 01 02:44:56 PM UTC 24 |
| Peak memory | 225268 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=990749277 -assert nopo stproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r epo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_same_csr_outstanding.990749277 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/0.spi_device_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/0.spi_device_tl_intg_err.3991028059 |
| Short name | T116 |
| Test name | |
| Test status | |
| Simulation time | 846359141 ps |
| CPU time | 7.17 seconds |
| Started | Sep 01 02:44:49 PM UTC 24 |
| Finished | Sep 01 02:44:57 PM UTC 24 |
| Peak memory | 227140 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3991028059 -assert nopostproc + UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_tl_intg_err.3991028059 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/0.spi_device_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/1.spi_device_csr_aliasing.740943897 |
| Short name | T1032 |
| Test name | |
| Test status | |
| Simulation time | 949661280 ps |
| CPU time | 26.48 seconds |
| Started | Sep 01 02:44:53 PM UTC 24 |
| Finished | Sep 01 02:45:21 PM UTC 24 |
| Peak memory | 225064 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=740943897 -assert nopostproc +UVM_ TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_csr_aliasing.740943897 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/1.spi_device_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/1.spi_device_csr_bit_bash.1165102152 |
| Short name | T1039 |
| Test name | |
| Test status | |
| Simulation time | 1397239046 ps |
| CPU time | 32.71 seconds |
| Started | Sep 01 02:44:53 PM UTC 24 |
| Finished | Sep 01 02:45:28 PM UTC 24 |
| Peak memory | 216948 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1165102152 -assert nopostproc +UVM _TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_csr_bit_bash.1165102152 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/1.spi_device_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/1.spi_device_csr_hw_reset.3333055544 |
| Short name | T1016 |
| Test name | |
| Test status | |
| Simulation time | 114913096 ps |
| CPU time | 1.79 seconds |
| Started | Sep 01 02:44:52 PM UTC 24 |
| Finished | Sep 01 02:44:55 PM UTC 24 |
| Peak memory | 223952 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3333055544 -assert nopostproc +UVM _TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_csr_hw_reset.3333055544 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/1.spi_device_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/1.spi_device_csr_mem_rw_with_rand_reset.516987058 |
| Short name | T130 |
| Test name | |
| Test status | |
| Simulation time | 88904630 ps |
| CPU time | 3.75 seconds |
| Started | Sep 01 02:44:54 PM UTC 24 |
| Finished | Sep 01 02:44:59 PM UTC 24 |
| Peak memory | 227116 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000 000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb _random_seed=516987058 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n ame 1.spi_device_csr_mem_rw_with_rand_reset.516987058 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/1.spi_device_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/1.spi_device_csr_rw.2665079458 |
| Short name | T139 |
| Test name | |
| Test status | |
| Simulation time | 39705806 ps |
| CPU time | 1.94 seconds |
| Started | Sep 01 02:44:52 PM UTC 24 |
| Finished | Sep 01 02:44:55 PM UTC 24 |
| Peak memory | 213668 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2665079458 -assert nopostproc +UVM_TESTN AME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_csr_rw.2665079458 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/1.spi_device_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/1.spi_device_intr_test.1737261951 |
| Short name | T1015 |
| Test name | |
| Test status | |
| Simulation time | 85339568 ps |
| CPU time | 1.12 seconds |
| Started | Sep 01 02:44:51 PM UTC 24 |
| Finished | Sep 01 02:44:53 PM UTC 24 |
| Peak memory | 211764 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1737261951 -assert nopostproc +UVM_TESTNAME =spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_08_31/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_intr_test.1737261951 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/1.spi_device_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/1.spi_device_mem_partial_access.4279409767 |
| Short name | T141 |
| Test name | |
| Test status | |
| Simulation time | 40312200 ps |
| CPU time | 2 seconds |
| Started | Sep 01 02:44:52 PM UTC 24 |
| Finished | Sep 01 02:44:55 PM UTC 24 |
| Peak memory | 223932 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4279409767 -assert nopos tproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re po/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_mem_partial_access.4279409767 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/1.spi_device_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/1.spi_device_mem_walk.2648165938 |
| Short name | T1014 |
| Test name | |
| Test status | |
| Simulation time | 15058476 ps |
| CPU time | 1.03 seconds |
| Started | Sep 01 02:44:51 PM UTC 24 |
| Finished | Sep 01 02:44:53 PM UTC 24 |
| Peak memory | 211760 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2648165938 -assert nopostproc +UVM _TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_mem_walk.2648165938 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/1.spi_device_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/1.spi_device_same_csr_outstanding.1139688222 |
| Short name | T1020 |
| Test name | |
| Test status | |
| Simulation time | 1275562725 ps |
| CPU time | 6.43 seconds |
| Started | Sep 01 02:44:53 PM UTC 24 |
| Finished | Sep 01 02:45:01 PM UTC 24 |
| Peak memory | 225068 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1139688222 -assert nop ostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_same_csr_outstand ing.1139688222 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/1.spi_device_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/1.spi_device_tl_errors.1656722259 |
| Short name | T129 |
| Test name | |
| Test status | |
| Simulation time | 196509987 ps |
| CPU time | 6.91 seconds |
| Started | Sep 01 02:44:51 PM UTC 24 |
| Finished | Sep 01 02:44:59 PM UTC 24 |
| Peak memory | 225440 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1656722259 -assert nopostproc +UVM_TESTNAME =spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_08_31/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_tl_errors.1656722259 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/1.spi_device_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/10.spi_device_csr_mem_rw_with_rand_reset.4047914105 |
| Short name | T1049 |
| Test name | |
| Test status | |
| Simulation time | 48441563 ps |
| CPU time | 2.37 seconds |
| Started | Sep 01 02:45:31 PM UTC 24 |
| Finished | Sep 01 02:45:34 PM UTC 24 |
| Peak memory | 227176 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000 000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb _random_seed=4047914105 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_ name 10.spi_device_csr_mem_rw_with_rand_reset.4047914105 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/10.spi_device_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/10.spi_device_csr_rw.1593919575 |
| Short name | T1046 |
| Test name | |
| Test status | |
| Simulation time | 30601361 ps |
| CPU time | 2.6 seconds |
| Started | Sep 01 02:45:28 PM UTC 24 |
| Finished | Sep 01 02:45:32 PM UTC 24 |
| Peak memory | 225064 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1593919575 -assert nopostproc +UVM_TESTN AME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_csr_rw.1593919575 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/10.spi_device_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/10.spi_device_intr_test.1911789755 |
| Short name | T1044 |
| Test name | |
| Test status | |
| Simulation time | 41678492 ps |
| CPU time | 0.94 seconds |
| Started | Sep 01 02:45:28 PM UTC 24 |
| Finished | Sep 01 02:45:30 PM UTC 24 |
| Peak memory | 211772 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1911789755 -assert nopostproc +UVM_TESTNAME =spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_08_31/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_intr_test.1911789755 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/10.spi_device_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/10.spi_device_same_csr_outstanding.1349067794 |
| Short name | T1052 |
| Test name | |
| Test status | |
| Simulation time | 131713891 ps |
| CPU time | 4.45 seconds |
| Started | Sep 01 02:45:30 PM UTC 24 |
| Finished | Sep 01 02:45:35 PM UTC 24 |
| Peak memory | 225156 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1349067794 -assert nop ostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_same_csr_outstan ding.1349067794 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/10.spi_device_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/10.spi_device_tl_intg_err.3522812677 |
| Short name | T215 |
| Test name | |
| Test status | |
| Simulation time | 365115027 ps |
| CPU time | 7.33 seconds |
| Started | Sep 01 02:45:28 PM UTC 24 |
| Finished | Sep 01 02:45:37 PM UTC 24 |
| Peak memory | 227168 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3522812677 -assert nopostproc + UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_tl_intg_err.3522812677 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/10.spi_device_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/11.spi_device_csr_mem_rw_with_rand_reset.3349620299 |
| Short name | T1058 |
| Test name | |
| Test status | |
| Simulation time | 148507056 ps |
| CPU time | 3.76 seconds |
| Started | Sep 01 02:45:33 PM UTC 24 |
| Finished | Sep 01 02:45:38 PM UTC 24 |
| Peak memory | 227316 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000 000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb _random_seed=3349620299 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_ name 11.spi_device_csr_mem_rw_with_rand_reset.3349620299 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/11.spi_device_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/11.spi_device_csr_rw.2552002378 |
| Short name | T1051 |
| Test name | |
| Test status | |
| Simulation time | 182051244 ps |
| CPU time | 1.93 seconds |
| Started | Sep 01 02:45:32 PM UTC 24 |
| Finished | Sep 01 02:45:35 PM UTC 24 |
| Peak memory | 223892 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2552002378 -assert nopostproc +UVM_TESTN AME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_csr_rw.2552002378 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/11.spi_device_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/11.spi_device_intr_test.1882149280 |
| Short name | T1048 |
| Test name | |
| Test status | |
| Simulation time | 150931683 ps |
| CPU time | 1.15 seconds |
| Started | Sep 01 02:45:32 PM UTC 24 |
| Finished | Sep 01 02:45:34 PM UTC 24 |
| Peak memory | 211772 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1882149280 -assert nopostproc +UVM_TESTNAME =spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_08_31/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_intr_test.1882149280 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/11.spi_device_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/11.spi_device_same_csr_outstanding.727533164 |
| Short name | T1055 |
| Test name | |
| Test status | |
| Simulation time | 328679364 ps |
| CPU time | 4.28 seconds |
| Started | Sep 01 02:45:32 PM UTC 24 |
| Finished | Sep 01 02:45:37 PM UTC 24 |
| Peak memory | 225044 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=727533164 -assert nopo stproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r epo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_same_csr_outstand ing.727533164 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/11.spi_device_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/11.spi_device_tl_intg_err.3832153149 |
| Short name | T1069 |
| Test name | |
| Test status | |
| Simulation time | 1453754548 ps |
| CPU time | 9.26 seconds |
| Started | Sep 01 02:45:32 PM UTC 24 |
| Finished | Sep 01 02:45:42 PM UTC 24 |
| Peak memory | 227244 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3832153149 -assert nopostproc + UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_tl_intg_err.3832153149 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/11.spi_device_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/12.spi_device_csr_mem_rw_with_rand_reset.3983912662 |
| Short name | T1063 |
| Test name | |
| Test status | |
| Simulation time | 157192228 ps |
| CPU time | 5.6 seconds |
| Started | Sep 01 02:45:34 PM UTC 24 |
| Finished | Sep 01 02:45:41 PM UTC 24 |
| Peak memory | 229504 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000 000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb _random_seed=3983912662 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_ name 12.spi_device_csr_mem_rw_with_rand_reset.3983912662 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/12.spi_device_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/12.spi_device_csr_rw.3724652122 |
| Short name | T1054 |
| Test name | |
| Test status | |
| Simulation time | 38260197 ps |
| CPU time | 1.84 seconds |
| Started | Sep 01 02:45:33 PM UTC 24 |
| Finished | Sep 01 02:45:36 PM UTC 24 |
| Peak memory | 213672 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3724652122 -assert nopostproc +UVM_TESTN AME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_csr_rw.3724652122 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/12.spi_device_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/12.spi_device_intr_test.3890380524 |
| Short name | T1053 |
| Test name | |
| Test status | |
| Simulation time | 15605162 ps |
| CPU time | 1.09 seconds |
| Started | Sep 01 02:45:33 PM UTC 24 |
| Finished | Sep 01 02:45:35 PM UTC 24 |
| Peak memory | 211772 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3890380524 -assert nopostproc +UVM_TESTNAME =spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_08_31/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_intr_test.3890380524 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/12.spi_device_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/12.spi_device_same_csr_outstanding.3545434328 |
| Short name | T1059 |
| Test name | |
| Test status | |
| Simulation time | 28205397 ps |
| CPU time | 2.71 seconds |
| Started | Sep 01 02:45:34 PM UTC 24 |
| Finished | Sep 01 02:45:38 PM UTC 24 |
| Peak memory | 225004 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3545434328 -assert nop ostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_same_csr_outstan ding.3545434328 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/12.spi_device_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/12.spi_device_tl_errors.1145333640 |
| Short name | T134 |
| Test name | |
| Test status | |
| Simulation time | 134774410 ps |
| CPU time | 4.76 seconds |
| Started | Sep 01 02:45:33 PM UTC 24 |
| Finished | Sep 01 02:45:39 PM UTC 24 |
| Peak memory | 225192 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1145333640 -assert nopostproc +UVM_TESTNAME =spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_08_31/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_tl_errors.1145333640 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/12.spi_device_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/12.spi_device_tl_intg_err.3516083068 |
| Short name | T1071 |
| Test name | |
| Test status | |
| Simulation time | 109918860 ps |
| CPU time | 8.97 seconds |
| Started | Sep 01 02:45:33 PM UTC 24 |
| Finished | Sep 01 02:45:43 PM UTC 24 |
| Peak memory | 225004 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3516083068 -assert nopostproc + UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_tl_intg_err.3516083068 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/12.spi_device_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/13.spi_device_csr_mem_rw_with_rand_reset.311434931 |
| Short name | T1066 |
| Test name | |
| Test status | |
| Simulation time | 43634970 ps |
| CPU time | 3.69 seconds |
| Started | Sep 01 02:45:37 PM UTC 24 |
| Finished | Sep 01 02:45:42 PM UTC 24 |
| Peak memory | 227372 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000 000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb _random_seed=311434931 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n ame 13.spi_device_csr_mem_rw_with_rand_reset.311434931 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/13.spi_device_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/13.spi_device_csr_rw.4278286373 |
| Short name | T1061 |
| Test name | |
| Test status | |
| Simulation time | 76125290 ps |
| CPU time | 2.63 seconds |
| Started | Sep 01 02:45:36 PM UTC 24 |
| Finished | Sep 01 02:45:39 PM UTC 24 |
| Peak memory | 214756 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4278286373 -assert nopostproc +UVM_TESTN AME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_csr_rw.4278286373 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/13.spi_device_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/13.spi_device_intr_test.1763450082 |
| Short name | T1057 |
| Test name | |
| Test status | |
| Simulation time | 15995417 ps |
| CPU time | 1.13 seconds |
| Started | Sep 01 02:45:36 PM UTC 24 |
| Finished | Sep 01 02:45:38 PM UTC 24 |
| Peak memory | 211772 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1763450082 -assert nopostproc +UVM_TESTNAME =spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_08_31/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_intr_test.1763450082 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/13.spi_device_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/13.spi_device_same_csr_outstanding.3073001254 |
| Short name | T1062 |
| Test name | |
| Test status | |
| Simulation time | 269013871 ps |
| CPU time | 2.96 seconds |
| Started | Sep 01 02:45:36 PM UTC 24 |
| Finished | Sep 01 02:45:40 PM UTC 24 |
| Peak memory | 214800 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3073001254 -assert nop ostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_same_csr_outstan ding.3073001254 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/13.spi_device_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/13.spi_device_tl_errors.2671612099 |
| Short name | T1072 |
| Test name | |
| Test status | |
| Simulation time | 1991986944 ps |
| CPU time | 6.94 seconds |
| Started | Sep 01 02:45:35 PM UTC 24 |
| Finished | Sep 01 02:45:44 PM UTC 24 |
| Peak memory | 225204 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2671612099 -assert nopostproc +UVM_TESTNAME =spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_08_31/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_tl_errors.2671612099 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/13.spi_device_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/13.spi_device_tl_intg_err.2988070319 |
| Short name | T1123 |
| Test name | |
| Test status | |
| Simulation time | 8965963573 ps |
| CPU time | 21.42 seconds |
| Started | Sep 01 02:45:35 PM UTC 24 |
| Finished | Sep 01 02:45:58 PM UTC 24 |
| Peak memory | 227316 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2988070319 -assert nopostproc + UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_tl_intg_err.2988070319 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/13.spi_device_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/14.spi_device_csr_mem_rw_with_rand_reset.1016008982 |
| Short name | T1068 |
| Test name | |
| Test status | |
| Simulation time | 41226941 ps |
| CPU time | 2.77 seconds |
| Started | Sep 01 02:45:38 PM UTC 24 |
| Finished | Sep 01 02:45:42 PM UTC 24 |
| Peak memory | 227120 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000 000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb _random_seed=1016008982 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_ name 14.spi_device_csr_mem_rw_with_rand_reset.1016008982 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/14.spi_device_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/14.spi_device_csr_rw.3274220923 |
| Short name | T1070 |
| Test name | |
| Test status | |
| Simulation time | 355589880 ps |
| CPU time | 3.71 seconds |
| Started | Sep 01 02:45:38 PM UTC 24 |
| Finished | Sep 01 02:45:43 PM UTC 24 |
| Peak memory | 225120 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3274220923 -assert nopostproc +UVM_TESTN AME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_csr_rw.3274220923 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/14.spi_device_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/14.spi_device_intr_test.2185404480 |
| Short name | T1060 |
| Test name | |
| Test status | |
| Simulation time | 25339879 ps |
| CPU time | 1.08 seconds |
| Started | Sep 01 02:45:37 PM UTC 24 |
| Finished | Sep 01 02:45:39 PM UTC 24 |
| Peak memory | 211772 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2185404480 -assert nopostproc +UVM_TESTNAME =spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_08_31/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_intr_test.2185404480 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/14.spi_device_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/14.spi_device_same_csr_outstanding.2423354519 |
| Short name | T1075 |
| Test name | |
| Test status | |
| Simulation time | 832003408 ps |
| CPU time | 5.98 seconds |
| Started | Sep 01 02:45:38 PM UTC 24 |
| Finished | Sep 01 02:45:45 PM UTC 24 |
| Peak memory | 225052 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2423354519 -assert nop ostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_same_csr_outstan ding.2423354519 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/14.spi_device_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/15.spi_device_csr_mem_rw_with_rand_reset.1214984585 |
| Short name | T1076 |
| Test name | |
| Test status | |
| Simulation time | 334539508 ps |
| CPU time | 3.53 seconds |
| Started | Sep 01 02:45:40 PM UTC 24 |
| Finished | Sep 01 02:45:45 PM UTC 24 |
| Peak memory | 227316 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000 000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb _random_seed=1214984585 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_ name 15.spi_device_csr_mem_rw_with_rand_reset.1214984585 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/15.spi_device_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/15.spi_device_csr_rw.503667128 |
| Short name | T1073 |
| Test name | |
| Test status | |
| Simulation time | 71947555 ps |
| CPU time | 2.42 seconds |
| Started | Sep 01 02:45:40 PM UTC 24 |
| Finished | Sep 01 02:45:44 PM UTC 24 |
| Peak memory | 224992 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=503667128 -assert nopostproc +UVM_TESTNA ME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_csr_rw.503667128 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/15.spi_device_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/15.spi_device_intr_test.2573936807 |
| Short name | T1065 |
| Test name | |
| Test status | |
| Simulation time | 12599080 ps |
| CPU time | 1.12 seconds |
| Started | Sep 01 02:45:39 PM UTC 24 |
| Finished | Sep 01 02:45:41 PM UTC 24 |
| Peak memory | 211772 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2573936807 -assert nopostproc +UVM_TESTNAME =spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_08_31/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_intr_test.2573936807 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/15.spi_device_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/15.spi_device_same_csr_outstanding.748322715 |
| Short name | T1074 |
| Test name | |
| Test status | |
| Simulation time | 196957135 ps |
| CPU time | 2.53 seconds |
| Started | Sep 01 02:45:40 PM UTC 24 |
| Finished | Sep 01 02:45:44 PM UTC 24 |
| Peak memory | 214768 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=748322715 -assert nopo stproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r epo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_same_csr_outstand ing.748322715 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/15.spi_device_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/15.spi_device_tl_errors.310296255 |
| Short name | T1083 |
| Test name | |
| Test status | |
| Simulation time | 390398369 ps |
| CPU time | 7.68 seconds |
| Started | Sep 01 02:45:39 PM UTC 24 |
| Finished | Sep 01 02:45:48 PM UTC 24 |
| Peak memory | 225232 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=310296255 -assert nopostproc +UVM_TESTNAME= spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_08_31/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_tl_errors.310296255 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/15.spi_device_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/15.spi_device_tl_intg_err.865664752 |
| Short name | T214 |
| Test name | |
| Test status | |
| Simulation time | 407603696 ps |
| CPU time | 11.27 seconds |
| Started | Sep 01 02:45:39 PM UTC 24 |
| Finished | Sep 01 02:45:52 PM UTC 24 |
| Peak memory | 225000 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=865664752 -assert nopostproc +U VM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_tl_intg_err.865664752 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/15.spi_device_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/16.spi_device_csr_mem_rw_with_rand_reset.205072868 |
| Short name | T1081 |
| Test name | |
| Test status | |
| Simulation time | 70103642 ps |
| CPU time | 3.39 seconds |
| Started | Sep 01 02:45:43 PM UTC 24 |
| Finished | Sep 01 02:45:48 PM UTC 24 |
| Peak memory | 227360 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000 000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb _random_seed=205072868 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n ame 16.spi_device_csr_mem_rw_with_rand_reset.205072868 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/16.spi_device_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/16.spi_device_csr_rw.1425244987 |
| Short name | T1078 |
| Test name | |
| Test status | |
| Simulation time | 59354453 ps |
| CPU time | 1.3 seconds |
| Started | Sep 01 02:45:43 PM UTC 24 |
| Finished | Sep 01 02:45:46 PM UTC 24 |
| Peak memory | 225932 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1425244987 -assert nopostproc +UVM_TESTN AME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_csr_rw.1425244987 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/16.spi_device_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/16.spi_device_intr_test.2970461930 |
| Short name | T1077 |
| Test name | |
| Test status | |
| Simulation time | 29172113 ps |
| CPU time | 1.02 seconds |
| Started | Sep 01 02:45:43 PM UTC 24 |
| Finished | Sep 01 02:45:45 PM UTC 24 |
| Peak memory | 211760 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2970461930 -assert nopostproc +UVM_TESTNAME =spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_08_31/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_intr_test.2970461930 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/16.spi_device_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/16.spi_device_same_csr_outstanding.2171597573 |
| Short name | T1086 |
| Test name | |
| Test status | |
| Simulation time | 600529696 ps |
| CPU time | 4.9 seconds |
| Started | Sep 01 02:45:43 PM UTC 24 |
| Finished | Sep 01 02:45:49 PM UTC 24 |
| Peak memory | 225292 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2171597573 -assert nop ostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_same_csr_outstan ding.2171597573 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/16.spi_device_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/16.spi_device_tl_errors.848262188 |
| Short name | T1080 |
| Test name | |
| Test status | |
| Simulation time | 189746393 ps |
| CPU time | 5.69 seconds |
| Started | Sep 01 02:45:41 PM UTC 24 |
| Finished | Sep 01 02:45:47 PM UTC 24 |
| Peak memory | 225400 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=848262188 -assert nopostproc +UVM_TESTNAME= spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_08_31/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_tl_errors.848262188 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/16.spi_device_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/16.spi_device_tl_intg_err.1448319004 |
| Short name | T211 |
| Test name | |
| Test status | |
| Simulation time | 698062962 ps |
| CPU time | 14.98 seconds |
| Started | Sep 01 02:45:42 PM UTC 24 |
| Finished | Sep 01 02:45:58 PM UTC 24 |
| Peak memory | 227116 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1448319004 -assert nopostproc + UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_tl_intg_err.1448319004 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/16.spi_device_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/17.spi_device_csr_mem_rw_with_rand_reset.3019343557 |
| Short name | T1085 |
| Test name | |
| Test status | |
| Simulation time | 52448681 ps |
| CPU time | 2.4 seconds |
| Started | Sep 01 02:45:45 PM UTC 24 |
| Finished | Sep 01 02:45:49 PM UTC 24 |
| Peak memory | 227320 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000 000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb _random_seed=3019343557 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_ name 17.spi_device_csr_mem_rw_with_rand_reset.3019343557 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/17.spi_device_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/17.spi_device_csr_rw.1253834104 |
| Short name | T1082 |
| Test name | |
| Test status | |
| Simulation time | 119012997 ps |
| CPU time | 2.69 seconds |
| Started | Sep 01 02:45:44 PM UTC 24 |
| Finished | Sep 01 02:45:48 PM UTC 24 |
| Peak memory | 214844 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1253834104 -assert nopostproc +UVM_TESTN AME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_csr_rw.1253834104 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/17.spi_device_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/17.spi_device_intr_test.2383750118 |
| Short name | T1079 |
| Test name | |
| Test status | |
| Simulation time | 103679793 ps |
| CPU time | 1.02 seconds |
| Started | Sep 01 02:45:44 PM UTC 24 |
| Finished | Sep 01 02:45:46 PM UTC 24 |
| Peak memory | 211772 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2383750118 -assert nopostproc +UVM_TESTNAME =spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_08_31/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_intr_test.2383750118 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/17.spi_device_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/17.spi_device_same_csr_outstanding.1581565162 |
| Short name | T1087 |
| Test name | |
| Test status | |
| Simulation time | 120198376 ps |
| CPU time | 4.22 seconds |
| Started | Sep 01 02:45:44 PM UTC 24 |
| Finished | Sep 01 02:45:49 PM UTC 24 |
| Peak memory | 225024 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1581565162 -assert nop ostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_same_csr_outstan ding.1581565162 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/17.spi_device_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/17.spi_device_tl_errors.4294414283 |
| Short name | T1088 |
| Test name | |
| Test status | |
| Simulation time | 713929745 ps |
| CPU time | 5.75 seconds |
| Started | Sep 01 02:45:43 PM UTC 24 |
| Finished | Sep 01 02:45:50 PM UTC 24 |
| Peak memory | 225336 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4294414283 -assert nopostproc +UVM_TESTNAME =spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_08_31/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_tl_errors.4294414283 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/17.spi_device_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/17.spi_device_tl_intg_err.3247596821 |
| Short name | T1130 |
| Test name | |
| Test status | |
| Simulation time | 2328705839 ps |
| CPU time | 16.21 seconds |
| Started | Sep 01 02:45:43 PM UTC 24 |
| Finished | Sep 01 02:46:01 PM UTC 24 |
| Peak memory | 227104 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3247596821 -assert nopostproc + UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_tl_intg_err.3247596821 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/17.spi_device_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/18.spi_device_csr_mem_rw_with_rand_reset.1422957127 |
| Short name | T1097 |
| Test name | |
| Test status | |
| Simulation time | 127170617 ps |
| CPU time | 5.47 seconds |
| Started | Sep 01 02:45:47 PM UTC 24 |
| Finished | Sep 01 02:45:53 PM UTC 24 |
| Peak memory | 227196 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000 000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb _random_seed=1422957127 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_ name 18.spi_device_csr_mem_rw_with_rand_reset.1422957127 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/18.spi_device_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/18.spi_device_csr_rw.2985748485 |
| Short name | T1089 |
| Test name | |
| Test status | |
| Simulation time | 158089149 ps |
| CPU time | 3.04 seconds |
| Started | Sep 01 02:45:46 PM UTC 24 |
| Finished | Sep 01 02:45:51 PM UTC 24 |
| Peak memory | 225056 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2985748485 -assert nopostproc +UVM_TESTN AME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_csr_rw.2985748485 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/18.spi_device_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/18.spi_device_intr_test.3465970014 |
| Short name | T1084 |
| Test name | |
| Test status | |
| Simulation time | 42941899 ps |
| CPU time | 1.08 seconds |
| Started | Sep 01 02:45:46 PM UTC 24 |
| Finished | Sep 01 02:45:49 PM UTC 24 |
| Peak memory | 211772 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3465970014 -assert nopostproc +UVM_TESTNAME =spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_08_31/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_intr_test.3465970014 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/18.spi_device_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/18.spi_device_same_csr_outstanding.3877438399 |
| Short name | T1095 |
| Test name | |
| Test status | |
| Simulation time | 228501535 ps |
| CPU time | 5.46 seconds |
| Started | Sep 01 02:45:47 PM UTC 24 |
| Finished | Sep 01 02:45:53 PM UTC 24 |
| Peak memory | 225064 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3877438399 -assert nop ostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_same_csr_outstan ding.3877438399 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/18.spi_device_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/18.spi_device_tl_errors.1318157015 |
| Short name | T1096 |
| Test name | |
| Test status | |
| Simulation time | 259974854 ps |
| CPU time | 6.83 seconds |
| Started | Sep 01 02:45:45 PM UTC 24 |
| Finished | Sep 01 02:45:53 PM UTC 24 |
| Peak memory | 225200 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1318157015 -assert nopostproc +UVM_TESTNAME =spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_08_31/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_tl_errors.1318157015 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/18.spi_device_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/18.spi_device_tl_intg_err.597387852 |
| Short name | T1131 |
| Test name | |
| Test status | |
| Simulation time | 1722657303 ps |
| CPU time | 15.69 seconds |
| Started | Sep 01 02:45:45 PM UTC 24 |
| Finished | Sep 01 02:46:02 PM UTC 24 |
| Peak memory | 227112 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=597387852 -assert nopostproc +U VM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_tl_intg_err.597387852 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/18.spi_device_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/19.spi_device_csr_mem_rw_with_rand_reset.3072428813 |
| Short name | T1102 |
| Test name | |
| Test status | |
| Simulation time | 51964574 ps |
| CPU time | 2.8 seconds |
| Started | Sep 01 02:45:50 PM UTC 24 |
| Finished | Sep 01 02:45:54 PM UTC 24 |
| Peak memory | 227360 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000 000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb _random_seed=3072428813 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_ name 19.spi_device_csr_mem_rw_with_rand_reset.3072428813 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/19.spi_device_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/19.spi_device_csr_rw.3748051994 |
| Short name | T1092 |
| Test name | |
| Test status | |
| Simulation time | 47679137 ps |
| CPU time | 2.16 seconds |
| Started | Sep 01 02:45:49 PM UTC 24 |
| Finished | Sep 01 02:45:52 PM UTC 24 |
| Peak memory | 214772 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3748051994 -assert nopostproc +UVM_TESTN AME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_csr_rw.3748051994 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/19.spi_device_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/19.spi_device_intr_test.2467991110 |
| Short name | T1090 |
| Test name | |
| Test status | |
| Simulation time | 48180231 ps |
| CPU time | 1.12 seconds |
| Started | Sep 01 02:45:49 PM UTC 24 |
| Finished | Sep 01 02:45:51 PM UTC 24 |
| Peak memory | 211772 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2467991110 -assert nopostproc +UVM_TESTNAME =spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_08_31/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_intr_test.2467991110 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/19.spi_device_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/19.spi_device_same_csr_outstanding.1775290522 |
| Short name | T1103 |
| Test name | |
| Test status | |
| Simulation time | 44143829 ps |
| CPU time | 4.25 seconds |
| Started | Sep 01 02:45:49 PM UTC 24 |
| Finished | Sep 01 02:45:54 PM UTC 24 |
| Peak memory | 225060 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1775290522 -assert nop ostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_same_csr_outstan ding.1775290522 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/19.spi_device_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/19.spi_device_tl_errors.330733982 |
| Short name | T1091 |
| Test name | |
| Test status | |
| Simulation time | 96529261 ps |
| CPU time | 3.15 seconds |
| Started | Sep 01 02:45:48 PM UTC 24 |
| Finished | Sep 01 02:45:52 PM UTC 24 |
| Peak memory | 225260 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=330733982 -assert nopostproc +UVM_TESTNAME= spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_08_31/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_tl_errors.330733982 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/19.spi_device_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/19.spi_device_tl_intg_err.3825319297 |
| Short name | T1125 |
| Test name | |
| Test status | |
| Simulation time | 2542827409 ps |
| CPU time | 8.85 seconds |
| Started | Sep 01 02:45:49 PM UTC 24 |
| Finished | Sep 01 02:45:59 PM UTC 24 |
| Peak memory | 225344 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3825319297 -assert nopostproc + UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_tl_intg_err.3825319297 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/19.spi_device_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/2.spi_device_csr_aliasing.3739537346 |
| Short name | T176 |
| Test name | |
| Test status | |
| Simulation time | 4627108064 ps |
| CPU time | 29.52 seconds |
| Started | Sep 01 02:44:59 PM UTC 24 |
| Finished | Sep 01 02:45:30 PM UTC 24 |
| Peak memory | 225208 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3739537346 -assert nopostproc +UVM _TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_csr_aliasing.3739537346 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/2.spi_device_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/2.spi_device_csr_bit_bash.4044489692 |
| Short name | T146 |
| Test name | |
| Test status | |
| Simulation time | 1082801338 ps |
| CPU time | 13.32 seconds |
| Started | Sep 01 02:44:58 PM UTC 24 |
| Finished | Sep 01 02:45:12 PM UTC 24 |
| Peak memory | 215024 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4044489692 -assert nopostproc +UVM _TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_csr_bit_bash.4044489692 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/2.spi_device_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/2.spi_device_csr_hw_reset.4285140900 |
| Short name | T107 |
| Test name | |
| Test status | |
| Simulation time | 55738045 ps |
| CPU time | 1.44 seconds |
| Started | Sep 01 02:44:57 PM UTC 24 |
| Finished | Sep 01 02:44:59 PM UTC 24 |
| Peak memory | 214024 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4285140900 -assert nopostproc +UVM _TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_csr_hw_reset.4285140900 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/2.spi_device_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/2.spi_device_csr_mem_rw_with_rand_reset.1377734656 |
| Short name | T135 |
| Test name | |
| Test status | |
| Simulation time | 95177495 ps |
| CPU time | 4.71 seconds |
| Started | Sep 01 02:44:59 PM UTC 24 |
| Finished | Sep 01 02:45:05 PM UTC 24 |
| Peak memory | 229172 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000 000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb _random_seed=1377734656 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_ name 2.spi_device_csr_mem_rw_with_rand_reset.1377734656 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/2.spi_device_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/2.spi_device_csr_rw.639235256 |
| Short name | T142 |
| Test name | |
| Test status | |
| Simulation time | 41477543 ps |
| CPU time | 1.85 seconds |
| Started | Sep 01 02:44:57 PM UTC 24 |
| Finished | Sep 01 02:44:59 PM UTC 24 |
| Peak memory | 213668 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=639235256 -assert nopostproc +UVM_TESTNA ME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_csr_rw.639235256 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/2.spi_device_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/2.spi_device_intr_test.581313037 |
| Short name | T1019 |
| Test name | |
| Test status | |
| Simulation time | 22229405 ps |
| CPU time | 1.18 seconds |
| Started | Sep 01 02:44:55 PM UTC 24 |
| Finished | Sep 01 02:44:58 PM UTC 24 |
| Peak memory | 211764 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=581313037 -assert nopostproc +UVM_TESTNAME= spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_08_31/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_intr_test.581313037 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/2.spi_device_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/2.spi_device_mem_partial_access.47230495 |
| Short name | T143 |
| Test name | |
| Test status | |
| Simulation time | 133708063 ps |
| CPU time | 3.43 seconds |
| Started | Sep 01 02:44:55 PM UTC 24 |
| Finished | Sep 01 02:45:00 PM UTC 24 |
| Peak memory | 225004 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=47230495 -assert nopostp roc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_mem_partial_access.47230495 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/2.spi_device_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/2.spi_device_mem_walk.143793853 |
| Short name | T1018 |
| Test name | |
| Test status | |
| Simulation time | 12201457 ps |
| CPU time | 1 seconds |
| Started | Sep 01 02:44:55 PM UTC 24 |
| Finished | Sep 01 02:44:57 PM UTC 24 |
| Peak memory | 211752 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=143793853 -assert nopostproc +UVM_ TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_mem_walk.143793853 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/2.spi_device_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/2.spi_device_same_csr_outstanding.1266326655 |
| Short name | T171 |
| Test name | |
| Test status | |
| Simulation time | 81997353 ps |
| CPU time | 3.06 seconds |
| Started | Sep 01 02:44:59 PM UTC 24 |
| Finished | Sep 01 02:45:03 PM UTC 24 |
| Peak memory | 225084 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1266326655 -assert nop ostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_same_csr_outstand ing.1266326655 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/2.spi_device_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/2.spi_device_tl_errors.3887399172 |
| Short name | T119 |
| Test name | |
| Test status | |
| Simulation time | 79349239 ps |
| CPU time | 2.83 seconds |
| Started | Sep 01 02:44:54 PM UTC 24 |
| Finished | Sep 01 02:44:58 PM UTC 24 |
| Peak memory | 227280 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3887399172 -assert nopostproc +UVM_TESTNAME =spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_08_31/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_tl_errors.3887399172 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/2.spi_device_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/20.spi_device_intr_test.427795470 |
| Short name | T1093 |
| Test name | |
| Test status | |
| Simulation time | 37466234 ps |
| CPU time | 1.09 seconds |
| Started | Sep 01 02:45:50 PM UTC 24 |
| Finished | Sep 01 02:45:52 PM UTC 24 |
| Peak memory | 211768 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=427795470 -assert nopostproc +UVM_TESTNAME= spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_08_31/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.spi_device_intr_test.427795470 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/20.spi_device_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/21.spi_device_intr_test.412201496 |
| Short name | T1094 |
| Test name | |
| Test status | |
| Simulation time | 32081216 ps |
| CPU time | 1.14 seconds |
| Started | Sep 01 02:45:50 PM UTC 24 |
| Finished | Sep 01 02:45:52 PM UTC 24 |
| Peak memory | 211768 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=412201496 -assert nopostproc +UVM_TESTNAME= spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_08_31/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.spi_device_intr_test.412201496 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/21.spi_device_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/22.spi_device_intr_test.2653772503 |
| Short name | T1098 |
| Test name | |
| Test status | |
| Simulation time | 49027272 ps |
| CPU time | 1.13 seconds |
| Started | Sep 01 02:45:51 PM UTC 24 |
| Finished | Sep 01 02:45:53 PM UTC 24 |
| Peak memory | 211772 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2653772503 -assert nopostproc +UVM_TESTNAME =spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_08_31/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.spi_device_intr_test.2653772503 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/22.spi_device_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/23.spi_device_intr_test.1603053260 |
| Short name | T1099 |
| Test name | |
| Test status | |
| Simulation time | 30142431 ps |
| CPU time | 1.09 seconds |
| Started | Sep 01 02:45:51 PM UTC 24 |
| Finished | Sep 01 02:45:53 PM UTC 24 |
| Peak memory | 211772 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1603053260 -assert nopostproc +UVM_TESTNAME =spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_08_31/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.spi_device_intr_test.1603053260 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/23.spi_device_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/24.spi_device_intr_test.1622080906 |
| Short name | T1101 |
| Test name | |
| Test status | |
| Simulation time | 27231185 ps |
| CPU time | 1.2 seconds |
| Started | Sep 01 02:45:51 PM UTC 24 |
| Finished | Sep 01 02:45:54 PM UTC 24 |
| Peak memory | 211772 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1622080906 -assert nopostproc +UVM_TESTNAME =spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_08_31/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.spi_device_intr_test.1622080906 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/24.spi_device_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/25.spi_device_intr_test.2950715852 |
| Short name | T1100 |
| Test name | |
| Test status | |
| Simulation time | 14181974 ps |
| CPU time | 1.04 seconds |
| Started | Sep 01 02:45:51 PM UTC 24 |
| Finished | Sep 01 02:45:53 PM UTC 24 |
| Peak memory | 211772 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2950715852 -assert nopostproc +UVM_TESTNAME =spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_08_31/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.spi_device_intr_test.2950715852 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/25.spi_device_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/26.spi_device_intr_test.3359134173 |
| Short name | T1104 |
| Test name | |
| Test status | |
| Simulation time | 31099583 ps |
| CPU time | 1.04 seconds |
| Started | Sep 01 02:45:52 PM UTC 24 |
| Finished | Sep 01 02:45:55 PM UTC 24 |
| Peak memory | 211772 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3359134173 -assert nopostproc +UVM_TESTNAME =spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_08_31/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.spi_device_intr_test.3359134173 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/26.spi_device_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/27.spi_device_intr_test.1594989329 |
| Short name | T1105 |
| Test name | |
| Test status | |
| Simulation time | 10367116 ps |
| CPU time | 1.03 seconds |
| Started | Sep 01 02:45:52 PM UTC 24 |
| Finished | Sep 01 02:45:55 PM UTC 24 |
| Peak memory | 211772 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1594989329 -assert nopostproc +UVM_TESTNAME =spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_08_31/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.spi_device_intr_test.1594989329 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/27.spi_device_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/28.spi_device_intr_test.3083495369 |
| Short name | T1106 |
| Test name | |
| Test status | |
| Simulation time | 54267638 ps |
| CPU time | 1.09 seconds |
| Started | Sep 01 02:45:52 PM UTC 24 |
| Finished | Sep 01 02:45:55 PM UTC 24 |
| Peak memory | 211772 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3083495369 -assert nopostproc +UVM_TESTNAME =spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_08_31/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.spi_device_intr_test.3083495369 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/28.spi_device_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/29.spi_device_intr_test.2923248978 |
| Short name | T1108 |
| Test name | |
| Test status | |
| Simulation time | 22092438 ps |
| CPU time | 1.16 seconds |
| Started | Sep 01 02:45:54 PM UTC 24 |
| Finished | Sep 01 02:45:56 PM UTC 24 |
| Peak memory | 211772 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2923248978 -assert nopostproc +UVM_TESTNAME =spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_08_31/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.spi_device_intr_test.2923248978 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/29.spi_device_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/3.spi_device_csr_aliasing.681603968 |
| Short name | T1050 |
| Test name | |
| Test status | |
| Simulation time | 5071790456 ps |
| CPU time | 29.68 seconds |
| Started | Sep 01 02:45:03 PM UTC 24 |
| Finished | Sep 01 02:45:35 PM UTC 24 |
| Peak memory | 225212 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=681603968 -assert nopostproc +UVM_ TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_csr_aliasing.681603968 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/3.spi_device_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/3.spi_device_csr_bit_bash.308859551 |
| Short name | T1031 |
| Test name | |
| Test status | |
| Simulation time | 638638621 ps |
| CPU time | 16.19 seconds |
| Started | Sep 01 02:45:03 PM UTC 24 |
| Finished | Sep 01 02:45:21 PM UTC 24 |
| Peak memory | 214732 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=308859551 -assert nopostproc +UVM_ TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_csr_bit_bash.308859551 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/3.spi_device_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/3.spi_device_csr_hw_reset.2233353687 |
| Short name | T108 |
| Test name | |
| Test status | |
| Simulation time | 19478887 ps |
| CPU time | 1.68 seconds |
| Started | Sep 01 02:45:01 PM UTC 24 |
| Finished | Sep 01 02:45:04 PM UTC 24 |
| Peak memory | 226300 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2233353687 -assert nopostproc +UVM _TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_csr_hw_reset.2233353687 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/3.spi_device_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/3.spi_device_csr_mem_rw_with_rand_reset.1623329688 |
| Short name | T137 |
| Test name | |
| Test status | |
| Simulation time | 559884772 ps |
| CPU time | 4.45 seconds |
| Started | Sep 01 02:45:05 PM UTC 24 |
| Finished | Sep 01 02:45:10 PM UTC 24 |
| Peak memory | 227200 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000 000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb _random_seed=1623329688 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_ name 3.spi_device_csr_mem_rw_with_rand_reset.1623329688 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/3.spi_device_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/3.spi_device_csr_rw.4214717747 |
| Short name | T1024 |
| Test name | |
| Test status | |
| Simulation time | 32853677 ps |
| CPU time | 1.73 seconds |
| Started | Sep 01 02:45:01 PM UTC 24 |
| Finished | Sep 01 02:45:04 PM UTC 24 |
| Peak memory | 213668 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4214717747 -assert nopostproc +UVM_TESTN AME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_csr_rw.4214717747 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/3.spi_device_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/3.spi_device_intr_test.1291881789 |
| Short name | T1022 |
| Test name | |
| Test status | |
| Simulation time | 47035361 ps |
| CPU time | 1.19 seconds |
| Started | Sep 01 02:45:00 PM UTC 24 |
| Finished | Sep 01 02:45:02 PM UTC 24 |
| Peak memory | 211764 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1291881789 -assert nopostproc +UVM_TESTNAME =spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_08_31/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_intr_test.1291881789 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/3.spi_device_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/3.spi_device_mem_partial_access.85917456 |
| Short name | T144 |
| Test name | |
| Test status | |
| Simulation time | 115511142 ps |
| CPU time | 2.14 seconds |
| Started | Sep 01 02:45:00 PM UTC 24 |
| Finished | Sep 01 02:45:03 PM UTC 24 |
| Peak memory | 225088 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=85917456 -assert nopostp roc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_mem_partial_access.85917456 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/3.spi_device_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/3.spi_device_mem_walk.1312651578 |
| Short name | T1021 |
| Test name | |
| Test status | |
| Simulation time | 34618803 ps |
| CPU time | 1.01 seconds |
| Started | Sep 01 02:45:00 PM UTC 24 |
| Finished | Sep 01 02:45:02 PM UTC 24 |
| Peak memory | 211760 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1312651578 -assert nopostproc +UVM _TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_mem_walk.1312651578 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/3.spi_device_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/3.spi_device_same_csr_outstanding.2414547599 |
| Short name | T1027 |
| Test name | |
| Test status | |
| Simulation time | 310894343 ps |
| CPU time | 5.86 seconds |
| Started | Sep 01 02:45:04 PM UTC 24 |
| Finished | Sep 01 02:45:10 PM UTC 24 |
| Peak memory | 225328 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2414547599 -assert nop ostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_same_csr_outstand ing.2414547599 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/3.spi_device_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/3.spi_device_tl_errors.674278424 |
| Short name | T126 |
| Test name | |
| Test status | |
| Simulation time | 3478468554 ps |
| CPU time | 6.39 seconds |
| Started | Sep 01 02:44:59 PM UTC 24 |
| Finished | Sep 01 02:45:06 PM UTC 24 |
| Peak memory | 225284 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=674278424 -assert nopostproc +UVM_TESTNAME= spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_08_31/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_tl_errors.674278424 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/3.spi_device_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/3.spi_device_tl_intg_err.1500950877 |
| Short name | T118 |
| Test name | |
| Test status | |
| Simulation time | 315482119 ps |
| CPU time | 25.47 seconds |
| Started | Sep 01 02:45:00 PM UTC 24 |
| Finished | Sep 01 02:45:27 PM UTC 24 |
| Peak memory | 224988 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1500950877 -assert nopostproc + UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_tl_intg_err.1500950877 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/3.spi_device_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/30.spi_device_intr_test.151297951 |
| Short name | T1107 |
| Test name | |
| Test status | |
| Simulation time | 12854689 ps |
| CPU time | 1.04 seconds |
| Started | Sep 01 02:45:54 PM UTC 24 |
| Finished | Sep 01 02:45:56 PM UTC 24 |
| Peak memory | 211768 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=151297951 -assert nopostproc +UVM_TESTNAME= spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_08_31/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.spi_device_intr_test.151297951 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/30.spi_device_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/31.spi_device_intr_test.2466008318 |
| Short name | T1111 |
| Test name | |
| Test status | |
| Simulation time | 15655867 ps |
| CPU time | 1.13 seconds |
| Started | Sep 01 02:45:54 PM UTC 24 |
| Finished | Sep 01 02:45:56 PM UTC 24 |
| Peak memory | 211772 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2466008318 -assert nopostproc +UVM_TESTNAME =spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_08_31/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.spi_device_intr_test.2466008318 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/31.spi_device_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/32.spi_device_intr_test.3704994346 |
| Short name | T1109 |
| Test name | |
| Test status | |
| Simulation time | 37749224 ps |
| CPU time | 1.05 seconds |
| Started | Sep 01 02:45:54 PM UTC 24 |
| Finished | Sep 01 02:45:56 PM UTC 24 |
| Peak memory | 211772 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3704994346 -assert nopostproc +UVM_TESTNAME =spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_08_31/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.spi_device_intr_test.3704994346 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/32.spi_device_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/33.spi_device_intr_test.3604522537 |
| Short name | T1110 |
| Test name | |
| Test status | |
| Simulation time | 14283816 ps |
| CPU time | 1.1 seconds |
| Started | Sep 01 02:45:54 PM UTC 24 |
| Finished | Sep 01 02:45:56 PM UTC 24 |
| Peak memory | 211772 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3604522537 -assert nopostproc +UVM_TESTNAME =spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_08_31/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.spi_device_intr_test.3604522537 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/33.spi_device_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/34.spi_device_intr_test.1540223166 |
| Short name | T1113 |
| Test name | |
| Test status | |
| Simulation time | 13126979 ps |
| CPU time | 1.11 seconds |
| Started | Sep 01 02:45:54 PM UTC 24 |
| Finished | Sep 01 02:45:56 PM UTC 24 |
| Peak memory | 211772 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1540223166 -assert nopostproc +UVM_TESTNAME =spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_08_31/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.spi_device_intr_test.1540223166 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/34.spi_device_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/35.spi_device_intr_test.3693502120 |
| Short name | T1112 |
| Test name | |
| Test status | |
| Simulation time | 34153115 ps |
| CPU time | 1.08 seconds |
| Started | Sep 01 02:45:54 PM UTC 24 |
| Finished | Sep 01 02:45:56 PM UTC 24 |
| Peak memory | 211772 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3693502120 -assert nopostproc +UVM_TESTNAME =spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_08_31/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.spi_device_intr_test.3693502120 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/35.spi_device_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/36.spi_device_intr_test.3667176939 |
| Short name | T1114 |
| Test name | |
| Test status | |
| Simulation time | 39533075 ps |
| CPU time | 1.11 seconds |
| Started | Sep 01 02:45:55 PM UTC 24 |
| Finished | Sep 01 02:45:57 PM UTC 24 |
| Peak memory | 211772 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3667176939 -assert nopostproc +UVM_TESTNAME =spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_08_31/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.spi_device_intr_test.3667176939 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/36.spi_device_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/37.spi_device_intr_test.401348003 |
| Short name | T1115 |
| Test name | |
| Test status | |
| Simulation time | 31532266 ps |
| CPU time | 1.11 seconds |
| Started | Sep 01 02:45:55 PM UTC 24 |
| Finished | Sep 01 02:45:57 PM UTC 24 |
| Peak memory | 211768 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=401348003 -assert nopostproc +UVM_TESTNAME= spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_08_31/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.spi_device_intr_test.401348003 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/37.spi_device_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/38.spi_device_intr_test.1015643940 |
| Short name | T1116 |
| Test name | |
| Test status | |
| Simulation time | 12530487 ps |
| CPU time | 1.15 seconds |
| Started | Sep 01 02:45:55 PM UTC 24 |
| Finished | Sep 01 02:45:57 PM UTC 24 |
| Peak memory | 211772 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1015643940 -assert nopostproc +UVM_TESTNAME =spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_08_31/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.spi_device_intr_test.1015643940 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/38.spi_device_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/39.spi_device_intr_test.2974049617 |
| Short name | T1118 |
| Test name | |
| Test status | |
| Simulation time | 16645449 ps |
| CPU time | 1.09 seconds |
| Started | Sep 01 02:45:55 PM UTC 24 |
| Finished | Sep 01 02:45:57 PM UTC 24 |
| Peak memory | 211748 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2974049617 -assert nopostproc +UVM_TESTNAME =spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_08_31/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.spi_device_intr_test.2974049617 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/39.spi_device_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/4.spi_device_csr_aliasing.1405724311 |
| Short name | T1067 |
| Test name | |
| Test status | |
| Simulation time | 5639150499 ps |
| CPU time | 29.26 seconds |
| Started | Sep 01 02:45:11 PM UTC 24 |
| Finished | Sep 01 02:45:42 PM UTC 24 |
| Peak memory | 227176 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1405724311 -assert nopostproc +UVM _TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_csr_aliasing.1405724311 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/4.spi_device_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/4.spi_device_csr_bit_bash.3827098898 |
| Short name | T1056 |
| Test name | |
| Test status | |
| Simulation time | 1258116455 ps |
| CPU time | 25.17 seconds |
| Started | Sep 01 02:45:11 PM UTC 24 |
| Finished | Sep 01 02:45:38 PM UTC 24 |
| Peak memory | 214708 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3827098898 -assert nopostproc +UVM _TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_csr_bit_bash.3827098898 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/4.spi_device_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/4.spi_device_csr_hw_reset.368657307 |
| Short name | T109 |
| Test name | |
| Test status | |
| Simulation time | 41172418 ps |
| CPU time | 1.45 seconds |
| Started | Sep 01 02:45:08 PM UTC 24 |
| Finished | Sep 01 02:45:10 PM UTC 24 |
| Peak memory | 213960 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=368657307 -assert nopostproc +UVM_ TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_csr_hw_reset.368657307 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/4.spi_device_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/4.spi_device_csr_mem_rw_with_rand_reset.1656882920 |
| Short name | T133 |
| Test name | |
| Test status | |
| Simulation time | 105695813 ps |
| CPU time | 2.75 seconds |
| Started | Sep 01 02:45:11 PM UTC 24 |
| Finished | Sep 01 02:45:15 PM UTC 24 |
| Peak memory | 227392 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000 000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb _random_seed=1656882920 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_ name 4.spi_device_csr_mem_rw_with_rand_reset.1656882920 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/4.spi_device_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/4.spi_device_csr_rw.1018579437 |
| Short name | T147 |
| Test name | |
| Test status | |
| Simulation time | 142942679 ps |
| CPU time | 3.99 seconds |
| Started | Sep 01 02:45:09 PM UTC 24 |
| Finished | Sep 01 02:45:14 PM UTC 24 |
| Peak memory | 225056 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1018579437 -assert nopostproc +UVM_TESTN AME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_csr_rw.1018579437 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/4.spi_device_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/4.spi_device_intr_test.1582670557 |
| Short name | T1025 |
| Test name | |
| Test status | |
| Simulation time | 16212706 ps |
| CPU time | 0.94 seconds |
| Started | Sep 01 02:45:05 PM UTC 24 |
| Finished | Sep 01 02:45:07 PM UTC 24 |
| Peak memory | 211764 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1582670557 -assert nopostproc +UVM_TESTNAME =spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_08_31/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_intr_test.1582670557 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/4.spi_device_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/4.spi_device_mem_partial_access.583220569 |
| Short name | T145 |
| Test name | |
| Test status | |
| Simulation time | 25798693 ps |
| CPU time | 2.22 seconds |
| Started | Sep 01 02:45:07 PM UTC 24 |
| Finished | Sep 01 02:45:10 PM UTC 24 |
| Peak memory | 225048 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=583220569 -assert nopost proc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep o/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_mem_partial_access.583220569 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/4.spi_device_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/4.spi_device_mem_walk.4102692577 |
| Short name | T1026 |
| Test name | |
| Test status | |
| Simulation time | 12670964 ps |
| CPU time | 1.04 seconds |
| Started | Sep 01 02:45:06 PM UTC 24 |
| Finished | Sep 01 02:45:08 PM UTC 24 |
| Peak memory | 211760 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4102692577 -assert nopostproc +UVM _TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_mem_walk.4102692577 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/4.spi_device_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/4.spi_device_same_csr_outstanding.301750142 |
| Short name | T1028 |
| Test name | |
| Test status | |
| Simulation time | 103695429 ps |
| CPU time | 2.59 seconds |
| Started | Sep 01 02:45:11 PM UTC 24 |
| Finished | Sep 01 02:45:15 PM UTC 24 |
| Peak memory | 215000 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=301750142 -assert nopo stproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r epo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_same_csr_outstanding.301750142 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/4.spi_device_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/4.spi_device_tl_errors.2003305126 |
| Short name | T127 |
| Test name | |
| Test status | |
| Simulation time | 1649861124 ps |
| CPU time | 6.67 seconds |
| Started | Sep 01 02:45:05 PM UTC 24 |
| Finished | Sep 01 02:45:12 PM UTC 24 |
| Peak memory | 231340 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2003305126 -assert nopostproc +UVM_TESTNAME =spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_08_31/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_tl_errors.2003305126 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/4.spi_device_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/4.spi_device_tl_intg_err.628065238 |
| Short name | T210 |
| Test name | |
| Test status | |
| Simulation time | 2474958486 ps |
| CPU time | 19.54 seconds |
| Started | Sep 01 02:45:05 PM UTC 24 |
| Finished | Sep 01 02:45:25 PM UTC 24 |
| Peak memory | 233228 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=628065238 -assert nopostproc +U VM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_tl_intg_err.628065238 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/4.spi_device_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/40.spi_device_intr_test.694667940 |
| Short name | T1119 |
| Test name | |
| Test status | |
| Simulation time | 32814551 ps |
| CPU time | 1.16 seconds |
| Started | Sep 01 02:45:55 PM UTC 24 |
| Finished | Sep 01 02:45:57 PM UTC 24 |
| Peak memory | 211744 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=694667940 -assert nopostproc +UVM_TESTNAME= spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_08_31/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.spi_device_intr_test.694667940 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/40.spi_device_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/41.spi_device_intr_test.182081263 |
| Short name | T1117 |
| Test name | |
| Test status | |
| Simulation time | 58599310 ps |
| CPU time | 1.05 seconds |
| Started | Sep 01 02:45:55 PM UTC 24 |
| Finished | Sep 01 02:45:57 PM UTC 24 |
| Peak memory | 211696 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=182081263 -assert nopostproc +UVM_TESTNAME= spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_08_31/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.spi_device_intr_test.182081263 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/41.spi_device_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/42.spi_device_intr_test.72869607 |
| Short name | T1120 |
| Test name | |
| Test status | |
| Simulation time | 13451254 ps |
| CPU time | 1.07 seconds |
| Started | Sep 01 02:45:55 PM UTC 24 |
| Finished | Sep 01 02:45:57 PM UTC 24 |
| Peak memory | 211764 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=72869607 -assert nopostproc +UVM_TESTNAME=s pi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_08_31/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.spi_device_intr_test.72869607 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/42.spi_device_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/43.spi_device_intr_test.3874450070 |
| Short name | T1121 |
| Test name | |
| Test status | |
| Simulation time | 74639644 ps |
| CPU time | 1.15 seconds |
| Started | Sep 01 02:45:55 PM UTC 24 |
| Finished | Sep 01 02:45:58 PM UTC 24 |
| Peak memory | 211772 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3874450070 -assert nopostproc +UVM_TESTNAME =spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_08_31/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.spi_device_intr_test.3874450070 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/43.spi_device_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/44.spi_device_intr_test.2884646365 |
| Short name | T1122 |
| Test name | |
| Test status | |
| Simulation time | 58907418 ps |
| CPU time | 1.18 seconds |
| Started | Sep 01 02:45:55 PM UTC 24 |
| Finished | Sep 01 02:45:58 PM UTC 24 |
| Peak memory | 211772 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2884646365 -assert nopostproc +UVM_TESTNAME =spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_08_31/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.spi_device_intr_test.2884646365 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/44.spi_device_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/45.spi_device_intr_test.2354079969 |
| Short name | T1124 |
| Test name | |
| Test status | |
| Simulation time | 12165963 ps |
| CPU time | 1.1 seconds |
| Started | Sep 01 02:45:57 PM UTC 24 |
| Finished | Sep 01 02:45:59 PM UTC 24 |
| Peak memory | 211772 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2354079969 -assert nopostproc +UVM_TESTNAME =spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_08_31/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.spi_device_intr_test.2354079969 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/45.spi_device_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/46.spi_device_intr_test.2551155666 |
| Short name | T1126 |
| Test name | |
| Test status | |
| Simulation time | 41181688 ps |
| CPU time | 1.1 seconds |
| Started | Sep 01 02:45:57 PM UTC 24 |
| Finished | Sep 01 02:45:59 PM UTC 24 |
| Peak memory | 211772 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2551155666 -assert nopostproc +UVM_TESTNAME =spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_08_31/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.spi_device_intr_test.2551155666 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/46.spi_device_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/47.spi_device_intr_test.3687401010 |
| Short name | T1127 |
| Test name | |
| Test status | |
| Simulation time | 86189686 ps |
| CPU time | 1.07 seconds |
| Started | Sep 01 02:45:57 PM UTC 24 |
| Finished | Sep 01 02:45:59 PM UTC 24 |
| Peak memory | 211772 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3687401010 -assert nopostproc +UVM_TESTNAME =spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_08_31/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.spi_device_intr_test.3687401010 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/47.spi_device_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/48.spi_device_intr_test.1511416527 |
| Short name | T1128 |
| Test name | |
| Test status | |
| Simulation time | 31939831 ps |
| CPU time | 1.11 seconds |
| Started | Sep 01 02:45:57 PM UTC 24 |
| Finished | Sep 01 02:45:59 PM UTC 24 |
| Peak memory | 211772 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1511416527 -assert nopostproc +UVM_TESTNAME =spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_08_31/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.spi_device_intr_test.1511416527 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/48.spi_device_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/49.spi_device_intr_test.3284412412 |
| Short name | T1129 |
| Test name | |
| Test status | |
| Simulation time | 11237757 ps |
| CPU time | 1.09 seconds |
| Started | Sep 01 02:45:57 PM UTC 24 |
| Finished | Sep 01 02:45:59 PM UTC 24 |
| Peak memory | 211772 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3284412412 -assert nopostproc +UVM_TESTNAME =spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_08_31/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.spi_device_intr_test.3284412412 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/49.spi_device_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/5.spi_device_csr_mem_rw_with_rand_reset.3140899952 |
| Short name | T1033 |
| Test name | |
| Test status | |
| Simulation time | 139590463 ps |
| CPU time | 3.29 seconds |
| Started | Sep 01 02:45:17 PM UTC 24 |
| Finished | Sep 01 02:45:21 PM UTC 24 |
| Peak memory | 227456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000 000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb _random_seed=3140899952 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_ name 5.spi_device_csr_mem_rw_with_rand_reset.3140899952 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/5.spi_device_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/5.spi_device_csr_rw.3556967713 |
| Short name | T148 |
| Test name | |
| Test status | |
| Simulation time | 301448731 ps |
| CPU time | 3.1 seconds |
| Started | Sep 01 02:45:16 PM UTC 24 |
| Finished | Sep 01 02:45:20 PM UTC 24 |
| Peak memory | 225060 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3556967713 -assert nopostproc +UVM_TESTN AME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_csr_rw.3556967713 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/5.spi_device_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/5.spi_device_intr_test.3238315435 |
| Short name | T1029 |
| Test name | |
| Test status | |
| Simulation time | 23338028 ps |
| CPU time | 1.07 seconds |
| Started | Sep 01 02:45:14 PM UTC 24 |
| Finished | Sep 01 02:45:17 PM UTC 24 |
| Peak memory | 211764 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3238315435 -assert nopostproc +UVM_TESTNAME =spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_08_31/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_intr_test.3238315435 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/5.spi_device_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/5.spi_device_same_csr_outstanding.3718135346 |
| Short name | T1034 |
| Test name | |
| Test status | |
| Simulation time | 165063393 ps |
| CPU time | 4.89 seconds |
| Started | Sep 01 02:45:16 PM UTC 24 |
| Finished | Sep 01 02:45:21 PM UTC 24 |
| Peak memory | 224992 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3718135346 -assert nop ostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_same_csr_outstand ing.3718135346 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/5.spi_device_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/5.spi_device_tl_errors.4040299537 |
| Short name | T131 |
| Test name | |
| Test status | |
| Simulation time | 101956766 ps |
| CPU time | 4.12 seconds |
| Started | Sep 01 02:45:13 PM UTC 24 |
| Finished | Sep 01 02:45:19 PM UTC 24 |
| Peak memory | 225136 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4040299537 -assert nopostproc +UVM_TESTNAME =spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_08_31/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_tl_errors.4040299537 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/5.spi_device_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/5.spi_device_tl_intg_err.2261215805 |
| Short name | T173 |
| Test name | |
| Test status | |
| Simulation time | 380682670 ps |
| CPU time | 11.29 seconds |
| Started | Sep 01 02:45:13 PM UTC 24 |
| Finished | Sep 01 02:45:26 PM UTC 24 |
| Peak memory | 227056 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2261215805 -assert nopostproc + UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_tl_intg_err.2261215805 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/5.spi_device_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/6.spi_device_csr_mem_rw_with_rand_reset.3063509569 |
| Short name | T1038 |
| Test name | |
| Test status | |
| Simulation time | 655810716 ps |
| CPU time | 4.56 seconds |
| Started | Sep 01 02:45:21 PM UTC 24 |
| Finished | Sep 01 02:45:27 PM UTC 24 |
| Peak memory | 229248 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000 000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb _random_seed=3063509569 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_ name 6.spi_device_csr_mem_rw_with_rand_reset.3063509569 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/6.spi_device_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/6.spi_device_csr_rw.3592264328 |
| Short name | T1035 |
| Test name | |
| Test status | |
| Simulation time | 62513824 ps |
| CPU time | 2.86 seconds |
| Started | Sep 01 02:45:20 PM UTC 24 |
| Finished | Sep 01 02:45:24 PM UTC 24 |
| Peak memory | 216868 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3592264328 -assert nopostproc +UVM_TESTN AME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_csr_rw.3592264328 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/6.spi_device_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/6.spi_device_intr_test.3694557558 |
| Short name | T1030 |
| Test name | |
| Test status | |
| Simulation time | 55430229 ps |
| CPU time | 1.11 seconds |
| Started | Sep 01 02:45:18 PM UTC 24 |
| Finished | Sep 01 02:45:20 PM UTC 24 |
| Peak memory | 211764 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3694557558 -assert nopostproc +UVM_TESTNAME =spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_08_31/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_intr_test.3694557558 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/6.spi_device_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/6.spi_device_same_csr_outstanding.700794197 |
| Short name | T174 |
| Test name | |
| Test status | |
| Simulation time | 765433715 ps |
| CPU time | 5.86 seconds |
| Started | Sep 01 02:45:20 PM UTC 24 |
| Finished | Sep 01 02:45:27 PM UTC 24 |
| Peak memory | 225036 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=700794197 -assert nopo stproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r epo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_same_csr_outstanding.700794197 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/6.spi_device_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/6.spi_device_tl_errors.2534556034 |
| Short name | T177 |
| Test name | |
| Test status | |
| Simulation time | 414075195 ps |
| CPU time | 2.67 seconds |
| Started | Sep 01 02:45:17 PM UTC 24 |
| Finished | Sep 01 02:45:20 PM UTC 24 |
| Peak memory | 225444 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2534556034 -assert nopostproc +UVM_TESTNAME =spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_08_31/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_tl_errors.2534556034 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/6.spi_device_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/6.spi_device_tl_intg_err.1875727906 |
| Short name | T175 |
| Test name | |
| Test status | |
| Simulation time | 360440447 ps |
| CPU time | 9.63 seconds |
| Started | Sep 01 02:45:17 PM UTC 24 |
| Finished | Sep 01 02:45:27 PM UTC 24 |
| Peak memory | 225072 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1875727906 -assert nopostproc + UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_tl_intg_err.1875727906 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/6.spi_device_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/7.spi_device_csr_mem_rw_with_rand_reset.1043366823 |
| Short name | T136 |
| Test name | |
| Test status | |
| Simulation time | 361978387 ps |
| CPU time | 3.24 seconds |
| Started | Sep 01 02:45:22 PM UTC 24 |
| Finished | Sep 01 02:45:27 PM UTC 24 |
| Peak memory | 227196 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000 000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb _random_seed=1043366823 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_ name 7.spi_device_csr_mem_rw_with_rand_reset.1043366823 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/7.spi_device_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/7.spi_device_csr_rw.4287194450 |
| Short name | T140 |
| Test name | |
| Test status | |
| Simulation time | 72490227 ps |
| CPU time | 3.47 seconds |
| Started | Sep 01 02:45:22 PM UTC 24 |
| Finished | Sep 01 02:45:27 PM UTC 24 |
| Peak memory | 224984 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4287194450 -assert nopostproc +UVM_TESTN AME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_csr_rw.4287194450 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/7.spi_device_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/7.spi_device_intr_test.1037062541 |
| Short name | T1036 |
| Test name | |
| Test status | |
| Simulation time | 14857758 ps |
| CPU time | 1.11 seconds |
| Started | Sep 01 02:45:22 PM UTC 24 |
| Finished | Sep 01 02:45:24 PM UTC 24 |
| Peak memory | 211764 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1037062541 -assert nopostproc +UVM_TESTNAME =spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_08_31/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_intr_test.1037062541 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/7.spi_device_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/7.spi_device_same_csr_outstanding.3959552247 |
| Short name | T1037 |
| Test name | |
| Test status | |
| Simulation time | 217348934 ps |
| CPU time | 2.62 seconds |
| Started | Sep 01 02:45:22 PM UTC 24 |
| Finished | Sep 01 02:45:26 PM UTC 24 |
| Peak memory | 225260 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3959552247 -assert nop ostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_same_csr_outstand ing.3959552247 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/7.spi_device_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/7.spi_device_tl_errors.3434677732 |
| Short name | T124 |
| Test name | |
| Test status | |
| Simulation time | 161956242 ps |
| CPU time | 5.47 seconds |
| Started | Sep 01 02:45:21 PM UTC 24 |
| Finished | Sep 01 02:45:28 PM UTC 24 |
| Peak memory | 225184 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3434677732 -assert nopostproc +UVM_TESTNAME =spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_08_31/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_tl_errors.3434677732 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/7.spi_device_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/7.spi_device_tl_intg_err.1447512413 |
| Short name | T102 |
| Test name | |
| Test status | |
| Simulation time | 1077108814 ps |
| CPU time | 9.47 seconds |
| Started | Sep 01 02:45:21 PM UTC 24 |
| Finished | Sep 01 02:45:32 PM UTC 24 |
| Peak memory | 225148 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1447512413 -assert nopostproc + UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_tl_intg_err.1447512413 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/7.spi_device_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/8.spi_device_csr_mem_rw_with_rand_reset.2871986926 |
| Short name | T178 |
| Test name | |
| Test status | |
| Simulation time | 106667940 ps |
| CPU time | 4.24 seconds |
| Started | Sep 01 02:45:27 PM UTC 24 |
| Finished | Sep 01 02:45:32 PM UTC 24 |
| Peak memory | 227372 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000 000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb _random_seed=2871986926 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_ name 8.spi_device_csr_mem_rw_with_rand_reset.2871986926 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/8.spi_device_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/8.spi_device_csr_rw.79427414 |
| Short name | T1042 |
| Test name | |
| Test status | |
| Simulation time | 35128334 ps |
| CPU time | 3.45 seconds |
| Started | Sep 01 02:45:26 PM UTC 24 |
| Finished | Sep 01 02:45:30 PM UTC 24 |
| Peak memory | 225260 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=79427414 -assert nopostproc +UVM_TESTNAM E=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_31/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_csr_rw.79427414 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/8.spi_device_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/8.spi_device_intr_test.3075033319 |
| Short name | T1040 |
| Test name | |
| Test status | |
| Simulation time | 87966213 ps |
| CPU time | 1.19 seconds |
| Started | Sep 01 02:45:26 PM UTC 24 |
| Finished | Sep 01 02:45:28 PM UTC 24 |
| Peak memory | 211764 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3075033319 -assert nopostproc +UVM_TESTNAME =spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_08_31/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_intr_test.3075033319 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/8.spi_device_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/8.spi_device_same_csr_outstanding.3420065670 |
| Short name | T1043 |
| Test name | |
| Test status | |
| Simulation time | 94906245 ps |
| CPU time | 2.54 seconds |
| Started | Sep 01 02:45:27 PM UTC 24 |
| Finished | Sep 01 02:45:30 PM UTC 24 |
| Peak memory | 225084 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3420065670 -assert nop ostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_same_csr_outstand ing.3420065670 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/8.spi_device_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/8.spi_device_tl_errors.3569486088 |
| Short name | T128 |
| Test name | |
| Test status | |
| Simulation time | 64639121 ps |
| CPU time | 3.54 seconds |
| Started | Sep 01 02:45:23 PM UTC 24 |
| Finished | Sep 01 02:45:27 PM UTC 24 |
| Peak memory | 225184 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3569486088 -assert nopostproc +UVM_TESTNAME =spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_08_31/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_tl_errors.3569486088 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/8.spi_device_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/9.spi_device_csr_mem_rw_with_rand_reset.2216140865 |
| Short name | T1045 |
| Test name | |
| Test status | |
| Simulation time | 25542622 ps |
| CPU time | 2.38 seconds |
| Started | Sep 01 02:45:28 PM UTC 24 |
| Finished | Sep 01 02:45:32 PM UTC 24 |
| Peak memory | 227264 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000 000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb _random_seed=2216140865 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_ name 9.spi_device_csr_mem_rw_with_rand_reset.2216140865 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/9.spi_device_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/9.spi_device_csr_rw.4036648803 |
| Short name | T170 |
| Test name | |
| Test status | |
| Simulation time | 89155308 ps |
| CPU time | 3.02 seconds |
| Started | Sep 01 02:45:28 PM UTC 24 |
| Finished | Sep 01 02:45:32 PM UTC 24 |
| Peak memory | 225332 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4036648803 -assert nopostproc +UVM_TESTN AME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_csr_rw.4036648803 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/9.spi_device_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/9.spi_device_intr_test.1610603059 |
| Short name | T1041 |
| Test name | |
| Test status | |
| Simulation time | 39813400 ps |
| CPU time | 0.86 seconds |
| Started | Sep 01 02:45:28 PM UTC 24 |
| Finished | Sep 01 02:45:30 PM UTC 24 |
| Peak memory | 211764 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1610603059 -assert nopostproc +UVM_TESTNAME =spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_08_31/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_intr_test.1610603059 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/9.spi_device_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/9.spi_device_same_csr_outstanding.4264573406 |
| Short name | T1047 |
| Test name | |
| Test status | |
| Simulation time | 46151699 ps |
| CPU time | 3.96 seconds |
| Started | Sep 01 02:45:28 PM UTC 24 |
| Finished | Sep 01 02:45:33 PM UTC 24 |
| Peak memory | 225188 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4264573406 -assert nop ostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_same_csr_outstand ing.4264573406 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/9.spi_device_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/9.spi_device_tl_errors.2369278177 |
| Short name | T100 |
| Test name | |
| Test status | |
| Simulation time | 50474058 ps |
| CPU time | 3.48 seconds |
| Started | Sep 01 02:45:27 PM UTC 24 |
| Finished | Sep 01 02:45:31 PM UTC 24 |
| Peak memory | 225196 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2369278177 -assert nopostproc +UVM_TESTNAME =spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_08_31/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_tl_errors.2369278177 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/9.spi_device_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/9.spi_device_tl_intg_err.1133238391 |
| Short name | T213 |
| Test name | |
| Test status | |
| Simulation time | 790366800 ps |
| CPU time | 22.48 seconds |
| Started | Sep 01 02:45:28 PM UTC 24 |
| Finished | Sep 01 02:45:52 PM UTC 24 |
| Peak memory | 225248 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1133238391 -assert nopostproc + UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_tl_intg_err.1133238391 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/9.spi_device_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/0.spi_device_cfg_cmd.3265987675 |
| Short name | T17 |
| Test name | |
| Test status | |
| Simulation time | 4224249393 ps |
| CPU time | 14.39 seconds |
| Started | Sep 01 02:46:00 PM UTC 24 |
| Finished | Sep 01 02:46:15 PM UTC 24 |
| Peak memory | 234956 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3265987675 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_cfg_cmd.3265987675 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/0.spi_device_cfg_cmd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/0.spi_device_csb_read.1904975290 |
| Short name | T1 |
| Test name | |
| Test status | |
| Simulation time | 15380084 ps |
| CPU time | 1.05 seconds |
| Started | Sep 01 02:45:57 PM UTC 24 |
| Finished | Sep 01 02:45:59 PM UTC 24 |
| Peak memory | 215604 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1904975290 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/sp i_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_csb_read.1904975290 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/0.spi_device_csb_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/0.spi_device_flash_all.709702675 |
| Short name | T51 |
| Test name | |
| Test status | |
| Simulation time | 24295235049 ps |
| CPU time | 89.3 seconds |
| Started | Sep 01 02:46:00 PM UTC 24 |
| Finished | Sep 01 02:47:31 PM UTC 24 |
| Peak memory | 249348 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=709702675 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/sp i_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_all.709702675 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/0.spi_device_flash_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/0.spi_device_flash_and_tpm.3579009615 |
| Short name | T69 |
| Test name | |
| Test status | |
| Simulation time | 42088193380 ps |
| CPU time | 113.75 seconds |
| Started | Sep 01 02:46:00 PM UTC 24 |
| Finished | Sep 01 02:47:56 PM UTC 24 |
| Peak memory | 245388 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3579009615 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_ 31/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_and_tpm.3579009615 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/0.spi_device_flash_and_tpm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/0.spi_device_flash_and_tpm_min_idle.1931245502 |
| Short name | T194 |
| Test name | |
| Test status | |
| Simulation time | 497882948067 ps |
| CPU time | 467.54 seconds |
| Started | Sep 01 02:46:00 PM UTC 24 |
| Finished | Sep 01 02:53:54 PM UTC 24 |
| Peak memory | 265852 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1931245502 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_31/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_and_tpm_min_idle.1931245502 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/0.spi_device_flash_and_tpm_min_idle/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/0.spi_device_flash_mode_ignore_cmds.3460845630 |
| Short name | T216 |
| Test name | |
| Test status | |
| Simulation time | 28830214524 ps |
| CPU time | 255.32 seconds |
| Started | Sep 01 02:46:00 PM UTC 24 |
| Finished | Sep 01 02:50:19 PM UTC 24 |
| Peak memory | 263740 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3460845630 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_31/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_mode_ignore_cmds.3460845630 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/0.spi_device_flash_mode_ignore_cmds/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/0.spi_device_intercept.1850168433 |
| Short name | T18 |
| Test name | |
| Test status | |
| Simulation time | 3695305579 ps |
| CPU time | 16.97 seconds |
| Started | Sep 01 02:45:58 PM UTC 24 |
| Finished | Sep 01 02:46:17 PM UTC 24 |
| Peak memory | 245412 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1850168433 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/s pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_intercept.1850168433 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/0.spi_device_intercept/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/0.spi_device_mailbox.2097236427 |
| Short name | T54 |
| Test name | |
| Test status | |
| Simulation time | 6785554086 ps |
| CPU time | 26.96 seconds |
| Started | Sep 01 02:45:59 PM UTC 24 |
| Finished | Sep 01 02:46:28 PM UTC 24 |
| Peak memory | 245344 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2097236427 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_mailbox.2097236427 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/0.spi_device_mailbox/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/0.spi_device_pass_addr_payload_swap.2997232745 |
| Short name | T60 |
| Test name | |
| Test status | |
| Simulation time | 12778178509 ps |
| CPU time | 36.25 seconds |
| Started | Sep 01 02:45:58 PM UTC 24 |
| Finished | Sep 01 02:46:36 PM UTC 24 |
| Peak memory | 235032 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2997232745 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_31/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_pass_addr_payload_swap.2997232745 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/0.spi_device_pass_addr_payload_swap/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/0.spi_device_read_buffer_direct.4255317355 |
| Short name | T16 |
| Test name | |
| Test status | |
| Simulation time | 3581107445 ps |
| CPU time | 13.68 seconds |
| Started | Sep 01 02:46:00 PM UTC 24 |
| Finished | Sep 01 02:46:15 PM UTC 24 |
| Peak memory | 233656 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4255317355 -assert nopostproc +UVM_TESTNAME=spi_device _base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_read_buffer_direct.4255317355 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/0.spi_device_read_buffer_direct/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/0.spi_device_tpm_rw.2886732662 |
| Short name | T3 |
| Test name | |
| Test status | |
| Simulation time | 75317680 ps |
| CPU time | 0.95 seconds |
| Started | Sep 01 02:45:58 PM UTC 24 |
| Finished | Sep 01 02:46:00 PM UTC 24 |
| Peak memory | 215864 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2886732662 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_rw.2886732662 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/0.spi_device_tpm_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/0.spi_device_tpm_sts_read.3654359276 |
| Short name | T4 |
| Test name | |
| Test status | |
| Simulation time | 28637505 ps |
| CPU time | 1.22 seconds |
| Started | Sep 01 02:45:58 PM UTC 24 |
| Finished | Sep 01 02:46:00 PM UTC 24 |
| Peak memory | 215864 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3654359276 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_3 1/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_sts_read.3654359276 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/0.spi_device_tpm_sts_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/1.spi_device_alert_test.1853393688 |
| Short name | T98 |
| Test name | |
| Test status | |
| Simulation time | 136410684 ps |
| CPU time | 1.06 seconds |
| Started | Sep 01 02:46:16 PM UTC 24 |
| Finished | Sep 01 02:46:18 PM UTC 24 |
| Peak memory | 215472 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1853393688 -assert nopostproc +UVM_TES TNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_alert_test.1853393688 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/1.spi_device_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/1.spi_device_cfg_cmd.1222252922 |
| Short name | T24 |
| Test name | |
| Test status | |
| Simulation time | 420683279 ps |
| CPU time | 3.37 seconds |
| Started | Sep 01 02:46:07 PM UTC 24 |
| Finished | Sep 01 02:46:11 PM UTC 24 |
| Peak memory | 234240 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1222252922 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_cfg_cmd.1222252922 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/1.spi_device_cfg_cmd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/1.spi_device_csb_read.3676789813 |
| Short name | T8 |
| Test name | |
| Test status | |
| Simulation time | 15788647 ps |
| CPU time | 1.19 seconds |
| Started | Sep 01 02:46:01 PM UTC 24 |
| Finished | Sep 01 02:46:03 PM UTC 24 |
| Peak memory | 215808 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3676789813 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/sp i_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_csb_read.3676789813 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/1.spi_device_csb_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/1.spi_device_flash_all.3898539411 |
| Short name | T93 |
| Test name | |
| Test status | |
| Simulation time | 41596704324 ps |
| CPU time | 131.12 seconds |
| Started | Sep 01 02:46:12 PM UTC 24 |
| Finished | Sep 01 02:48:26 PM UTC 24 |
| Peak memory | 267860 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3898539411 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/s pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_all.3898539411 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/1.spi_device_flash_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/1.spi_device_flash_and_tpm.3217678756 |
| Short name | T200 |
| Test name | |
| Test status | |
| Simulation time | 125899474136 ps |
| CPU time | 328.37 seconds |
| Started | Sep 01 02:46:13 PM UTC 24 |
| Finished | Sep 01 02:51:46 PM UTC 24 |
| Peak memory | 261764 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3217678756 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_ 31/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_and_tpm.3217678756 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/1.spi_device_flash_and_tpm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/1.spi_device_flash_mode.2244175579 |
| Short name | T15 |
| Test name | |
| Test status | |
| Simulation time | 638708976 ps |
| CPU time | 6.2 seconds |
| Started | Sep 01 02:46:07 PM UTC 24 |
| Finished | Sep 01 02:46:14 PM UTC 24 |
| Peak memory | 251352 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2244175579 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/ spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_mode.2244175579 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/1.spi_device_flash_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/1.spi_device_pass_addr_payload_swap.2480704795 |
| Short name | T14 |
| Test name | |
| Test status | |
| Simulation time | 2512430475 ps |
| CPU time | 6.2 seconds |
| Started | Sep 01 02:46:05 PM UTC 24 |
| Finished | Sep 01 02:46:12 PM UTC 24 |
| Peak memory | 235164 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2480704795 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_31/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_pass_addr_payload_swap.2480704795 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/1.spi_device_pass_addr_payload_swap/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/1.spi_device_pass_cmd_filtering.1865190869 |
| Short name | T19 |
| Test name | |
| Test status | |
| Simulation time | 6442834911 ps |
| CPU time | 12.1 seconds |
| Started | Sep 01 02:46:03 PM UTC 24 |
| Finished | Sep 01 02:46:17 PM UTC 24 |
| Peak memory | 235080 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1865190869 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_08_31/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_pass_cmd_filtering.1865190869 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/1.spi_device_pass_cmd_filtering/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/1.spi_device_read_buffer_direct.2658048131 |
| Short name | T39 |
| Test name | |
| Test status | |
| Simulation time | 783425872 ps |
| CPU time | 7.84 seconds |
| Started | Sep 01 02:46:12 PM UTC 24 |
| Finished | Sep 01 02:46:21 PM UTC 24 |
| Peak memory | 231388 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2658048131 -assert nopostproc +UVM_TESTNAME=spi_device _base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_read_buffer_direct.2658048131 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/1.spi_device_read_buffer_direct/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/1.spi_device_sec_cm.2470470591 |
| Short name | T21 |
| Test name | |
| Test status | |
| Simulation time | 182000214 ps |
| CPU time | 1.97 seconds |
| Started | Sep 01 02:46:16 PM UTC 24 |
| Finished | Sep 01 02:46:19 PM UTC 24 |
| Peak memory | 259776 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2470470591 -assert nopostproc +UVM_TEST NAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_sec_cm.2470470591 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/1.spi_device_sec_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/1.spi_device_tpm_all.826271237 |
| Short name | T43 |
| Test name | |
| Test status | |
| Simulation time | 25243634260 ps |
| CPU time | 49.97 seconds |
| Started | Sep 01 02:46:02 PM UTC 24 |
| Finished | Sep 01 02:46:54 PM UTC 24 |
| Peak memory | 227564 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=826271237 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_all.826271237 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/1.spi_device_tpm_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/1.spi_device_tpm_read_hw_reg.1933834933 |
| Short name | T26 |
| Test name | |
| Test status | |
| Simulation time | 2401125100 ps |
| CPU time | 13.41 seconds |
| Started | Sep 01 02:46:01 PM UTC 24 |
| Finished | Sep 01 02:46:16 PM UTC 24 |
| Peak memory | 227608 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1933834933 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_31/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_read_hw_reg.1933834933 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/1.spi_device_tpm_read_hw_reg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/1.spi_device_tpm_rw.1520639893 |
| Short name | T12 |
| Test name | |
| Test status | |
| Simulation time | 93569040 ps |
| CPU time | 1.46 seconds |
| Started | Sep 01 02:46:03 PM UTC 24 |
| Finished | Sep 01 02:46:06 PM UTC 24 |
| Peak memory | 216484 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1520639893 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_rw.1520639893 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/1.spi_device_tpm_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/1.spi_device_tpm_sts_read.1632077127 |
| Short name | T11 |
| Test name | |
| Test status | |
| Simulation time | 115292754 ps |
| CPU time | 1.12 seconds |
| Started | Sep 01 02:46:03 PM UTC 24 |
| Finished | Sep 01 02:46:06 PM UTC 24 |
| Peak memory | 215864 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1632077127 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_3 1/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_sts_read.1632077127 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/1.spi_device_tpm_sts_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/1.spi_device_upload.990822018 |
| Short name | T53 |
| Test name | |
| Test status | |
| Simulation time | 973633034 ps |
| CPU time | 10.61 seconds |
| Started | Sep 01 02:46:07 PM UTC 24 |
| Finished | Sep 01 02:46:19 PM UTC 24 |
| Peak memory | 234964 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=990822018 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/spi_d evice_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_upload.990822018 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/1.spi_device_upload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/10.spi_device_alert_test.2163912187 |
| Short name | T437 |
| Test name | |
| Test status | |
| Simulation time | 14000522 ps |
| CPU time | 1.12 seconds |
| Started | Sep 01 02:50:40 PM UTC 24 |
| Finished | Sep 01 02:50:43 PM UTC 24 |
| Peak memory | 215740 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2163912187 -assert nopostproc +UVM_TES TNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_alert_test.2163912187 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/10.spi_device_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/10.spi_device_cfg_cmd.3075449707 |
| Short name | T444 |
| Test name | |
| Test status | |
| Simulation time | 7565412384 ps |
| CPU time | 33.28 seconds |
| Started | Sep 01 02:50:25 PM UTC 24 |
| Finished | Sep 01 02:50:59 PM UTC 24 |
| Peak memory | 245320 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3075449707 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_cfg_cmd.3075449707 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/10.spi_device_cfg_cmd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/10.spi_device_csb_read.2124545056 |
| Short name | T430 |
| Test name | |
| Test status | |
| Simulation time | 16304653 ps |
| CPU time | 1.19 seconds |
| Started | Sep 01 02:50:13 PM UTC 24 |
| Finished | Sep 01 02:50:15 PM UTC 24 |
| Peak memory | 215804 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2124545056 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/sp i_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_csb_read.2124545056 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/10.spi_device_csb_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/10.spi_device_flash_all.1680218576 |
| Short name | T227 |
| Test name | |
| Test status | |
| Simulation time | 4909234071 ps |
| CPU time | 78.89 seconds |
| Started | Sep 01 02:50:32 PM UTC 24 |
| Finished | Sep 01 02:51:53 PM UTC 24 |
| Peak memory | 267868 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1680218576 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/s pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_all.1680218576 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/10.spi_device_flash_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/10.spi_device_flash_and_tpm_min_idle.1569895325 |
| Short name | T446 |
| Test name | |
| Test status | |
| Simulation time | 888997931 ps |
| CPU time | 31.07 seconds |
| Started | Sep 01 02:50:36 PM UTC 24 |
| Finished | Sep 01 02:51:09 PM UTC 24 |
| Peak memory | 261620 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1569895325 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_31/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_and_tpm_min_idle.1569895325 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/10.spi_device_flash_and_tpm_min_idle/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/10.spi_device_flash_mode.445197651 |
| Short name | T439 |
| Test name | |
| Test status | |
| Simulation time | 657228129 ps |
| CPU time | 18.19 seconds |
| Started | Sep 01 02:50:26 PM UTC 24 |
| Finished | Sep 01 02:50:45 PM UTC 24 |
| Peak memory | 251340 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=445197651 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/s pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_mode.445197651 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/10.spi_device_flash_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/10.spi_device_intercept.1159185219 |
| Short name | T287 |
| Test name | |
| Test status | |
| Simulation time | 3875941775 ps |
| CPU time | 18.6 seconds |
| Started | Sep 01 02:50:21 PM UTC 24 |
| Finished | Sep 01 02:50:41 PM UTC 24 |
| Peak memory | 235212 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1159185219 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/s pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_intercept.1159185219 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/10.spi_device_intercept/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/10.spi_device_mailbox.3804927026 |
| Short name | T301 |
| Test name | |
| Test status | |
| Simulation time | 37026657 ps |
| CPU time | 3.54 seconds |
| Started | Sep 01 02:50:22 PM UTC 24 |
| Finished | Sep 01 02:50:27 PM UTC 24 |
| Peak memory | 245208 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3804927026 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_mailbox.3804927026 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/10.spi_device_mailbox/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/10.spi_device_pass_addr_payload_swap.4082682185 |
| Short name | T435 |
| Test name | |
| Test status | |
| Simulation time | 411846756 ps |
| CPU time | 3.32 seconds |
| Started | Sep 01 02:50:20 PM UTC 24 |
| Finished | Sep 01 02:50:25 PM UTC 24 |
| Peak memory | 233484 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4082682185 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_31/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_pass_addr_payload_swap.4082682185 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/10.spi_device_pass_addr_payload_swap/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/10.spi_device_pass_cmd_filtering.1685152668 |
| Short name | T304 |
| Test name | |
| Test status | |
| Simulation time | 10176643120 ps |
| CPU time | 13.98 seconds |
| Started | Sep 01 02:50:20 PM UTC 24 |
| Finished | Sep 01 02:50:35 PM UTC 24 |
| Peak memory | 235028 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1685152668 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_08_31/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_pass_cmd_filtering.1685152668 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/10.spi_device_pass_cmd_filtering/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/10.spi_device_read_buffer_direct.1715810125 |
| Short name | T436 |
| Test name | |
| Test status | |
| Simulation time | 472651012 ps |
| CPU time | 9.32 seconds |
| Started | Sep 01 02:50:29 PM UTC 24 |
| Finished | Sep 01 02:50:39 PM UTC 24 |
| Peak memory | 233364 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1715810125 -assert nopostproc +UVM_TESTNAME=spi_device _base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_read_buffer_direct.1715810125 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/10.spi_device_read_buffer_direct/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/10.spi_device_tpm_all.3957342403 |
| Short name | T384 |
| Test name | |
| Test status | |
| Simulation time | 909015599 ps |
| CPU time | 13.86 seconds |
| Started | Sep 01 02:50:16 PM UTC 24 |
| Finished | Sep 01 02:50:31 PM UTC 24 |
| Peak memory | 227496 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3957342403 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_all.3957342403 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/10.spi_device_tpm_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/10.spi_device_tpm_read_hw_reg.4248992604 |
| Short name | T434 |
| Test name | |
| Test status | |
| Simulation time | 1610772214 ps |
| CPU time | 6.41 seconds |
| Started | Sep 01 02:50:16 PM UTC 24 |
| Finished | Sep 01 02:50:23 PM UTC 24 |
| Peak memory | 227428 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4248992604 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_31/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_read_hw_reg.4248992604 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/10.spi_device_tpm_read_hw_reg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/10.spi_device_tpm_rw.128616009 |
| Short name | T433 |
| Test name | |
| Test status | |
| Simulation time | 31405881 ps |
| CPU time | 1.11 seconds |
| Started | Sep 01 02:50:19 PM UTC 24 |
| Finished | Sep 01 02:50:21 PM UTC 24 |
| Peak memory | 215736 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=128616009 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/spi_d evice_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_rw.128616009 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/10.spi_device_tpm_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/10.spi_device_tpm_sts_read.1406412346 |
| Short name | T432 |
| Test name | |
| Test status | |
| Simulation time | 138481008 ps |
| CPU time | 1.25 seconds |
| Started | Sep 01 02:50:17 PM UTC 24 |
| Finished | Sep 01 02:50:19 PM UTC 24 |
| Peak memory | 215868 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1406412346 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_3 1/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_sts_read.1406412346 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/10.spi_device_tpm_sts_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/10.spi_device_upload.370039158 |
| Short name | T312 |
| Test name | |
| Test status | |
| Simulation time | 6101634345 ps |
| CPU time | 38.02 seconds |
| Started | Sep 01 02:50:25 PM UTC 24 |
| Finished | Sep 01 02:51:04 PM UTC 24 |
| Peak memory | 251424 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=370039158 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/spi_d evice_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_upload.370039158 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/10.spi_device_upload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/11.spi_device_alert_test.2280417296 |
| Short name | T447 |
| Test name | |
| Test status | |
| Simulation time | 13076023 ps |
| CPU time | 1.06 seconds |
| Started | Sep 01 02:51:08 PM UTC 24 |
| Finished | Sep 01 02:51:10 PM UTC 24 |
| Peak memory | 215680 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2280417296 -assert nopostproc +UVM_TES TNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_alert_test.2280417296 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/11.spi_device_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/11.spi_device_cfg_cmd.1133756501 |
| Short name | T308 |
| Test name | |
| Test status | |
| Simulation time | 2032374651 ps |
| CPU time | 7.26 seconds |
| Started | Sep 01 02:51:00 PM UTC 24 |
| Finished | Sep 01 02:51:08 PM UTC 24 |
| Peak memory | 245212 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1133756501 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_cfg_cmd.1133756501 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/11.spi_device_cfg_cmd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/11.spi_device_csb_read.542685343 |
| Short name | T438 |
| Test name | |
| Test status | |
| Simulation time | 26951503 ps |
| CPU time | 1.24 seconds |
| Started | Sep 01 02:50:42 PM UTC 24 |
| Finished | Sep 01 02:50:45 PM UTC 24 |
| Peak memory | 215808 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=542685343 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_csb_read.542685343 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/11.spi_device_csb_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/11.spi_device_flash_all.1867485878 |
| Short name | T529 |
| Test name | |
| Test status | |
| Simulation time | 117048908822 ps |
| CPU time | 288.18 seconds |
| Started | Sep 01 02:51:04 PM UTC 24 |
| Finished | Sep 01 02:55:56 PM UTC 24 |
| Peak memory | 261764 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1867485878 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/s pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_all.1867485878 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/11.spi_device_flash_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/11.spi_device_flash_and_tpm.1377898641 |
| Short name | T281 |
| Test name | |
| Test status | |
| Simulation time | 5475647733 ps |
| CPU time | 39.3 seconds |
| Started | Sep 01 02:51:05 PM UTC 24 |
| Finished | Sep 01 02:51:46 PM UTC 24 |
| Peak memory | 267924 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1377898641 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_ 31/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_and_tpm.1377898641 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/11.spi_device_flash_and_tpm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/11.spi_device_flash_and_tpm_min_idle.162362613 |
| Short name | T292 |
| Test name | |
| Test status | |
| Simulation time | 25849353831 ps |
| CPU time | 258.5 seconds |
| Started | Sep 01 02:51:05 PM UTC 24 |
| Finished | Sep 01 02:55:27 PM UTC 24 |
| Peak memory | 261852 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=162362613 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_31/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_and_tpm_min_idle.162362613 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/11.spi_device_flash_and_tpm_min_idle/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/11.spi_device_flash_mode_ignore_cmds.953230080 |
| Short name | T277 |
| Test name | |
| Test status | |
| Simulation time | 6727518589 ps |
| CPU time | 47.3 seconds |
| Started | Sep 01 02:51:01 PM UTC 24 |
| Finished | Sep 01 02:51:50 PM UTC 24 |
| Peak memory | 251468 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=953230080 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_31/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_mode_ignore_cmds.953230080 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/11.spi_device_flash_mode_ignore_cmds/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/11.spi_device_intercept.990857242 |
| Short name | T443 |
| Test name | |
| Test status | |
| Simulation time | 102719564 ps |
| CPU time | 3.12 seconds |
| Started | Sep 01 02:50:54 PM UTC 24 |
| Finished | Sep 01 02:50:59 PM UTC 24 |
| Peak memory | 244896 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=990857242 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/sp i_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_intercept.990857242 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/11.spi_device_intercept/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/11.spi_device_mailbox.2885801940 |
| Short name | T257 |
| Test name | |
| Test status | |
| Simulation time | 3792823451 ps |
| CPU time | 30.98 seconds |
| Started | Sep 01 02:50:57 PM UTC 24 |
| Finished | Sep 01 02:51:30 PM UTC 24 |
| Peak memory | 261708 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2885801940 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_mailbox.2885801940 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/11.spi_device_mailbox/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/11.spi_device_pass_addr_payload_swap.627758261 |
| Short name | T326 |
| Test name | |
| Test status | |
| Simulation time | 3273317122 ps |
| CPU time | 20.42 seconds |
| Started | Sep 01 02:50:54 PM UTC 24 |
| Finished | Sep 01 02:51:16 PM UTC 24 |
| Peak memory | 245324 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=627758261 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_31/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_pass_addr_payload_swap.627758261 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/11.spi_device_pass_addr_payload_swap/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/11.spi_device_pass_cmd_filtering.3712940294 |
| Short name | T253 |
| Test name | |
| Test status | |
| Simulation time | 368221254 ps |
| CPU time | 9.35 seconds |
| Started | Sep 01 02:50:52 PM UTC 24 |
| Finished | Sep 01 02:51:03 PM UTC 24 |
| Peak memory | 251348 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3712940294 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_08_31/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_pass_cmd_filtering.3712940294 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/11.spi_device_pass_cmd_filtering/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/11.spi_device_read_buffer_direct.573610775 |
| Short name | T445 |
| Test name | |
| Test status | |
| Simulation time | 100780237 ps |
| CPU time | 6.47 seconds |
| Started | Sep 01 02:51:01 PM UTC 24 |
| Finished | Sep 01 02:51:08 PM UTC 24 |
| Peak memory | 231324 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=573610775 -assert nopostproc +UVM_TESTNAME=spi_device_ base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_read_buffer_direct.573610775 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/11.spi_device_read_buffer_direct/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/11.spi_device_stress_all.1315578988 |
| Short name | T269 |
| Test name | |
| Test status | |
| Simulation time | 82068822735 ps |
| CPU time | 117.13 seconds |
| Started | Sep 01 02:51:07 PM UTC 24 |
| Finished | Sep 01 02:53:07 PM UTC 24 |
| Peak memory | 251524 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1315578988 -assert nopostproc +UVM_ TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_stress_all.1315578988 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/11.spi_device_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/11.spi_device_tpm_read_hw_reg.363685322 |
| Short name | T442 |
| Test name | |
| Test status | |
| Simulation time | 1597308306 ps |
| CPU time | 11.47 seconds |
| Started | Sep 01 02:50:46 PM UTC 24 |
| Finished | Sep 01 02:50:58 PM UTC 24 |
| Peak memory | 227480 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=363685322 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08 _31/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_read_hw_reg.363685322 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/11.spi_device_tpm_read_hw_reg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/11.spi_device_tpm_rw.4172839456 |
| Short name | T441 |
| Test name | |
| Test status | |
| Simulation time | 107255571 ps |
| CPU time | 1.71 seconds |
| Started | Sep 01 02:50:50 PM UTC 24 |
| Finished | Sep 01 02:50:53 PM UTC 24 |
| Peak memory | 215864 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4172839456 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_rw.4172839456 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/11.spi_device_tpm_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/11.spi_device_tpm_sts_read.2148389667 |
| Short name | T440 |
| Test name | |
| Test status | |
| Simulation time | 111525115 ps |
| CPU time | 1.66 seconds |
| Started | Sep 01 02:50:47 PM UTC 24 |
| Finished | Sep 01 02:50:50 PM UTC 24 |
| Peak memory | 215868 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2148389667 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_3 1/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_sts_read.2148389667 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/11.spi_device_tpm_sts_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/11.spi_device_upload.3201464625 |
| Short name | T334 |
| Test name | |
| Test status | |
| Simulation time | 38839722 ps |
| CPU time | 3.4 seconds |
| Started | Sep 01 02:51:00 PM UTC 24 |
| Finished | Sep 01 02:51:04 PM UTC 24 |
| Peak memory | 251344 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3201464625 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_upload.3201464625 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/11.spi_device_upload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/12.spi_device_alert_test.2840159585 |
| Short name | T454 |
| Test name | |
| Test status | |
| Simulation time | 17260642 ps |
| CPU time | 1.15 seconds |
| Started | Sep 01 02:51:35 PM UTC 24 |
| Finished | Sep 01 02:51:37 PM UTC 24 |
| Peak memory | 215680 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2840159585 -assert nopostproc +UVM_TES TNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_alert_test.2840159585 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/12.spi_device_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/12.spi_device_cfg_cmd.2810331611 |
| Short name | T112 |
| Test name | |
| Test status | |
| Simulation time | 868281859 ps |
| CPU time | 6.06 seconds |
| Started | Sep 01 02:51:23 PM UTC 24 |
| Finished | Sep 01 02:51:30 PM UTC 24 |
| Peak memory | 245152 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2810331611 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_cfg_cmd.2810331611 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/12.spi_device_cfg_cmd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/12.spi_device_csb_read.2787060308 |
| Short name | T448 |
| Test name | |
| Test status | |
| Simulation time | 62256972 ps |
| CPU time | 1.18 seconds |
| Started | Sep 01 02:51:09 PM UTC 24 |
| Finished | Sep 01 02:51:11 PM UTC 24 |
| Peak memory | 215808 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2787060308 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/sp i_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_csb_read.2787060308 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/12.spi_device_csb_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/12.spi_device_flash_all.3213034225 |
| Short name | T278 |
| Test name | |
| Test status | |
| Simulation time | 21635705491 ps |
| CPU time | 225.37 seconds |
| Started | Sep 01 02:51:31 PM UTC 24 |
| Finished | Sep 01 02:55:20 PM UTC 24 |
| Peak memory | 261708 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3213034225 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/s pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_all.3213034225 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/12.spi_device_flash_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/12.spi_device_flash_mode_ignore_cmds.1511728810 |
| Short name | T453 |
| Test name | |
| Test status | |
| Simulation time | 28968470 ps |
| CPU time | 1.23 seconds |
| Started | Sep 01 02:51:28 PM UTC 24 |
| Finished | Sep 01 02:51:31 PM UTC 24 |
| Peak memory | 225736 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1511728810 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_31/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_mode_ignore_cmds.1511728810 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/12.spi_device_flash_mode_ignore_cmds/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/12.spi_device_intercept.2242873926 |
| Short name | T235 |
| Test name | |
| Test status | |
| Simulation time | 1406015829 ps |
| CPU time | 19.19 seconds |
| Started | Sep 01 02:51:17 PM UTC 24 |
| Finished | Sep 01 02:51:37 PM UTC 24 |
| Peak memory | 245152 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2242873926 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/s pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_intercept.2242873926 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/12.spi_device_intercept/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/12.spi_device_mailbox.2426318287 |
| Short name | T465 |
| Test name | |
| Test status | |
| Simulation time | 4750300747 ps |
| CPU time | 51.39 seconds |
| Started | Sep 01 02:51:21 PM UTC 24 |
| Finished | Sep 01 02:52:14 PM UTC 24 |
| Peak memory | 245264 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2426318287 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_mailbox.2426318287 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/12.spi_device_mailbox/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/12.spi_device_pass_addr_payload_swap.254721012 |
| Short name | T324 |
| Test name | |
| Test status | |
| Simulation time | 2356855514 ps |
| CPU time | 9.88 seconds |
| Started | Sep 01 02:51:16 PM UTC 24 |
| Finished | Sep 01 02:51:27 PM UTC 24 |
| Peak memory | 235024 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=254721012 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_31/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_pass_addr_payload_swap.254721012 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/12.spi_device_pass_addr_payload_swap/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/12.spi_device_pass_cmd_filtering.3622396589 |
| Short name | T238 |
| Test name | |
| Test status | |
| Simulation time | 17522342231 ps |
| CPU time | 13.14 seconds |
| Started | Sep 01 02:51:16 PM UTC 24 |
| Finished | Sep 01 02:51:30 PM UTC 24 |
| Peak memory | 235044 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3622396589 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_08_31/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_pass_cmd_filtering.3622396589 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/12.spi_device_pass_cmd_filtering/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/12.spi_device_read_buffer_direct.3279279337 |
| Short name | T459 |
| Test name | |
| Test status | |
| Simulation time | 5348272338 ps |
| CPU time | 18.1 seconds |
| Started | Sep 01 02:51:29 PM UTC 24 |
| Finished | Sep 01 02:51:48 PM UTC 24 |
| Peak memory | 233832 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3279279337 -assert nopostproc +UVM_TESTNAME=spi_device _base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_read_buffer_direct.3279279337 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/12.spi_device_read_buffer_direct/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/12.spi_device_tpm_all.111008393 |
| Short name | T452 |
| Test name | |
| Test status | |
| Simulation time | 6566703622 ps |
| CPU time | 15.03 seconds |
| Started | Sep 01 02:51:12 PM UTC 24 |
| Finished | Sep 01 02:51:28 PM UTC 24 |
| Peak memory | 227548 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=111008393 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_all.111008393 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/12.spi_device_tpm_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/12.spi_device_tpm_read_hw_reg.1116302609 |
| Short name | T451 |
| Test name | |
| Test status | |
| Simulation time | 2344232831 ps |
| CPU time | 10.95 seconds |
| Started | Sep 01 02:51:10 PM UTC 24 |
| Finished | Sep 01 02:51:23 PM UTC 24 |
| Peak memory | 227544 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1116302609 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_31/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_read_hw_reg.1116302609 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/12.spi_device_tpm_read_hw_reg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/12.spi_device_tpm_rw.2897937634 |
| Short name | T449 |
| Test name | |
| Test status | |
| Simulation time | 22180414 ps |
| CPU time | 1.23 seconds |
| Started | Sep 01 02:51:13 PM UTC 24 |
| Finished | Sep 01 02:51:15 PM UTC 24 |
| Peak memory | 215864 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2897937634 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_rw.2897937634 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/12.spi_device_tpm_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/12.spi_device_tpm_sts_read.2956365118 |
| Short name | T450 |
| Test name | |
| Test status | |
| Simulation time | 99469183 ps |
| CPU time | 1.5 seconds |
| Started | Sep 01 02:51:13 PM UTC 24 |
| Finished | Sep 01 02:51:15 PM UTC 24 |
| Peak memory | 215868 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2956365118 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_3 1/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_sts_read.2956365118 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/12.spi_device_tpm_sts_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/12.spi_device_upload.3350689206 |
| Short name | T346 |
| Test name | |
| Test status | |
| Simulation time | 5779012219 ps |
| CPU time | 30.21 seconds |
| Started | Sep 01 02:51:21 PM UTC 24 |
| Finished | Sep 01 02:51:53 PM UTC 24 |
| Peak memory | 245276 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3350689206 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_upload.3350689206 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/12.spi_device_upload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/13.spi_device_alert_test.3719942952 |
| Short name | T431 |
| Test name | |
| Test status | |
| Simulation time | 40349812 ps |
| CPU time | 1.12 seconds |
| Started | Sep 01 02:52:03 PM UTC 24 |
| Finished | Sep 01 02:52:05 PM UTC 24 |
| Peak memory | 215740 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3719942952 -assert nopostproc +UVM_TES TNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_alert_test.3719942952 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/13.spi_device_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/13.spi_device_cfg_cmd.620877871 |
| Short name | T462 |
| Test name | |
| Test status | |
| Simulation time | 4191808376 ps |
| CPU time | 17.73 seconds |
| Started | Sep 01 02:51:49 PM UTC 24 |
| Finished | Sep 01 02:52:08 PM UTC 24 |
| Peak memory | 245260 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=620877871 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_cfg_cmd.620877871 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/13.spi_device_cfg_cmd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/13.spi_device_csb_read.1065697555 |
| Short name | T455 |
| Test name | |
| Test status | |
| Simulation time | 13815122 ps |
| CPU time | 1.1 seconds |
| Started | Sep 01 02:51:38 PM UTC 24 |
| Finished | Sep 01 02:51:40 PM UTC 24 |
| Peak memory | 215456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1065697555 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/sp i_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_csb_read.1065697555 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/13.spi_device_csb_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/13.spi_device_flash_all.1063010400 |
| Short name | T268 |
| Test name | |
| Test status | |
| Simulation time | 23347061903 ps |
| CPU time | 72.61 seconds |
| Started | Sep 01 02:51:53 PM UTC 24 |
| Finished | Sep 01 02:53:08 PM UTC 24 |
| Peak memory | 261788 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1063010400 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/s pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_all.1063010400 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/13.spi_device_flash_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/13.spi_device_flash_and_tpm_min_idle.2430568032 |
| Short name | T40 |
| Test name | |
| Test status | |
| Simulation time | 29030367888 ps |
| CPU time | 131.99 seconds |
| Started | Sep 01 02:52:03 PM UTC 24 |
| Finished | Sep 01 02:54:17 PM UTC 24 |
| Peak memory | 263760 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2430568032 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_31/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_and_tpm_min_idle.2430568032 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/13.spi_device_flash_and_tpm_min_idle/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/13.spi_device_flash_mode.3805159177 |
| Short name | T372 |
| Test name | |
| Test status | |
| Simulation time | 805810170 ps |
| CPU time | 14.04 seconds |
| Started | Sep 01 02:51:50 PM UTC 24 |
| Finished | Sep 01 02:52:05 PM UTC 24 |
| Peak memory | 245196 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3805159177 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/ spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_mode.3805159177 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/13.spi_device_flash_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/13.spi_device_flash_mode_ignore_cmds.1379519066 |
| Short name | T510 |
| Test name | |
| Test status | |
| Simulation time | 105962969742 ps |
| CPU time | 191.32 seconds |
| Started | Sep 01 02:51:53 PM UTC 24 |
| Finished | Sep 01 02:55:08 PM UTC 24 |
| Peak memory | 267776 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1379519066 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_31/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_mode_ignore_cmds.1379519066 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/13.spi_device_flash_mode_ignore_cmds/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/13.spi_device_intercept.2109245107 |
| Short name | T311 |
| Test name | |
| Test status | |
| Simulation time | 3248374637 ps |
| CPU time | 14.27 seconds |
| Started | Sep 01 02:51:47 PM UTC 24 |
| Finished | Sep 01 02:52:02 PM UTC 24 |
| Peak memory | 235148 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2109245107 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/s pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_intercept.2109245107 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/13.spi_device_intercept/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/13.spi_device_mailbox.1814707453 |
| Short name | T307 |
| Test name | |
| Test status | |
| Simulation time | 14506244305 ps |
| CPU time | 72.41 seconds |
| Started | Sep 01 02:51:48 PM UTC 24 |
| Finished | Sep 01 02:53:02 PM UTC 24 |
| Peak memory | 251460 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1814707453 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_mailbox.1814707453 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/13.spi_device_mailbox/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/13.spi_device_pass_addr_payload_swap.2123736097 |
| Short name | T274 |
| Test name | |
| Test status | |
| Simulation time | 2670624578 ps |
| CPU time | 11.02 seconds |
| Started | Sep 01 02:51:47 PM UTC 24 |
| Finished | Sep 01 02:51:59 PM UTC 24 |
| Peak memory | 234960 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2123736097 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_31/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_pass_addr_payload_swap.2123736097 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/13.spi_device_pass_addr_payload_swap/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/13.spi_device_pass_cmd_filtering.1569954835 |
| Short name | T340 |
| Test name | |
| Test status | |
| Simulation time | 2225833703 ps |
| CPU time | 15.02 seconds |
| Started | Sep 01 02:51:46 PM UTC 24 |
| Finished | Sep 01 02:52:02 PM UTC 24 |
| Peak memory | 243952 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1569954835 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_08_31/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_pass_cmd_filtering.1569954835 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/13.spi_device_pass_cmd_filtering/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/13.spi_device_read_buffer_direct.571680234 |
| Short name | T461 |
| Test name | |
| Test status | |
| Simulation time | 648990172 ps |
| CPU time | 7.43 seconds |
| Started | Sep 01 02:51:53 PM UTC 24 |
| Finished | Sep 01 02:52:02 PM UTC 24 |
| Peak memory | 231264 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=571680234 -assert nopostproc +UVM_TESTNAME=spi_device_ base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_read_buffer_direct.571680234 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/13.spi_device_read_buffer_direct/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/13.spi_device_stress_all.812268968 |
| Short name | T82 |
| Test name | |
| Test status | |
| Simulation time | 579730389770 ps |
| CPU time | 1522.89 seconds |
| Started | Sep 01 02:52:03 PM UTC 24 |
| Finished | Sep 01 03:17:44 PM UTC 24 |
| Peak memory | 300688 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=812268968 -assert nopostproc +UVM_T ESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_stress_all.812268968 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/13.spi_device_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/13.spi_device_tpm_all.4109533174 |
| Short name | T458 |
| Test name | |
| Test status | |
| Simulation time | 2895030163 ps |
| CPU time | 5.6 seconds |
| Started | Sep 01 02:51:41 PM UTC 24 |
| Finished | Sep 01 02:51:48 PM UTC 24 |
| Peak memory | 227608 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4109533174 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_all.4109533174 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/13.spi_device_tpm_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/13.spi_device_tpm_read_hw_reg.1540286406 |
| Short name | T460 |
| Test name | |
| Test status | |
| Simulation time | 5503003974 ps |
| CPU time | 12.81 seconds |
| Started | Sep 01 02:51:38 PM UTC 24 |
| Finished | Sep 01 02:51:52 PM UTC 24 |
| Peak memory | 227620 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1540286406 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_31/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_read_hw_reg.1540286406 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/13.spi_device_tpm_read_hw_reg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/13.spi_device_tpm_rw.1927845888 |
| Short name | T457 |
| Test name | |
| Test status | |
| Simulation time | 56769502 ps |
| CPU time | 1.36 seconds |
| Started | Sep 01 02:51:44 PM UTC 24 |
| Finished | Sep 01 02:51:47 PM UTC 24 |
| Peak memory | 215864 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1927845888 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_rw.1927845888 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/13.spi_device_tpm_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/13.spi_device_tpm_sts_read.3204193857 |
| Short name | T456 |
| Test name | |
| Test status | |
| Simulation time | 204232302 ps |
| CPU time | 1.26 seconds |
| Started | Sep 01 02:51:41 PM UTC 24 |
| Finished | Sep 01 02:51:44 PM UTC 24 |
| Peak memory | 215868 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3204193857 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_3 1/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_sts_read.3204193857 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/13.spi_device_tpm_sts_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/13.spi_device_upload.3943797371 |
| Short name | T223 |
| Test name | |
| Test status | |
| Simulation time | 1230356736 ps |
| CPU time | 15.23 seconds |
| Started | Sep 01 02:51:49 PM UTC 24 |
| Finished | Sep 01 02:52:05 PM UTC 24 |
| Peak memory | 234956 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3943797371 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_upload.3943797371 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/13.spi_device_upload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/14.spi_device_alert_test.538523764 |
| Short name | T468 |
| Test name | |
| Test status | |
| Simulation time | 13576971 ps |
| CPU time | 1.04 seconds |
| Started | Sep 01 02:52:38 PM UTC 24 |
| Finished | Sep 01 02:52:40 PM UTC 24 |
| Peak memory | 215800 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=538523764 -assert nopostproc +UVM_TEST NAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_alert_test.538523764 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/14.spi_device_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/14.spi_device_cfg_cmd.3442115909 |
| Short name | T343 |
| Test name | |
| Test status | |
| Simulation time | 541295460 ps |
| CPU time | 3.81 seconds |
| Started | Sep 01 02:52:21 PM UTC 24 |
| Finished | Sep 01 02:52:26 PM UTC 24 |
| Peak memory | 234956 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3442115909 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_cfg_cmd.3442115909 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/14.spi_device_cfg_cmd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/14.spi_device_csb_read.1141162705 |
| Short name | T463 |
| Test name | |
| Test status | |
| Simulation time | 16912745 ps |
| CPU time | 1.22 seconds |
| Started | Sep 01 02:52:06 PM UTC 24 |
| Finished | Sep 01 02:52:08 PM UTC 24 |
| Peak memory | 215808 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1141162705 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/sp i_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_csb_read.1141162705 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/14.spi_device_csb_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/14.spi_device_flash_all.1584266559 |
| Short name | T240 |
| Test name | |
| Test status | |
| Simulation time | 770862948584 ps |
| CPU time | 510.23 seconds |
| Started | Sep 01 02:52:30 PM UTC 24 |
| Finished | Sep 01 03:01:07 PM UTC 24 |
| Peak memory | 284232 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1584266559 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/s pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_all.1584266559 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/14.spi_device_flash_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/14.spi_device_flash_and_tpm.164563526 |
| Short name | T544 |
| Test name | |
| Test status | |
| Simulation time | 28476443048 ps |
| CPU time | 237.39 seconds |
| Started | Sep 01 02:52:34 PM UTC 24 |
| Finished | Sep 01 02:56:35 PM UTC 24 |
| Peak memory | 261780 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=164563526 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_3 1/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_and_tpm.164563526 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/14.spi_device_flash_and_tpm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/14.spi_device_flash_and_tpm_min_idle.151415179 |
| Short name | T159 |
| Test name | |
| Test status | |
| Simulation time | 72532855740 ps |
| CPU time | 272.73 seconds |
| Started | Sep 01 02:52:34 PM UTC 24 |
| Finished | Sep 01 02:57:11 PM UTC 24 |
| Peak memory | 249552 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=151415179 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_31/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_and_tpm_min_idle.151415179 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/14.spi_device_flash_and_tpm_min_idle/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/14.spi_device_flash_mode.2789315461 |
| Short name | T379 |
| Test name | |
| Test status | |
| Simulation time | 943404948 ps |
| CPU time | 7.6 seconds |
| Started | Sep 01 02:52:25 PM UTC 24 |
| Finished | Sep 01 02:52:34 PM UTC 24 |
| Peak memory | 245212 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2789315461 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/ spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_mode.2789315461 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/14.spi_device_flash_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/14.spi_device_flash_mode_ignore_cmds.3841887028 |
| Short name | T256 |
| Test name | |
| Test status | |
| Simulation time | 4252772747 ps |
| CPU time | 69.57 seconds |
| Started | Sep 01 02:52:26 PM UTC 24 |
| Finished | Sep 01 02:53:37 PM UTC 24 |
| Peak memory | 261728 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3841887028 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_31/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_mode_ignore_cmds.3841887028 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/14.spi_device_flash_mode_ignore_cmds/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/14.spi_device_intercept.3814506824 |
| Short name | T306 |
| Test name | |
| Test status | |
| Simulation time | 636922806 ps |
| CPU time | 8.05 seconds |
| Started | Sep 01 02:52:14 PM UTC 24 |
| Finished | Sep 01 02:52:23 PM UTC 24 |
| Peak memory | 234956 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3814506824 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/s pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_intercept.3814506824 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/14.spi_device_intercept/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/14.spi_device_mailbox.3518048791 |
| Short name | T305 |
| Test name | |
| Test status | |
| Simulation time | 2387583568 ps |
| CPU time | 16.3 seconds |
| Started | Sep 01 02:52:15 PM UTC 24 |
| Finished | Sep 01 02:52:33 PM UTC 24 |
| Peak memory | 245264 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3518048791 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_mailbox.3518048791 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/14.spi_device_mailbox/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/14.spi_device_pass_addr_payload_swap.3632686016 |
| Short name | T329 |
| Test name | |
| Test status | |
| Simulation time | 7845483703 ps |
| CPU time | 26.74 seconds |
| Started | Sep 01 02:52:14 PM UTC 24 |
| Finished | Sep 01 02:52:42 PM UTC 24 |
| Peak memory | 235148 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3632686016 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_31/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_pass_addr_payload_swap.3632686016 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/14.spi_device_pass_addr_payload_swap/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/14.spi_device_pass_cmd_filtering.3890741036 |
| Short name | T317 |
| Test name | |
| Test status | |
| Simulation time | 1935974798 ps |
| CPU time | 11.45 seconds |
| Started | Sep 01 02:52:12 PM UTC 24 |
| Finished | Sep 01 02:52:25 PM UTC 24 |
| Peak memory | 245192 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3890741036 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_08_31/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_pass_cmd_filtering.3890741036 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/14.spi_device_pass_cmd_filtering/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/14.spi_device_read_buffer_direct.79066407 |
| Short name | T467 |
| Test name | |
| Test status | |
| Simulation time | 86383783 ps |
| CPU time | 5.32 seconds |
| Started | Sep 01 02:52:27 PM UTC 24 |
| Finished | Sep 01 02:52:33 PM UTC 24 |
| Peak memory | 234072 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=79066407 -assert nopostproc +UVM_TESTNAME=spi_device_b ase_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_read_buffer_direct.79066407 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/14.spi_device_read_buffer_direct/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/14.spi_device_stress_all.861575515 |
| Short name | T351 |
| Test name | |
| Test status | |
| Simulation time | 351339092964 ps |
| CPU time | 730.4 seconds |
| Started | Sep 01 02:52:35 PM UTC 24 |
| Finished | Sep 01 03:04:55 PM UTC 24 |
| Peak memory | 278220 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=861575515 -assert nopostproc +UVM_T ESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_stress_all.861575515 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/14.spi_device_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/14.spi_device_tpm_all.236720078 |
| Short name | T381 |
| Test name | |
| Test status | |
| Simulation time | 1410074846 ps |
| CPU time | 26.61 seconds |
| Started | Sep 01 02:52:09 PM UTC 24 |
| Finished | Sep 01 02:52:37 PM UTC 24 |
| Peak memory | 227484 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=236720078 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_all.236720078 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/14.spi_device_tpm_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/14.spi_device_tpm_read_hw_reg.1793361614 |
| Short name | T466 |
| Test name | |
| Test status | |
| Simulation time | 2688031313 ps |
| CPU time | 11.52 seconds |
| Started | Sep 01 02:52:07 PM UTC 24 |
| Finished | Sep 01 02:52:20 PM UTC 24 |
| Peak memory | 227536 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1793361614 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_31/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_read_hw_reg.1793361614 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/14.spi_device_tpm_read_hw_reg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/14.spi_device_tpm_rw.1462653379 |
| Short name | T391 |
| Test name | |
| Test status | |
| Simulation time | 106426206 ps |
| CPU time | 3.52 seconds |
| Started | Sep 01 02:52:09 PM UTC 24 |
| Finished | Sep 01 02:52:14 PM UTC 24 |
| Peak memory | 227432 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1462653379 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_rw.1462653379 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/14.spi_device_tpm_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/14.spi_device_tpm_sts_read.543034959 |
| Short name | T464 |
| Test name | |
| Test status | |
| Simulation time | 48752223 ps |
| CPU time | 1.37 seconds |
| Started | Sep 01 02:52:09 PM UTC 24 |
| Finished | Sep 01 02:52:12 PM UTC 24 |
| Peak memory | 215864 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=543034959 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31 /spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_sts_read.543034959 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/14.spi_device_tpm_sts_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/14.spi_device_upload.132815627 |
| Short name | T236 |
| Test name | |
| Test status | |
| Simulation time | 1730041868 ps |
| CPU time | 9.71 seconds |
| Started | Sep 01 02:52:19 PM UTC 24 |
| Finished | Sep 01 02:52:30 PM UTC 24 |
| Peak memory | 241780 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=132815627 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/spi_d evice_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_upload.132815627 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/14.spi_device_upload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/15.spi_device_alert_test.3453985603 |
| Short name | T477 |
| Test name | |
| Test status | |
| Simulation time | 30172360 ps |
| CPU time | 1.09 seconds |
| Started | Sep 01 02:53:15 PM UTC 24 |
| Finished | Sep 01 02:53:17 PM UTC 24 |
| Peak memory | 215680 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3453985603 -assert nopostproc +UVM_TES TNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_alert_test.3453985603 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/15.spi_device_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/15.spi_device_cfg_cmd.3754133537 |
| Short name | T347 |
| Test name | |
| Test status | |
| Simulation time | 120915627 ps |
| CPU time | 3.05 seconds |
| Started | Sep 01 02:53:05 PM UTC 24 |
| Finished | Sep 01 02:53:09 PM UTC 24 |
| Peak memory | 245136 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3754133537 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_cfg_cmd.3754133537 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/15.spi_device_cfg_cmd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/15.spi_device_csb_read.3255342859 |
| Short name | T469 |
| Test name | |
| Test status | |
| Simulation time | 19797934 ps |
| CPU time | 1.24 seconds |
| Started | Sep 01 02:52:38 PM UTC 24 |
| Finished | Sep 01 02:52:41 PM UTC 24 |
| Peak memory | 215632 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3255342859 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/sp i_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_csb_read.3255342859 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/15.spi_device_csb_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/15.spi_device_flash_and_tpm.1866863343 |
| Short name | T88 |
| Test name | |
| Test status | |
| Simulation time | 27442906572 ps |
| CPU time | 73.3 seconds |
| Started | Sep 01 02:53:11 PM UTC 24 |
| Finished | Sep 01 02:54:26 PM UTC 24 |
| Peak memory | 251540 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1866863343 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_ 31/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_and_tpm.1866863343 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/15.spi_device_flash_and_tpm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/15.spi_device_flash_and_tpm_min_idle.3724416117 |
| Short name | T91 |
| Test name | |
| Test status | |
| Simulation time | 4890873122 ps |
| CPU time | 78.93 seconds |
| Started | Sep 01 02:53:12 PM UTC 24 |
| Finished | Sep 01 02:54:33 PM UTC 24 |
| Peak memory | 267896 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3724416117 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_31/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_and_tpm_min_idle.3724416117 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/15.spi_device_flash_and_tpm_min_idle/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/15.spi_device_flash_mode.2847427037 |
| Short name | T476 |
| Test name | |
| Test status | |
| Simulation time | 1284467441 ps |
| CPU time | 5.35 seconds |
| Started | Sep 01 02:53:07 PM UTC 24 |
| Finished | Sep 01 02:53:14 PM UTC 24 |
| Peak memory | 245212 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2847427037 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/ spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_mode.2847427037 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/15.spi_device_flash_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/15.spi_device_flash_mode_ignore_cmds.319284796 |
| Short name | T475 |
| Test name | |
| Test status | |
| Simulation time | 12027308 ps |
| CPU time | 1.19 seconds |
| Started | Sep 01 02:53:09 PM UTC 24 |
| Finished | Sep 01 02:53:11 PM UTC 24 |
| Peak memory | 225736 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=319284796 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_31/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_mode_ignore_cmds.319284796 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/15.spi_device_flash_mode_ignore_cmds/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/15.spi_device_intercept.3999328927 |
| Short name | T474 |
| Test name | |
| Test status | |
| Simulation time | 3249553460 ps |
| CPU time | 9.92 seconds |
| Started | Sep 01 02:52:56 PM UTC 24 |
| Finished | Sep 01 02:53:07 PM UTC 24 |
| Peak memory | 235036 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3999328927 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/s pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_intercept.3999328927 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/15.spi_device_intercept/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/15.spi_device_mailbox.1809894145 |
| Short name | T336 |
| Test name | |
| Test status | |
| Simulation time | 4103566022 ps |
| CPU time | 36.97 seconds |
| Started | Sep 01 02:53:00 PM UTC 24 |
| Finished | Sep 01 02:53:39 PM UTC 24 |
| Peak memory | 247372 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1809894145 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_mailbox.1809894145 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/15.spi_device_mailbox/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/15.spi_device_pass_addr_payload_swap.100759870 |
| Short name | T322 |
| Test name | |
| Test status | |
| Simulation time | 1073019132 ps |
| CPU time | 15.1 seconds |
| Started | Sep 01 02:52:48 PM UTC 24 |
| Finished | Sep 01 02:53:04 PM UTC 24 |
| Peak memory | 245144 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=100759870 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_31/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_pass_addr_payload_swap.100759870 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/15.spi_device_pass_addr_payload_swap/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/15.spi_device_pass_cmd_filtering.2558648836 |
| Short name | T264 |
| Test name | |
| Test status | |
| Simulation time | 37994088167 ps |
| CPU time | 43.37 seconds |
| Started | Sep 01 02:52:46 PM UTC 24 |
| Finished | Sep 01 02:53:31 PM UTC 24 |
| Peak memory | 245364 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2558648836 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_08_31/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_pass_cmd_filtering.2558648836 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/15.spi_device_pass_cmd_filtering/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/15.spi_device_read_buffer_direct.1215624964 |
| Short name | T479 |
| Test name | |
| Test status | |
| Simulation time | 4199485173 ps |
| CPU time | 14.32 seconds |
| Started | Sep 01 02:53:09 PM UTC 24 |
| Finished | Sep 01 02:53:24 PM UTC 24 |
| Peak memory | 231384 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1215624964 -assert nopostproc +UVM_TESTNAME=spi_device _base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_read_buffer_direct.1215624964 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/15.spi_device_read_buffer_direct/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/15.spi_device_stress_all.3949021402 |
| Short name | T196 |
| Test name | |
| Test status | |
| Simulation time | 28619005 ps |
| CPU time | 1.32 seconds |
| Started | Sep 01 02:53:13 PM UTC 24 |
| Finished | Sep 01 02:53:15 PM UTC 24 |
| Peak memory | 215736 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3949021402 -assert nopostproc +UVM_ TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_stress_all.3949021402 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/15.spi_device_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/15.spi_device_tpm_all.3955045425 |
| Short name | T481 |
| Test name | |
| Test status | |
| Simulation time | 7848890976 ps |
| CPU time | 43.73 seconds |
| Started | Sep 01 02:52:43 PM UTC 24 |
| Finished | Sep 01 02:53:28 PM UTC 24 |
| Peak memory | 227672 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3955045425 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_all.3955045425 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/15.spi_device_tpm_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/15.spi_device_tpm_read_hw_reg.2183362537 |
| Short name | T471 |
| Test name | |
| Test status | |
| Simulation time | 925312821 ps |
| CPU time | 4.98 seconds |
| Started | Sep 01 02:52:42 PM UTC 24 |
| Finished | Sep 01 02:52:48 PM UTC 24 |
| Peak memory | 227624 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2183362537 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_31/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_read_hw_reg.2183362537 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/15.spi_device_tpm_read_hw_reg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/15.spi_device_tpm_rw.1023506496 |
| Short name | T472 |
| Test name | |
| Test status | |
| Simulation time | 1090897257 ps |
| CPU time | 9.35 seconds |
| Started | Sep 01 02:52:45 PM UTC 24 |
| Finished | Sep 01 02:52:55 PM UTC 24 |
| Peak memory | 227416 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1023506496 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_rw.1023506496 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/15.spi_device_tpm_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/15.spi_device_tpm_sts_read.1505577313 |
| Short name | T470 |
| Test name | |
| Test status | |
| Simulation time | 723042700 ps |
| CPU time | 1.48 seconds |
| Started | Sep 01 02:52:43 PM UTC 24 |
| Finished | Sep 01 02:52:45 PM UTC 24 |
| Peak memory | 215868 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1505577313 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_3 1/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_sts_read.1505577313 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/15.spi_device_tpm_sts_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/15.spi_device_upload.1871565652 |
| Short name | T254 |
| Test name | |
| Test status | |
| Simulation time | 10370977396 ps |
| CPU time | 7.4 seconds |
| Started | Sep 01 02:53:03 PM UTC 24 |
| Finished | Sep 01 02:53:12 PM UTC 24 |
| Peak memory | 235088 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1871565652 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_upload.1871565652 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/15.spi_device_upload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/16.spi_device_alert_test.1252482101 |
| Short name | T189 |
| Test name | |
| Test status | |
| Simulation time | 14418550 ps |
| CPU time | 1.15 seconds |
| Started | Sep 01 02:53:46 PM UTC 24 |
| Finished | Sep 01 02:53:48 PM UTC 24 |
| Peak memory | 215740 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1252482101 -assert nopostproc +UVM_TES TNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_alert_test.1252482101 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/16.spi_device_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/16.spi_device_cfg_cmd.4223495195 |
| Short name | T296 |
| Test name | |
| Test status | |
| Simulation time | 282648747 ps |
| CPU time | 4.4 seconds |
| Started | Sep 01 02:53:36 PM UTC 24 |
| Finished | Sep 01 02:53:42 PM UTC 24 |
| Peak memory | 245152 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4223495195 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_cfg_cmd.4223495195 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/16.spi_device_cfg_cmd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/16.spi_device_csb_read.993802912 |
| Short name | T478 |
| Test name | |
| Test status | |
| Simulation time | 14473585 ps |
| CPU time | 1.22 seconds |
| Started | Sep 01 02:53:16 PM UTC 24 |
| Finished | Sep 01 02:53:18 PM UTC 24 |
| Peak memory | 215804 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=993802912 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_csb_read.993802912 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/16.spi_device_csb_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/16.spi_device_flash_all.1154866342 |
| Short name | T252 |
| Test name | |
| Test status | |
| Simulation time | 120690002834 ps |
| CPU time | 307.63 seconds |
| Started | Sep 01 02:53:41 PM UTC 24 |
| Finished | Sep 01 02:58:54 PM UTC 24 |
| Peak memory | 278092 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1154866342 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/s pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_all.1154866342 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/16.spi_device_flash_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/16.spi_device_flash_and_tpm.805273292 |
| Short name | T271 |
| Test name | |
| Test status | |
| Simulation time | 23855663978 ps |
| CPU time | 81.6 seconds |
| Started | Sep 01 02:53:43 PM UTC 24 |
| Finished | Sep 01 02:55:06 PM UTC 24 |
| Peak memory | 263880 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=805273292 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_3 1/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_and_tpm.805273292 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/16.spi_device_flash_and_tpm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/16.spi_device_flash_and_tpm_min_idle.1517160826 |
| Short name | T904 |
| Test name | |
| Test status | |
| Simulation time | 222175899967 ps |
| CPU time | 638.68 seconds |
| Started | Sep 01 02:53:43 PM UTC 24 |
| Finished | Sep 01 03:04:29 PM UTC 24 |
| Peak memory | 274060 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1517160826 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_31/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_and_tpm_min_idle.1517160826 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/16.spi_device_flash_and_tpm_min_idle/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/16.spi_device_flash_mode.2163844375 |
| Short name | T270 |
| Test name | |
| Test status | |
| Simulation time | 2081081624 ps |
| CPU time | 17.37 seconds |
| Started | Sep 01 02:53:38 PM UTC 24 |
| Finished | Sep 01 02:53:57 PM UTC 24 |
| Peak memory | 245256 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2163844375 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/ spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_mode.2163844375 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/16.spi_device_flash_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/16.spi_device_intercept.2983463894 |
| Short name | T484 |
| Test name | |
| Test status | |
| Simulation time | 135648695 ps |
| CPU time | 6.98 seconds |
| Started | Sep 01 02:53:32 PM UTC 24 |
| Finished | Sep 01 02:53:41 PM UTC 24 |
| Peak memory | 245152 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2983463894 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/s pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_intercept.2983463894 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/16.spi_device_intercept/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/16.spi_device_mailbox.4265442166 |
| Short name | T335 |
| Test name | |
| Test status | |
| Simulation time | 356126602 ps |
| CPU time | 4.85 seconds |
| Started | Sep 01 02:53:33 PM UTC 24 |
| Finished | Sep 01 02:53:40 PM UTC 24 |
| Peak memory | 234896 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4265442166 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_mailbox.4265442166 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/16.spi_device_mailbox/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/16.spi_device_pass_addr_payload_swap.828478753 |
| Short name | T195 |
| Test name | |
| Test status | |
| Simulation time | 21625188081 ps |
| CPU time | 26.15 seconds |
| Started | Sep 01 02:53:29 PM UTC 24 |
| Finished | Sep 01 02:53:56 PM UTC 24 |
| Peak memory | 245348 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=828478753 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_31/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_pass_addr_payload_swap.828478753 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/16.spi_device_pass_addr_payload_swap/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/16.spi_device_pass_cmd_filtering.3609116641 |
| Short name | T483 |
| Test name | |
| Test status | |
| Simulation time | 160238776 ps |
| CPU time | 6.46 seconds |
| Started | Sep 01 02:53:28 PM UTC 24 |
| Finished | Sep 01 02:53:35 PM UTC 24 |
| Peak memory | 245212 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3609116641 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_08_31/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_pass_cmd_filtering.3609116641 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/16.spi_device_pass_cmd_filtering/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/16.spi_device_read_buffer_direct.2401344705 |
| Short name | T192 |
| Test name | |
| Test status | |
| Simulation time | 835364539 ps |
| CPU time | 10.66 seconds |
| Started | Sep 01 02:53:40 PM UTC 24 |
| Finished | Sep 01 02:53:52 PM UTC 24 |
| Peak memory | 231248 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2401344705 -assert nopostproc +UVM_TESTNAME=spi_device _base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_read_buffer_direct.2401344705 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/16.spi_device_read_buffer_direct/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/16.spi_device_stress_all.1031570402 |
| Short name | T186 |
| Test name | |
| Test status | |
| Simulation time | 133409850595 ps |
| CPU time | 824.21 seconds |
| Started | Sep 01 02:53:45 PM UTC 24 |
| Finished | Sep 01 03:07:39 PM UTC 24 |
| Peak memory | 294576 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1031570402 -assert nopostproc +UVM_ TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_stress_all.1031570402 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/16.spi_device_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/16.spi_device_tpm_all.4258042121 |
| Short name | T190 |
| Test name | |
| Test status | |
| Simulation time | 1793375285 ps |
| CPU time | 27.95 seconds |
| Started | Sep 01 02:53:21 PM UTC 24 |
| Finished | Sep 01 02:53:51 PM UTC 24 |
| Peak memory | 227496 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4258042121 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_all.4258042121 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/16.spi_device_tpm_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/16.spi_device_tpm_read_hw_reg.3162248168 |
| Short name | T187 |
| Test name | |
| Test status | |
| Simulation time | 25451841168 ps |
| CPU time | 23.45 seconds |
| Started | Sep 01 02:53:19 PM UTC 24 |
| Finished | Sep 01 02:53:44 PM UTC 24 |
| Peak memory | 229572 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3162248168 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_31/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_read_hw_reg.3162248168 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/16.spi_device_tpm_read_hw_reg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/16.spi_device_tpm_rw.3412750295 |
| Short name | T482 |
| Test name | |
| Test status | |
| Simulation time | 1976029879 ps |
| CPU time | 3.45 seconds |
| Started | Sep 01 02:53:28 PM UTC 24 |
| Finished | Sep 01 02:53:32 PM UTC 24 |
| Peak memory | 227544 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3412750295 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_rw.3412750295 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/16.spi_device_tpm_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/16.spi_device_tpm_sts_read.2698159834 |
| Short name | T480 |
| Test name | |
| Test status | |
| Simulation time | 119180020 ps |
| CPU time | 1.12 seconds |
| Started | Sep 01 02:53:24 PM UTC 24 |
| Finished | Sep 01 02:53:27 PM UTC 24 |
| Peak memory | 215868 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2698159834 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_3 1/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_sts_read.2698159834 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/16.spi_device_tpm_sts_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/16.spi_device_upload.23603386 |
| Short name | T193 |
| Test name | |
| Test status | |
| Simulation time | 16032795849 ps |
| CPU time | 43.63 seconds |
| Started | Sep 01 02:53:34 PM UTC 24 |
| Finished | Sep 01 02:54:20 PM UTC 24 |
| Peak memory | 235032 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=23603386 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/spi_de vice_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_upload.23603386 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/16.spi_device_upload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/17.spi_device_alert_test.3989605536 |
| Short name | T473 |
| Test name | |
| Test status | |
| Simulation time | 15530550 ps |
| CPU time | 1.13 seconds |
| Started | Sep 01 02:54:17 PM UTC 24 |
| Finished | Sep 01 02:54:19 PM UTC 24 |
| Peak memory | 215740 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3989605536 -assert nopostproc +UVM_TES TNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_alert_test.3989605536 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/17.spi_device_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/17.spi_device_cfg_cmd.2498221778 |
| Short name | T84 |
| Test name | |
| Test status | |
| Simulation time | 18010896903 ps |
| CPU time | 17.8 seconds |
| Started | Sep 01 02:54:02 PM UTC 24 |
| Finished | Sep 01 02:54:21 PM UTC 24 |
| Peak memory | 245340 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2498221778 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_cfg_cmd.2498221778 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/17.spi_device_cfg_cmd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/17.spi_device_csb_read.3650539244 |
| Short name | T191 |
| Test name | |
| Test status | |
| Simulation time | 179429920 ps |
| CPU time | 1.19 seconds |
| Started | Sep 01 02:53:49 PM UTC 24 |
| Finished | Sep 01 02:53:51 PM UTC 24 |
| Peak memory | 215804 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3650539244 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/sp i_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_csb_read.3650539244 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/17.spi_device_csb_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/17.spi_device_flash_all.3100971931 |
| Short name | T262 |
| Test name | |
| Test status | |
| Simulation time | 14352861314 ps |
| CPU time | 42.63 seconds |
| Started | Sep 01 02:54:09 PM UTC 24 |
| Finished | Sep 01 02:54:53 PM UTC 24 |
| Peak memory | 263772 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3100971931 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/s pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_all.3100971931 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/17.spi_device_flash_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/17.spi_device_flash_and_tpm.891296700 |
| Short name | T266 |
| Test name | |
| Test status | |
| Simulation time | 28400761330 ps |
| CPU time | 176.26 seconds |
| Started | Sep 01 02:54:13 PM UTC 24 |
| Finished | Sep 01 02:57:13 PM UTC 24 |
| Peak memory | 278164 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=891296700 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_3 1/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_and_tpm.891296700 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/17.spi_device_flash_and_tpm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/17.spi_device_flash_mode.1997810423 |
| Short name | T492 |
| Test name | |
| Test status | |
| Simulation time | 1762263216 ps |
| CPU time | 7.61 seconds |
| Started | Sep 01 02:54:04 PM UTC 24 |
| Finished | Sep 01 02:54:13 PM UTC 24 |
| Peak memory | 234956 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1997810423 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/ spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_mode.1997810423 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/17.spi_device_flash_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/17.spi_device_flash_mode_ignore_cmds.998905563 |
| Short name | T295 |
| Test name | |
| Test status | |
| Simulation time | 90423346005 ps |
| CPU time | 366.61 seconds |
| Started | Sep 01 02:54:06 PM UTC 24 |
| Finished | Sep 01 03:00:18 PM UTC 24 |
| Peak memory | 265804 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=998905563 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_31/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_mode_ignore_cmds.998905563 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/17.spi_device_flash_mode_ignore_cmds/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/17.spi_device_intercept.3358683794 |
| Short name | T490 |
| Test name | |
| Test status | |
| Simulation time | 2484663540 ps |
| CPU time | 9.13 seconds |
| Started | Sep 01 02:53:58 PM UTC 24 |
| Finished | Sep 01 02:54:08 PM UTC 24 |
| Peak memory | 245404 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3358683794 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/s pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_intercept.3358683794 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/17.spi_device_intercept/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/17.spi_device_mailbox.543698812 |
| Short name | T232 |
| Test name | |
| Test status | |
| Simulation time | 845480664 ps |
| CPU time | 16.94 seconds |
| Started | Sep 01 02:53:58 PM UTC 24 |
| Finished | Sep 01 02:54:16 PM UTC 24 |
| Peak memory | 234900 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=543698812 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_mailbox.543698812 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/17.spi_device_mailbox/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/17.spi_device_pass_addr_payload_swap.1448699802 |
| Short name | T487 |
| Test name | |
| Test status | |
| Simulation time | 32007871 ps |
| CPU time | 2.19 seconds |
| Started | Sep 01 02:53:58 PM UTC 24 |
| Finished | Sep 01 02:54:01 PM UTC 24 |
| Peak memory | 233452 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1448699802 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_31/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_pass_addr_payload_swap.1448699802 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/17.spi_device_pass_addr_payload_swap/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/17.spi_device_pass_cmd_filtering.733483655 |
| Short name | T491 |
| Test name | |
| Test status | |
| Simulation time | 1516813352 ps |
| CPU time | 9.58 seconds |
| Started | Sep 01 02:53:58 PM UTC 24 |
| Finished | Sep 01 02:54:08 PM UTC 24 |
| Peak memory | 234992 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=733483655 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _08_31/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_pass_cmd_filtering.733483655 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/17.spi_device_pass_cmd_filtering/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/17.spi_device_read_buffer_direct.576774227 |
| Short name | T493 |
| Test name | |
| Test status | |
| Simulation time | 143939277 ps |
| CPU time | 4.98 seconds |
| Started | Sep 01 02:54:08 PM UTC 24 |
| Finished | Sep 01 02:54:14 PM UTC 24 |
| Peak memory | 233604 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=576774227 -assert nopostproc +UVM_TESTNAME=spi_device_ base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_read_buffer_direct.576774227 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/17.spi_device_read_buffer_direct/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/17.spi_device_stress_all.965849428 |
| Short name | T150 |
| Test name | |
| Test status | |
| Simulation time | 35276150174 ps |
| CPU time | 161.41 seconds |
| Started | Sep 01 02:54:17 PM UTC 24 |
| Finished | Sep 01 02:57:01 PM UTC 24 |
| Peak memory | 267864 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=965849428 -assert nopostproc +UVM_T ESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_stress_all.965849428 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/17.spi_device_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/17.spi_device_tpm_all.1258296872 |
| Short name | T495 |
| Test name | |
| Test status | |
| Simulation time | 4480331048 ps |
| CPU time | 42.62 seconds |
| Started | Sep 01 02:53:53 PM UTC 24 |
| Finished | Sep 01 02:54:37 PM UTC 24 |
| Peak memory | 227624 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1258296872 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_all.1258296872 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/17.spi_device_tpm_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/17.spi_device_tpm_read_hw_reg.2116250293 |
| Short name | T488 |
| Test name | |
| Test status | |
| Simulation time | 6367433099 ps |
| CPU time | 9.48 seconds |
| Started | Sep 01 02:53:52 PM UTC 24 |
| Finished | Sep 01 02:54:03 PM UTC 24 |
| Peak memory | 227544 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2116250293 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_31/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_read_hw_reg.2116250293 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/17.spi_device_tpm_read_hw_reg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/17.spi_device_tpm_rw.795007694 |
| Short name | T486 |
| Test name | |
| Test status | |
| Simulation time | 331213618 ps |
| CPU time | 5.06 seconds |
| Started | Sep 01 02:53:54 PM UTC 24 |
| Finished | Sep 01 02:54:00 PM UTC 24 |
| Peak memory | 227496 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=795007694 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/spi_d evice_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_rw.795007694 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/17.spi_device_tpm_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/17.spi_device_tpm_sts_read.4151353564 |
| Short name | T485 |
| Test name | |
| Test status | |
| Simulation time | 31344868 ps |
| CPU time | 1.27 seconds |
| Started | Sep 01 02:53:54 PM UTC 24 |
| Finished | Sep 01 02:53:56 PM UTC 24 |
| Peak memory | 215868 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4151353564 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_3 1/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_sts_read.4151353564 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/17.spi_device_tpm_sts_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/17.spi_device_upload.16458162 |
| Short name | T489 |
| Test name | |
| Test status | |
| Simulation time | 90460948 ps |
| CPU time | 3.4 seconds |
| Started | Sep 01 02:54:01 PM UTC 24 |
| Finished | Sep 01 02:54:05 PM UTC 24 |
| Peak memory | 234772 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=16458162 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/spi_de vice_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_upload.16458162 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/17.spi_device_upload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/18.spi_device_alert_test.1897958926 |
| Short name | T499 |
| Test name | |
| Test status | |
| Simulation time | 37803685 ps |
| CPU time | 1.09 seconds |
| Started | Sep 01 02:54:44 PM UTC 24 |
| Finished | Sep 01 02:54:46 PM UTC 24 |
| Peak memory | 215680 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1897958926 -assert nopostproc +UVM_TES TNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_alert_test.1897958926 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/18.spi_device_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/18.spi_device_cfg_cmd.1318408037 |
| Short name | T501 |
| Test name | |
| Test status | |
| Simulation time | 1626003366 ps |
| CPU time | 14.8 seconds |
| Started | Sep 01 02:54:33 PM UTC 24 |
| Finished | Sep 01 02:54:49 PM UTC 24 |
| Peak memory | 245200 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1318408037 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_cfg_cmd.1318408037 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/18.spi_device_cfg_cmd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/18.spi_device_csb_read.2060703034 |
| Short name | T83 |
| Test name | |
| Test status | |
| Simulation time | 27733553 ps |
| CPU time | 1.18 seconds |
| Started | Sep 01 02:54:18 PM UTC 24 |
| Finished | Sep 01 02:54:20 PM UTC 24 |
| Peak memory | 215808 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2060703034 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/sp i_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_csb_read.2060703034 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/18.spi_device_csb_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/18.spi_device_flash_all.4122224931 |
| Short name | T282 |
| Test name | |
| Test status | |
| Simulation time | 8573687330 ps |
| CPU time | 86.77 seconds |
| Started | Sep 01 02:54:38 PM UTC 24 |
| Finished | Sep 01 02:56:07 PM UTC 24 |
| Peak memory | 261768 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4122224931 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/s pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_all.4122224931 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/18.spi_device_flash_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/18.spi_device_flash_and_tpm.2441245334 |
| Short name | T504 |
| Test name | |
| Test status | |
| Simulation time | 409363033 ps |
| CPU time | 11.66 seconds |
| Started | Sep 01 02:54:38 PM UTC 24 |
| Finished | Sep 01 02:54:51 PM UTC 24 |
| Peak memory | 251428 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2441245334 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_ 31/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_and_tpm.2441245334 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/18.spi_device_flash_and_tpm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/18.spi_device_flash_and_tpm_min_idle.4052886825 |
| Short name | T621 |
| Test name | |
| Test status | |
| Simulation time | 45412107039 ps |
| CPU time | 234.03 seconds |
| Started | Sep 01 02:54:39 PM UTC 24 |
| Finished | Sep 01 02:58:37 PM UTC 24 |
| Peak memory | 265904 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4052886825 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_31/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_and_tpm_min_idle.4052886825 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/18.spi_device_flash_and_tpm_min_idle/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/18.spi_device_flash_mode.3999442419 |
| Short name | T500 |
| Test name | |
| Test status | |
| Simulation time | 586750501 ps |
| CPU time | 11.85 seconds |
| Started | Sep 01 02:54:34 PM UTC 24 |
| Finished | Sep 01 02:54:47 PM UTC 24 |
| Peak memory | 251296 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3999442419 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/ spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_mode.3999442419 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/18.spi_device_flash_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/18.spi_device_flash_mode_ignore_cmds.711373890 |
| Short name | T156 |
| Test name | |
| Test status | |
| Simulation time | 10379363406 ps |
| CPU time | 150.09 seconds |
| Started | Sep 01 02:54:34 PM UTC 24 |
| Finished | Sep 01 02:57:07 PM UTC 24 |
| Peak memory | 267856 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=711373890 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_31/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_mode_ignore_cmds.711373890 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/18.spi_device_flash_mode_ignore_cmds/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/18.spi_device_intercept.1627953076 |
| Short name | T494 |
| Test name | |
| Test status | |
| Simulation time | 367776612 ps |
| CPU time | 6.55 seconds |
| Started | Sep 01 02:54:26 PM UTC 24 |
| Finished | Sep 01 02:54:33 PM UTC 24 |
| Peak memory | 234956 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1627953076 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/s pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_intercept.1627953076 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/18.spi_device_intercept/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/18.spi_device_mailbox.189137567 |
| Short name | T496 |
| Test name | |
| Test status | |
| Simulation time | 2946717192 ps |
| CPU time | 10.04 seconds |
| Started | Sep 01 02:54:27 PM UTC 24 |
| Finished | Sep 01 02:54:38 PM UTC 24 |
| Peak memory | 245344 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=189137567 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_mailbox.189137567 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/18.spi_device_mailbox/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/18.spi_device_pass_addr_payload_swap.193585 |
| Short name | T497 |
| Test name | |
| Test status | |
| Simulation time | 686992536 ps |
| CPU time | 11.33 seconds |
| Started | Sep 01 02:54:26 PM UTC 24 |
| Finished | Sep 01 02:54:38 PM UTC 24 |
| Peak memory | 245196 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=193585 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UV M_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_08_31/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_pass_addr_payload_swap.193585 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/18.spi_device_pass_addr_payload_swap/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/18.spi_device_pass_cmd_filtering.3974438280 |
| Short name | T89 |
| Test name | |
| Test status | |
| Simulation time | 1921872092 ps |
| CPU time | 5.8 seconds |
| Started | Sep 01 02:54:23 PM UTC 24 |
| Finished | Sep 01 02:54:30 PM UTC 24 |
| Peak memory | 245204 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3974438280 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_08_31/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_pass_cmd_filtering.3974438280 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/18.spi_device_pass_cmd_filtering/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/18.spi_device_read_buffer_direct.1176347741 |
| Short name | T498 |
| Test name | |
| Test status | |
| Simulation time | 151087791 ps |
| CPU time | 3.93 seconds |
| Started | Sep 01 02:54:38 PM UTC 24 |
| Finished | Sep 01 02:54:43 PM UTC 24 |
| Peak memory | 231104 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1176347741 -assert nopostproc +UVM_TESTNAME=spi_device _base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_read_buffer_direct.1176347741 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/18.spi_device_read_buffer_direct/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/18.spi_device_stress_all.556485308 |
| Short name | T81 |
| Test name | |
| Test status | |
| Simulation time | 89638623619 ps |
| CPU time | 1036.79 seconds |
| Started | Sep 01 02:54:40 PM UTC 24 |
| Finished | Sep 01 03:12:09 PM UTC 24 |
| Peak memory | 294540 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=556485308 -assert nopostproc +UVM_T ESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_stress_all.556485308 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/18.spi_device_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/18.spi_device_tpm_all.3645955120 |
| Short name | T511 |
| Test name | |
| Test status | |
| Simulation time | 4625927709 ps |
| CPU time | 45.81 seconds |
| Started | Sep 01 02:54:21 PM UTC 24 |
| Finished | Sep 01 02:55:08 PM UTC 24 |
| Peak memory | 227612 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3645955120 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_all.3645955120 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/18.spi_device_tpm_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/18.spi_device_tpm_read_hw_reg.3618928352 |
| Short name | T508 |
| Test name | |
| Test status | |
| Simulation time | 7145315387 ps |
| CPU time | 40.39 seconds |
| Started | Sep 01 02:54:21 PM UTC 24 |
| Finished | Sep 01 02:55:03 PM UTC 24 |
| Peak memory | 227620 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3618928352 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_31/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_read_hw_reg.3618928352 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/18.spi_device_tpm_read_hw_reg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/18.spi_device_tpm_rw.4283293535 |
| Short name | T86 |
| Test name | |
| Test status | |
| Simulation time | 303134184 ps |
| CPU time | 1.57 seconds |
| Started | Sep 01 02:54:22 PM UTC 24 |
| Finished | Sep 01 02:54:25 PM UTC 24 |
| Peak memory | 216276 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4283293535 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_rw.4283293535 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/18.spi_device_tpm_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/18.spi_device_tpm_sts_read.1626287857 |
| Short name | T87 |
| Test name | |
| Test status | |
| Simulation time | 459271629 ps |
| CPU time | 1.64 seconds |
| Started | Sep 01 02:54:22 PM UTC 24 |
| Finished | Sep 01 02:54:25 PM UTC 24 |
| Peak memory | 215868 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1626287857 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_3 1/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_sts_read.1626287857 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/18.spi_device_tpm_sts_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/18.spi_device_upload.304874863 |
| Short name | T502 |
| Test name | |
| Test status | |
| Simulation time | 3504836960 ps |
| CPU time | 17.41 seconds |
| Started | Sep 01 02:54:31 PM UTC 24 |
| Finished | Sep 01 02:54:49 PM UTC 24 |
| Peak memory | 245284 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=304874863 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/spi_d evice_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_upload.304874863 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/18.spi_device_upload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/19.spi_device_alert_test.1183655339 |
| Short name | T513 |
| Test name | |
| Test status | |
| Simulation time | 30828120 ps |
| CPU time | 1.08 seconds |
| Started | Sep 01 02:55:12 PM UTC 24 |
| Finished | Sep 01 02:55:14 PM UTC 24 |
| Peak memory | 215740 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1183655339 -assert nopostproc +UVM_TES TNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_alert_test.1183655339 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/19.spi_device_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/19.spi_device_cfg_cmd.1145524223 |
| Short name | T509 |
| Test name | |
| Test status | |
| Simulation time | 54045215 ps |
| CPU time | 3.71 seconds |
| Started | Sep 01 02:55:01 PM UTC 24 |
| Finished | Sep 01 02:55:06 PM UTC 24 |
| Peak memory | 245148 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1145524223 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_cfg_cmd.1145524223 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/19.spi_device_cfg_cmd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/19.spi_device_csb_read.3998478565 |
| Short name | T503 |
| Test name | |
| Test status | |
| Simulation time | 192515321 ps |
| CPU time | 1.21 seconds |
| Started | Sep 01 02:54:48 PM UTC 24 |
| Finished | Sep 01 02:54:50 PM UTC 24 |
| Peak memory | 215636 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3998478565 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/sp i_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_csb_read.3998478565 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/19.spi_device_csb_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/19.spi_device_flash_all.3627717936 |
| Short name | T556 |
| Test name | |
| Test status | |
| Simulation time | 10265639979 ps |
| CPU time | 108.44 seconds |
| Started | Sep 01 02:55:06 PM UTC 24 |
| Finished | Sep 01 02:56:57 PM UTC 24 |
| Peak memory | 261720 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3627717936 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/s pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_all.3627717936 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/19.spi_device_flash_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/19.spi_device_flash_and_tpm.208237381 |
| Short name | T663 |
| Test name | |
| Test status | |
| Simulation time | 263576651759 ps |
| CPU time | 264.19 seconds |
| Started | Sep 01 02:55:07 PM UTC 24 |
| Finished | Sep 01 02:59:36 PM UTC 24 |
| Peak memory | 267912 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=208237381 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_3 1/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_and_tpm.208237381 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/19.spi_device_flash_and_tpm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/19.spi_device_flash_and_tpm_min_idle.1426207330 |
| Short name | T584 |
| Test name | |
| Test status | |
| Simulation time | 26516348665 ps |
| CPU time | 164.16 seconds |
| Started | Sep 01 02:55:08 PM UTC 24 |
| Finished | Sep 01 02:57:56 PM UTC 24 |
| Peak memory | 261776 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1426207330 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_31/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_and_tpm_min_idle.1426207330 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/19.spi_device_flash_and_tpm_min_idle/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/19.spi_device_flash_mode.1682265281 |
| Short name | T376 |
| Test name | |
| Test status | |
| Simulation time | 6748553388 ps |
| CPU time | 24.61 seconds |
| Started | Sep 01 02:55:02 PM UTC 24 |
| Finished | Sep 01 02:55:28 PM UTC 24 |
| Peak memory | 247384 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1682265281 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/ spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_mode.1682265281 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/19.spi_device_flash_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/19.spi_device_flash_mode_ignore_cmds.1891695386 |
| Short name | T606 |
| Test name | |
| Test status | |
| Simulation time | 265811879264 ps |
| CPU time | 189.08 seconds |
| Started | Sep 01 02:55:04 PM UTC 24 |
| Finished | Sep 01 02:58:16 PM UTC 24 |
| Peak memory | 263772 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1891695386 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_31/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_mode_ignore_cmds.1891695386 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/19.spi_device_flash_mode_ignore_cmds/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/19.spi_device_intercept.2472118826 |
| Short name | T345 |
| Test name | |
| Test status | |
| Simulation time | 389494907 ps |
| CPU time | 4.46 seconds |
| Started | Sep 01 02:54:54 PM UTC 24 |
| Finished | Sep 01 02:55:00 PM UTC 24 |
| Peak memory | 245260 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2472118826 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/s pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_intercept.2472118826 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/19.spi_device_intercept/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/19.spi_device_mailbox.56524835 |
| Short name | T314 |
| Test name | |
| Test status | |
| Simulation time | 742336476 ps |
| CPU time | 15.32 seconds |
| Started | Sep 01 02:54:57 PM UTC 24 |
| Finished | Sep 01 02:55:13 PM UTC 24 |
| Peak memory | 245280 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=56524835 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/spi_d evice_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_mailbox.56524835 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/19.spi_device_mailbox/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/19.spi_device_pass_addr_payload_swap.1778445787 |
| Short name | T344 |
| Test name | |
| Test status | |
| Simulation time | 26647704392 ps |
| CPU time | 17.52 seconds |
| Started | Sep 01 02:54:54 PM UTC 24 |
| Finished | Sep 01 02:55:13 PM UTC 24 |
| Peak memory | 245272 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1778445787 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_31/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_pass_addr_payload_swap.1778445787 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/19.spi_device_pass_addr_payload_swap/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/19.spi_device_pass_cmd_filtering.1331086354 |
| Short name | T303 |
| Test name | |
| Test status | |
| Simulation time | 478348200 ps |
| CPU time | 6.95 seconds |
| Started | Sep 01 02:54:52 PM UTC 24 |
| Finished | Sep 01 02:55:00 PM UTC 24 |
| Peak memory | 234912 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1331086354 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_08_31/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_pass_cmd_filtering.1331086354 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/19.spi_device_pass_cmd_filtering/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/19.spi_device_read_buffer_direct.1556196763 |
| Short name | T514 |
| Test name | |
| Test status | |
| Simulation time | 782311156 ps |
| CPU time | 8.55 seconds |
| Started | Sep 01 02:55:05 PM UTC 24 |
| Finished | Sep 01 02:55:15 PM UTC 24 |
| Peak memory | 231256 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1556196763 -assert nopostproc +UVM_TESTNAME=spi_device _base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_read_buffer_direct.1556196763 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/19.spi_device_read_buffer_direct/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/19.spi_device_stress_all.3467674762 |
| Short name | T80 |
| Test name | |
| Test status | |
| Simulation time | 605175975859 ps |
| CPU time | 481.57 seconds |
| Started | Sep 01 02:55:09 PM UTC 24 |
| Finished | Sep 01 03:03:18 PM UTC 24 |
| Peak memory | 300672 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3467674762 -assert nopostproc +UVM_ TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_stress_all.3467674762 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/19.spi_device_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/19.spi_device_tpm_all.3942591122 |
| Short name | T507 |
| Test name | |
| Test status | |
| Simulation time | 289056448 ps |
| CPU time | 6.49 seconds |
| Started | Sep 01 02:54:51 PM UTC 24 |
| Finished | Sep 01 02:54:59 PM UTC 24 |
| Peak memory | 227420 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3942591122 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_all.3942591122 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/19.spi_device_tpm_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/19.spi_device_tpm_read_hw_reg.1180215189 |
| Short name | T512 |
| Test name | |
| Test status | |
| Simulation time | 22628073532 ps |
| CPU time | 18.94 seconds |
| Started | Sep 01 02:54:50 PM UTC 24 |
| Finished | Sep 01 02:55:11 PM UTC 24 |
| Peak memory | 227612 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1180215189 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_31/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_read_hw_reg.1180215189 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/19.spi_device_tpm_read_hw_reg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/19.spi_device_tpm_rw.274919034 |
| Short name | T506 |
| Test name | |
| Test status | |
| Simulation time | 566912647 ps |
| CPU time | 3.3 seconds |
| Started | Sep 01 02:54:51 PM UTC 24 |
| Finished | Sep 01 02:54:56 PM UTC 24 |
| Peak memory | 227536 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=274919034 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/spi_d evice_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_rw.274919034 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/19.spi_device_tpm_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/19.spi_device_tpm_sts_read.1899716718 |
| Short name | T505 |
| Test name | |
| Test status | |
| Simulation time | 28029116 ps |
| CPU time | 1.21 seconds |
| Started | Sep 01 02:54:51 PM UTC 24 |
| Finished | Sep 01 02:54:54 PM UTC 24 |
| Peak memory | 215868 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1899716718 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_3 1/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_sts_read.1899716718 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/19.spi_device_tpm_sts_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/19.spi_device_upload.89551171 |
| Short name | T339 |
| Test name | |
| Test status | |
| Simulation time | 2283475948 ps |
| CPU time | 11.68 seconds |
| Started | Sep 01 02:55:00 PM UTC 24 |
| Finished | Sep 01 02:55:13 PM UTC 24 |
| Peak memory | 245264 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=89551171 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/spi_de vice_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_upload.89551171 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/19.spi_device_upload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/2.spi_device_alert_test.1305714329 |
| Short name | T99 |
| Test name | |
| Test status | |
| Simulation time | 14660670 ps |
| CPU time | 1.12 seconds |
| Started | Sep 01 02:46:41 PM UTC 24 |
| Finished | Sep 01 02:46:43 PM UTC 24 |
| Peak memory | 215680 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1305714329 -assert nopostproc +UVM_TES TNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_alert_test.1305714329 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/2.spi_device_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/2.spi_device_cfg_cmd.2985177595 |
| Short name | T64 |
| Test name | |
| Test status | |
| Simulation time | 1413128255 ps |
| CPU time | 5.14 seconds |
| Started | Sep 01 02:46:23 PM UTC 24 |
| Finished | Sep 01 02:46:29 PM UTC 24 |
| Peak memory | 235036 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2985177595 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_cfg_cmd.2985177595 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/2.spi_device_cfg_cmd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/2.spi_device_csb_read.1800636201 |
| Short name | T27 |
| Test name | |
| Test status | |
| Simulation time | 110660958 ps |
| CPU time | 1.2 seconds |
| Started | Sep 01 02:46:16 PM UTC 24 |
| Finished | Sep 01 02:46:19 PM UTC 24 |
| Peak memory | 215808 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1800636201 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/sp i_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_csb_read.1800636201 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/2.spi_device_csb_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/2.spi_device_flash_all.3400230322 |
| Short name | T259 |
| Test name | |
| Test status | |
| Simulation time | 36658802345 ps |
| CPU time | 338.35 seconds |
| Started | Sep 01 02:46:35 PM UTC 24 |
| Finished | Sep 01 02:52:18 PM UTC 24 |
| Peak memory | 280100 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3400230322 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/s pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_all.3400230322 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/2.spi_device_flash_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/2.spi_device_flash_and_tpm.1157747797 |
| Short name | T239 |
| Test name | |
| Test status | |
| Simulation time | 197687271288 ps |
| CPU time | 434.83 seconds |
| Started | Sep 01 02:46:36 PM UTC 24 |
| Finished | Sep 01 02:53:56 PM UTC 24 |
| Peak memory | 263812 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1157747797 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_ 31/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_and_tpm.1157747797 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/2.spi_device_flash_and_tpm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/2.spi_device_flash_mode.3457397831 |
| Short name | T52 |
| Test name | |
| Test status | |
| Simulation time | 196080804 ps |
| CPU time | 6.98 seconds |
| Started | Sep 01 02:46:28 PM UTC 24 |
| Finished | Sep 01 02:46:37 PM UTC 24 |
| Peak memory | 245216 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3457397831 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/ spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_mode.3457397831 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/2.spi_device_flash_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/2.spi_device_intercept.4028587929 |
| Short name | T207 |
| Test name | |
| Test status | |
| Simulation time | 9071433825 ps |
| CPU time | 70.1 seconds |
| Started | Sep 01 02:46:21 PM UTC 24 |
| Finished | Sep 01 02:47:33 PM UTC 24 |
| Peak memory | 235144 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4028587929 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/s pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_intercept.4028587929 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/2.spi_device_intercept/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/2.spi_device_mailbox.2671959272 |
| Short name | T56 |
| Test name | |
| Test status | |
| Simulation time | 460034462 ps |
| CPU time | 19.3 seconds |
| Started | Sep 01 02:46:22 PM UTC 24 |
| Finished | Sep 01 02:46:43 PM UTC 24 |
| Peak memory | 261580 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2671959272 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_mailbox.2671959272 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/2.spi_device_mailbox/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/2.spi_device_pass_addr_payload_swap.468698208 |
| Short name | T58 |
| Test name | |
| Test status | |
| Simulation time | 8269295583 ps |
| CPU time | 27.15 seconds |
| Started | Sep 01 02:46:20 PM UTC 24 |
| Finished | Sep 01 02:46:48 PM UTC 24 |
| Peak memory | 247444 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=468698208 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_31/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_pass_addr_payload_swap.468698208 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/2.spi_device_pass_addr_payload_swap/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/2.spi_device_pass_cmd_filtering.555620001 |
| Short name | T61 |
| Test name | |
| Test status | |
| Simulation time | 74882222948 ps |
| CPU time | 26.53 seconds |
| Started | Sep 01 02:46:20 PM UTC 24 |
| Finished | Sep 01 02:46:48 PM UTC 24 |
| Peak memory | 245332 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=555620001 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _08_31/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_pass_cmd_filtering.555620001 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/2.spi_device_pass_cmd_filtering/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/2.spi_device_read_buffer_direct.4109385815 |
| Short name | T97 |
| Test name | |
| Test status | |
| Simulation time | 11504690942 ps |
| CPU time | 21.45 seconds |
| Started | Sep 01 02:46:31 PM UTC 24 |
| Finished | Sep 01 02:46:54 PM UTC 24 |
| Peak memory | 231392 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4109385815 -assert nopostproc +UVM_TESTNAME=spi_device _base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_read_buffer_direct.4109385815 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/2.spi_device_read_buffer_direct/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/2.spi_device_sec_cm.2881040473 |
| Short name | T22 |
| Test name | |
| Test status | |
| Simulation time | 195497494 ps |
| CPU time | 1.52 seconds |
| Started | Sep 01 02:46:38 PM UTC 24 |
| Finished | Sep 01 02:46:40 PM UTC 24 |
| Peak memory | 257916 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2881040473 -assert nopostproc +UVM_TEST NAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_sec_cm.2881040473 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/2.spi_device_sec_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/2.spi_device_tpm_all.1179353078 |
| Short name | T47 |
| Test name | |
| Test status | |
| Simulation time | 35918092189 ps |
| CPU time | 42.47 seconds |
| Started | Sep 01 02:46:18 PM UTC 24 |
| Finished | Sep 01 02:47:02 PM UTC 24 |
| Peak memory | 227732 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1179353078 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_all.1179353078 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/2.spi_device_tpm_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/2.spi_device_tpm_read_hw_reg.1847664373 |
| Short name | T30 |
| Test name | |
| Test status | |
| Simulation time | 3271483282 ps |
| CPU time | 18.67 seconds |
| Started | Sep 01 02:46:18 PM UTC 24 |
| Finished | Sep 01 02:46:37 PM UTC 24 |
| Peak memory | 227612 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1847664373 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_31/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_read_hw_reg.1847664373 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/2.spi_device_tpm_read_hw_reg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/2.spi_device_tpm_rw.3387477248 |
| Short name | T29 |
| Test name | |
| Test status | |
| Simulation time | 51375307 ps |
| CPU time | 1.76 seconds |
| Started | Sep 01 02:46:20 PM UTC 24 |
| Finished | Sep 01 02:46:23 PM UTC 24 |
| Peak memory | 216396 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3387477248 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_rw.3387477248 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/2.spi_device_tpm_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/2.spi_device_tpm_sts_read.3724847124 |
| Short name | T28 |
| Test name | |
| Test status | |
| Simulation time | 24040477 ps |
| CPU time | 1.14 seconds |
| Started | Sep 01 02:46:20 PM UTC 24 |
| Finished | Sep 01 02:46:22 PM UTC 24 |
| Peak memory | 215864 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3724847124 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_3 1/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_sts_read.3724847124 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/2.spi_device_tpm_sts_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/2.spi_device_upload.1966662278 |
| Short name | T59 |
| Test name | |
| Test status | |
| Simulation time | 609460515 ps |
| CPU time | 10.02 seconds |
| Started | Sep 01 02:46:23 PM UTC 24 |
| Finished | Sep 01 02:46:34 PM UTC 24 |
| Peak memory | 234904 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1966662278 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_upload.1966662278 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/2.spi_device_upload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/20.spi_device_alert_test.2691317700 |
| Short name | T520 |
| Test name | |
| Test status | |
| Simulation time | 16280286 ps |
| CPU time | 1.16 seconds |
| Started | Sep 01 02:55:34 PM UTC 24 |
| Finished | Sep 01 02:55:37 PM UTC 24 |
| Peak memory | 215740 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2691317700 -assert nopostproc +UVM_TES TNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_alert_test.2691317700 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/20.spi_device_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/20.spi_device_cfg_cmd.2514899665 |
| Short name | T299 |
| Test name | |
| Test status | |
| Simulation time | 2125098952 ps |
| CPU time | 20.08 seconds |
| Started | Sep 01 02:55:26 PM UTC 24 |
| Finished | Sep 01 02:55:47 PM UTC 24 |
| Peak memory | 245212 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2514899665 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_cfg_cmd.2514899665 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/20.spi_device_cfg_cmd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/20.spi_device_csb_read.573229888 |
| Short name | T515 |
| Test name | |
| Test status | |
| Simulation time | 70647299 ps |
| CPU time | 1.2 seconds |
| Started | Sep 01 02:55:14 PM UTC 24 |
| Finished | Sep 01 02:55:16 PM UTC 24 |
| Peak memory | 215636 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=573229888 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_csb_read.573229888 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/20.spi_device_csb_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/20.spi_device_flash_all.3827832198 |
| Short name | T519 |
| Test name | |
| Test status | |
| Simulation time | 19285919 ps |
| CPU time | 1.24 seconds |
| Started | Sep 01 02:55:31 PM UTC 24 |
| Finished | Sep 01 02:55:33 PM UTC 24 |
| Peak memory | 225728 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3827832198 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/s pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_all.3827832198 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/20.spi_device_flash_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/20.spi_device_flash_and_tpm.3915419896 |
| Short name | T331 |
| Test name | |
| Test status | |
| Simulation time | 69580898000 ps |
| CPU time | 218.54 seconds |
| Started | Sep 01 02:55:32 PM UTC 24 |
| Finished | Sep 01 02:59:14 PM UTC 24 |
| Peak memory | 265876 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3915419896 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_ 31/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_and_tpm.3915419896 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/20.spi_device_flash_and_tpm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/20.spi_device_flash_and_tpm_min_idle.1981857107 |
| Short name | T600 |
| Test name | |
| Test status | |
| Simulation time | 52476549933 ps |
| CPU time | 156.24 seconds |
| Started | Sep 01 02:55:33 PM UTC 24 |
| Finished | Sep 01 02:58:12 PM UTC 24 |
| Peak memory | 261776 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1981857107 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_31/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_and_tpm_min_idle.1981857107 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/20.spi_device_flash_and_tpm_min_idle/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/20.spi_device_flash_mode.2938056467 |
| Short name | T373 |
| Test name | |
| Test status | |
| Simulation time | 2277561329 ps |
| CPU time | 22.33 seconds |
| Started | Sep 01 02:55:28 PM UTC 24 |
| Finished | Sep 01 02:55:51 PM UTC 24 |
| Peak memory | 245388 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2938056467 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/ spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_mode.2938056467 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/20.spi_device_flash_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/20.spi_device_intercept.2582286695 |
| Short name | T342 |
| Test name | |
| Test status | |
| Simulation time | 398166871 ps |
| CPU time | 9.74 seconds |
| Started | Sep 01 02:55:19 PM UTC 24 |
| Finished | Sep 01 02:55:30 PM UTC 24 |
| Peak memory | 235100 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2582286695 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/s pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_intercept.2582286695 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/20.spi_device_intercept/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/20.spi_device_mailbox.1264874784 |
| Short name | T534 |
| Test name | |
| Test status | |
| Simulation time | 9761677911 ps |
| CPU time | 48.03 seconds |
| Started | Sep 01 02:55:20 PM UTC 24 |
| Finished | Sep 01 02:56:10 PM UTC 24 |
| Peak memory | 245344 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1264874784 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_mailbox.1264874784 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/20.spi_device_mailbox/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/20.spi_device_pass_addr_payload_swap.958627850 |
| Short name | T325 |
| Test name | |
| Test status | |
| Simulation time | 6233011115 ps |
| CPU time | 11.77 seconds |
| Started | Sep 01 02:55:18 PM UTC 24 |
| Finished | Sep 01 02:55:31 PM UTC 24 |
| Peak memory | 235028 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=958627850 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_31/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_pass_addr_payload_swap.958627850 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/20.spi_device_pass_addr_payload_swap/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/20.spi_device_pass_cmd_filtering.788592250 |
| Short name | T518 |
| Test name | |
| Test status | |
| Simulation time | 1435928449 ps |
| CPU time | 6.9 seconds |
| Started | Sep 01 02:55:17 PM UTC 24 |
| Finished | Sep 01 02:55:25 PM UTC 24 |
| Peak memory | 245212 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=788592250 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _08_31/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_pass_cmd_filtering.788592250 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/20.spi_device_pass_cmd_filtering/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/20.spi_device_read_buffer_direct.2768509700 |
| Short name | T521 |
| Test name | |
| Test status | |
| Simulation time | 220847955 ps |
| CPU time | 6.8 seconds |
| Started | Sep 01 02:55:29 PM UTC 24 |
| Finished | Sep 01 02:55:37 PM UTC 24 |
| Peak memory | 231316 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2768509700 -assert nopostproc +UVM_TESTNAME=spi_device _base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_read_buffer_direct.2768509700 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/20.spi_device_read_buffer_direct/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/20.spi_device_stress_all.2553269196 |
| Short name | T181 |
| Test name | |
| Test status | |
| Simulation time | 15439778646 ps |
| CPU time | 145.73 seconds |
| Started | Sep 01 02:55:33 PM UTC 24 |
| Finished | Sep 01 02:58:02 PM UTC 24 |
| Peak memory | 251460 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2553269196 -assert nopostproc +UVM_ TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_stress_all.2553269196 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/20.spi_device_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/20.spi_device_tpm_all.1280037742 |
| Short name | T523 |
| Test name | |
| Test status | |
| Simulation time | 1722309008 ps |
| CPU time | 21.44 seconds |
| Started | Sep 01 02:55:15 PM UTC 24 |
| Finished | Sep 01 02:55:38 PM UTC 24 |
| Peak memory | 227432 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1280037742 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_all.1280037742 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/20.spi_device_tpm_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/20.spi_device_tpm_read_hw_reg.3433536290 |
| Short name | T522 |
| Test name | |
| Test status | |
| Simulation time | 89586019684 ps |
| CPU time | 21.97 seconds |
| Started | Sep 01 02:55:14 PM UTC 24 |
| Finished | Sep 01 02:55:37 PM UTC 24 |
| Peak memory | 227628 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3433536290 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_31/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_read_hw_reg.3433536290 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/20.spi_device_tpm_read_hw_reg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/20.spi_device_tpm_rw.1515159036 |
| Short name | T517 |
| Test name | |
| Test status | |
| Simulation time | 138915548 ps |
| CPU time | 1.82 seconds |
| Started | Sep 01 02:55:16 PM UTC 24 |
| Finished | Sep 01 02:55:19 PM UTC 24 |
| Peak memory | 216532 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1515159036 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_rw.1515159036 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/20.spi_device_tpm_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/20.spi_device_tpm_sts_read.1252275948 |
| Short name | T516 |
| Test name | |
| Test status | |
| Simulation time | 371695326 ps |
| CPU time | 1.27 seconds |
| Started | Sep 01 02:55:15 PM UTC 24 |
| Finished | Sep 01 02:55:17 PM UTC 24 |
| Peak memory | 215868 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1252275948 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_3 1/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_sts_read.1252275948 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/20.spi_device_tpm_sts_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/20.spi_device_upload.2155365740 |
| Short name | T221 |
| Test name | |
| Test status | |
| Simulation time | 562370015 ps |
| CPU time | 6.98 seconds |
| Started | Sep 01 02:55:25 PM UTC 24 |
| Finished | Sep 01 02:55:33 PM UTC 24 |
| Peak memory | 245156 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2155365740 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_upload.2155365740 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/20.spi_device_upload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/21.spi_device_alert_test.299900482 |
| Short name | T536 |
| Test name | |
| Test status | |
| Simulation time | 23348507 ps |
| CPU time | 1.09 seconds |
| Started | Sep 01 02:56:11 PM UTC 24 |
| Finished | Sep 01 02:56:13 PM UTC 24 |
| Peak memory | 215804 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=299900482 -assert nopostproc +UVM_TEST NAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_alert_test.299900482 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/21.spi_device_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/21.spi_device_cfg_cmd.119560962 |
| Short name | T530 |
| Test name | |
| Test status | |
| Simulation time | 127893523 ps |
| CPU time | 3.27 seconds |
| Started | Sep 01 02:55:52 PM UTC 24 |
| Finished | Sep 01 02:55:57 PM UTC 24 |
| Peak memory | 244880 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=119560962 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_cfg_cmd.119560962 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/21.spi_device_cfg_cmd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/21.spi_device_csb_read.2730643501 |
| Short name | T524 |
| Test name | |
| Test status | |
| Simulation time | 155924106 ps |
| CPU time | 1.25 seconds |
| Started | Sep 01 02:55:38 PM UTC 24 |
| Finished | Sep 01 02:55:40 PM UTC 24 |
| Peak memory | 215808 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2730643501 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/sp i_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_csb_read.2730643501 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/21.spi_device_csb_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/21.spi_device_flash_all.2814718989 |
| Short name | T596 |
| Test name | |
| Test status | |
| Simulation time | 23097160905 ps |
| CPU time | 124.22 seconds |
| Started | Sep 01 02:56:01 PM UTC 24 |
| Finished | Sep 01 02:58:07 PM UTC 24 |
| Peak memory | 261720 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2814718989 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/s pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_all.2814718989 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/21.spi_device_flash_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/21.spi_device_flash_and_tpm.3732534665 |
| Short name | T394 |
| Test name | |
| Test status | |
| Simulation time | 37937697417 ps |
| CPU time | 114.48 seconds |
| Started | Sep 01 02:56:02 PM UTC 24 |
| Finished | Sep 01 02:57:59 PM UTC 24 |
| Peak memory | 261752 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3732534665 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_ 31/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_and_tpm.3732534665 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/21.spi_device_flash_and_tpm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/21.spi_device_flash_and_tpm_min_idle.4262174847 |
| Short name | T542 |
| Test name | |
| Test status | |
| Simulation time | 1521539589 ps |
| CPU time | 17.73 seconds |
| Started | Sep 01 02:56:08 PM UTC 24 |
| Finished | Sep 01 02:56:27 PM UTC 24 |
| Peak memory | 234940 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4262174847 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_31/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_and_tpm_min_idle.4262174847 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/21.spi_device_flash_and_tpm_min_idle/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/21.spi_device_flash_mode.1868531890 |
| Short name | T535 |
| Test name | |
| Test status | |
| Simulation time | 519095659 ps |
| CPU time | 13.68 seconds |
| Started | Sep 01 02:55:57 PM UTC 24 |
| Finished | Sep 01 02:56:11 PM UTC 24 |
| Peak memory | 261580 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1868531890 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/ spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_mode.1868531890 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/21.spi_device_flash_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/21.spi_device_flash_mode_ignore_cmds.3789373230 |
| Short name | T555 |
| Test name | |
| Test status | |
| Simulation time | 4783243077 ps |
| CPU time | 58.48 seconds |
| Started | Sep 01 02:55:57 PM UTC 24 |
| Finished | Sep 01 02:56:57 PM UTC 24 |
| Peak memory | 247372 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3789373230 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_31/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_mode_ignore_cmds.3789373230 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/21.spi_device_flash_mode_ignore_cmds/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/21.spi_device_intercept.2177662120 |
| Short name | T528 |
| Test name | |
| Test status | |
| Simulation time | 2308490714 ps |
| CPU time | 9.68 seconds |
| Started | Sep 01 02:55:45 PM UTC 24 |
| Finished | Sep 01 02:55:56 PM UTC 24 |
| Peak memory | 245388 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2177662120 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/s pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_intercept.2177662120 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/21.spi_device_intercept/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/21.spi_device_mailbox.3450351585 |
| Short name | T243 |
| Test name | |
| Test status | |
| Simulation time | 20400156124 ps |
| CPU time | 54.56 seconds |
| Started | Sep 01 02:55:46 PM UTC 24 |
| Finished | Sep 01 02:56:42 PM UTC 24 |
| Peak memory | 245332 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3450351585 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_mailbox.3450351585 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/21.spi_device_mailbox/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/21.spi_device_pass_addr_payload_swap.428456746 |
| Short name | T531 |
| Test name | |
| Test status | |
| Simulation time | 1152537129 ps |
| CPU time | 15.06 seconds |
| Started | Sep 01 02:55:44 PM UTC 24 |
| Finished | Sep 01 02:56:00 PM UTC 24 |
| Peak memory | 235088 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=428456746 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_31/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_pass_addr_payload_swap.428456746 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/21.spi_device_pass_addr_payload_swap/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/21.spi_device_pass_cmd_filtering.4211521002 |
| Short name | T543 |
| Test name | |
| Test status | |
| Simulation time | 18518662387 ps |
| CPU time | 47.37 seconds |
| Started | Sep 01 02:55:42 PM UTC 24 |
| Finished | Sep 01 02:56:31 PM UTC 24 |
| Peak memory | 235032 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4211521002 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_08_31/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_pass_cmd_filtering.4211521002 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/21.spi_device_pass_cmd_filtering/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/21.spi_device_read_buffer_direct.1155090858 |
| Short name | T533 |
| Test name | |
| Test status | |
| Simulation time | 2489469550 ps |
| CPU time | 10.77 seconds |
| Started | Sep 01 02:55:58 PM UTC 24 |
| Finished | Sep 01 02:56:09 PM UTC 24 |
| Peak memory | 231384 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1155090858 -assert nopostproc +UVM_TESTNAME=spi_device _base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_read_buffer_direct.1155090858 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/21.spi_device_read_buffer_direct/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/21.spi_device_stress_all.3063946038 |
| Short name | T155 |
| Test name | |
| Test status | |
| Simulation time | 10586749386 ps |
| CPU time | 54.82 seconds |
| Started | Sep 01 02:56:10 PM UTC 24 |
| Finished | Sep 01 02:57:06 PM UTC 24 |
| Peak memory | 265904 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3063946038 -assert nopostproc +UVM_ TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_stress_all.3063946038 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/21.spi_device_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/21.spi_device_tpm_all.3010356561 |
| Short name | T538 |
| Test name | |
| Test status | |
| Simulation time | 5449643504 ps |
| CPU time | 38.38 seconds |
| Started | Sep 01 02:55:38 PM UTC 24 |
| Finished | Sep 01 02:56:17 PM UTC 24 |
| Peak memory | 227548 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3010356561 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_all.3010356561 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/21.spi_device_tpm_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/21.spi_device_tpm_read_hw_reg.3923989360 |
| Short name | T527 |
| Test name | |
| Test status | |
| Simulation time | 1398041003 ps |
| CPU time | 5.28 seconds |
| Started | Sep 01 02:55:38 PM UTC 24 |
| Finished | Sep 01 02:55:44 PM UTC 24 |
| Peak memory | 227324 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3923989360 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_31/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_read_hw_reg.3923989360 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/21.spi_device_tpm_read_hw_reg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/21.spi_device_tpm_rw.526768132 |
| Short name | T526 |
| Test name | |
| Test status | |
| Simulation time | 12178355 ps |
| CPU time | 1.11 seconds |
| Started | Sep 01 02:55:41 PM UTC 24 |
| Finished | Sep 01 02:55:43 PM UTC 24 |
| Peak memory | 215736 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=526768132 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/spi_d evice_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_rw.526768132 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/21.spi_device_tpm_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/21.spi_device_tpm_sts_read.1269746791 |
| Short name | T525 |
| Test name | |
| Test status | |
| Simulation time | 104066018 ps |
| CPU time | 1.21 seconds |
| Started | Sep 01 02:55:39 PM UTC 24 |
| Finished | Sep 01 02:55:41 PM UTC 24 |
| Peak memory | 215868 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1269746791 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_3 1/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_sts_read.1269746791 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/21.spi_device_tpm_sts_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/21.spi_device_upload.3614258828 |
| Short name | T532 |
| Test name | |
| Test status | |
| Simulation time | 1122590369 ps |
| CPU time | 11.52 seconds |
| Started | Sep 01 02:55:48 PM UTC 24 |
| Finished | Sep 01 02:56:01 PM UTC 24 |
| Peak memory | 245344 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3614258828 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_upload.3614258828 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/21.spi_device_upload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/22.spi_device_alert_test.2374887893 |
| Short name | T551 |
| Test name | |
| Test status | |
| Simulation time | 21972515 ps |
| CPU time | 1.12 seconds |
| Started | Sep 01 02:56:50 PM UTC 24 |
| Finished | Sep 01 02:56:53 PM UTC 24 |
| Peak memory | 215740 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2374887893 -assert nopostproc +UVM_TES TNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_alert_test.2374887893 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/22.spi_device_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/22.spi_device_cfg_cmd.2510284156 |
| Short name | T286 |
| Test name | |
| Test status | |
| Simulation time | 641842688 ps |
| CPU time | 8.47 seconds |
| Started | Sep 01 02:56:32 PM UTC 24 |
| Finished | Sep 01 02:56:42 PM UTC 24 |
| Peak memory | 245152 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2510284156 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_cfg_cmd.2510284156 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/22.spi_device_cfg_cmd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/22.spi_device_csb_read.2858960665 |
| Short name | T537 |
| Test name | |
| Test status | |
| Simulation time | 20613719 ps |
| CPU time | 1.22 seconds |
| Started | Sep 01 02:56:12 PM UTC 24 |
| Finished | Sep 01 02:56:15 PM UTC 24 |
| Peak memory | 215632 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2858960665 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/sp i_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_csb_read.2858960665 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/22.spi_device_csb_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/22.spi_device_flash_all.1610590460 |
| Short name | T545 |
| Test name | |
| Test status | |
| Simulation time | 227822846 ps |
| CPU time | 1.22 seconds |
| Started | Sep 01 02:56:43 PM UTC 24 |
| Finished | Sep 01 02:56:45 PM UTC 24 |
| Peak memory | 225728 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1610590460 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/s pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_all.1610590460 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/22.spi_device_flash_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/22.spi_device_flash_and_tpm.4256956950 |
| Short name | T226 |
| Test name | |
| Test status | |
| Simulation time | 96562050993 ps |
| CPU time | 262.65 seconds |
| Started | Sep 01 02:56:46 PM UTC 24 |
| Finished | Sep 01 03:01:12 PM UTC 24 |
| Peak memory | 267984 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4256956950 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_ 31/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_and_tpm.4256956950 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/22.spi_device_flash_and_tpm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/22.spi_device_flash_and_tpm_min_idle.2640784069 |
| Short name | T598 |
| Test name | |
| Test status | |
| Simulation time | 10969558552 ps |
| CPU time | 81.68 seconds |
| Started | Sep 01 02:56:46 PM UTC 24 |
| Finished | Sep 01 02:58:10 PM UTC 24 |
| Peak memory | 267940 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2640784069 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_31/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_and_tpm_min_idle.2640784069 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/22.spi_device_flash_and_tpm_min_idle/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/22.spi_device_flash_mode.289001951 |
| Short name | T547 |
| Test name | |
| Test status | |
| Simulation time | 2271605911 ps |
| CPU time | 10.48 seconds |
| Started | Sep 01 02:56:36 PM UTC 24 |
| Finished | Sep 01 02:56:47 PM UTC 24 |
| Peak memory | 235020 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=289001951 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/s pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_mode.289001951 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/22.spi_device_flash_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/22.spi_device_flash_mode_ignore_cmds.4137307844 |
| Short name | T327 |
| Test name | |
| Test status | |
| Simulation time | 3243203163 ps |
| CPU time | 75.45 seconds |
| Started | Sep 01 02:56:36 PM UTC 24 |
| Finished | Sep 01 02:57:53 PM UTC 24 |
| Peak memory | 263820 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4137307844 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_31/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_mode_ignore_cmds.4137307844 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/22.spi_device_flash_mode_ignore_cmds/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/22.spi_device_intercept.3207190774 |
| Short name | T546 |
| Test name | |
| Test status | |
| Simulation time | 3160224577 ps |
| CPU time | 19.2 seconds |
| Started | Sep 01 02:56:25 PM UTC 24 |
| Finished | Sep 01 02:56:45 PM UTC 24 |
| Peak memory | 245336 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3207190774 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/s pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_intercept.3207190774 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/22.spi_device_intercept/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/22.spi_device_mailbox.3445599340 |
| Short name | T337 |
| Test name | |
| Test status | |
| Simulation time | 6193813369 ps |
| CPU time | 53.09 seconds |
| Started | Sep 01 02:56:28 PM UTC 24 |
| Finished | Sep 01 02:57:23 PM UTC 24 |
| Peak memory | 245264 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3445599340 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_mailbox.3445599340 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/22.spi_device_mailbox/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/22.spi_device_pass_addr_payload_swap.2067613381 |
| Short name | T360 |
| Test name | |
| Test status | |
| Simulation time | 712519642 ps |
| CPU time | 7.1 seconds |
| Started | Sep 01 02:56:23 PM UTC 24 |
| Finished | Sep 01 02:56:31 PM UTC 24 |
| Peak memory | 245220 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2067613381 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_31/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_pass_addr_payload_swap.2067613381 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/22.spi_device_pass_addr_payload_swap/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/22.spi_device_pass_cmd_filtering.4083070997 |
| Short name | T568 |
| Test name | |
| Test status | |
| Simulation time | 23431569479 ps |
| CPU time | 60.42 seconds |
| Started | Sep 01 02:56:22 PM UTC 24 |
| Finished | Sep 01 02:57:24 PM UTC 24 |
| Peak memory | 261860 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4083070997 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_08_31/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_pass_cmd_filtering.4083070997 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/22.spi_device_pass_cmd_filtering/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/22.spi_device_read_buffer_direct.744315088 |
| Short name | T153 |
| Test name | |
| Test status | |
| Simulation time | 5545116380 ps |
| CPU time | 19.98 seconds |
| Started | Sep 01 02:56:43 PM UTC 24 |
| Finished | Sep 01 02:57:04 PM UTC 24 |
| Peak memory | 231392 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=744315088 -assert nopostproc +UVM_TESTNAME=spi_device_ base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_read_buffer_direct.744315088 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/22.spi_device_read_buffer_direct/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/22.spi_device_stress_all.1030996559 |
| Short name | T550 |
| Test name | |
| Test status | |
| Simulation time | 46137573 ps |
| CPU time | 1.62 seconds |
| Started | Sep 01 02:56:48 PM UTC 24 |
| Finished | Sep 01 02:56:51 PM UTC 24 |
| Peak memory | 216232 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1030996559 -assert nopostproc +UVM_ TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_stress_all.1030996559 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/22.spi_device_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/22.spi_device_tpm_all.2476087032 |
| Short name | T548 |
| Test name | |
| Test status | |
| Simulation time | 5760509752 ps |
| CPU time | 32.34 seconds |
| Started | Sep 01 02:56:15 PM UTC 24 |
| Finished | Sep 01 02:56:49 PM UTC 24 |
| Peak memory | 227608 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2476087032 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_all.2476087032 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/22.spi_device_tpm_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/22.spi_device_tpm_read_hw_reg.122677693 |
| Short name | T539 |
| Test name | |
| Test status | |
| Simulation time | 90037974 ps |
| CPU time | 2.74 seconds |
| Started | Sep 01 02:56:14 PM UTC 24 |
| Finished | Sep 01 02:56:18 PM UTC 24 |
| Peak memory | 216588 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=122677693 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08 _31/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_read_hw_reg.122677693 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/22.spi_device_tpm_read_hw_reg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/22.spi_device_tpm_rw.1633732124 |
| Short name | T541 |
| Test name | |
| Test status | |
| Simulation time | 61843804 ps |
| CPU time | 1.08 seconds |
| Started | Sep 01 02:56:20 PM UTC 24 |
| Finished | Sep 01 02:56:22 PM UTC 24 |
| Peak memory | 215740 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1633732124 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_rw.1633732124 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/22.spi_device_tpm_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/22.spi_device_tpm_sts_read.754708310 |
| Short name | T540 |
| Test name | |
| Test status | |
| Simulation time | 30113518 ps |
| CPU time | 1.36 seconds |
| Started | Sep 01 02:56:19 PM UTC 24 |
| Finished | Sep 01 02:56:21 PM UTC 24 |
| Peak memory | 215864 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=754708310 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31 /spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_sts_read.754708310 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/22.spi_device_tpm_sts_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/22.spi_device_upload.3261805587 |
| Short name | T549 |
| Test name | |
| Test status | |
| Simulation time | 1168286650 ps |
| CPU time | 16.84 seconds |
| Started | Sep 01 02:56:31 PM UTC 24 |
| Finished | Sep 01 02:56:50 PM UTC 24 |
| Peak memory | 245212 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3261805587 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_upload.3261805587 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/22.spi_device_upload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/23.spi_device_alert_test.3647496895 |
| Short name | T558 |
| Test name | |
| Test status | |
| Simulation time | 15744507 ps |
| CPU time | 1.13 seconds |
| Started | Sep 01 02:57:10 PM UTC 24 |
| Finished | Sep 01 02:57:12 PM UTC 24 |
| Peak memory | 215740 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3647496895 -assert nopostproc +UVM_TES TNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_alert_test.3647496895 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/23.spi_device_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/23.spi_device_cfg_cmd.3642294767 |
| Short name | T158 |
| Test name | |
| Test status | |
| Simulation time | 2052640717 ps |
| CPU time | 8.12 seconds |
| Started | Sep 01 02:57:01 PM UTC 24 |
| Finished | Sep 01 02:57:11 PM UTC 24 |
| Peak memory | 245200 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3642294767 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_cfg_cmd.3642294767 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/23.spi_device_cfg_cmd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/23.spi_device_csb_read.3752961218 |
| Short name | T552 |
| Test name | |
| Test status | |
| Simulation time | 19591993 ps |
| CPU time | 1.18 seconds |
| Started | Sep 01 02:56:50 PM UTC 24 |
| Finished | Sep 01 02:56:53 PM UTC 24 |
| Peak memory | 215808 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3752961218 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/sp i_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_csb_read.3752961218 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/23.spi_device_csb_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/23.spi_device_flash_all.640995679 |
| Short name | T647 |
| Test name | |
| Test status | |
| Simulation time | 13480736181 ps |
| CPU time | 129.19 seconds |
| Started | Sep 01 02:57:05 PM UTC 24 |
| Finished | Sep 01 02:59:17 PM UTC 24 |
| Peak memory | 261788 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=640995679 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/sp i_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_all.640995679 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/23.spi_device_flash_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/23.spi_device_flash_and_tpm.524120592 |
| Short name | T610 |
| Test name | |
| Test status | |
| Simulation time | 22263909426 ps |
| CPU time | 75.61 seconds |
| Started | Sep 01 02:57:05 PM UTC 24 |
| Finished | Sep 01 02:58:23 PM UTC 24 |
| Peak memory | 261764 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=524120592 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_3 1/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_and_tpm.524120592 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/23.spi_device_flash_and_tpm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/23.spi_device_flash_and_tpm_min_idle.1322243702 |
| Short name | T632 |
| Test name | |
| Test status | |
| Simulation time | 27937012620 ps |
| CPU time | 105.81 seconds |
| Started | Sep 01 02:57:08 PM UTC 24 |
| Finished | Sep 01 02:58:55 PM UTC 24 |
| Peak memory | 235144 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1322243702 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_31/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_and_tpm_min_idle.1322243702 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/23.spi_device_flash_and_tpm_min_idle/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/23.spi_device_flash_mode.1978919746 |
| Short name | T374 |
| Test name | |
| Test status | |
| Simulation time | 338494458 ps |
| CPU time | 12.64 seconds |
| Started | Sep 01 02:57:02 PM UTC 24 |
| Finished | Sep 01 02:57:15 PM UTC 24 |
| Peak memory | 261596 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1978919746 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/ spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_mode.1978919746 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/23.spi_device_flash_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/23.spi_device_flash_mode_ignore_cmds.1771044391 |
| Short name | T924 |
| Test name | |
| Test status | |
| Simulation time | 583685217066 ps |
| CPU time | 473.62 seconds |
| Started | Sep 01 02:57:04 PM UTC 24 |
| Finished | Sep 01 03:05:04 PM UTC 24 |
| Peak memory | 278176 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1771044391 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_31/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_mode_ignore_cmds.1771044391 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/23.spi_device_flash_mode_ignore_cmds/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/23.spi_device_intercept.2989207188 |
| Short name | T288 |
| Test name | |
| Test status | |
| Simulation time | 5118999171 ps |
| CPU time | 19.77 seconds |
| Started | Sep 01 02:56:58 PM UTC 24 |
| Finished | Sep 01 02:57:19 PM UTC 24 |
| Peak memory | 245452 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2989207188 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/s pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_intercept.2989207188 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/23.spi_device_intercept/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/23.spi_device_mailbox.951060035 |
| Short name | T592 |
| Test name | |
| Test status | |
| Simulation time | 28983998306 ps |
| CPU time | 64.73 seconds |
| Started | Sep 01 02:56:58 PM UTC 24 |
| Finished | Sep 01 02:58:05 PM UTC 24 |
| Peak memory | 251428 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=951060035 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_mailbox.951060035 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/23.spi_device_mailbox/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/23.spi_device_pass_addr_payload_swap.1631357121 |
| Short name | T560 |
| Test name | |
| Test status | |
| Simulation time | 5717859891 ps |
| CPU time | 16.52 seconds |
| Started | Sep 01 02:56:57 PM UTC 24 |
| Finished | Sep 01 02:57:15 PM UTC 24 |
| Peak memory | 251368 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1631357121 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_31/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_pass_addr_payload_swap.1631357121 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/23.spi_device_pass_addr_payload_swap/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/23.spi_device_pass_cmd_filtering.1572114619 |
| Short name | T154 |
| Test name | |
| Test status | |
| Simulation time | 304112566 ps |
| CPU time | 6.05 seconds |
| Started | Sep 01 02:56:57 PM UTC 24 |
| Finished | Sep 01 02:57:04 PM UTC 24 |
| Peak memory | 234940 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1572114619 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_08_31/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_pass_cmd_filtering.1572114619 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/23.spi_device_pass_cmd_filtering/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/23.spi_device_read_buffer_direct.2591529928 |
| Short name | T157 |
| Test name | |
| Test status | |
| Simulation time | 313946830 ps |
| CPU time | 5.38 seconds |
| Started | Sep 01 02:57:04 PM UTC 24 |
| Finished | Sep 01 02:57:10 PM UTC 24 |
| Peak memory | 231256 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2591529928 -assert nopostproc +UVM_TESTNAME=spi_device _base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_read_buffer_direct.2591529928 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/23.spi_device_read_buffer_direct/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/23.spi_device_stress_all.2313229638 |
| Short name | T260 |
| Test name | |
| Test status | |
| Simulation time | 41713608774 ps |
| CPU time | 176.09 seconds |
| Started | Sep 01 02:57:08 PM UTC 24 |
| Finished | Sep 01 03:00:07 PM UTC 24 |
| Peak memory | 278172 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2313229638 -assert nopostproc +UVM_ TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_stress_all.2313229638 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/23.spi_device_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/23.spi_device_tpm_all.294753462 |
| Short name | T554 |
| Test name | |
| Test status | |
| Simulation time | 31378555 ps |
| CPU time | 1.13 seconds |
| Started | Sep 01 02:56:54 PM UTC 24 |
| Finished | Sep 01 02:56:56 PM UTC 24 |
| Peak memory | 215684 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=294753462 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_all.294753462 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/23.spi_device_tpm_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/23.spi_device_tpm_read_hw_reg.4105009171 |
| Short name | T563 |
| Test name | |
| Test status | |
| Simulation time | 5975328843 ps |
| CPU time | 25.03 seconds |
| Started | Sep 01 02:56:52 PM UTC 24 |
| Finished | Sep 01 02:57:18 PM UTC 24 |
| Peak memory | 227624 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4105009171 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_31/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_read_hw_reg.4105009171 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/23.spi_device_tpm_read_hw_reg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/23.spi_device_tpm_rw.130046420 |
| Short name | T557 |
| Test name | |
| Test status | |
| Simulation time | 56621688 ps |
| CPU time | 2.4 seconds |
| Started | Sep 01 02:56:54 PM UTC 24 |
| Finished | Sep 01 02:56:57 PM UTC 24 |
| Peak memory | 227560 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=130046420 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/spi_d evice_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_rw.130046420 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/23.spi_device_tpm_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/23.spi_device_tpm_sts_read.1949133016 |
| Short name | T553 |
| Test name | |
| Test status | |
| Simulation time | 15084501 ps |
| CPU time | 1.06 seconds |
| Started | Sep 01 02:56:54 PM UTC 24 |
| Finished | Sep 01 02:56:56 PM UTC 24 |
| Peak memory | 215808 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1949133016 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_3 1/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_sts_read.1949133016 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/23.spi_device_tpm_sts_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/23.spi_device_upload.3941883350 |
| Short name | T152 |
| Test name | |
| Test status | |
| Simulation time | 80540453 ps |
| CPU time | 3.8 seconds |
| Started | Sep 01 02:56:58 PM UTC 24 |
| Finished | Sep 01 02:57:03 PM UTC 24 |
| Peak memory | 245148 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3941883350 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_upload.3941883350 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/23.spi_device_upload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/24.spi_device_alert_test.2139518612 |
| Short name | T569 |
| Test name | |
| Test status | |
| Simulation time | 56081807 ps |
| CPU time | 1.11 seconds |
| Started | Sep 01 02:57:25 PM UTC 24 |
| Finished | Sep 01 02:57:27 PM UTC 24 |
| Peak memory | 215740 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2139518612 -assert nopostproc +UVM_TES TNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_alert_test.2139518612 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/24.spi_device_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/24.spi_device_cfg_cmd.2813703960 |
| Short name | T567 |
| Test name | |
| Test status | |
| Simulation time | 73255107 ps |
| CPU time | 5.05 seconds |
| Started | Sep 01 02:57:18 PM UTC 24 |
| Finished | Sep 01 02:57:24 PM UTC 24 |
| Peak memory | 245136 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2813703960 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_cfg_cmd.2813703960 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/24.spi_device_cfg_cmd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/24.spi_device_csb_read.1332623879 |
| Short name | T559 |
| Test name | |
| Test status | |
| Simulation time | 15143850 ps |
| CPU time | 0.96 seconds |
| Started | Sep 01 02:57:11 PM UTC 24 |
| Finished | Sep 01 02:57:13 PM UTC 24 |
| Peak memory | 215804 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1332623879 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/sp i_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_csb_read.1332623879 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/24.spi_device_csb_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/24.spi_device_flash_all.3596472717 |
| Short name | T794 |
| Test name | |
| Test status | |
| Simulation time | 245142421705 ps |
| CPU time | 309.79 seconds |
| Started | Sep 01 02:57:20 PM UTC 24 |
| Finished | Sep 01 03:02:34 PM UTC 24 |
| Peak memory | 263768 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3596472717 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/s pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_all.3596472717 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/24.spi_device_flash_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/24.spi_device_flash_and_tpm.3513697336 |
| Short name | T628 |
| Test name | |
| Test status | |
| Simulation time | 3914203005 ps |
| CPU time | 83.25 seconds |
| Started | Sep 01 02:57:23 PM UTC 24 |
| Finished | Sep 01 02:58:49 PM UTC 24 |
| Peak memory | 261696 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3513697336 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_ 31/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_and_tpm.3513697336 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/24.spi_device_flash_and_tpm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/24.spi_device_flash_and_tpm_min_idle.1510477432 |
| Short name | T588 |
| Test name | |
| Test status | |
| Simulation time | 1414100644 ps |
| CPU time | 32.78 seconds |
| Started | Sep 01 02:57:23 PM UTC 24 |
| Finished | Sep 01 02:57:57 PM UTC 24 |
| Peak memory | 263824 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1510477432 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_31/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_and_tpm_min_idle.1510477432 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/24.spi_device_flash_and_tpm_min_idle/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/24.spi_device_flash_mode.111093590 |
| Short name | T566 |
| Test name | |
| Test status | |
| Simulation time | 78219929 ps |
| CPU time | 3.95 seconds |
| Started | Sep 01 02:57:18 PM UTC 24 |
| Finished | Sep 01 02:57:23 PM UTC 24 |
| Peak memory | 245152 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=111093590 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/s pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_mode.111093590 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/24.spi_device_flash_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/24.spi_device_intercept.843793414 |
| Short name | T575 |
| Test name | |
| Test status | |
| Simulation time | 1877101147 ps |
| CPU time | 16.3 seconds |
| Started | Sep 01 02:57:16 PM UTC 24 |
| Finished | Sep 01 02:57:34 PM UTC 24 |
| Peak memory | 245152 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=843793414 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/sp i_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_intercept.843793414 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/24.spi_device_intercept/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/24.spi_device_mailbox.3439659948 |
| Short name | T649 |
| Test name | |
| Test status | |
| Simulation time | 10900387580 ps |
| CPU time | 120.29 seconds |
| Started | Sep 01 02:57:16 PM UTC 24 |
| Finished | Sep 01 02:59:19 PM UTC 24 |
| Peak memory | 251412 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3439659948 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_mailbox.3439659948 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/24.spi_device_mailbox/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/24.spi_device_pass_addr_payload_swap.3575768360 |
| Short name | T564 |
| Test name | |
| Test status | |
| Simulation time | 31760208 ps |
| CPU time | 3.23 seconds |
| Started | Sep 01 02:57:14 PM UTC 24 |
| Finished | Sep 01 02:57:18 PM UTC 24 |
| Peak memory | 244904 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3575768360 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_31/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_pass_addr_payload_swap.3575768360 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/24.spi_device_pass_addr_payload_swap/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/24.spi_device_pass_cmd_filtering.3478617902 |
| Short name | T574 |
| Test name | |
| Test status | |
| Simulation time | 4319839539 ps |
| CPU time | 15.59 seconds |
| Started | Sep 01 02:57:14 PM UTC 24 |
| Finished | Sep 01 02:57:31 PM UTC 24 |
| Peak memory | 245336 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3478617902 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_08_31/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_pass_cmd_filtering.3478617902 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/24.spi_device_pass_cmd_filtering/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/24.spi_device_read_buffer_direct.2564922917 |
| Short name | T578 |
| Test name | |
| Test status | |
| Simulation time | 10534976607 ps |
| CPU time | 16.2 seconds |
| Started | Sep 01 02:57:19 PM UTC 24 |
| Finished | Sep 01 02:57:36 PM UTC 24 |
| Peak memory | 233916 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2564922917 -assert nopostproc +UVM_TESTNAME=spi_device _base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_read_buffer_direct.2564922917 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/24.spi_device_read_buffer_direct/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/24.spi_device_stress_all.1611304657 |
| Short name | T571 |
| Test name | |
| Test status | |
| Simulation time | 343863809 ps |
| CPU time | 1.55 seconds |
| Started | Sep 01 02:57:25 PM UTC 24 |
| Finished | Sep 01 02:57:27 PM UTC 24 |
| Peak memory | 225928 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1611304657 -assert nopostproc +UVM_ TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_stress_all.1611304657 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/24.spi_device_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/24.spi_device_tpm_all.665641297 |
| Short name | T582 |
| Test name | |
| Test status | |
| Simulation time | 20511709975 ps |
| CPU time | 39.32 seconds |
| Started | Sep 01 02:57:12 PM UTC 24 |
| Finished | Sep 01 02:57:53 PM UTC 24 |
| Peak memory | 227644 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=665641297 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_all.665641297 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/24.spi_device_tpm_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/24.spi_device_tpm_read_hw_reg.2788432876 |
| Short name | T565 |
| Test name | |
| Test status | |
| Simulation time | 2193063649 ps |
| CPU time | 8.64 seconds |
| Started | Sep 01 02:57:12 PM UTC 24 |
| Finished | Sep 01 02:57:22 PM UTC 24 |
| Peak memory | 227540 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2788432876 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_31/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_read_hw_reg.2788432876 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/24.spi_device_tpm_read_hw_reg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/24.spi_device_tpm_rw.2702309786 |
| Short name | T562 |
| Test name | |
| Test status | |
| Simulation time | 24965778 ps |
| CPU time | 1.58 seconds |
| Started | Sep 01 02:57:14 PM UTC 24 |
| Finished | Sep 01 02:57:16 PM UTC 24 |
| Peak memory | 216392 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2702309786 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_rw.2702309786 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/24.spi_device_tpm_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/24.spi_device_tpm_sts_read.522874766 |
| Short name | T561 |
| Test name | |
| Test status | |
| Simulation time | 120413991 ps |
| CPU time | 1.48 seconds |
| Started | Sep 01 02:57:12 PM UTC 24 |
| Finished | Sep 01 02:57:15 PM UTC 24 |
| Peak memory | 215864 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=522874766 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31 /spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_sts_read.522874766 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/24.spi_device_tpm_sts_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/24.spi_device_upload.3146717794 |
| Short name | T572 |
| Test name | |
| Test status | |
| Simulation time | 1263189226 ps |
| CPU time | 12.97 seconds |
| Started | Sep 01 02:57:16 PM UTC 24 |
| Finished | Sep 01 02:57:31 PM UTC 24 |
| Peak memory | 234956 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3146717794 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_upload.3146717794 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/24.spi_device_upload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/25.spi_device_alert_test.4155356115 |
| Short name | T585 |
| Test name | |
| Test status | |
| Simulation time | 11856289 ps |
| CPU time | 1.13 seconds |
| Started | Sep 01 02:57:54 PM UTC 24 |
| Finished | Sep 01 02:57:56 PM UTC 24 |
| Peak memory | 215740 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4155356115 -assert nopostproc +UVM_TES TNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_alert_test.4155356115 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/25.spi_device_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/25.spi_device_cfg_cmd.3711734585 |
| Short name | T310 |
| Test name | |
| Test status | |
| Simulation time | 78002639 ps |
| CPU time | 3.59 seconds |
| Started | Sep 01 02:57:38 PM UTC 24 |
| Finished | Sep 01 02:57:42 PM UTC 24 |
| Peak memory | 245208 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3711734585 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_cfg_cmd.3711734585 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/25.spi_device_cfg_cmd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/25.spi_device_csb_read.4110517926 |
| Short name | T570 |
| Test name | |
| Test status | |
| Simulation time | 23704908 ps |
| CPU time | 1.16 seconds |
| Started | Sep 01 02:57:25 PM UTC 24 |
| Finished | Sep 01 02:57:27 PM UTC 24 |
| Peak memory | 215804 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4110517926 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/sp i_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_csb_read.4110517926 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/25.spi_device_csb_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/25.spi_device_flash_all.1699794223 |
| Short name | T608 |
| Test name | |
| Test status | |
| Simulation time | 1187550966 ps |
| CPU time | 28.65 seconds |
| Started | Sep 01 02:57:46 PM UTC 24 |
| Finished | Sep 01 02:58:17 PM UTC 24 |
| Peak memory | 245192 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1699794223 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/s pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_all.1699794223 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/25.spi_device_flash_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/25.spi_device_flash_and_tpm_min_idle.1460208169 |
| Short name | T248 |
| Test name | |
| Test status | |
| Simulation time | 4176537764 ps |
| CPU time | 128.62 seconds |
| Started | Sep 01 02:57:47 PM UTC 24 |
| Finished | Sep 01 02:59:59 PM UTC 24 |
| Peak memory | 284304 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1460208169 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_31/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_and_tpm_min_idle.1460208169 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/25.spi_device_flash_and_tpm_min_idle/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/25.spi_device_flash_mode.434129686 |
| Short name | T614 |
| Test name | |
| Test status | |
| Simulation time | 8806418742 ps |
| CPU time | 38.46 seconds |
| Started | Sep 01 02:57:44 PM UTC 24 |
| Finished | Sep 01 02:58:26 PM UTC 24 |
| Peak memory | 247388 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=434129686 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/s pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_mode.434129686 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/25.spi_device_flash_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/25.spi_device_flash_mode_ignore_cmds.1201274913 |
| Short name | T707 |
| Test name | |
| Test status | |
| Simulation time | 16538214348 ps |
| CPU time | 172.27 seconds |
| Started | Sep 01 02:57:45 PM UTC 24 |
| Finished | Sep 01 03:00:41 PM UTC 24 |
| Peak memory | 261840 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1201274913 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_31/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_mode_ignore_cmds.1201274913 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/25.spi_device_flash_mode_ignore_cmds/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/25.spi_device_intercept.378463609 |
| Short name | T583 |
| Test name | |
| Test status | |
| Simulation time | 16557528627 ps |
| CPU time | 18.17 seconds |
| Started | Sep 01 02:57:35 PM UTC 24 |
| Finished | Sep 01 02:57:54 PM UTC 24 |
| Peak memory | 235088 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=378463609 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/sp i_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_intercept.378463609 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/25.spi_device_intercept/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/25.spi_device_mailbox.3812669406 |
| Short name | T338 |
| Test name | |
| Test status | |
| Simulation time | 610868339 ps |
| CPU time | 24.02 seconds |
| Started | Sep 01 02:57:35 PM UTC 24 |
| Finished | Sep 01 02:58:01 PM UTC 24 |
| Peak memory | 261536 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3812669406 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_mailbox.3812669406 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/25.spi_device_mailbox/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/25.spi_device_pass_addr_payload_swap.1174103705 |
| Short name | T580 |
| Test name | |
| Test status | |
| Simulation time | 7500843112 ps |
| CPU time | 11.73 seconds |
| Started | Sep 01 02:57:32 PM UTC 24 |
| Finished | Sep 01 02:57:45 PM UTC 24 |
| Peak memory | 245348 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1174103705 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_31/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_pass_addr_payload_swap.1174103705 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/25.spi_device_pass_addr_payload_swap/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/25.spi_device_pass_cmd_filtering.2835946018 |
| Short name | T577 |
| Test name | |
| Test status | |
| Simulation time | 202874275 ps |
| CPU time | 2.57 seconds |
| Started | Sep 01 02:57:32 PM UTC 24 |
| Finished | Sep 01 02:57:35 PM UTC 24 |
| Peak memory | 233488 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2835946018 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_08_31/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_pass_cmd_filtering.2835946018 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/25.spi_device_pass_cmd_filtering/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/25.spi_device_read_buffer_direct.2367277062 |
| Short name | T587 |
| Test name | |
| Test status | |
| Simulation time | 612448356 ps |
| CPU time | 10.09 seconds |
| Started | Sep 01 02:57:45 PM UTC 24 |
| Finished | Sep 01 02:57:57 PM UTC 24 |
| Peak memory | 229208 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2367277062 -assert nopostproc +UVM_TESTNAME=spi_device _base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_read_buffer_direct.2367277062 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/25.spi_device_read_buffer_direct/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/25.spi_device_stress_all.1952907548 |
| Short name | T182 |
| Test name | |
| Test status | |
| Simulation time | 148149235276 ps |
| CPU time | 150.69 seconds |
| Started | Sep 01 02:57:51 PM UTC 24 |
| Finished | Sep 01 03:00:24 PM UTC 24 |
| Peak memory | 261772 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1952907548 -assert nopostproc +UVM_ TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_stress_all.1952907548 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/25.spi_device_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/25.spi_device_tpm_all.509449356 |
| Short name | T579 |
| Test name | |
| Test status | |
| Simulation time | 4588937898 ps |
| CPU time | 14.72 seconds |
| Started | Sep 01 02:57:28 PM UTC 24 |
| Finished | Sep 01 02:57:44 PM UTC 24 |
| Peak memory | 227608 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=509449356 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_all.509449356 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/25.spi_device_tpm_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/25.spi_device_tpm_read_hw_reg.768950925 |
| Short name | T581 |
| Test name | |
| Test status | |
| Simulation time | 2494556878 ps |
| CPU time | 16.68 seconds |
| Started | Sep 01 02:57:28 PM UTC 24 |
| Finished | Sep 01 02:57:46 PM UTC 24 |
| Peak memory | 227536 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=768950925 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08 _31/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_read_hw_reg.768950925 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/25.spi_device_tpm_read_hw_reg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/25.spi_device_tpm_rw.2912232060 |
| Short name | T576 |
| Test name | |
| Test status | |
| Simulation time | 23305401 ps |
| CPU time | 1.03 seconds |
| Started | Sep 01 02:57:32 PM UTC 24 |
| Finished | Sep 01 02:57:34 PM UTC 24 |
| Peak memory | 215844 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2912232060 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_rw.2912232060 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/25.spi_device_tpm_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/25.spi_device_tpm_sts_read.3222535157 |
| Short name | T573 |
| Test name | |
| Test status | |
| Simulation time | 262221499 ps |
| CPU time | 1.24 seconds |
| Started | Sep 01 02:57:28 PM UTC 24 |
| Finished | Sep 01 02:57:31 PM UTC 24 |
| Peak memory | 215868 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3222535157 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_3 1/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_sts_read.3222535157 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/25.spi_device_tpm_sts_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/25.spi_device_upload.1413200330 |
| Short name | T318 |
| Test name | |
| Test status | |
| Simulation time | 203037915 ps |
| CPU time | 5.86 seconds |
| Started | Sep 01 02:57:36 PM UTC 24 |
| Finished | Sep 01 02:57:44 PM UTC 24 |
| Peak memory | 245140 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1413200330 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_upload.1413200330 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/25.spi_device_upload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/26.spi_device_alert_test.3224635399 |
| Short name | T601 |
| Test name | |
| Test status | |
| Simulation time | 48529461 ps |
| CPU time | 1.14 seconds |
| Started | Sep 01 02:58:11 PM UTC 24 |
| Finished | Sep 01 02:58:13 PM UTC 24 |
| Peak memory | 215680 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3224635399 -assert nopostproc +UVM_TES TNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_alert_test.3224635399 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/26.spi_device_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/26.spi_device_cfg_cmd.3657934004 |
| Short name | T603 |
| Test name | |
| Test status | |
| Simulation time | 1825779765 ps |
| CPU time | 12.25 seconds |
| Started | Sep 01 02:58:01 PM UTC 24 |
| Finished | Sep 01 02:58:15 PM UTC 24 |
| Peak memory | 235020 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3657934004 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_cfg_cmd.3657934004 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/26.spi_device_cfg_cmd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/26.spi_device_csb_read.3796701565 |
| Short name | T586 |
| Test name | |
| Test status | |
| Simulation time | 67188918 ps |
| CPU time | 1.16 seconds |
| Started | Sep 01 02:57:54 PM UTC 24 |
| Finished | Sep 01 02:57:56 PM UTC 24 |
| Peak memory | 215808 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3796701565 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/sp i_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_csb_read.3796701565 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/26.spi_device_csb_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/26.spi_device_flash_all.3740324144 |
| Short name | T681 |
| Test name | |
| Test status | |
| Simulation time | 97668780234 ps |
| CPU time | 110.22 seconds |
| Started | Sep 01 02:58:06 PM UTC 24 |
| Finished | Sep 01 02:59:58 PM UTC 24 |
| Peak memory | 261708 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3740324144 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/s pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_all.3740324144 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/26.spi_device_flash_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/26.spi_device_flash_and_tpm.1567482009 |
| Short name | T719 |
| Test name | |
| Test status | |
| Simulation time | 46935193966 ps |
| CPU time | 167.5 seconds |
| Started | Sep 01 02:58:08 PM UTC 24 |
| Finished | Sep 01 03:00:59 PM UTC 24 |
| Peak memory | 278216 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1567482009 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_ 31/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_and_tpm.1567482009 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/26.spi_device_flash_and_tpm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/26.spi_device_flash_and_tpm_min_idle.3564666604 |
| Short name | T655 |
| Test name | |
| Test status | |
| Simulation time | 10900445629 ps |
| CPU time | 77.25 seconds |
| Started | Sep 01 02:58:08 PM UTC 24 |
| Finished | Sep 01 02:59:28 PM UTC 24 |
| Peak memory | 267928 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3564666604 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_31/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_and_tpm_min_idle.3564666604 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/26.spi_device_flash_and_tpm_min_idle/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/26.spi_device_flash_mode.1318801645 |
| Short name | T611 |
| Test name | |
| Test status | |
| Simulation time | 1143556745 ps |
| CPU time | 18.86 seconds |
| Started | Sep 01 02:58:03 PM UTC 24 |
| Finished | Sep 01 02:58:23 PM UTC 24 |
| Peak memory | 245136 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1318801645 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/ spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_mode.1318801645 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/26.spi_device_flash_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/26.spi_device_flash_mode_ignore_cmds.1764356810 |
| Short name | T595 |
| Test name | |
| Test status | |
| Simulation time | 34940581 ps |
| CPU time | 1.25 seconds |
| Started | Sep 01 02:58:05 PM UTC 24 |
| Finished | Sep 01 02:58:07 PM UTC 24 |
| Peak memory | 225736 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1764356810 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_31/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_mode_ignore_cmds.1764356810 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/26.spi_device_flash_mode_ignore_cmds/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/26.spi_device_intercept.2201980082 |
| Short name | T593 |
| Test name | |
| Test status | |
| Simulation time | 133666688 ps |
| CPU time | 4.15 seconds |
| Started | Sep 01 02:58:00 PM UTC 24 |
| Finished | Sep 01 02:58:05 PM UTC 24 |
| Peak memory | 234956 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2201980082 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/s pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_intercept.2201980082 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/26.spi_device_intercept/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/26.spi_device_mailbox.1279543164 |
| Short name | T604 |
| Test name | |
| Test status | |
| Simulation time | 621705328 ps |
| CPU time | 13.65 seconds |
| Started | Sep 01 02:58:00 PM UTC 24 |
| Finished | Sep 01 02:58:15 PM UTC 24 |
| Peak memory | 234976 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1279543164 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_mailbox.1279543164 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/26.spi_device_mailbox/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/26.spi_device_pass_addr_payload_swap.4048434558 |
| Short name | T597 |
| Test name | |
| Test status | |
| Simulation time | 284138589 ps |
| CPU time | 9.56 seconds |
| Started | Sep 01 02:57:59 PM UTC 24 |
| Finished | Sep 01 02:58:09 PM UTC 24 |
| Peak memory | 245288 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4048434558 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_31/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_pass_addr_payload_swap.4048434558 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/26.spi_device_pass_addr_payload_swap/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/26.spi_device_pass_cmd_filtering.2641661796 |
| Short name | T626 |
| Test name | |
| Test status | |
| Simulation time | 14286670438 ps |
| CPU time | 46.04 seconds |
| Started | Sep 01 02:57:59 PM UTC 24 |
| Finished | Sep 01 02:58:46 PM UTC 24 |
| Peak memory | 245276 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2641661796 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_08_31/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_pass_cmd_filtering.2641661796 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/26.spi_device_pass_cmd_filtering/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/26.spi_device_read_buffer_direct.1173854318 |
| Short name | T599 |
| Test name | |
| Test status | |
| Simulation time | 583733890 ps |
| CPU time | 5.23 seconds |
| Started | Sep 01 02:58:06 PM UTC 24 |
| Finished | Sep 01 02:58:12 PM UTC 24 |
| Peak memory | 233548 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1173854318 -assert nopostproc +UVM_TESTNAME=spi_device _base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_read_buffer_direct.1173854318 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/26.spi_device_read_buffer_direct/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/26.spi_device_stress_all.3790020083 |
| Short name | T183 |
| Test name | |
| Test status | |
| Simulation time | 20830643683 ps |
| CPU time | 141.3 seconds |
| Started | Sep 01 02:58:08 PM UTC 24 |
| Finished | Sep 01 03:00:33 PM UTC 24 |
| Peak memory | 261740 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3790020083 -assert nopostproc +UVM_ TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_stress_all.3790020083 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/26.spi_device_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/26.spi_device_tpm_all.101567593 |
| Short name | T619 |
| Test name | |
| Test status | |
| Simulation time | 10602442737 ps |
| CPU time | 36.9 seconds |
| Started | Sep 01 02:57:56 PM UTC 24 |
| Finished | Sep 01 02:58:34 PM UTC 24 |
| Peak memory | 227612 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=101567593 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_all.101567593 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/26.spi_device_tpm_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/26.spi_device_tpm_read_hw_reg.1084084092 |
| Short name | T591 |
| Test name | |
| Test status | |
| Simulation time | 562085210 ps |
| CPU time | 8.14 seconds |
| Started | Sep 01 02:57:55 PM UTC 24 |
| Finished | Sep 01 02:58:04 PM UTC 24 |
| Peak memory | 227496 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1084084092 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_31/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_read_hw_reg.1084084092 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/26.spi_device_tpm_read_hw_reg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/26.spi_device_tpm_rw.1139862184 |
| Short name | T589 |
| Test name | |
| Test status | |
| Simulation time | 115593280 ps |
| CPU time | 0.9 seconds |
| Started | Sep 01 02:57:57 PM UTC 24 |
| Finished | Sep 01 02:57:59 PM UTC 24 |
| Peak memory | 215736 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1139862184 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_rw.1139862184 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/26.spi_device_tpm_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/26.spi_device_tpm_sts_read.3006658566 |
| Short name | T590 |
| Test name | |
| Test status | |
| Simulation time | 186557284 ps |
| CPU time | 1.37 seconds |
| Started | Sep 01 02:57:57 PM UTC 24 |
| Finished | Sep 01 02:58:00 PM UTC 24 |
| Peak memory | 215836 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3006658566 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_3 1/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_sts_read.3006658566 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/26.spi_device_tpm_sts_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/26.spi_device_upload.696258466 |
| Short name | T594 |
| Test name | |
| Test status | |
| Simulation time | 2612965515 ps |
| CPU time | 4.65 seconds |
| Started | Sep 01 02:58:01 PM UTC 24 |
| Finished | Sep 01 02:58:07 PM UTC 24 |
| Peak memory | 245324 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=696258466 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/spi_d evice_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_upload.696258466 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/26.spi_device_upload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/27.spi_device_alert_test.3103180482 |
| Short name | T616 |
| Test name | |
| Test status | |
| Simulation time | 22609521 ps |
| CPU time | 1.09 seconds |
| Started | Sep 01 02:58:26 PM UTC 24 |
| Finished | Sep 01 02:58:29 PM UTC 24 |
| Peak memory | 215680 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3103180482 -assert nopostproc +UVM_TES TNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_alert_test.3103180482 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/27.spi_device_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/27.spi_device_cfg_cmd.275547568 |
| Short name | T612 |
| Test name | |
| Test status | |
| Simulation time | 224106050 ps |
| CPU time | 4.65 seconds |
| Started | Sep 01 02:58:18 PM UTC 24 |
| Finished | Sep 01 02:58:24 PM UTC 24 |
| Peak memory | 234976 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=275547568 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_cfg_cmd.275547568 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/27.spi_device_cfg_cmd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/27.spi_device_csb_read.3035167919 |
| Short name | T602 |
| Test name | |
| Test status | |
| Simulation time | 22687458 ps |
| CPU time | 1.16 seconds |
| Started | Sep 01 02:58:11 PM UTC 24 |
| Finished | Sep 01 02:58:13 PM UTC 24 |
| Peak memory | 215808 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3035167919 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/sp i_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_csb_read.3035167919 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/27.spi_device_csb_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/27.spi_device_flash_all.2807765798 |
| Short name | T746 |
| Test name | |
| Test status | |
| Simulation time | 89904264877 ps |
| CPU time | 182.96 seconds |
| Started | Sep 01 02:58:25 PM UTC 24 |
| Finished | Sep 01 03:01:31 PM UTC 24 |
| Peak memory | 261708 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2807765798 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/s pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_all.2807765798 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/27.spi_device_flash_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/27.spi_device_flash_and_tpm.935794865 |
| Short name | T635 |
| Test name | |
| Test status | |
| Simulation time | 4901493335 ps |
| CPU time | 31.97 seconds |
| Started | Sep 01 02:58:26 PM UTC 24 |
| Finished | Sep 01 02:59:00 PM UTC 24 |
| Peak memory | 229556 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=935794865 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_3 1/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_and_tpm.935794865 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/27.spi_device_flash_and_tpm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/27.spi_device_flash_and_tpm_min_idle.584582543 |
| Short name | T682 |
| Test name | |
| Test status | |
| Simulation time | 25234368516 ps |
| CPU time | 90.74 seconds |
| Started | Sep 01 02:58:26 PM UTC 24 |
| Finished | Sep 01 02:59:59 PM UTC 24 |
| Peak memory | 261904 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=584582543 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_31/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_and_tpm_min_idle.584582543 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/27.spi_device_flash_and_tpm_min_idle/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/27.spi_device_flash_mode.137797267 |
| Short name | T377 |
| Test name | |
| Test status | |
| Simulation time | 32374336755 ps |
| CPU time | 48.41 seconds |
| Started | Sep 01 02:58:21 PM UTC 24 |
| Finished | Sep 01 02:59:11 PM UTC 24 |
| Peak memory | 245324 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=137797267 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/s pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_mode.137797267 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/27.spi_device_flash_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/27.spi_device_flash_mode_ignore_cmds.3948157460 |
| Short name | T831 |
| Test name | |
| Test status | |
| Simulation time | 34903405655 ps |
| CPU time | 288.3 seconds |
| Started | Sep 01 02:58:24 PM UTC 24 |
| Finished | Sep 01 03:03:16 PM UTC 24 |
| Peak memory | 261712 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3948157460 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_31/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_mode_ignore_cmds.3948157460 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/27.spi_device_flash_mode_ignore_cmds/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/27.spi_device_intercept.3083938319 |
| Short name | T615 |
| Test name | |
| Test status | |
| Simulation time | 634421969 ps |
| CPU time | 7.88 seconds |
| Started | Sep 01 02:58:17 PM UTC 24 |
| Finished | Sep 01 02:58:26 PM UTC 24 |
| Peak memory | 234964 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3083938319 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/s pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_intercept.3083938319 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/27.spi_device_intercept/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/27.spi_device_mailbox.52440156 |
| Short name | T675 |
| Test name | |
| Test status | |
| Simulation time | 34069742442 ps |
| CPU time | 87.43 seconds |
| Started | Sep 01 02:58:18 PM UTC 24 |
| Finished | Sep 01 02:59:48 PM UTC 24 |
| Peak memory | 261668 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=52440156 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/spi_d evice_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_mailbox.52440156 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/27.spi_device_mailbox/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/27.spi_device_pass_addr_payload_swap.2129259140 |
| Short name | T328 |
| Test name | |
| Test status | |
| Simulation time | 944667440 ps |
| CPU time | 15.7 seconds |
| Started | Sep 01 02:58:16 PM UTC 24 |
| Finished | Sep 01 02:58:33 PM UTC 24 |
| Peak memory | 234904 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2129259140 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_31/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_pass_addr_payload_swap.2129259140 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/27.spi_device_pass_addr_payload_swap/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/27.spi_device_pass_cmd_filtering.628795730 |
| Short name | T294 |
| Test name | |
| Test status | |
| Simulation time | 423501611 ps |
| CPU time | 7.81 seconds |
| Started | Sep 01 02:58:16 PM UTC 24 |
| Finished | Sep 01 02:58:25 PM UTC 24 |
| Peak memory | 234972 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=628795730 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _08_31/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_pass_cmd_filtering.628795730 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/27.spi_device_pass_cmd_filtering/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/27.spi_device_read_buffer_direct.2490768622 |
| Short name | T618 |
| Test name | |
| Test status | |
| Simulation time | 635447608 ps |
| CPU time | 9.64 seconds |
| Started | Sep 01 02:58:24 PM UTC 24 |
| Finished | Sep 01 02:58:34 PM UTC 24 |
| Peak memory | 233488 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2490768622 -assert nopostproc +UVM_TESTNAME=spi_device _base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_read_buffer_direct.2490768622 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/27.spi_device_read_buffer_direct/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/27.spi_device_stress_all.98440700 |
| Short name | T792 |
| Test name | |
| Test status | |
| Simulation time | 85381481561 ps |
| CPU time | 243.2 seconds |
| Started | Sep 01 02:58:26 PM UTC 24 |
| Finished | Sep 01 03:02:34 PM UTC 24 |
| Peak memory | 263968 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=98440700 -assert nopostproc +UVM_TE STNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_stress_all.98440700 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/27.spi_device_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/27.spi_device_tpm_all.1709068465 |
| Short name | T613 |
| Test name | |
| Test status | |
| Simulation time | 1735187617 ps |
| CPU time | 10.63 seconds |
| Started | Sep 01 02:58:13 PM UTC 24 |
| Finished | Sep 01 02:58:25 PM UTC 24 |
| Peak memory | 227476 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1709068465 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_all.1709068465 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/27.spi_device_tpm_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/27.spi_device_tpm_read_hw_reg.396758052 |
| Short name | T609 |
| Test name | |
| Test status | |
| Simulation time | 648225037 ps |
| CPU time | 6.07 seconds |
| Started | Sep 01 02:58:13 PM UTC 24 |
| Finished | Sep 01 02:58:20 PM UTC 24 |
| Peak memory | 227544 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=396758052 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08 _31/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_read_hw_reg.396758052 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/27.spi_device_tpm_read_hw_reg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/27.spi_device_tpm_rw.3311903532 |
| Short name | T605 |
| Test name | |
| Test status | |
| Simulation time | 26001013 ps |
| CPU time | 0.92 seconds |
| Started | Sep 01 02:58:14 PM UTC 24 |
| Finished | Sep 01 02:58:16 PM UTC 24 |
| Peak memory | 215740 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3311903532 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_rw.3311903532 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/27.spi_device_tpm_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/27.spi_device_tpm_sts_read.1056111407 |
| Short name | T607 |
| Test name | |
| Test status | |
| Simulation time | 34074800 ps |
| CPU time | 1.12 seconds |
| Started | Sep 01 02:58:14 PM UTC 24 |
| Finished | Sep 01 02:58:16 PM UTC 24 |
| Peak memory | 215868 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1056111407 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_3 1/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_sts_read.1056111407 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/27.spi_device_tpm_sts_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/27.spi_device_upload.887873996 |
| Short name | T640 |
| Test name | |
| Test status | |
| Simulation time | 9466996224 ps |
| CPU time | 44.62 seconds |
| Started | Sep 01 02:58:18 PM UTC 24 |
| Finished | Sep 01 02:59:04 PM UTC 24 |
| Peak memory | 245328 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=887873996 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/spi_d evice_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_upload.887873996 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/27.spi_device_upload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/28.spi_device_alert_test.1767980174 |
| Short name | T633 |
| Test name | |
| Test status | |
| Simulation time | 13677920 ps |
| CPU time | 1.13 seconds |
| Started | Sep 01 02:58:55 PM UTC 24 |
| Finished | Sep 01 02:58:57 PM UTC 24 |
| Peak memory | 215680 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1767980174 -assert nopostproc +UVM_TES TNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_alert_test.1767980174 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/28.spi_device_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/28.spi_device_cfg_cmd.3946045880 |
| Short name | T629 |
| Test name | |
| Test status | |
| Simulation time | 270163025 ps |
| CPU time | 7.67 seconds |
| Started | Sep 01 02:58:41 PM UTC 24 |
| Finished | Sep 01 02:58:50 PM UTC 24 |
| Peak memory | 234956 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3946045880 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_cfg_cmd.3946045880 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/28.spi_device_cfg_cmd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/28.spi_device_csb_read.2821481195 |
| Short name | T617 |
| Test name | |
| Test status | |
| Simulation time | 15930510 ps |
| CPU time | 1.13 seconds |
| Started | Sep 01 02:58:30 PM UTC 24 |
| Finished | Sep 01 02:58:32 PM UTC 24 |
| Peak memory | 215808 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2821481195 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/sp i_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_csb_read.2821481195 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/28.spi_device_csb_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/28.spi_device_flash_all.377313233 |
| Short name | T359 |
| Test name | |
| Test status | |
| Simulation time | 29208443520 ps |
| CPU time | 197.82 seconds |
| Started | Sep 01 02:58:48 PM UTC 24 |
| Finished | Sep 01 03:02:09 PM UTC 24 |
| Peak memory | 265764 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=377313233 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/sp i_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_all.377313233 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/28.spi_device_flash_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/28.spi_device_flash_and_tpm.1634563426 |
| Short name | T765 |
| Test name | |
| Test status | |
| Simulation time | 64506330613 ps |
| CPU time | 186.58 seconds |
| Started | Sep 01 02:58:49 PM UTC 24 |
| Finished | Sep 01 03:01:59 PM UTC 24 |
| Peak memory | 261772 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1634563426 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_ 31/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_and_tpm.1634563426 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/28.spi_device_flash_and_tpm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/28.spi_device_flash_and_tpm_min_idle.4229527234 |
| Short name | T355 |
| Test name | |
| Test status | |
| Simulation time | 165985324882 ps |
| CPU time | 467.72 seconds |
| Started | Sep 01 02:58:51 PM UTC 24 |
| Finished | Sep 01 03:06:45 PM UTC 24 |
| Peak memory | 284296 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4229527234 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_31/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_and_tpm_min_idle.4229527234 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/28.spi_device_flash_and_tpm_min_idle/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/28.spi_device_flash_mode.923300294 |
| Short name | T630 |
| Test name | |
| Test status | |
| Simulation time | 134186834 ps |
| CPU time | 3.62 seconds |
| Started | Sep 01 02:58:45 PM UTC 24 |
| Finished | Sep 01 02:58:50 PM UTC 24 |
| Peak memory | 234948 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=923300294 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/s pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_mode.923300294 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/28.spi_device_flash_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/28.spi_device_flash_mode_ignore_cmds.3345862505 |
| Short name | T225 |
| Test name | |
| Test status | |
| Simulation time | 36762966257 ps |
| CPU time | 108.08 seconds |
| Started | Sep 01 02:58:45 PM UTC 24 |
| Finished | Sep 01 03:00:36 PM UTC 24 |
| Peak memory | 263904 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3345862505 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_31/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_mode_ignore_cmds.3345862505 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/28.spi_device_flash_mode_ignore_cmds/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/28.spi_device_intercept.236882381 |
| Short name | T625 |
| Test name | |
| Test status | |
| Simulation time | 440039427 ps |
| CPU time | 5.74 seconds |
| Started | Sep 01 02:58:38 PM UTC 24 |
| Finished | Sep 01 02:58:44 PM UTC 24 |
| Peak memory | 245212 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=236882381 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/sp i_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_intercept.236882381 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/28.spi_device_intercept/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/28.spi_device_mailbox.851925575 |
| Short name | T638 |
| Test name | |
| Test status | |
| Simulation time | 1369871334 ps |
| CPU time | 21.19 seconds |
| Started | Sep 01 02:58:40 PM UTC 24 |
| Finished | Sep 01 02:59:02 PM UTC 24 |
| Peak memory | 234812 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=851925575 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_mailbox.851925575 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/28.spi_device_mailbox/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/28.spi_device_pass_addr_payload_swap.1227996385 |
| Short name | T636 |
| Test name | |
| Test status | |
| Simulation time | 26176453506 ps |
| CPU time | 21.49 seconds |
| Started | Sep 01 02:58:38 PM UTC 24 |
| Finished | Sep 01 02:59:00 PM UTC 24 |
| Peak memory | 245396 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1227996385 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_31/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_pass_addr_payload_swap.1227996385 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/28.spi_device_pass_addr_payload_swap/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/28.spi_device_pass_cmd_filtering.3698001025 |
| Short name | T622 |
| Test name | |
| Test status | |
| Simulation time | 34996742 ps |
| CPU time | 2.68 seconds |
| Started | Sep 01 02:58:35 PM UTC 24 |
| Finished | Sep 01 02:58:39 PM UTC 24 |
| Peak memory | 244756 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3698001025 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_08_31/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_pass_cmd_filtering.3698001025 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/28.spi_device_pass_cmd_filtering/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/28.spi_device_read_buffer_direct.1491047300 |
| Short name | T644 |
| Test name | |
| Test status | |
| Simulation time | 8167879344 ps |
| CPU time | 25.49 seconds |
| Started | Sep 01 02:58:48 PM UTC 24 |
| Finished | Sep 01 02:59:14 PM UTC 24 |
| Peak memory | 233388 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1491047300 -assert nopostproc +UVM_TESTNAME=spi_device _base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_read_buffer_direct.1491047300 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/28.spi_device_read_buffer_direct/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/28.spi_device_stress_all.4288866574 |
| Short name | T631 |
| Test name | |
| Test status | |
| Simulation time | 111997430 ps |
| CPU time | 1.65 seconds |
| Started | Sep 01 02:58:51 PM UTC 24 |
| Finished | Sep 01 02:58:54 PM UTC 24 |
| Peak memory | 215760 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4288866574 -assert nopostproc +UVM_ TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_stress_all.4288866574 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/28.spi_device_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/28.spi_device_tpm_all.1299939102 |
| Short name | T664 |
| Test name | |
| Test status | |
| Simulation time | 12328043488 ps |
| CPU time | 61.04 seconds |
| Started | Sep 01 02:58:33 PM UTC 24 |
| Finished | Sep 01 02:59:36 PM UTC 24 |
| Peak memory | 227692 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1299939102 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_all.1299939102 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/28.spi_device_tpm_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/28.spi_device_tpm_read_hw_reg.1162955771 |
| Short name | T627 |
| Test name | |
| Test status | |
| Simulation time | 1467746462 ps |
| CPU time | 14.68 seconds |
| Started | Sep 01 02:58:31 PM UTC 24 |
| Finished | Sep 01 02:58:47 PM UTC 24 |
| Peak memory | 227544 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1162955771 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_31/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_read_hw_reg.1162955771 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/28.spi_device_tpm_read_hw_reg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/28.spi_device_tpm_rw.3211839336 |
| Short name | T623 |
| Test name | |
| Test status | |
| Simulation time | 220911505 ps |
| CPU time | 3.75 seconds |
| Started | Sep 01 02:58:35 PM UTC 24 |
| Finished | Sep 01 02:58:40 PM UTC 24 |
| Peak memory | 227168 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3211839336 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_rw.3211839336 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/28.spi_device_tpm_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/28.spi_device_tpm_sts_read.3646268457 |
| Short name | T620 |
| Test name | |
| Test status | |
| Simulation time | 235965639 ps |
| CPU time | 1.28 seconds |
| Started | Sep 01 02:58:34 PM UTC 24 |
| Finished | Sep 01 02:58:36 PM UTC 24 |
| Peak memory | 215868 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3646268457 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_3 1/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_sts_read.3646268457 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/28.spi_device_tpm_sts_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/28.spi_device_upload.3722030679 |
| Short name | T624 |
| Test name | |
| Test status | |
| Simulation time | 77897499 ps |
| CPU time | 3.16 seconds |
| Started | Sep 01 02:58:40 PM UTC 24 |
| Finished | Sep 01 02:58:44 PM UTC 24 |
| Peak memory | 234720 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3722030679 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_upload.3722030679 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/28.spi_device_upload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/29.spi_device_alert_test.510853092 |
| Short name | T650 |
| Test name | |
| Test status | |
| Simulation time | 50345048 ps |
| CPU time | 1.16 seconds |
| Started | Sep 01 02:59:18 PM UTC 24 |
| Finished | Sep 01 02:59:20 PM UTC 24 |
| Peak memory | 215680 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=510853092 -assert nopostproc +UVM_TEST NAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_alert_test.510853092 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/29.spi_device_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/29.spi_device_cfg_cmd.4166518968 |
| Short name | T646 |
| Test name | |
| Test status | |
| Simulation time | 2183485020 ps |
| CPU time | 10.5 seconds |
| Started | Sep 01 02:59:05 PM UTC 24 |
| Finished | Sep 01 02:59:17 PM UTC 24 |
| Peak memory | 245260 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4166518968 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_cfg_cmd.4166518968 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/29.spi_device_cfg_cmd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/29.spi_device_csb_read.3255833547 |
| Short name | T634 |
| Test name | |
| Test status | |
| Simulation time | 75385565 ps |
| CPU time | 1.11 seconds |
| Started | Sep 01 02:58:55 PM UTC 24 |
| Finished | Sep 01 02:58:57 PM UTC 24 |
| Peak memory | 215808 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3255833547 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/sp i_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_csb_read.3255833547 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/29.spi_device_csb_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/29.spi_device_flash_all.649176321 |
| Short name | T368 |
| Test name | |
| Test status | |
| Simulation time | 29351783726 ps |
| CPU time | 67.4 seconds |
| Started | Sep 01 02:59:13 PM UTC 24 |
| Finished | Sep 01 03:00:22 PM UTC 24 |
| Peak memory | 251468 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=649176321 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/sp i_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_all.649176321 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/29.spi_device_flash_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/29.spi_device_flash_and_tpm.1541946209 |
| Short name | T976 |
| Test name | |
| Test status | |
| Simulation time | 35177872033 ps |
| CPU time | 425.18 seconds |
| Started | Sep 01 02:59:15 PM UTC 24 |
| Finished | Sep 01 03:06:26 PM UTC 24 |
| Peak memory | 267892 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1541946209 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_ 31/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_and_tpm.1541946209 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/29.spi_device_flash_and_tpm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/29.spi_device_flash_and_tpm_min_idle.3502210028 |
| Short name | T366 |
| Test name | |
| Test status | |
| Simulation time | 29124205286 ps |
| CPU time | 153.76 seconds |
| Started | Sep 01 02:59:15 PM UTC 24 |
| Finished | Sep 01 03:01:52 PM UTC 24 |
| Peak memory | 280192 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3502210028 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_31/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_and_tpm_min_idle.3502210028 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/29.spi_device_flash_and_tpm_min_idle/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/29.spi_device_flash_mode.2398732625 |
| Short name | T648 |
| Test name | |
| Test status | |
| Simulation time | 385714078 ps |
| CPU time | 6.62 seconds |
| Started | Sep 01 02:59:10 PM UTC 24 |
| Finished | Sep 01 02:59:18 PM UTC 24 |
| Peak memory | 234896 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2398732625 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/ spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_mode.2398732625 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/29.spi_device_flash_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/29.spi_device_flash_mode_ignore_cmds.3561114371 |
| Short name | T728 |
| Test name | |
| Test status | |
| Simulation time | 10773576542 ps |
| CPU time | 119.5 seconds |
| Started | Sep 01 02:59:10 PM UTC 24 |
| Finished | Sep 01 03:01:12 PM UTC 24 |
| Peak memory | 261728 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3561114371 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_31/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_mode_ignore_cmds.3561114371 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/29.spi_device_flash_mode_ignore_cmds/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/29.spi_device_intercept.1488048486 |
| Short name | T642 |
| Test name | |
| Test status | |
| Simulation time | 287357733 ps |
| CPU time | 6.08 seconds |
| Started | Sep 01 02:59:03 PM UTC 24 |
| Finished | Sep 01 02:59:10 PM UTC 24 |
| Peak memory | 234896 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1488048486 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/s pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_intercept.1488048486 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/29.spi_device_intercept/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/29.spi_device_mailbox.561612610 |
| Short name | T645 |
| Test name | |
| Test status | |
| Simulation time | 984881960 ps |
| CPU time | 10.14 seconds |
| Started | Sep 01 02:59:04 PM UTC 24 |
| Finished | Sep 01 02:59:15 PM UTC 24 |
| Peak memory | 245200 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=561612610 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_mailbox.561612610 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/29.spi_device_mailbox/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/29.spi_device_pass_addr_payload_swap.2243670298 |
| Short name | T341 |
| Test name | |
| Test status | |
| Simulation time | 1503670967 ps |
| CPU time | 15.38 seconds |
| Started | Sep 01 02:59:02 PM UTC 24 |
| Finished | Sep 01 02:59:18 PM UTC 24 |
| Peak memory | 261580 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2243670298 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_31/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_pass_addr_payload_swap.2243670298 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/29.spi_device_pass_addr_payload_swap/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/29.spi_device_pass_cmd_filtering.2752889186 |
| Short name | T666 |
| Test name | |
| Test status | |
| Simulation time | 28592134876 ps |
| CPU time | 36.15 seconds |
| Started | Sep 01 02:59:02 PM UTC 24 |
| Finished | Sep 01 02:59:39 PM UTC 24 |
| Peak memory | 235080 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2752889186 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_08_31/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_pass_cmd_filtering.2752889186 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/29.spi_device_pass_cmd_filtering/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/29.spi_device_read_buffer_direct.3847023164 |
| Short name | T660 |
| Test name | |
| Test status | |
| Simulation time | 1437883949 ps |
| CPU time | 20.2 seconds |
| Started | Sep 01 02:59:13 PM UTC 24 |
| Finished | Sep 01 02:59:34 PM UTC 24 |
| Peak memory | 233448 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3847023164 -assert nopostproc +UVM_TESTNAME=spi_device _base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_read_buffer_direct.3847023164 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/29.spi_device_read_buffer_direct/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/29.spi_device_stress_all.775537514 |
| Short name | T42 |
| Test name | |
| Test status | |
| Simulation time | 11515816409 ps |
| CPU time | 215.07 seconds |
| Started | Sep 01 02:59:16 PM UTC 24 |
| Finished | Sep 01 03:02:55 PM UTC 24 |
| Peak memory | 282248 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=775537514 -assert nopostproc +UVM_T ESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_stress_all.775537514 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/29.spi_device_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/29.spi_device_tpm_all.2311624885 |
| Short name | T641 |
| Test name | |
| Test status | |
| Simulation time | 3712909905 ps |
| CPU time | 10.28 seconds |
| Started | Sep 01 02:58:58 PM UTC 24 |
| Finished | Sep 01 02:59:09 PM UTC 24 |
| Peak memory | 227688 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2311624885 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_all.2311624885 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/29.spi_device_tpm_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/29.spi_device_tpm_read_hw_reg.55818520 |
| Short name | T643 |
| Test name | |
| Test status | |
| Simulation time | 5137545771 ps |
| CPU time | 14.16 seconds |
| Started | Sep 01 02:58:57 PM UTC 24 |
| Finished | Sep 01 02:59:12 PM UTC 24 |
| Peak memory | 227612 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=55818520 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_ 31/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_read_hw_reg.55818520 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/29.spi_device_tpm_read_hw_reg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/29.spi_device_tpm_rw.1169507142 |
| Short name | T639 |
| Test name | |
| Test status | |
| Simulation time | 105499219 ps |
| CPU time | 1.94 seconds |
| Started | Sep 01 02:59:00 PM UTC 24 |
| Finished | Sep 01 02:59:03 PM UTC 24 |
| Peak memory | 226596 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1169507142 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_rw.1169507142 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/29.spi_device_tpm_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/29.spi_device_tpm_sts_read.791471562 |
| Short name | T637 |
| Test name | |
| Test status | |
| Simulation time | 133092484 ps |
| CPU time | 1.42 seconds |
| Started | Sep 01 02:58:58 PM UTC 24 |
| Finished | Sep 01 02:59:00 PM UTC 24 |
| Peak memory | 215864 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=791471562 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31 /spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_sts_read.791471562 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/29.spi_device_tpm_sts_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/29.spi_device_upload.1594258227 |
| Short name | T656 |
| Test name | |
| Test status | |
| Simulation time | 30746777621 ps |
| CPU time | 23.79 seconds |
| Started | Sep 01 02:59:04 PM UTC 24 |
| Finished | Sep 01 02:59:29 PM UTC 24 |
| Peak memory | 251484 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1594258227 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_upload.1594258227 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/29.spi_device_upload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/3.spi_device_alert_test.3817143423 |
| Short name | T103 |
| Test name | |
| Test status | |
| Simulation time | 13464413 ps |
| CPU time | 1.11 seconds |
| Started | Sep 01 02:47:15 PM UTC 24 |
| Finished | Sep 01 02:47:17 PM UTC 24 |
| Peak memory | 215680 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3817143423 -assert nopostproc +UVM_TES TNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_alert_test.3817143423 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/3.spi_device_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/3.spi_device_cfg_cmd.987147916 |
| Short name | T120 |
| Test name | |
| Test status | |
| Simulation time | 32078888 ps |
| CPU time | 3.09 seconds |
| Started | Sep 01 02:46:55 PM UTC 24 |
| Finished | Sep 01 02:46:59 PM UTC 24 |
| Peak memory | 244880 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=987147916 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_cfg_cmd.987147916 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/3.spi_device_cfg_cmd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/3.spi_device_csb_read.4004733911 |
| Short name | T396 |
| Test name | |
| Test status | |
| Simulation time | 22824190 ps |
| CPU time | 1.22 seconds |
| Started | Sep 01 02:46:43 PM UTC 24 |
| Finished | Sep 01 02:46:45 PM UTC 24 |
| Peak memory | 215744 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4004733911 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/sp i_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_csb_read.4004733911 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/3.spi_device_csb_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/3.spi_device_flash_all.2795094684 |
| Short name | T92 |
| Test name | |
| Test status | |
| Simulation time | 18277504910 ps |
| CPU time | 69.7 seconds |
| Started | Sep 01 02:47:02 PM UTC 24 |
| Finished | Sep 01 02:48:14 PM UTC 24 |
| Peak memory | 265804 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2795094684 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/s pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_all.2795094684 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/3.spi_device_flash_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/3.spi_device_flash_and_tpm.3772694709 |
| Short name | T62 |
| Test name | |
| Test status | |
| Simulation time | 6775345564 ps |
| CPU time | 28.5 seconds |
| Started | Sep 01 02:47:02 PM UTC 24 |
| Finished | Sep 01 02:47:32 PM UTC 24 |
| Peak memory | 245448 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3772694709 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_ 31/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_and_tpm.3772694709 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/3.spi_device_flash_and_tpm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/3.spi_device_flash_mode.2267533537 |
| Short name | T78 |
| Test name | |
| Test status | |
| Simulation time | 790887876 ps |
| CPU time | 14.57 seconds |
| Started | Sep 01 02:47:00 PM UTC 24 |
| Finished | Sep 01 02:47:16 PM UTC 24 |
| Peak memory | 251408 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2267533537 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/ spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_mode.2267533537 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/3.spi_device_flash_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/3.spi_device_flash_mode_ignore_cmds.2544006928 |
| Short name | T203 |
| Test name | |
| Test status | |
| Simulation time | 13441115505 ps |
| CPU time | 177.72 seconds |
| Started | Sep 01 02:47:00 PM UTC 24 |
| Finished | Sep 01 02:50:01 PM UTC 24 |
| Peak memory | 261844 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2544006928 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_31/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_mode_ignore_cmds.2544006928 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/3.spi_device_flash_mode_ignore_cmds/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/3.spi_device_intercept.3466492069 |
| Short name | T57 |
| Test name | |
| Test status | |
| Simulation time | 507190228 ps |
| CPU time | 9.91 seconds |
| Started | Sep 01 02:46:51 PM UTC 24 |
| Finished | Sep 01 02:47:02 PM UTC 24 |
| Peak memory | 245204 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3466492069 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/s pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_intercept.3466492069 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/3.spi_device_intercept/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/3.spi_device_mailbox.736893465 |
| Short name | T122 |
| Test name | |
| Test status | |
| Simulation time | 5619677284 ps |
| CPU time | 40.76 seconds |
| Started | Sep 01 02:46:52 PM UTC 24 |
| Finished | Sep 01 02:47:34 PM UTC 24 |
| Peak memory | 245268 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=736893465 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_mailbox.736893465 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/3.spi_device_mailbox/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/3.spi_device_pass_addr_payload_swap.2834133060 |
| Short name | T55 |
| Test name | |
| Test status | |
| Simulation time | 2476797954 ps |
| CPU time | 9.8 seconds |
| Started | Sep 01 02:46:50 PM UTC 24 |
| Finished | Sep 01 02:47:01 PM UTC 24 |
| Peak memory | 245292 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2834133060 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_31/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_pass_addr_payload_swap.2834133060 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/3.spi_device_pass_addr_payload_swap/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/3.spi_device_pass_cmd_filtering.3998203626 |
| Short name | T94 |
| Test name | |
| Test status | |
| Simulation time | 6503931939 ps |
| CPU time | 26.86 seconds |
| Started | Sep 01 02:46:50 PM UTC 24 |
| Finished | Sep 01 02:47:18 PM UTC 24 |
| Peak memory | 245260 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3998203626 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_08_31/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_pass_cmd_filtering.3998203626 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/3.spi_device_pass_cmd_filtering/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/3.spi_device_read_buffer_direct.2938298917 |
| Short name | T77 |
| Test name | |
| Test status | |
| Simulation time | 4272635436 ps |
| CPU time | 13.14 seconds |
| Started | Sep 01 02:47:01 PM UTC 24 |
| Finished | Sep 01 02:47:15 PM UTC 24 |
| Peak memory | 231392 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2938298917 -assert nopostproc +UVM_TESTNAME=spi_device _base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_read_buffer_direct.2938298917 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/3.spi_device_read_buffer_direct/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/3.spi_device_sec_cm.1922904573 |
| Short name | T23 |
| Test name | |
| Test status | |
| Simulation time | 164507601 ps |
| CPU time | 1.88 seconds |
| Started | Sep 01 02:47:11 PM UTC 24 |
| Finished | Sep 01 02:47:13 PM UTC 24 |
| Peak memory | 257912 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1922904573 -assert nopostproc +UVM_TEST NAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_sec_cm.1922904573 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/3.spi_device_sec_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/3.spi_device_tpm_all.2187097595 |
| Short name | T96 |
| Test name | |
| Test status | |
| Simulation time | 9943356263 ps |
| CPU time | 40.86 seconds |
| Started | Sep 01 02:46:46 PM UTC 24 |
| Finished | Sep 01 02:47:29 PM UTC 24 |
| Peak memory | 227584 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2187097595 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_all.2187097595 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/3.spi_device_tpm_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/3.spi_device_tpm_read_hw_reg.3923564620 |
| Short name | T76 |
| Test name | |
| Test status | |
| Simulation time | 14284628688 ps |
| CPU time | 22.66 seconds |
| Started | Sep 01 02:46:44 PM UTC 24 |
| Finished | Sep 01 02:47:08 PM UTC 24 |
| Peak memory | 227676 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3923564620 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_31/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_read_hw_reg.3923564620 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/3.spi_device_tpm_read_hw_reg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/3.spi_device_tpm_rw.3760966183 |
| Short name | T32 |
| Test name | |
| Test status | |
| Simulation time | 111011633 ps |
| CPU time | 1.79 seconds |
| Started | Sep 01 02:46:48 PM UTC 24 |
| Finished | Sep 01 02:46:51 PM UTC 24 |
| Peak memory | 215632 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3760966183 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_rw.3760966183 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/3.spi_device_tpm_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/3.spi_device_tpm_sts_read.1927605997 |
| Short name | T31 |
| Test name | |
| Test status | |
| Simulation time | 52300964 ps |
| CPU time | 1.15 seconds |
| Started | Sep 01 02:46:47 PM UTC 24 |
| Finished | Sep 01 02:46:50 PM UTC 24 |
| Peak memory | 215864 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1927605997 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_3 1/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_sts_read.1927605997 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/3.spi_device_tpm_sts_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/3.spi_device_upload.2250452463 |
| Short name | T75 |
| Test name | |
| Test status | |
| Simulation time | 1833888998 ps |
| CPU time | 11.77 seconds |
| Started | Sep 01 02:46:55 PM UTC 24 |
| Finished | Sep 01 02:47:08 PM UTC 24 |
| Peak memory | 251348 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2250452463 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_upload.2250452463 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/3.spi_device_upload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/30.spi_device_alert_test.2797216310 |
| Short name | T667 |
| Test name | |
| Test status | |
| Simulation time | 15714754 ps |
| CPU time | 1.14 seconds |
| Started | Sep 01 02:59:37 PM UTC 24 |
| Finished | Sep 01 02:59:39 PM UTC 24 |
| Peak memory | 215740 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2797216310 -assert nopostproc +UVM_TES TNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_alert_test.2797216310 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/30.spi_device_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/30.spi_device_cfg_cmd.3657322193 |
| Short name | T665 |
| Test name | |
| Test status | |
| Simulation time | 307936545 ps |
| CPU time | 7.55 seconds |
| Started | Sep 01 02:59:30 PM UTC 24 |
| Finished | Sep 01 02:59:39 PM UTC 24 |
| Peak memory | 245136 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3657322193 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_cfg_cmd.3657322193 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/30.spi_device_cfg_cmd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/30.spi_device_csb_read.2267614389 |
| Short name | T651 |
| Test name | |
| Test status | |
| Simulation time | 41021282 ps |
| CPU time | 1.22 seconds |
| Started | Sep 01 02:59:18 PM UTC 24 |
| Finished | Sep 01 02:59:20 PM UTC 24 |
| Peak memory | 215808 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2267614389 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/sp i_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_csb_read.2267614389 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/30.spi_device_csb_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/30.spi_device_flash_all.2284941830 |
| Short name | T774 |
| Test name | |
| Test status | |
| Simulation time | 62841324957 ps |
| CPU time | 154.51 seconds |
| Started | Sep 01 02:59:35 PM UTC 24 |
| Finished | Sep 01 03:02:12 PM UTC 24 |
| Peak memory | 261784 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2284941830 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/s pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_all.2284941830 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/30.spi_device_flash_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/30.spi_device_flash_and_tpm.3620308546 |
| Short name | T834 |
| Test name | |
| Test status | |
| Simulation time | 47033990899 ps |
| CPU time | 220.45 seconds |
| Started | Sep 01 02:59:36 PM UTC 24 |
| Finished | Sep 01 03:03:20 PM UTC 24 |
| Peak memory | 263824 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3620308546 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_ 31/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_and_tpm.3620308546 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/30.spi_device_flash_and_tpm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/30.spi_device_flash_and_tpm_min_idle.3605523188 |
| Short name | T742 |
| Test name | |
| Test status | |
| Simulation time | 38233820902 ps |
| CPU time | 108.37 seconds |
| Started | Sep 01 02:59:36 PM UTC 24 |
| Finished | Sep 01 03:01:27 PM UTC 24 |
| Peak memory | 261776 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3605523188 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_31/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_and_tpm_min_idle.3605523188 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/30.spi_device_flash_and_tpm_min_idle/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/30.spi_device_flash_mode.1685754966 |
| Short name | T669 |
| Test name | |
| Test status | |
| Simulation time | 1583687305 ps |
| CPU time | 11.36 seconds |
| Started | Sep 01 02:59:30 PM UTC 24 |
| Finished | Sep 01 02:59:43 PM UTC 24 |
| Peak memory | 251340 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1685754966 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/ spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_mode.1685754966 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/30.spi_device_flash_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/30.spi_device_flash_mode_ignore_cmds.819534926 |
| Short name | T661 |
| Test name | |
| Test status | |
| Simulation time | 25788605 ps |
| CPU time | 1.18 seconds |
| Started | Sep 01 02:59:33 PM UTC 24 |
| Finished | Sep 01 02:59:35 PM UTC 24 |
| Peak memory | 225712 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=819534926 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_31/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_mode_ignore_cmds.819534926 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/30.spi_device_flash_mode_ignore_cmds/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/30.spi_device_intercept.246436649 |
| Short name | T657 |
| Test name | |
| Test status | |
| Simulation time | 134505190 ps |
| CPU time | 4.03 seconds |
| Started | Sep 01 02:59:25 PM UTC 24 |
| Finished | Sep 01 02:59:30 PM UTC 24 |
| Peak memory | 245196 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=246436649 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/sp i_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_intercept.246436649 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/30.spi_device_intercept/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/30.spi_device_mailbox.2355411352 |
| Short name | T659 |
| Test name | |
| Test status | |
| Simulation time | 30730331 ps |
| CPU time | 2.8 seconds |
| Started | Sep 01 02:59:28 PM UTC 24 |
| Finished | Sep 01 02:59:32 PM UTC 24 |
| Peak memory | 239576 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2355411352 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_mailbox.2355411352 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/30.spi_device_mailbox/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/30.spi_device_pass_addr_payload_swap.2787828966 |
| Short name | T333 |
| Test name | |
| Test status | |
| Simulation time | 1010608403 ps |
| CPU time | 6.72 seconds |
| Started | Sep 01 02:59:24 PM UTC 24 |
| Finished | Sep 01 02:59:31 PM UTC 24 |
| Peak memory | 234904 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2787828966 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_31/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_pass_addr_payload_swap.2787828966 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/30.spi_device_pass_addr_payload_swap/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/30.spi_device_pass_cmd_filtering.3853071662 |
| Short name | T685 |
| Test name | |
| Test status | |
| Simulation time | 29406263494 ps |
| CPU time | 44.08 seconds |
| Started | Sep 01 02:59:20 PM UTC 24 |
| Finished | Sep 01 03:00:06 PM UTC 24 |
| Peak memory | 261776 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3853071662 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_08_31/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_pass_cmd_filtering.3853071662 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/30.spi_device_pass_cmd_filtering/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/30.spi_device_read_buffer_direct.2335709865 |
| Short name | T674 |
| Test name | |
| Test status | |
| Simulation time | 933777794 ps |
| CPU time | 13.2 seconds |
| Started | Sep 01 02:59:33 PM UTC 24 |
| Finished | Sep 01 02:59:47 PM UTC 24 |
| Peak memory | 233364 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2335709865 -assert nopostproc +UVM_TESTNAME=spi_device _base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_read_buffer_direct.2335709865 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/30.spi_device_read_buffer_direct/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/30.spi_device_stress_all.702945709 |
| Short name | T163 |
| Test name | |
| Test status | |
| Simulation time | 112743118812 ps |
| CPU time | 1535.78 seconds |
| Started | Sep 01 02:59:37 PM UTC 24 |
| Finished | Sep 01 03:25:32 PM UTC 24 |
| Peak memory | 294488 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=702945709 -assert nopostproc +UVM_T ESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_stress_all.702945709 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/30.spi_device_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/30.spi_device_tpm_all.2394189085 |
| Short name | T654 |
| Test name | |
| Test status | |
| Simulation time | 242562167 ps |
| CPU time | 7.22 seconds |
| Started | Sep 01 02:59:19 PM UTC 24 |
| Finished | Sep 01 02:59:27 PM UTC 24 |
| Peak memory | 227544 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2394189085 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_all.2394189085 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/30.spi_device_tpm_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/30.spi_device_tpm_read_hw_reg.4089285613 |
| Short name | T662 |
| Test name | |
| Test status | |
| Simulation time | 1283993233 ps |
| CPU time | 14.81 seconds |
| Started | Sep 01 02:59:19 PM UTC 24 |
| Finished | Sep 01 02:59:35 PM UTC 24 |
| Peak memory | 227448 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4089285613 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_31/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_read_hw_reg.4089285613 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/30.spi_device_tpm_read_hw_reg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/30.spi_device_tpm_rw.1366827247 |
| Short name | T653 |
| Test name | |
| Test status | |
| Simulation time | 178109421 ps |
| CPU time | 2.34 seconds |
| Started | Sep 01 02:59:20 PM UTC 24 |
| Finished | Sep 01 02:59:24 PM UTC 24 |
| Peak memory | 227436 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1366827247 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_rw.1366827247 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/30.spi_device_tpm_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/30.spi_device_tpm_sts_read.2541756123 |
| Short name | T652 |
| Test name | |
| Test status | |
| Simulation time | 22072106 ps |
| CPU time | 1.24 seconds |
| Started | Sep 01 02:59:20 PM UTC 24 |
| Finished | Sep 01 02:59:22 PM UTC 24 |
| Peak memory | 215868 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2541756123 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_3 1/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_sts_read.2541756123 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/30.spi_device_tpm_sts_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/30.spi_device_upload.149224266 |
| Short name | T670 |
| Test name | |
| Test status | |
| Simulation time | 6094173513 ps |
| CPU time | 15.21 seconds |
| Started | Sep 01 02:59:29 PM UTC 24 |
| Finished | Sep 01 02:59:45 PM UTC 24 |
| Peak memory | 245284 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=149224266 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/spi_d evice_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_upload.149224266 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/30.spi_device_upload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/31.spi_device_alert_test.953030173 |
| Short name | T684 |
| Test name | |
| Test status | |
| Simulation time | 11313041 ps |
| CPU time | 1.09 seconds |
| Started | Sep 01 03:00:00 PM UTC 24 |
| Finished | Sep 01 03:00:03 PM UTC 24 |
| Peak memory | 215740 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=953030173 -assert nopostproc +UVM_TEST NAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_alert_test.953030173 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/31.spi_device_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/31.spi_device_cfg_cmd.143055229 |
| Short name | T220 |
| Test name | |
| Test status | |
| Simulation time | 1803155146 ps |
| CPU time | 29.34 seconds |
| Started | Sep 01 02:59:49 PM UTC 24 |
| Finished | Sep 01 03:00:21 PM UTC 24 |
| Peak memory | 234960 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=143055229 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_cfg_cmd.143055229 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/31.spi_device_cfg_cmd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/31.spi_device_csb_read.3093847684 |
| Short name | T668 |
| Test name | |
| Test status | |
| Simulation time | 35922810 ps |
| CPU time | 1.19 seconds |
| Started | Sep 01 02:59:40 PM UTC 24 |
| Finished | Sep 01 02:59:42 PM UTC 24 |
| Peak memory | 215804 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3093847684 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/sp i_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_csb_read.3093847684 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/31.spi_device_csb_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/31.spi_device_flash_all.767048231 |
| Short name | T319 |
| Test name | |
| Test status | |
| Simulation time | 5438366615 ps |
| CPU time | 56.95 seconds |
| Started | Sep 01 02:59:58 PM UTC 24 |
| Finished | Sep 01 03:00:57 PM UTC 24 |
| Peak memory | 249412 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=767048231 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/sp i_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_all.767048231 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/31.spi_device_flash_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/31.spi_device_flash_and_tpm.2344655334 |
| Short name | T658 |
| Test name | |
| Test status | |
| Simulation time | 3763061501 ps |
| CPU time | 64.56 seconds |
| Started | Sep 01 02:59:59 PM UTC 24 |
| Finished | Sep 01 03:01:05 PM UTC 24 |
| Peak memory | 247380 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2344655334 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_ 31/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_and_tpm.2344655334 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/31.spi_device_flash_and_tpm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/31.spi_device_flash_and_tpm_min_idle.3913351891 |
| Short name | T751 |
| Test name | |
| Test status | |
| Simulation time | 11989376987 ps |
| CPU time | 97.99 seconds |
| Started | Sep 01 02:59:59 PM UTC 24 |
| Finished | Sep 01 03:01:39 PM UTC 24 |
| Peak memory | 251532 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3913351891 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_31/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_and_tpm_min_idle.3913351891 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/31.spi_device_flash_and_tpm_min_idle/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/31.spi_device_flash_mode.1752584238 |
| Short name | T680 |
| Test name | |
| Test status | |
| Simulation time | 92758863 ps |
| CPU time | 4.36 seconds |
| Started | Sep 01 02:59:52 PM UTC 24 |
| Finished | Sep 01 02:59:58 PM UTC 24 |
| Peak memory | 245212 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1752584238 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/ spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_mode.1752584238 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/31.spi_device_flash_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/31.spi_device_flash_mode_ignore_cmds.2264721543 |
| Short name | T678 |
| Test name | |
| Test status | |
| Simulation time | 104142800 ps |
| CPU time | 1.26 seconds |
| Started | Sep 01 02:59:53 PM UTC 24 |
| Finished | Sep 01 02:59:56 PM UTC 24 |
| Peak memory | 225736 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2264721543 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_31/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_mode_ignore_cmds.2264721543 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/31.spi_device_flash_mode_ignore_cmds/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/31.spi_device_intercept.35517350 |
| Short name | T689 |
| Test name | |
| Test status | |
| Simulation time | 1827564114 ps |
| CPU time | 22.78 seconds |
| Started | Sep 01 02:59:47 PM UTC 24 |
| Finished | Sep 01 03:00:11 PM UTC 24 |
| Peak memory | 234960 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=35517350 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_intercept.35517350 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/31.spi_device_intercept/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/31.spi_device_mailbox.2934391826 |
| Short name | T693 |
| Test name | |
| Test status | |
| Simulation time | 1973036138 ps |
| CPU time | 27.58 seconds |
| Started | Sep 01 02:59:48 PM UTC 24 |
| Finished | Sep 01 03:00:17 PM UTC 24 |
| Peak memory | 245260 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2934391826 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_mailbox.2934391826 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/31.spi_device_mailbox/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/31.spi_device_pass_addr_payload_swap.3881916632 |
| Short name | T321 |
| Test name | |
| Test status | |
| Simulation time | 5723822070 ps |
| CPU time | 18.14 seconds |
| Started | Sep 01 02:59:47 PM UTC 24 |
| Finished | Sep 01 03:00:06 PM UTC 24 |
| Peak memory | 261712 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3881916632 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_31/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_pass_addr_payload_swap.3881916632 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/31.spi_device_pass_addr_payload_swap/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/31.spi_device_pass_cmd_filtering.2113441849 |
| Short name | T676 |
| Test name | |
| Test status | |
| Simulation time | 438276915 ps |
| CPU time | 3.8 seconds |
| Started | Sep 01 02:59:47 PM UTC 24 |
| Finished | Sep 01 02:59:51 PM UTC 24 |
| Peak memory | 245208 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2113441849 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_08_31/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_pass_cmd_filtering.2113441849 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/31.spi_device_pass_cmd_filtering/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/31.spi_device_read_buffer_direct.3654512050 |
| Short name | T683 |
| Test name | |
| Test status | |
| Simulation time | 157735187 ps |
| CPU time | 3.56 seconds |
| Started | Sep 01 02:59:57 PM UTC 24 |
| Finished | Sep 01 03:00:02 PM UTC 24 |
| Peak memory | 231256 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3654512050 -assert nopostproc +UVM_TESTNAME=spi_device _base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_read_buffer_direct.3654512050 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/31.spi_device_read_buffer_direct/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/31.spi_device_stress_all.1850766737 |
| Short name | T855 |
| Test name | |
| Test status | |
| Simulation time | 19411918139 ps |
| CPU time | 215.51 seconds |
| Started | Sep 01 03:00:00 PM UTC 24 |
| Finished | Sep 01 03:03:40 PM UTC 24 |
| Peak memory | 261772 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1850766737 -assert nopostproc +UVM_ TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_stress_all.1850766737 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/31.spi_device_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/31.spi_device_tpm_all.1082066616 |
| Short name | T679 |
| Test name | |
| Test status | |
| Simulation time | 3456434817 ps |
| CPU time | 14.33 seconds |
| Started | Sep 01 02:59:41 PM UTC 24 |
| Finished | Sep 01 02:59:56 PM UTC 24 |
| Peak memory | 227624 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1082066616 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_all.1082066616 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/31.spi_device_tpm_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/31.spi_device_tpm_read_hw_reg.1089969399 |
| Short name | T672 |
| Test name | |
| Test status | |
| Simulation time | 4247822707 ps |
| CPU time | 3.85 seconds |
| Started | Sep 01 02:59:41 PM UTC 24 |
| Finished | Sep 01 02:59:46 PM UTC 24 |
| Peak memory | 227524 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1089969399 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_31/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_read_hw_reg.1089969399 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/31.spi_device_tpm_read_hw_reg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/31.spi_device_tpm_rw.1244761363 |
| Short name | T673 |
| Test name | |
| Test status | |
| Simulation time | 69037475 ps |
| CPU time | 1.31 seconds |
| Started | Sep 01 02:59:44 PM UTC 24 |
| Finished | Sep 01 02:59:46 PM UTC 24 |
| Peak memory | 215864 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1244761363 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_rw.1244761363 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/31.spi_device_tpm_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/31.spi_device_tpm_sts_read.2210949369 |
| Short name | T671 |
| Test name | |
| Test status | |
| Simulation time | 145363627 ps |
| CPU time | 1.49 seconds |
| Started | Sep 01 02:59:43 PM UTC 24 |
| Finished | Sep 01 02:59:46 PM UTC 24 |
| Peak memory | 215868 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2210949369 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_3 1/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_sts_read.2210949369 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/31.spi_device_tpm_sts_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/31.spi_device_upload.3218311932 |
| Short name | T677 |
| Test name | |
| Test status | |
| Simulation time | 210967382 ps |
| CPU time | 3.1 seconds |
| Started | Sep 01 02:59:48 PM UTC 24 |
| Finished | Sep 01 02:59:52 PM UTC 24 |
| Peak memory | 234648 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3218311932 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_upload.3218311932 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/31.spi_device_upload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/32.spi_device_alert_test.235636698 |
| Short name | T698 |
| Test name | |
| Test status | |
| Simulation time | 13371063 ps |
| CPU time | 1.14 seconds |
| Started | Sep 01 03:00:23 PM UTC 24 |
| Finished | Sep 01 03:00:26 PM UTC 24 |
| Peak memory | 215740 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=235636698 -assert nopostproc +UVM_TEST NAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_alert_test.235636698 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/32.spi_device_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/32.spi_device_cfg_cmd.4205774961 |
| Short name | T694 |
| Test name | |
| Test status | |
| Simulation time | 46904736 ps |
| CPU time | 3.52 seconds |
| Started | Sep 01 03:00:16 PM UTC 24 |
| Finished | Sep 01 03:00:21 PM UTC 24 |
| Peak memory | 234896 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4205774961 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_cfg_cmd.4205774961 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/32.spi_device_cfg_cmd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/32.spi_device_csb_read.2696315472 |
| Short name | T686 |
| Test name | |
| Test status | |
| Simulation time | 41575647 ps |
| CPU time | 1.12 seconds |
| Started | Sep 01 03:00:02 PM UTC 24 |
| Finished | Sep 01 03:00:07 PM UTC 24 |
| Peak memory | 215804 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2696315472 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/sp i_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_csb_read.2696315472 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/32.spi_device_csb_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/32.spi_device_flash_all.114004989 |
| Short name | T1005 |
| Test name | |
| Test status | |
| Simulation time | 243244118662 ps |
| CPU time | 653.14 seconds |
| Started | Sep 01 03:00:20 PM UTC 24 |
| Finished | Sep 01 03:11:22 PM UTC 24 |
| Peak memory | 284316 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=114004989 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/sp i_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_all.114004989 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/32.spi_device_flash_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/32.spi_device_flash_and_tpm.218195568 |
| Short name | T823 |
| Test name | |
| Test status | |
| Simulation time | 59568641662 ps |
| CPU time | 162.13 seconds |
| Started | Sep 01 03:00:22 PM UTC 24 |
| Finished | Sep 01 03:03:07 PM UTC 24 |
| Peak memory | 251600 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=218195568 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_3 1/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_and_tpm.218195568 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/32.spi_device_flash_and_tpm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/32.spi_device_flash_and_tpm_min_idle.1061415877 |
| Short name | T362 |
| Test name | |
| Test status | |
| Simulation time | 107704574372 ps |
| CPU time | 611.22 seconds |
| Started | Sep 01 03:00:22 PM UTC 24 |
| Finished | Sep 01 03:10:41 PM UTC 24 |
| Peak memory | 276088 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1061415877 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_31/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_and_tpm_min_idle.1061415877 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/32.spi_device_flash_and_tpm_min_idle/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/32.spi_device_flash_mode.1749051565 |
| Short name | T697 |
| Test name | |
| Test status | |
| Simulation time | 145986237 ps |
| CPU time | 6.38 seconds |
| Started | Sep 01 03:00:17 PM UTC 24 |
| Finished | Sep 01 03:00:25 PM UTC 24 |
| Peak memory | 234900 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1749051565 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/ spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_mode.1749051565 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/32.spi_device_flash_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/32.spi_device_flash_mode_ignore_cmds.371026704 |
| Short name | T721 |
| Test name | |
| Test status | |
| Simulation time | 73216567405 ps |
| CPU time | 48.96 seconds |
| Started | Sep 01 03:00:17 PM UTC 24 |
| Finished | Sep 01 03:01:08 PM UTC 24 |
| Peak memory | 261772 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=371026704 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_31/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_mode_ignore_cmds.371026704 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/32.spi_device_flash_mode_ignore_cmds/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/32.spi_device_intercept.2317704833 |
| Short name | T699 |
| Test name | |
| Test status | |
| Simulation time | 3850675462 ps |
| CPU time | 13.22 seconds |
| Started | Sep 01 03:00:11 PM UTC 24 |
| Finished | Sep 01 03:00:26 PM UTC 24 |
| Peak memory | 245340 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2317704833 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/s pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_intercept.2317704833 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/32.spi_device_intercept/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/32.spi_device_mailbox.4007653603 |
| Short name | T722 |
| Test name | |
| Test status | |
| Simulation time | 6978422009 ps |
| CPU time | 56.22 seconds |
| Started | Sep 01 03:00:11 PM UTC 24 |
| Finished | Sep 01 03:01:09 PM UTC 24 |
| Peak memory | 261708 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4007653603 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_mailbox.4007653603 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/32.spi_device_mailbox/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/32.spi_device_pass_addr_payload_swap.1550251274 |
| Short name | T357 |
| Test name | |
| Test status | |
| Simulation time | 2861974312 ps |
| CPU time | 11.13 seconds |
| Started | Sep 01 03:00:09 PM UTC 24 |
| Finished | Sep 01 03:00:21 PM UTC 24 |
| Peak memory | 245324 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1550251274 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_31/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_pass_addr_payload_swap.1550251274 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/32.spi_device_pass_addr_payload_swap/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/32.spi_device_pass_cmd_filtering.552463426 |
| Short name | T692 |
| Test name | |
| Test status | |
| Simulation time | 1572830094 ps |
| CPU time | 7.59 seconds |
| Started | Sep 01 03:00:08 PM UTC 24 |
| Finished | Sep 01 03:00:16 PM UTC 24 |
| Peak memory | 234964 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=552463426 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _08_31/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_pass_cmd_filtering.552463426 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/32.spi_device_pass_cmd_filtering/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/32.spi_device_read_buffer_direct.3489196284 |
| Short name | T701 |
| Test name | |
| Test status | |
| Simulation time | 232017785 ps |
| CPU time | 8.01 seconds |
| Started | Sep 01 03:00:18 PM UTC 24 |
| Finished | Sep 01 03:00:28 PM UTC 24 |
| Peak memory | 233364 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3489196284 -assert nopostproc +UVM_TESTNAME=spi_device _base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_read_buffer_direct.3489196284 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/32.spi_device_read_buffer_direct/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/32.spi_device_stress_all.18033698 |
| Short name | T365 |
| Test name | |
| Test status | |
| Simulation time | 35517507139 ps |
| CPU time | 371.13 seconds |
| Started | Sep 01 03:00:22 PM UTC 24 |
| Finished | Sep 01 03:06:38 PM UTC 24 |
| Peak memory | 284276 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=18033698 -assert nopostproc +UVM_TE STNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_stress_all.18033698 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/32.spi_device_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/32.spi_device_tpm_all.1118273244 |
| Short name | T704 |
| Test name | |
| Test status | |
| Simulation time | 3654261723 ps |
| CPU time | 23.62 seconds |
| Started | Sep 01 03:00:06 PM UTC 24 |
| Finished | Sep 01 03:00:31 PM UTC 24 |
| Peak memory | 227548 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1118273244 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_all.1118273244 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/32.spi_device_tpm_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/32.spi_device_tpm_read_hw_reg.4251720469 |
| Short name | T691 |
| Test name | |
| Test status | |
| Simulation time | 1349788756 ps |
| CPU time | 8.19 seconds |
| Started | Sep 01 03:00:03 PM UTC 24 |
| Finished | Sep 01 03:00:15 PM UTC 24 |
| Peak memory | 227492 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4251720469 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_31/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_read_hw_reg.4251720469 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/32.spi_device_tpm_read_hw_reg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/32.spi_device_tpm_rw.2189396964 |
| Short name | T688 |
| Test name | |
| Test status | |
| Simulation time | 27311267 ps |
| CPU time | 1.36 seconds |
| Started | Sep 01 03:00:08 PM UTC 24 |
| Finished | Sep 01 03:00:10 PM UTC 24 |
| Peak memory | 215864 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2189396964 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_rw.2189396964 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/32.spi_device_tpm_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/32.spi_device_tpm_sts_read.2042821987 |
| Short name | T687 |
| Test name | |
| Test status | |
| Simulation time | 109421948 ps |
| CPU time | 1.2 seconds |
| Started | Sep 01 03:00:08 PM UTC 24 |
| Finished | Sep 01 03:00:10 PM UTC 24 |
| Peak memory | 215868 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2042821987 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_3 1/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_sts_read.2042821987 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/32.spi_device_tpm_sts_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/32.spi_device_upload.3664930561 |
| Short name | T695 |
| Test name | |
| Test status | |
| Simulation time | 3223888101 ps |
| CPU time | 8.23 seconds |
| Started | Sep 01 03:00:12 PM UTC 24 |
| Finished | Sep 01 03:00:22 PM UTC 24 |
| Peak memory | 235216 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3664930561 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_upload.3664930561 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/32.spi_device_upload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/33.spi_device_alert_test.1226496823 |
| Short name | T713 |
| Test name | |
| Test status | |
| Simulation time | 23375101 ps |
| CPU time | 1.12 seconds |
| Started | Sep 01 03:00:48 PM UTC 24 |
| Finished | Sep 01 03:00:50 PM UTC 24 |
| Peak memory | 215680 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1226496823 -assert nopostproc +UVM_TES TNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_alert_test.1226496823 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/33.spi_device_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/33.spi_device_cfg_cmd.2160944137 |
| Short name | T710 |
| Test name | |
| Test status | |
| Simulation time | 2267503838 ps |
| CPU time | 13.63 seconds |
| Started | Sep 01 03:00:32 PM UTC 24 |
| Finished | Sep 01 03:00:47 PM UTC 24 |
| Peak memory | 245216 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2160944137 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_cfg_cmd.2160944137 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/33.spi_device_cfg_cmd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/33.spi_device_csb_read.868512701 |
| Short name | T700 |
| Test name | |
| Test status | |
| Simulation time | 69325922 ps |
| CPU time | 1.16 seconds |
| Started | Sep 01 03:00:24 PM UTC 24 |
| Finished | Sep 01 03:00:26 PM UTC 24 |
| Peak memory | 215636 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=868512701 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_csb_read.868512701 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/33.spi_device_csb_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/33.spi_device_flash_all.396336374 |
| Short name | T350 |
| Test name | |
| Test status | |
| Simulation time | 32118630378 ps |
| CPU time | 95 seconds |
| Started | Sep 01 03:00:38 PM UTC 24 |
| Finished | Sep 01 03:02:15 PM UTC 24 |
| Peak memory | 267852 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=396336374 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/sp i_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_all.396336374 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/33.spi_device_flash_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/33.spi_device_flash_and_tpm.861833683 |
| Short name | T782 |
| Test name | |
| Test status | |
| Simulation time | 5474030640 ps |
| CPU time | 94.65 seconds |
| Started | Sep 01 03:00:41 PM UTC 24 |
| Finished | Sep 01 03:02:18 PM UTC 24 |
| Peak memory | 251644 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=861833683 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_3 1/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_and_tpm.861833683 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/33.spi_device_flash_and_tpm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/33.spi_device_flash_and_tpm_min_idle.2648792039 |
| Short name | T242 |
| Test name | |
| Test status | |
| Simulation time | 19882640061 ps |
| CPU time | 290.7 seconds |
| Started | Sep 01 03:00:46 PM UTC 24 |
| Finished | Sep 01 03:05:41 PM UTC 24 |
| Peak memory | 278160 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2648792039 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_31/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_and_tpm_min_idle.2648792039 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/33.spi_device_flash_and_tpm_min_idle/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/33.spi_device_flash_mode.2519546249 |
| Short name | T711 |
| Test name | |
| Test status | |
| Simulation time | 2116632696 ps |
| CPU time | 13 seconds |
| Started | Sep 01 03:00:34 PM UTC 24 |
| Finished | Sep 01 03:00:48 PM UTC 24 |
| Peak memory | 234952 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2519546249 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/ spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_mode.2519546249 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/33.spi_device_flash_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/33.spi_device_flash_mode_ignore_cmds.1645328523 |
| Short name | T364 |
| Test name | |
| Test status | |
| Simulation time | 6413897782 ps |
| CPU time | 82.52 seconds |
| Started | Sep 01 03:00:37 PM UTC 24 |
| Finished | Sep 01 03:02:01 PM UTC 24 |
| Peak memory | 270768 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1645328523 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_31/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_mode_ignore_cmds.1645328523 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/33.spi_device_flash_mode_ignore_cmds/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/33.spi_device_intercept.2484267616 |
| Short name | T718 |
| Test name | |
| Test status | |
| Simulation time | 9448658642 ps |
| CPU time | 25.86 seconds |
| Started | Sep 01 03:00:29 PM UTC 24 |
| Finished | Sep 01 03:00:56 PM UTC 24 |
| Peak memory | 235212 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2484267616 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/s pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_intercept.2484267616 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/33.spi_device_intercept/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/33.spi_device_mailbox.2979324428 |
| Short name | T712 |
| Test name | |
| Test status | |
| Simulation time | 955887582 ps |
| CPU time | 18.42 seconds |
| Started | Sep 01 03:00:30 PM UTC 24 |
| Finished | Sep 01 03:00:50 PM UTC 24 |
| Peak memory | 234956 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2979324428 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_mailbox.2979324428 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/33.spi_device_mailbox/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/33.spi_device_pass_addr_payload_swap.3617467082 |
| Short name | T705 |
| Test name | |
| Test status | |
| Simulation time | 118369326 ps |
| CPU time | 6.34 seconds |
| Started | Sep 01 03:00:29 PM UTC 24 |
| Finished | Sep 01 03:00:36 PM UTC 24 |
| Peak memory | 245220 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3617467082 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_31/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_pass_addr_payload_swap.3617467082 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/33.spi_device_pass_addr_payload_swap/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/33.spi_device_pass_cmd_filtering.3617723599 |
| Short name | T708 |
| Test name | |
| Test status | |
| Simulation time | 5849830409 ps |
| CPU time | 16.02 seconds |
| Started | Sep 01 03:00:28 PM UTC 24 |
| Finished | Sep 01 03:00:45 PM UTC 24 |
| Peak memory | 235024 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3617723599 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_08_31/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_pass_cmd_filtering.3617723599 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/33.spi_device_pass_cmd_filtering/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/33.spi_device_read_buffer_direct.3650384938 |
| Short name | T716 |
| Test name | |
| Test status | |
| Simulation time | 4273627953 ps |
| CPU time | 15.74 seconds |
| Started | Sep 01 03:00:37 PM UTC 24 |
| Finished | Sep 01 03:00:54 PM UTC 24 |
| Peak memory | 231508 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3650384938 -assert nopostproc +UVM_TESTNAME=spi_device _base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_read_buffer_direct.3650384938 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/33.spi_device_read_buffer_direct/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/33.spi_device_stress_all.1596941703 |
| Short name | T184 |
| Test name | |
| Test status | |
| Simulation time | 173755929 ps |
| CPU time | 1.42 seconds |
| Started | Sep 01 03:00:47 PM UTC 24 |
| Finished | Sep 01 03:00:49 PM UTC 24 |
| Peak memory | 215740 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1596941703 -assert nopostproc +UVM_ TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_stress_all.1596941703 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/33.spi_device_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/33.spi_device_tpm_all.228088360 |
| Short name | T723 |
| Test name | |
| Test status | |
| Simulation time | 28313955607 ps |
| CPU time | 41.7 seconds |
| Started | Sep 01 03:00:26 PM UTC 24 |
| Finished | Sep 01 03:01:09 PM UTC 24 |
| Peak memory | 227544 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=228088360 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_all.228088360 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/33.spi_device_tpm_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/33.spi_device_tpm_read_hw_reg.2731942833 |
| Short name | T709 |
| Test name | |
| Test status | |
| Simulation time | 14174023317 ps |
| CPU time | 20.25 seconds |
| Started | Sep 01 03:00:25 PM UTC 24 |
| Finished | Sep 01 03:00:46 PM UTC 24 |
| Peak memory | 227688 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2731942833 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_31/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_read_hw_reg.2731942833 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/33.spi_device_tpm_read_hw_reg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/33.spi_device_tpm_rw.2142554322 |
| Short name | T703 |
| Test name | |
| Test status | |
| Simulation time | 274612972 ps |
| CPU time | 2.35 seconds |
| Started | Sep 01 03:00:26 PM UTC 24 |
| Finished | Sep 01 03:00:30 PM UTC 24 |
| Peak memory | 227540 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2142554322 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_rw.2142554322 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/33.spi_device_tpm_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/33.spi_device_tpm_sts_read.1060422550 |
| Short name | T702 |
| Test name | |
| Test status | |
| Simulation time | 40084490 ps |
| CPU time | 1.16 seconds |
| Started | Sep 01 03:00:26 PM UTC 24 |
| Finished | Sep 01 03:00:28 PM UTC 24 |
| Peak memory | 215868 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1060422550 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_3 1/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_sts_read.1060422550 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/33.spi_device_tpm_sts_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/33.spi_device_upload.278680768 |
| Short name | T706 |
| Test name | |
| Test status | |
| Simulation time | 75504082 ps |
| CPU time | 3.35 seconds |
| Started | Sep 01 03:00:32 PM UTC 24 |
| Finished | Sep 01 03:00:37 PM UTC 24 |
| Peak memory | 246944 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=278680768 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/spi_d evice_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_upload.278680768 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/33.spi_device_upload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/34.spi_device_alert_test.2617479183 |
| Short name | T725 |
| Test name | |
| Test status | |
| Simulation time | 70246115 ps |
| CPU time | 1.08 seconds |
| Started | Sep 01 03:01:10 PM UTC 24 |
| Finished | Sep 01 03:01:12 PM UTC 24 |
| Peak memory | 215628 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2617479183 -assert nopostproc +UVM_TES TNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_alert_test.2617479183 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/34.spi_device_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/34.spi_device_cfg_cmd.3244520318 |
| Short name | T696 |
| Test name | |
| Test status | |
| Simulation time | 1204467209 ps |
| CPU time | 4.64 seconds |
| Started | Sep 01 03:01:00 PM UTC 24 |
| Finished | Sep 01 03:01:06 PM UTC 24 |
| Peak memory | 234892 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3244520318 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_cfg_cmd.3244520318 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/34.spi_device_cfg_cmd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/34.spi_device_csb_read.1893825710 |
| Short name | T714 |
| Test name | |
| Test status | |
| Simulation time | 28210918 ps |
| CPU time | 1.2 seconds |
| Started | Sep 01 03:00:49 PM UTC 24 |
| Finished | Sep 01 03:00:51 PM UTC 24 |
| Peak memory | 215636 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1893825710 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/sp i_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_csb_read.1893825710 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/34.spi_device_csb_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/34.spi_device_flash_all.1221470572 |
| Short name | T857 |
| Test name | |
| Test status | |
| Simulation time | 19741266138 ps |
| CPU time | 150.72 seconds |
| Started | Sep 01 03:01:07 PM UTC 24 |
| Finished | Sep 01 03:03:41 PM UTC 24 |
| Peak memory | 261784 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1221470572 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/s pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_all.1221470572 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/34.spi_device_flash_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/34.spi_device_flash_and_tpm.3135580027 |
| Short name | T367 |
| Test name | |
| Test status | |
| Simulation time | 16421573981 ps |
| CPU time | 131.82 seconds |
| Started | Sep 01 03:01:07 PM UTC 24 |
| Finished | Sep 01 03:03:22 PM UTC 24 |
| Peak memory | 267832 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3135580027 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_ 31/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_and_tpm.3135580027 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/34.spi_device_flash_and_tpm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/34.spi_device_flash_and_tpm_min_idle.4283214839 |
| Short name | T743 |
| Test name | |
| Test status | |
| Simulation time | 3312673848 ps |
| CPU time | 18.5 seconds |
| Started | Sep 01 03:01:07 PM UTC 24 |
| Finished | Sep 01 03:01:27 PM UTC 24 |
| Peak memory | 234464 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4283214839 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_31/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_and_tpm_min_idle.4283214839 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/34.spi_device_flash_and_tpm_min_idle/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/34.spi_device_flash_mode.883877669 |
| Short name | T729 |
| Test name | |
| Test status | |
| Simulation time | 1241229265 ps |
| CPU time | 6.94 seconds |
| Started | Sep 01 03:01:05 PM UTC 24 |
| Finished | Sep 01 03:01:13 PM UTC 24 |
| Peak memory | 245192 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=883877669 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/s pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_mode.883877669 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/34.spi_device_flash_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/34.spi_device_flash_mode_ignore_cmds.3945393845 |
| Short name | T731 |
| Test name | |
| Test status | |
| Simulation time | 1356242770 ps |
| CPU time | 9.03 seconds |
| Started | Sep 01 03:01:05 PM UTC 24 |
| Finished | Sep 01 03:01:15 PM UTC 24 |
| Peak memory | 245280 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3945393845 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_31/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_mode_ignore_cmds.3945393845 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/34.spi_device_flash_mode_ignore_cmds/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/34.spi_device_intercept.704301807 |
| Short name | T690 |
| Test name | |
| Test status | |
| Simulation time | 173057243 ps |
| CPU time | 6.88 seconds |
| Started | Sep 01 03:00:56 PM UTC 24 |
| Finished | Sep 01 03:01:04 PM UTC 24 |
| Peak memory | 245260 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=704301807 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/sp i_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_intercept.704301807 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/34.spi_device_intercept/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/34.spi_device_mailbox.3384881710 |
| Short name | T739 |
| Test name | |
| Test status | |
| Simulation time | 7622612112 ps |
| CPU time | 25.29 seconds |
| Started | Sep 01 03:00:57 PM UTC 24 |
| Finished | Sep 01 03:01:24 PM UTC 24 |
| Peak memory | 245260 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3384881710 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_mailbox.3384881710 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/34.spi_device_mailbox/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/34.spi_device_pass_addr_payload_swap.3987854911 |
| Short name | T724 |
| Test name | |
| Test status | |
| Simulation time | 961035280 ps |
| CPU time | 12.93 seconds |
| Started | Sep 01 03:00:56 PM UTC 24 |
| Finished | Sep 01 03:01:10 PM UTC 24 |
| Peak memory | 234968 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3987854911 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_31/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_pass_addr_payload_swap.3987854911 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/34.spi_device_pass_addr_payload_swap/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/34.spi_device_pass_cmd_filtering.1603050001 |
| Short name | T736 |
| Test name | |
| Test status | |
| Simulation time | 5989594805 ps |
| CPU time | 26.01 seconds |
| Started | Sep 01 03:00:54 PM UTC 24 |
| Finished | Sep 01 03:01:22 PM UTC 24 |
| Peak memory | 251496 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1603050001 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_08_31/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_pass_cmd_filtering.1603050001 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/34.spi_device_pass_cmd_filtering/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/34.spi_device_read_buffer_direct.2462306124 |
| Short name | T727 |
| Test name | |
| Test status | |
| Simulation time | 647117183 ps |
| CPU time | 5.27 seconds |
| Started | Sep 01 03:01:06 PM UTC 24 |
| Finished | Sep 01 03:01:12 PM UTC 24 |
| Peak memory | 231256 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2462306124 -assert nopostproc +UVM_TESTNAME=spi_device _base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_read_buffer_direct.2462306124 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/34.spi_device_read_buffer_direct/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/34.spi_device_stress_all.642415043 |
| Short name | T369 |
| Test name | |
| Test status | |
| Simulation time | 21626152624 ps |
| CPU time | 266.47 seconds |
| Started | Sep 01 03:01:09 PM UTC 24 |
| Finished | Sep 01 03:05:39 PM UTC 24 |
| Peak memory | 267912 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=642415043 -assert nopostproc +UVM_T ESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_stress_all.642415043 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/34.spi_device_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/34.spi_device_tpm_all.3198856395 |
| Short name | T754 |
| Test name | |
| Test status | |
| Simulation time | 68481149017 ps |
| CPU time | 53.59 seconds |
| Started | Sep 01 03:00:51 PM UTC 24 |
| Finished | Sep 01 03:01:46 PM UTC 24 |
| Peak memory | 227612 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3198856395 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_all.3198856395 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/34.spi_device_tpm_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/34.spi_device_tpm_read_hw_reg.3937319516 |
| Short name | T732 |
| Test name | |
| Test status | |
| Simulation time | 4892994967 ps |
| CPU time | 24.35 seconds |
| Started | Sep 01 03:00:51 PM UTC 24 |
| Finished | Sep 01 03:01:16 PM UTC 24 |
| Peak memory | 227536 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3937319516 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_31/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_read_hw_reg.3937319516 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/34.spi_device_tpm_read_hw_reg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/34.spi_device_tpm_rw.2108812632 |
| Short name | T717 |
| Test name | |
| Test status | |
| Simulation time | 65090427 ps |
| CPU time | 1.14 seconds |
| Started | Sep 01 03:00:52 PM UTC 24 |
| Finished | Sep 01 03:00:54 PM UTC 24 |
| Peak memory | 215864 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2108812632 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_rw.2108812632 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/34.spi_device_tpm_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/34.spi_device_tpm_sts_read.2776424420 |
| Short name | T715 |
| Test name | |
| Test status | |
| Simulation time | 106629363 ps |
| CPU time | 1.22 seconds |
| Started | Sep 01 03:00:51 PM UTC 24 |
| Finished | Sep 01 03:00:53 PM UTC 24 |
| Peak memory | 215868 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2776424420 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_3 1/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_sts_read.2776424420 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/34.spi_device_tpm_sts_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/34.spi_device_upload.2952541316 |
| Short name | T720 |
| Test name | |
| Test status | |
| Simulation time | 247157994 ps |
| CPU time | 7.06 seconds |
| Started | Sep 01 03:00:58 PM UTC 24 |
| Finished | Sep 01 03:01:06 PM UTC 24 |
| Peak memory | 245156 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2952541316 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_upload.2952541316 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/34.spi_device_upload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/35.spi_device_alert_test.2917294184 |
| Short name | T744 |
| Test name | |
| Test status | |
| Simulation time | 14674590 ps |
| CPU time | 1.11 seconds |
| Started | Sep 01 03:01:25 PM UTC 24 |
| Finished | Sep 01 03:01:28 PM UTC 24 |
| Peak memory | 215740 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2917294184 -assert nopostproc +UVM_TES TNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_alert_test.2917294184 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/35.spi_device_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/35.spi_device_cfg_cmd.1880639267 |
| Short name | T741 |
| Test name | |
| Test status | |
| Simulation time | 1091088976 ps |
| CPU time | 8.65 seconds |
| Started | Sep 01 03:01:16 PM UTC 24 |
| Finished | Sep 01 03:01:26 PM UTC 24 |
| Peak memory | 245208 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1880639267 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_cfg_cmd.1880639267 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/35.spi_device_cfg_cmd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/35.spi_device_csb_read.3833650260 |
| Short name | T726 |
| Test name | |
| Test status | |
| Simulation time | 27140022 ps |
| CPU time | 1.18 seconds |
| Started | Sep 01 03:01:10 PM UTC 24 |
| Finished | Sep 01 03:01:12 PM UTC 24 |
| Peak memory | 215808 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3833650260 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/sp i_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_csb_read.3833650260 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/35.spi_device_csb_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/35.spi_device_flash_and_tpm.1568263627 |
| Short name | T761 |
| Test name | |
| Test status | |
| Simulation time | 13546922238 ps |
| CPU time | 32.37 seconds |
| Started | Sep 01 03:01:23 PM UTC 24 |
| Finished | Sep 01 03:01:57 PM UTC 24 |
| Peak memory | 231636 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1568263627 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_ 31/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_and_tpm.1568263627 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/35.spi_device_flash_and_tpm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/35.spi_device_flash_and_tpm_min_idle.373319044 |
| Short name | T785 |
| Test name | |
| Test status | |
| Simulation time | 20834421066 ps |
| CPU time | 59.67 seconds |
| Started | Sep 01 03:01:23 PM UTC 24 |
| Finished | Sep 01 03:02:24 PM UTC 24 |
| Peak memory | 245324 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=373319044 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_31/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_and_tpm_min_idle.373319044 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/35.spi_device_flash_and_tpm_min_idle/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/35.spi_device_flash_mode.2155913206 |
| Short name | T375 |
| Test name | |
| Test status | |
| Simulation time | 4893476915 ps |
| CPU time | 11.42 seconds |
| Started | Sep 01 03:01:17 PM UTC 24 |
| Finished | Sep 01 03:01:30 PM UTC 24 |
| Peak memory | 245184 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2155913206 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/ spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_mode.2155913206 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/35.spi_device_flash_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/35.spi_device_flash_mode_ignore_cmds.3941204541 |
| Short name | T769 |
| Test name | |
| Test status | |
| Simulation time | 5088029912 ps |
| CPU time | 46.16 seconds |
| Started | Sep 01 03:01:17 PM UTC 24 |
| Finished | Sep 01 03:02:05 PM UTC 24 |
| Peak memory | 251472 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3941204541 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_31/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_mode_ignore_cmds.3941204541 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/35.spi_device_flash_mode_ignore_cmds/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/35.spi_device_intercept.2156271274 |
| Short name | T737 |
| Test name | |
| Test status | |
| Simulation time | 816946753 ps |
| CPU time | 6.14 seconds |
| Started | Sep 01 03:01:15 PM UTC 24 |
| Finished | Sep 01 03:01:22 PM UTC 24 |
| Peak memory | 245208 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2156271274 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/s pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_intercept.2156271274 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/35.spi_device_intercept/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/35.spi_device_mailbox.4260930409 |
| Short name | T764 |
| Test name | |
| Test status | |
| Simulation time | 12025871769 ps |
| CPU time | 42.2 seconds |
| Started | Sep 01 03:01:15 PM UTC 24 |
| Finished | Sep 01 03:01:58 PM UTC 24 |
| Peak memory | 251488 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4260930409 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_mailbox.4260930409 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/35.spi_device_mailbox/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/35.spi_device_pass_addr_payload_swap.3900805420 |
| Short name | T735 |
| Test name | |
| Test status | |
| Simulation time | 764550326 ps |
| CPU time | 5.47 seconds |
| Started | Sep 01 03:01:15 PM UTC 24 |
| Finished | Sep 01 03:01:21 PM UTC 24 |
| Peak memory | 245184 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3900805420 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_31/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_pass_addr_payload_swap.3900805420 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/35.spi_device_pass_addr_payload_swap/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/35.spi_device_pass_cmd_filtering.2287414782 |
| Short name | T740 |
| Test name | |
| Test status | |
| Simulation time | 3947269830 ps |
| CPU time | 9.35 seconds |
| Started | Sep 01 03:01:15 PM UTC 24 |
| Finished | Sep 01 03:01:25 PM UTC 24 |
| Peak memory | 234940 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2287414782 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_08_31/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_pass_cmd_filtering.2287414782 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/35.spi_device_pass_cmd_filtering/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/35.spi_device_read_buffer_direct.2152463839 |
| Short name | T755 |
| Test name | |
| Test status | |
| Simulation time | 19459150222 ps |
| CPU time | 25.58 seconds |
| Started | Sep 01 03:01:20 PM UTC 24 |
| Finished | Sep 01 03:01:46 PM UTC 24 |
| Peak memory | 233692 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2152463839 -assert nopostproc +UVM_TESTNAME=spi_device _base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_read_buffer_direct.2152463839 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/35.spi_device_read_buffer_direct/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/35.spi_device_stress_all.1394838606 |
| Short name | T998 |
| Test name | |
| Test status | |
| Simulation time | 89579094179 ps |
| CPU time | 465.64 seconds |
| Started | Sep 01 03:01:24 PM UTC 24 |
| Finished | Sep 01 03:09:16 PM UTC 24 |
| Peak memory | 263820 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1394838606 -assert nopostproc +UVM_ TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_stress_all.1394838606 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/35.spi_device_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/35.spi_device_tpm_all.3624076364 |
| Short name | T749 |
| Test name | |
| Test status | |
| Simulation time | 1744260294 ps |
| CPU time | 18.26 seconds |
| Started | Sep 01 03:01:14 PM UTC 24 |
| Finished | Sep 01 03:01:34 PM UTC 24 |
| Peak memory | 231516 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3624076364 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_all.3624076364 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/35.spi_device_tpm_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/35.spi_device_tpm_read_hw_reg.3564269157 |
| Short name | T730 |
| Test name | |
| Test status | |
| Simulation time | 14576281 ps |
| CPU time | 1.1 seconds |
| Started | Sep 01 03:01:11 PM UTC 24 |
| Finished | Sep 01 03:01:13 PM UTC 24 |
| Peak memory | 215800 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3564269157 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_31/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_read_hw_reg.3564269157 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/35.spi_device_tpm_read_hw_reg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/35.spi_device_tpm_rw.3677786257 |
| Short name | T734 |
| Test name | |
| Test status | |
| Simulation time | 73579501 ps |
| CPU time | 3.57 seconds |
| Started | Sep 01 03:01:15 PM UTC 24 |
| Finished | Sep 01 03:01:19 PM UTC 24 |
| Peak memory | 227420 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3677786257 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_rw.3677786257 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/35.spi_device_tpm_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/35.spi_device_tpm_sts_read.6799026 |
| Short name | T733 |
| Test name | |
| Test status | |
| Simulation time | 71824499 ps |
| CPU time | 1.45 seconds |
| Started | Sep 01 03:01:14 PM UTC 24 |
| Finished | Sep 01 03:01:17 PM UTC 24 |
| Peak memory | 215864 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=6799026 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U VM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/s pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_sts_read.6799026 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/35.spi_device_tpm_sts_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/35.spi_device_upload.2323182836 |
| Short name | T748 |
| Test name | |
| Test status | |
| Simulation time | 2460929265 ps |
| CPU time | 16.48 seconds |
| Started | Sep 01 03:01:15 PM UTC 24 |
| Finished | Sep 01 03:01:32 PM UTC 24 |
| Peak memory | 235088 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2323182836 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_upload.2323182836 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/35.spi_device_upload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/36.spi_device_alert_test.2896324448 |
| Short name | T759 |
| Test name | |
| Test status | |
| Simulation time | 13633730 ps |
| CPU time | 1.12 seconds |
| Started | Sep 01 03:01:51 PM UTC 24 |
| Finished | Sep 01 03:01:54 PM UTC 24 |
| Peak memory | 215680 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2896324448 -assert nopostproc +UVM_TES TNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_alert_test.2896324448 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/36.spi_device_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/36.spi_device_cfg_cmd.3739505258 |
| Short name | T753 |
| Test name | |
| Test status | |
| Simulation time | 354922305 ps |
| CPU time | 4.08 seconds |
| Started | Sep 01 03:01:37 PM UTC 24 |
| Finished | Sep 01 03:01:42 PM UTC 24 |
| Peak memory | 234960 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3739505258 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_cfg_cmd.3739505258 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/36.spi_device_cfg_cmd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/36.spi_device_csb_read.975695835 |
| Short name | T745 |
| Test name | |
| Test status | |
| Simulation time | 50738490 ps |
| CPU time | 1.1 seconds |
| Started | Sep 01 03:01:27 PM UTC 24 |
| Finished | Sep 01 03:01:29 PM UTC 24 |
| Peak memory | 215808 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=975695835 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_csb_read.975695835 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/36.spi_device_csb_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/36.spi_device_flash_all.3723762550 |
| Short name | T871 |
| Test name | |
| Test status | |
| Simulation time | 9336142461 ps |
| CPU time | 129.35 seconds |
| Started | Sep 01 03:01:46 PM UTC 24 |
| Finished | Sep 01 03:03:58 PM UTC 24 |
| Peak memory | 265924 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3723762550 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/s pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_all.3723762550 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/36.spi_device_flash_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/36.spi_device_flash_and_tpm.2314931836 |
| Short name | T852 |
| Test name | |
| Test status | |
| Simulation time | 6808741381 ps |
| CPU time | 104.56 seconds |
| Started | Sep 01 03:01:48 PM UTC 24 |
| Finished | Sep 01 03:03:35 PM UTC 24 |
| Peak memory | 251600 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2314931836 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_ 31/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_and_tpm.2314931836 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/36.spi_device_flash_and_tpm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/36.spi_device_flash_and_tpm_min_idle.1392944920 |
| Short name | T803 |
| Test name | |
| Test status | |
| Simulation time | 13807504631 ps |
| CPU time | 51.9 seconds |
| Started | Sep 01 03:01:49 PM UTC 24 |
| Finished | Sep 01 03:02:42 PM UTC 24 |
| Peak memory | 261760 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1392944920 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_31/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_and_tpm_min_idle.1392944920 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/36.spi_device_flash_and_tpm_min_idle/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/36.spi_device_flash_mode.3648345234 |
| Short name | T795 |
| Test name | |
| Test status | |
| Simulation time | 4853518189 ps |
| CPU time | 55.22 seconds |
| Started | Sep 01 03:01:40 PM UTC 24 |
| Finished | Sep 01 03:02:37 PM UTC 24 |
| Peak memory | 245340 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3648345234 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/ spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_mode.3648345234 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/36.spi_device_flash_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/36.spi_device_flash_mode_ignore_cmds.75048445 |
| Short name | T999 |
| Test name | |
| Test status | |
| Simulation time | 210503988841 ps |
| CPU time | 453.5 seconds |
| Started | Sep 01 03:01:42 PM UTC 24 |
| Finished | Sep 01 03:09:23 PM UTC 24 |
| Peak memory | 267856 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=75048445 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_31/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_mode_ignore_cmds.75048445 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/36.spi_device_flash_mode_ignore_cmds/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/36.spi_device_intercept.3572502816 |
| Short name | T758 |
| Test name | |
| Test status | |
| Simulation time | 5465003538 ps |
| CPU time | 15.92 seconds |
| Started | Sep 01 03:01:33 PM UTC 24 |
| Finished | Sep 01 03:01:51 PM UTC 24 |
| Peak memory | 245340 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3572502816 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/s pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_intercept.3572502816 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/36.spi_device_intercept/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/36.spi_device_mailbox.4032337895 |
| Short name | T752 |
| Test name | |
| Test status | |
| Simulation time | 978358856 ps |
| CPU time | 4.94 seconds |
| Started | Sep 01 03:01:34 PM UTC 24 |
| Finished | Sep 01 03:01:41 PM UTC 24 |
| Peak memory | 245212 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4032337895 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_mailbox.4032337895 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/36.spi_device_mailbox/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/36.spi_device_pass_addr_payload_swap.1755534159 |
| Short name | T757 |
| Test name | |
| Test status | |
| Simulation time | 2362303556 ps |
| CPU time | 16.6 seconds |
| Started | Sep 01 03:01:32 PM UTC 24 |
| Finished | Sep 01 03:01:51 PM UTC 24 |
| Peak memory | 235032 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1755534159 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_31/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_pass_addr_payload_swap.1755534159 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/36.spi_device_pass_addr_payload_swap/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/36.spi_device_pass_cmd_filtering.4005214029 |
| Short name | T289 |
| Test name | |
| Test status | |
| Simulation time | 2362588920 ps |
| CPU time | 15.13 seconds |
| Started | Sep 01 03:01:31 PM UTC 24 |
| Finished | Sep 01 03:01:48 PM UTC 24 |
| Peak memory | 261712 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4005214029 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_08_31/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_pass_cmd_filtering.4005214029 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/36.spi_device_pass_cmd_filtering/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/36.spi_device_read_buffer_direct.2590460789 |
| Short name | T767 |
| Test name | |
| Test status | |
| Simulation time | 2728534866 ps |
| CPU time | 17.05 seconds |
| Started | Sep 01 03:01:43 PM UTC 24 |
| Finished | Sep 01 03:02:02 PM UTC 24 |
| Peak memory | 233492 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2590460789 -assert nopostproc +UVM_TESTNAME=spi_device _base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_read_buffer_direct.2590460789 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/36.spi_device_read_buffer_direct/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/36.spi_device_stress_all.1746595453 |
| Short name | T358 |
| Test name | |
| Test status | |
| Simulation time | 68459291607 ps |
| CPU time | 174.92 seconds |
| Started | Sep 01 03:01:50 PM UTC 24 |
| Finished | Sep 01 03:04:48 PM UTC 24 |
| Peak memory | 310860 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1746595453 -assert nopostproc +UVM_ TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_stress_all.1746595453 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/36.spi_device_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/36.spi_device_tpm_all.1999062426 |
| Short name | T770 |
| Test name | |
| Test status | |
| Simulation time | 1316340584 ps |
| CPU time | 35.91 seconds |
| Started | Sep 01 03:01:28 PM UTC 24 |
| Finished | Sep 01 03:02:05 PM UTC 24 |
| Peak memory | 227484 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1999062426 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_all.1999062426 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/36.spi_device_tpm_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/36.spi_device_tpm_read_hw_reg.3278175012 |
| Short name | T756 |
| Test name | |
| Test status | |
| Simulation time | 2799568163 ps |
| CPU time | 19.27 seconds |
| Started | Sep 01 03:01:28 PM UTC 24 |
| Finished | Sep 01 03:01:49 PM UTC 24 |
| Peak memory | 227576 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3278175012 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_31/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_read_hw_reg.3278175012 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/36.spi_device_tpm_read_hw_reg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/36.spi_device_tpm_rw.2754050986 |
| Short name | T750 |
| Test name | |
| Test status | |
| Simulation time | 117698300 ps |
| CPU time | 5.33 seconds |
| Started | Sep 01 03:01:29 PM UTC 24 |
| Finished | Sep 01 03:01:36 PM UTC 24 |
| Peak memory | 227516 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2754050986 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_rw.2754050986 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/36.spi_device_tpm_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/36.spi_device_tpm_sts_read.690639356 |
| Short name | T747 |
| Test name | |
| Test status | |
| Simulation time | 66610480 ps |
| CPU time | 1.36 seconds |
| Started | Sep 01 03:01:29 PM UTC 24 |
| Finished | Sep 01 03:01:32 PM UTC 24 |
| Peak memory | 215864 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=690639356 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31 /spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_sts_read.690639356 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/36.spi_device_tpm_sts_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/36.spi_device_upload.1224889476 |
| Short name | T800 |
| Test name | |
| Test status | |
| Simulation time | 48081052196 ps |
| CPU time | 62.09 seconds |
| Started | Sep 01 03:01:35 PM UTC 24 |
| Finished | Sep 01 03:02:40 PM UTC 24 |
| Peak memory | 265764 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1224889476 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_upload.1224889476 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/36.spi_device_upload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/37.spi_device_alert_test.872021063 |
| Short name | T777 |
| Test name | |
| Test status | |
| Simulation time | 184713304 ps |
| CPU time | 1.12 seconds |
| Started | Sep 01 03:02:12 PM UTC 24 |
| Finished | Sep 01 03:02:14 PM UTC 24 |
| Peak memory | 215680 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=872021063 -assert nopostproc +UVM_TEST NAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_alert_test.872021063 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/37.spi_device_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/37.spi_device_cfg_cmd.3808905131 |
| Short name | T771 |
| Test name | |
| Test status | |
| Simulation time | 75206810 ps |
| CPU time | 3.96 seconds |
| Started | Sep 01 03:02:03 PM UTC 24 |
| Finished | Sep 01 03:02:08 PM UTC 24 |
| Peak memory | 234896 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3808905131 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_cfg_cmd.3808905131 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/37.spi_device_cfg_cmd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/37.spi_device_csb_read.1761100171 |
| Short name | T760 |
| Test name | |
| Test status | |
| Simulation time | 18652159 ps |
| CPU time | 1.21 seconds |
| Started | Sep 01 03:01:53 PM UTC 24 |
| Finished | Sep 01 03:01:55 PM UTC 24 |
| Peak memory | 215632 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1761100171 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/sp i_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_csb_read.1761100171 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/37.spi_device_csb_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/37.spi_device_flash_all.2085804847 |
| Short name | T323 |
| Test name | |
| Test status | |
| Simulation time | 1416432149 ps |
| CPU time | 10.69 seconds |
| Started | Sep 01 03:02:06 PM UTC 24 |
| Finished | Sep 01 03:02:18 PM UTC 24 |
| Peak memory | 234956 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2085804847 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/s pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_all.2085804847 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/37.spi_device_flash_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/37.spi_device_flash_and_tpm.3030873733 |
| Short name | T876 |
| Test name | |
| Test status | |
| Simulation time | 7020650795 ps |
| CPU time | 110.87 seconds |
| Started | Sep 01 03:02:08 PM UTC 24 |
| Finished | Sep 01 03:04:01 PM UTC 24 |
| Peak memory | 261780 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3030873733 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_ 31/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_and_tpm.3030873733 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/37.spi_device_flash_and_tpm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/37.spi_device_flash_and_tpm_min_idle.3696236796 |
| Short name | T1000 |
| Test name | |
| Test status | |
| Simulation time | 86447175371 ps |
| CPU time | 446.81 seconds |
| Started | Sep 01 03:02:10 PM UTC 24 |
| Finished | Sep 01 03:09:43 PM UTC 24 |
| Peak memory | 267912 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3696236796 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_31/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_and_tpm_min_idle.3696236796 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/37.spi_device_flash_and_tpm_min_idle/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/37.spi_device_flash_mode.1024849375 |
| Short name | T773 |
| Test name | |
| Test status | |
| Simulation time | 145275367 ps |
| CPU time | 7.66 seconds |
| Started | Sep 01 03:02:03 PM UTC 24 |
| Finished | Sep 01 03:02:11 PM UTC 24 |
| Peak memory | 245212 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1024849375 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/ spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_mode.1024849375 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/37.spi_device_flash_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/37.spi_device_flash_mode_ignore_cmds.4203056639 |
| Short name | T825 |
| Test name | |
| Test status | |
| Simulation time | 4382928244 ps |
| CPU time | 63.35 seconds |
| Started | Sep 01 03:02:05 PM UTC 24 |
| Finished | Sep 01 03:03:10 PM UTC 24 |
| Peak memory | 261708 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4203056639 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_31/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_mode_ignore_cmds.4203056639 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/37.spi_device_flash_mode_ignore_cmds/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/37.spi_device_intercept.644247423 |
| Short name | T786 |
| Test name | |
| Test status | |
| Simulation time | 24221364060 ps |
| CPU time | 23.6 seconds |
| Started | Sep 01 03:02:00 PM UTC 24 |
| Finished | Sep 01 03:02:25 PM UTC 24 |
| Peak memory | 235228 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=644247423 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/sp i_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_intercept.644247423 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/37.spi_device_intercept/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/37.spi_device_mailbox.1772628514 |
| Short name | T768 |
| Test name | |
| Test status | |
| Simulation time | 289352447 ps |
| CPU time | 3.16 seconds |
| Started | Sep 01 03:02:00 PM UTC 24 |
| Finished | Sep 01 03:02:04 PM UTC 24 |
| Peak memory | 234956 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1772628514 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_mailbox.1772628514 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/37.spi_device_mailbox/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/37.spi_device_pass_addr_payload_swap.3733607707 |
| Short name | T809 |
| Test name | |
| Test status | |
| Simulation time | 49874487492 ps |
| CPU time | 47.76 seconds |
| Started | Sep 01 03:02:00 PM UTC 24 |
| Finished | Sep 01 03:02:49 PM UTC 24 |
| Peak memory | 251432 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3733607707 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_31/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_pass_addr_payload_swap.3733607707 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/37.spi_device_pass_addr_payload_swap/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/37.spi_device_pass_cmd_filtering.965423392 |
| Short name | T772 |
| Test name | |
| Test status | |
| Simulation time | 289015734 ps |
| CPU time | 8.72 seconds |
| Started | Sep 01 03:01:58 PM UTC 24 |
| Finished | Sep 01 03:02:08 PM UTC 24 |
| Peak memory | 249296 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=965423392 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _08_31/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_pass_cmd_filtering.965423392 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/37.spi_device_pass_cmd_filtering/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/37.spi_device_read_buffer_direct.1092762635 |
| Short name | T778 |
| Test name | |
| Test status | |
| Simulation time | 1135326940 ps |
| CPU time | 7.61 seconds |
| Started | Sep 01 03:02:06 PM UTC 24 |
| Finished | Sep 01 03:02:15 PM UTC 24 |
| Peak memory | 233364 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1092762635 -assert nopostproc +UVM_TESTNAME=spi_device _base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_read_buffer_direct.1092762635 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/37.spi_device_read_buffer_direct/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/37.spi_device_stress_all.2602983391 |
| Short name | T775 |
| Test name | |
| Test status | |
| Simulation time | 164996190 ps |
| CPU time | 1.38 seconds |
| Started | Sep 01 03:02:10 PM UTC 24 |
| Finished | Sep 01 03:02:12 PM UTC 24 |
| Peak memory | 215800 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2602983391 -assert nopostproc +UVM_ TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_stress_all.2602983391 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/37.spi_device_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/37.spi_device_tpm_all.1007666938 |
| Short name | T762 |
| Test name | |
| Test status | |
| Simulation time | 43195896 ps |
| CPU time | 1.11 seconds |
| Started | Sep 01 03:01:55 PM UTC 24 |
| Finished | Sep 01 03:01:57 PM UTC 24 |
| Peak memory | 215684 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1007666938 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_all.1007666938 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/37.spi_device_tpm_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/37.spi_device_tpm_read_hw_reg.2155649706 |
| Short name | T776 |
| Test name | |
| Test status | |
| Simulation time | 21745411696 ps |
| CPU time | 19.05 seconds |
| Started | Sep 01 03:01:53 PM UTC 24 |
| Finished | Sep 01 03:02:13 PM UTC 24 |
| Peak memory | 229676 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2155649706 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_31/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_read_hw_reg.2155649706 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/37.spi_device_tpm_read_hw_reg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/37.spi_device_tpm_rw.777026767 |
| Short name | T766 |
| Test name | |
| Test status | |
| Simulation time | 114563666 ps |
| CPU time | 1.84 seconds |
| Started | Sep 01 03:01:58 PM UTC 24 |
| Finished | Sep 01 03:02:01 PM UTC 24 |
| Peak memory | 226744 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=777026767 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/spi_d evice_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_rw.777026767 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/37.spi_device_tpm_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/37.spi_device_tpm_sts_read.1969764929 |
| Short name | T763 |
| Test name | |
| Test status | |
| Simulation time | 50283004 ps |
| CPU time | 1.33 seconds |
| Started | Sep 01 03:01:56 PM UTC 24 |
| Finished | Sep 01 03:01:58 PM UTC 24 |
| Peak memory | 215868 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1969764929 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_3 1/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_sts_read.1969764929 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/37.spi_device_tpm_sts_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/37.spi_device_upload.2986252673 |
| Short name | T780 |
| Test name | |
| Test status | |
| Simulation time | 299076312 ps |
| CPU time | 11.92 seconds |
| Started | Sep 01 03:02:03 PM UTC 24 |
| Finished | Sep 01 03:02:16 PM UTC 24 |
| Peak memory | 247200 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2986252673 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_upload.2986252673 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/37.spi_device_upload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/38.spi_device_alert_test.3152250958 |
| Short name | T790 |
| Test name | |
| Test status | |
| Simulation time | 11834908 ps |
| CPU time | 1.14 seconds |
| Started | Sep 01 03:02:30 PM UTC 24 |
| Finished | Sep 01 03:02:32 PM UTC 24 |
| Peak memory | 215680 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3152250958 -assert nopostproc +UVM_TES TNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_alert_test.3152250958 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/38.spi_device_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/38.spi_device_cfg_cmd.445782478 |
| Short name | T787 |
| Test name | |
| Test status | |
| Simulation time | 769814703 ps |
| CPU time | 7.7 seconds |
| Started | Sep 01 03:02:20 PM UTC 24 |
| Finished | Sep 01 03:02:28 PM UTC 24 |
| Peak memory | 234896 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=445782478 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_cfg_cmd.445782478 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/38.spi_device_cfg_cmd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/38.spi_device_csb_read.2613439850 |
| Short name | T779 |
| Test name | |
| Test status | |
| Simulation time | 21378136 ps |
| CPU time | 1.17 seconds |
| Started | Sep 01 03:02:13 PM UTC 24 |
| Finished | Sep 01 03:02:16 PM UTC 24 |
| Peak memory | 215808 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2613439850 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/sp i_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_csb_read.2613439850 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/38.spi_device_csb_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/38.spi_device_flash_all.3620427551 |
| Short name | T860 |
| Test name | |
| Test status | |
| Simulation time | 6652168722 ps |
| CPU time | 79.94 seconds |
| Started | Sep 01 03:02:21 PM UTC 24 |
| Finished | Sep 01 03:03:43 PM UTC 24 |
| Peak memory | 245264 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3620427551 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/s pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_all.3620427551 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/38.spi_device_flash_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/38.spi_device_flash_and_tpm_min_idle.2057954157 |
| Short name | T1010 |
| Test name | |
| Test status | |
| Simulation time | 606650799715 ps |
| CPU time | 742.15 seconds |
| Started | Sep 01 03:02:26 PM UTC 24 |
| Finished | Sep 01 03:14:57 PM UTC 24 |
| Peak memory | 294560 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2057954157 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_31/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_and_tpm_min_idle.2057954157 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/38.spi_device_flash_and_tpm_min_idle/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/38.spi_device_flash_mode.1064726215 |
| Short name | T796 |
| Test name | |
| Test status | |
| Simulation time | 2042978100 ps |
| CPU time | 16.09 seconds |
| Started | Sep 01 03:02:20 PM UTC 24 |
| Finished | Sep 01 03:02:37 PM UTC 24 |
| Peak memory | 249292 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1064726215 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/ spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_mode.1064726215 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/38.spi_device_flash_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/38.spi_device_flash_mode_ignore_cmds.1723144444 |
| Short name | T228 |
| Test name | |
| Test status | |
| Simulation time | 11780465687 ps |
| CPU time | 54.92 seconds |
| Started | Sep 01 03:02:20 PM UTC 24 |
| Finished | Sep 01 03:03:16 PM UTC 24 |
| Peak memory | 261728 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1723144444 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_31/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_mode_ignore_cmds.1723144444 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/38.spi_device_flash_mode_ignore_cmds/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/38.spi_device_intercept.1807056849 |
| Short name | T738 |
| Test name | |
| Test status | |
| Simulation time | 36366031 ps |
| CPU time | 3.14 seconds |
| Started | Sep 01 03:02:17 PM UTC 24 |
| Finished | Sep 01 03:02:21 PM UTC 24 |
| Peak memory | 245004 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1807056849 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/s pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_intercept.1807056849 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/38.spi_device_intercept/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/38.spi_device_mailbox.1454357658 |
| Short name | T802 |
| Test name | |
| Test status | |
| Simulation time | 8075427889 ps |
| CPU time | 23.98 seconds |
| Started | Sep 01 03:02:17 PM UTC 24 |
| Finished | Sep 01 03:02:42 PM UTC 24 |
| Peak memory | 245324 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1454357658 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_mailbox.1454357658 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/38.spi_device_mailbox/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/38.spi_device_pass_addr_payload_swap.3805166976 |
| Short name | T789 |
| Test name | |
| Test status | |
| Simulation time | 1725875400 ps |
| CPU time | 12.53 seconds |
| Started | Sep 01 03:02:17 PM UTC 24 |
| Finished | Sep 01 03:02:30 PM UTC 24 |
| Peak memory | 234976 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3805166976 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_31/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_pass_addr_payload_swap.3805166976 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/38.spi_device_pass_addr_payload_swap/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/38.spi_device_pass_cmd_filtering.2055989260 |
| Short name | T788 |
| Test name | |
| Test status | |
| Simulation time | 2933190072 ps |
| CPU time | 11.75 seconds |
| Started | Sep 01 03:02:17 PM UTC 24 |
| Finished | Sep 01 03:02:30 PM UTC 24 |
| Peak memory | 251372 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2055989260 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_08_31/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_pass_cmd_filtering.2055989260 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/38.spi_device_pass_cmd_filtering/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/38.spi_device_read_buffer_direct.2598224398 |
| Short name | T801 |
| Test name | |
| Test status | |
| Simulation time | 11341867251 ps |
| CPU time | 18.42 seconds |
| Started | Sep 01 03:02:21 PM UTC 24 |
| Finished | Sep 01 03:02:41 PM UTC 24 |
| Peak memory | 231384 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2598224398 -assert nopostproc +UVM_TESTNAME=spi_device _base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_read_buffer_direct.2598224398 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/38.spi_device_read_buffer_direct/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/38.spi_device_stress_all.3789416008 |
| Short name | T919 |
| Test name | |
| Test status | |
| Simulation time | 8388298579 ps |
| CPU time | 141.01 seconds |
| Started | Sep 01 03:02:26 PM UTC 24 |
| Finished | Sep 01 03:04:49 PM UTC 24 |
| Peak memory | 278220 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3789416008 -assert nopostproc +UVM_ TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_stress_all.3789416008 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/38.spi_device_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/38.spi_device_tpm_all.2069855298 |
| Short name | T793 |
| Test name | |
| Test status | |
| Simulation time | 4307587357 ps |
| CPU time | 17.98 seconds |
| Started | Sep 01 03:02:15 PM UTC 24 |
| Finished | Sep 01 03:02:34 PM UTC 24 |
| Peak memory | 231700 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2069855298 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_all.2069855298 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/38.spi_device_tpm_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/38.spi_device_tpm_read_hw_reg.1188711969 |
| Short name | T784 |
| Test name | |
| Test status | |
| Simulation time | 2561987933 ps |
| CPU time | 4.77 seconds |
| Started | Sep 01 03:02:13 PM UTC 24 |
| Finished | Sep 01 03:02:19 PM UTC 24 |
| Peak memory | 227580 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1188711969 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_31/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_read_hw_reg.1188711969 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/38.spi_device_tpm_read_hw_reg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/38.spi_device_tpm_rw.501145886 |
| Short name | T783 |
| Test name | |
| Test status | |
| Simulation time | 24117464 ps |
| CPU time | 1.38 seconds |
| Started | Sep 01 03:02:17 PM UTC 24 |
| Finished | Sep 01 03:02:19 PM UTC 24 |
| Peak memory | 215860 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=501145886 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/spi_d evice_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_rw.501145886 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/38.spi_device_tpm_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/38.spi_device_tpm_sts_read.1638666576 |
| Short name | T781 |
| Test name | |
| Test status | |
| Simulation time | 28563219 ps |
| CPU time | 1.32 seconds |
| Started | Sep 01 03:02:15 PM UTC 24 |
| Finished | Sep 01 03:02:17 PM UTC 24 |
| Peak memory | 215860 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1638666576 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_3 1/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_sts_read.1638666576 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/38.spi_device_tpm_sts_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/38.spi_device_upload.942547912 |
| Short name | T807 |
| Test name | |
| Test status | |
| Simulation time | 4513169074 ps |
| CPU time | 29.3 seconds |
| Started | Sep 01 03:02:18 PM UTC 24 |
| Finished | Sep 01 03:02:49 PM UTC 24 |
| Peak memory | 251424 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=942547912 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/spi_d evice_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_upload.942547912 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/38.spi_device_upload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/39.spi_device_alert_test.4257833005 |
| Short name | T811 |
| Test name | |
| Test status | |
| Simulation time | 11709374 ps |
| CPU time | 1.12 seconds |
| Started | Sep 01 03:02:49 PM UTC 24 |
| Finished | Sep 01 03:02:51 PM UTC 24 |
| Peak memory | 215740 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4257833005 -assert nopostproc +UVM_TES TNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_alert_test.4257833005 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/39.spi_device_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/39.spi_device_cfg_cmd.102242604 |
| Short name | T810 |
| Test name | |
| Test status | |
| Simulation time | 1385962676 ps |
| CPU time | 9.24 seconds |
| Started | Sep 01 03:02:39 PM UTC 24 |
| Finished | Sep 01 03:02:50 PM UTC 24 |
| Peak memory | 245196 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=102242604 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_cfg_cmd.102242604 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/39.spi_device_cfg_cmd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/39.spi_device_csb_read.3781686443 |
| Short name | T791 |
| Test name | |
| Test status | |
| Simulation time | 58198700 ps |
| CPU time | 1.22 seconds |
| Started | Sep 01 03:02:31 PM UTC 24 |
| Finished | Sep 01 03:02:33 PM UTC 24 |
| Peak memory | 215456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3781686443 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/sp i_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_csb_read.3781686443 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/39.spi_device_csb_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/39.spi_device_flash_all.1004261605 |
| Short name | T353 |
| Test name | |
| Test status | |
| Simulation time | 344814828 ps |
| CPU time | 12.29 seconds |
| Started | Sep 01 03:02:43 PM UTC 24 |
| Finished | Sep 01 03:02:56 PM UTC 24 |
| Peak memory | 251336 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1004261605 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/s pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_all.1004261605 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/39.spi_device_flash_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/39.spi_device_flash_and_tpm.1515168292 |
| Short name | T987 |
| Test name | |
| Test status | |
| Simulation time | 28993041191 ps |
| CPU time | 291.9 seconds |
| Started | Sep 01 03:02:44 PM UTC 24 |
| Finished | Sep 01 03:07:40 PM UTC 24 |
| Peak memory | 261824 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1515168292 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_ 31/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_and_tpm.1515168292 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/39.spi_device_flash_and_tpm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/39.spi_device_flash_and_tpm_min_idle.3667142481 |
| Short name | T160 |
| Test name | |
| Test status | |
| Simulation time | 10340014501 ps |
| CPU time | 91.64 seconds |
| Started | Sep 01 03:02:44 PM UTC 24 |
| Finished | Sep 01 03:04:18 PM UTC 24 |
| Peak memory | 278128 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3667142481 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_31/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_and_tpm_min_idle.3667142481 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/39.spi_device_flash_and_tpm_min_idle/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/39.spi_device_flash_mode.2671725792 |
| Short name | T817 |
| Test name | |
| Test status | |
| Simulation time | 8465258989 ps |
| CPU time | 21.66 seconds |
| Started | Sep 01 03:02:39 PM UTC 24 |
| Finished | Sep 01 03:03:02 PM UTC 24 |
| Peak memory | 245388 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2671725792 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/ spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_mode.2671725792 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/39.spi_device_flash_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/39.spi_device_flash_mode_ignore_cmds.1804844509 |
| Short name | T835 |
| Test name | |
| Test status | |
| Simulation time | 4845248032 ps |
| CPU time | 39.07 seconds |
| Started | Sep 01 03:02:40 PM UTC 24 |
| Finished | Sep 01 03:03:21 PM UTC 24 |
| Peak memory | 261652 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1804844509 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_31/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_mode_ignore_cmds.1804844509 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/39.spi_device_flash_mode_ignore_cmds/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/39.spi_device_intercept.2117380559 |
| Short name | T808 |
| Test name | |
| Test status | |
| Simulation time | 1571058153 ps |
| CPU time | 10.06 seconds |
| Started | Sep 01 03:02:38 PM UTC 24 |
| Finished | Sep 01 03:02:49 PM UTC 24 |
| Peak memory | 243948 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2117380559 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/s pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_intercept.2117380559 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/39.spi_device_intercept/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/39.spi_device_mailbox.2262988619 |
| Short name | T805 |
| Test name | |
| Test status | |
| Simulation time | 3977471841 ps |
| CPU time | 7.36 seconds |
| Started | Sep 01 03:02:38 PM UTC 24 |
| Finished | Sep 01 03:02:46 PM UTC 24 |
| Peak memory | 235020 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2262988619 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_mailbox.2262988619 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/39.spi_device_mailbox/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/39.spi_device_pass_addr_payload_swap.3457781823 |
| Short name | T806 |
| Test name | |
| Test status | |
| Simulation time | 1161582224 ps |
| CPU time | 11.34 seconds |
| Started | Sep 01 03:02:35 PM UTC 24 |
| Finished | Sep 01 03:02:48 PM UTC 24 |
| Peak memory | 245196 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3457781823 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_31/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_pass_addr_payload_swap.3457781823 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/39.spi_device_pass_addr_payload_swap/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/39.spi_device_pass_cmd_filtering.4256781384 |
| Short name | T839 |
| Test name | |
| Test status | |
| Simulation time | 31463784831 ps |
| CPU time | 46.33 seconds |
| Started | Sep 01 03:02:35 PM UTC 24 |
| Finished | Sep 01 03:03:23 PM UTC 24 |
| Peak memory | 235092 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4256781384 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_08_31/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_pass_cmd_filtering.4256781384 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/39.spi_device_pass_cmd_filtering/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/39.spi_device_read_buffer_direct.2354573598 |
| Short name | T815 |
| Test name | |
| Test status | |
| Simulation time | 5798468858 ps |
| CPU time | 15.42 seconds |
| Started | Sep 01 03:02:42 PM UTC 24 |
| Finished | Sep 01 03:02:58 PM UTC 24 |
| Peak memory | 233492 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2354573598 -assert nopostproc +UVM_TESTNAME=spi_device _base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_read_buffer_direct.2354573598 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/39.spi_device_read_buffer_direct/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/39.spi_device_stress_all.2366587710 |
| Short name | T870 |
| Test name | |
| Test status | |
| Simulation time | 17486659113 ps |
| CPU time | 69.91 seconds |
| Started | Sep 01 03:02:47 PM UTC 24 |
| Finished | Sep 01 03:03:58 PM UTC 24 |
| Peak memory | 251612 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2366587710 -assert nopostproc +UVM_ TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_stress_all.2366587710 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/39.spi_device_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/39.spi_device_tpm_all.685651661 |
| Short name | T822 |
| Test name | |
| Test status | |
| Simulation time | 1722564887 ps |
| CPU time | 33.04 seconds |
| Started | Sep 01 03:02:33 PM UTC 24 |
| Finished | Sep 01 03:03:07 PM UTC 24 |
| Peak memory | 227500 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=685651661 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_all.685651661 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/39.spi_device_tpm_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/39.spi_device_tpm_read_hw_reg.4036710098 |
| Short name | T798 |
| Test name | |
| Test status | |
| Simulation time | 631812058 ps |
| CPU time | 5.97 seconds |
| Started | Sep 01 03:02:31 PM UTC 24 |
| Finished | Sep 01 03:02:38 PM UTC 24 |
| Peak memory | 227420 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4036710098 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_31/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_read_hw_reg.4036710098 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/39.spi_device_tpm_read_hw_reg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/39.spi_device_tpm_rw.4215958984 |
| Short name | T799 |
| Test name | |
| Test status | |
| Simulation time | 32763979 ps |
| CPU time | 1.95 seconds |
| Started | Sep 01 03:02:35 PM UTC 24 |
| Finished | Sep 01 03:02:38 PM UTC 24 |
| Peak memory | 226752 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4215958984 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_rw.4215958984 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/39.spi_device_tpm_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/39.spi_device_tpm_sts_read.3919264630 |
| Short name | T797 |
| Test name | |
| Test status | |
| Simulation time | 43703260 ps |
| CPU time | 1.23 seconds |
| Started | Sep 01 03:02:35 PM UTC 24 |
| Finished | Sep 01 03:02:38 PM UTC 24 |
| Peak memory | 215868 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3919264630 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_3 1/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_sts_read.3919264630 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/39.spi_device_tpm_sts_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/39.spi_device_upload.1312187165 |
| Short name | T804 |
| Test name | |
| Test status | |
| Simulation time | 43141502 ps |
| CPU time | 3.13 seconds |
| Started | Sep 01 03:02:39 PM UTC 24 |
| Finished | Sep 01 03:02:43 PM UTC 24 |
| Peak memory | 244956 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1312187165 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_upload.1312187165 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/39.spi_device_upload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/4.spi_device_alert_test.3001927002 |
| Short name | T399 |
| Test name | |
| Test status | |
| Simulation time | 15163234 ps |
| CPU time | 1.13 seconds |
| Started | Sep 01 02:47:37 PM UTC 24 |
| Finished | Sep 01 02:47:40 PM UTC 24 |
| Peak memory | 215740 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3001927002 -assert nopostproc +UVM_TES TNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_alert_test.3001927002 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/4.spi_device_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/4.spi_device_cfg_cmd.2635672350 |
| Short name | T95 |
| Test name | |
| Test status | |
| Simulation time | 2621800179 ps |
| CPU time | 12.18 seconds |
| Started | Sep 01 02:47:30 PM UTC 24 |
| Finished | Sep 01 02:47:43 PM UTC 24 |
| Peak memory | 235080 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2635672350 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_cfg_cmd.2635672350 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/4.spi_device_cfg_cmd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/4.spi_device_csb_read.1778452386 |
| Short name | T397 |
| Test name | |
| Test status | |
| Simulation time | 32372196 ps |
| CPU time | 1.22 seconds |
| Started | Sep 01 02:47:17 PM UTC 24 |
| Finished | Sep 01 02:47:19 PM UTC 24 |
| Peak memory | 215804 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1778452386 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/sp i_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_csb_read.1778452386 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/4.spi_device_csb_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/4.spi_device_flash_all.2673313116 |
| Short name | T70 |
| Test name | |
| Test status | |
| Simulation time | 1469775731 ps |
| CPU time | 53.76 seconds |
| Started | Sep 01 02:47:34 PM UTC 24 |
| Finished | Sep 01 02:48:29 PM UTC 24 |
| Peak memory | 261588 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2673313116 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/s pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_all.2673313116 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/4.spi_device_flash_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/4.spi_device_flash_and_tpm.1761945572 |
| Short name | T233 |
| Test name | |
| Test status | |
| Simulation time | 112997809894 ps |
| CPU time | 297.88 seconds |
| Started | Sep 01 02:47:35 PM UTC 24 |
| Finished | Sep 01 02:52:37 PM UTC 24 |
| Peak memory | 261868 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1761945572 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_ 31/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_and_tpm.1761945572 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/4.spi_device_flash_and_tpm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/4.spi_device_flash_mode_ignore_cmds.3757222160 |
| Short name | T330 |
| Test name | |
| Test status | |
| Simulation time | 213475455976 ps |
| CPU time | 552.95 seconds |
| Started | Sep 01 02:47:33 PM UTC 24 |
| Finished | Sep 01 02:56:53 PM UTC 24 |
| Peak memory | 278116 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3757222160 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_31/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_mode_ignore_cmds.3757222160 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/4.spi_device_flash_mode_ignore_cmds/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/4.spi_device_intercept.3866005799 |
| Short name | T113 |
| Test name | |
| Test status | |
| Simulation time | 369698344 ps |
| CPU time | 8.1 seconds |
| Started | Sep 01 02:47:27 PM UTC 24 |
| Finished | Sep 01 02:47:37 PM UTC 24 |
| Peak memory | 241856 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3866005799 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/s pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_intercept.3866005799 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/4.spi_device_intercept/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/4.spi_device_mailbox.3774168318 |
| Short name | T283 |
| Test name | |
| Test status | |
| Simulation time | 1043690279 ps |
| CPU time | 5.45 seconds |
| Started | Sep 01 02:47:27 PM UTC 24 |
| Finished | Sep 01 02:47:34 PM UTC 24 |
| Peak memory | 231612 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3774168318 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_mailbox.3774168318 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/4.spi_device_mailbox/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/4.spi_device_pass_addr_payload_swap.295220056 |
| Short name | T121 |
| Test name | |
| Test status | |
| Simulation time | 1150345065 ps |
| CPU time | 3.07 seconds |
| Started | Sep 01 02:47:24 PM UTC 24 |
| Finished | Sep 01 02:47:29 PM UTC 24 |
| Peak memory | 234960 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=295220056 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_31/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_pass_addr_payload_swap.295220056 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/4.spi_device_pass_addr_payload_swap/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/4.spi_device_pass_cmd_filtering.165215762 |
| Short name | T198 |
| Test name | |
| Test status | |
| Simulation time | 965247858 ps |
| CPU time | 8.73 seconds |
| Started | Sep 01 02:47:24 PM UTC 24 |
| Finished | Sep 01 02:47:34 PM UTC 24 |
| Peak memory | 234960 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=165215762 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _08_31/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_pass_cmd_filtering.165215762 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/4.spi_device_pass_cmd_filtering/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/4.spi_device_read_buffer_direct.2886403409 |
| Short name | T166 |
| Test name | |
| Test status | |
| Simulation time | 9959458435 ps |
| CPU time | 13.53 seconds |
| Started | Sep 01 02:47:33 PM UTC 24 |
| Finished | Sep 01 02:47:47 PM UTC 24 |
| Peak memory | 233564 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2886403409 -assert nopostproc +UVM_TESTNAME=spi_device _base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_read_buffer_direct.2886403409 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/4.spi_device_read_buffer_direct/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/4.spi_device_sec_cm.2198710553 |
| Short name | T33 |
| Test name | |
| Test status | |
| Simulation time | 96673741 ps |
| CPU time | 1.85 seconds |
| Started | Sep 01 02:47:35 PM UTC 24 |
| Finished | Sep 01 02:47:38 PM UTC 24 |
| Peak memory | 257912 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2198710553 -assert nopostproc +UVM_TEST NAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_sec_cm.2198710553 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/4.spi_device_sec_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/4.spi_device_tpm_all.3725025620 |
| Short name | T123 |
| Test name | |
| Test status | |
| Simulation time | 39006359729 ps |
| CPU time | 55.91 seconds |
| Started | Sep 01 02:47:19 PM UTC 24 |
| Finished | Sep 01 02:48:16 PM UTC 24 |
| Peak memory | 227640 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3725025620 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_all.3725025620 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/4.spi_device_tpm_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/4.spi_device_tpm_read_hw_reg.1781634448 |
| Short name | T402 |
| Test name | |
| Test status | |
| Simulation time | 22834443361 ps |
| CPU time | 26.71 seconds |
| Started | Sep 01 02:47:18 PM UTC 24 |
| Finished | Sep 01 02:47:46 PM UTC 24 |
| Peak memory | 227676 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1781634448 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_31/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_read_hw_reg.1781634448 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/4.spi_device_tpm_read_hw_reg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/4.spi_device_tpm_rw.1121949030 |
| Short name | T45 |
| Test name | |
| Test status | |
| Simulation time | 36690751 ps |
| CPU time | 1.72 seconds |
| Started | Sep 01 02:47:20 PM UTC 24 |
| Finished | Sep 01 02:47:23 PM UTC 24 |
| Peak memory | 215864 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1121949030 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_rw.1121949030 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/4.spi_device_tpm_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/4.spi_device_tpm_sts_read.3752068437 |
| Short name | T398 |
| Test name | |
| Test status | |
| Simulation time | 33166856 ps |
| CPU time | 1.38 seconds |
| Started | Sep 01 02:47:20 PM UTC 24 |
| Finished | Sep 01 02:47:23 PM UTC 24 |
| Peak memory | 215864 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3752068437 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_3 1/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_sts_read.3752068437 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/4.spi_device_tpm_sts_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/4.spi_device_upload.429531845 |
| Short name | T65 |
| Test name | |
| Test status | |
| Simulation time | 3333872189 ps |
| CPU time | 27.33 seconds |
| Started | Sep 01 02:47:30 PM UTC 24 |
| Finished | Sep 01 02:47:58 PM UTC 24 |
| Peak memory | 235032 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=429531845 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/spi_d evice_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_upload.429531845 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/4.spi_device_upload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/40.spi_device_alert_test.319887071 |
| Short name | T826 |
| Test name | |
| Test status | |
| Simulation time | 132926836 ps |
| CPU time | 1.09 seconds |
| Started | Sep 01 03:03:09 PM UTC 24 |
| Finished | Sep 01 03:03:11 PM UTC 24 |
| Peak memory | 215680 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=319887071 -assert nopostproc +UVM_TEST NAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_alert_test.319887071 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/40.spi_device_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/40.spi_device_cfg_cmd.1623413165 |
| Short name | T820 |
| Test name | |
| Test status | |
| Simulation time | 2085740796 ps |
| CPU time | 5.35 seconds |
| Started | Sep 01 03:03:00 PM UTC 24 |
| Finished | Sep 01 03:03:07 PM UTC 24 |
| Peak memory | 234896 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1623413165 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_cfg_cmd.1623413165 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/40.spi_device_cfg_cmd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/40.spi_device_csb_read.2364388257 |
| Short name | T812 |
| Test name | |
| Test status | |
| Simulation time | 71614627 ps |
| CPU time | 1.17 seconds |
| Started | Sep 01 03:02:50 PM UTC 24 |
| Finished | Sep 01 03:02:53 PM UTC 24 |
| Peak memory | 215808 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2364388257 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/sp i_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_csb_read.2364388257 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/40.spi_device_csb_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/40.spi_device_flash_all.1995322717 |
| Short name | T245 |
| Test name | |
| Test status | |
| Simulation time | 97166856387 ps |
| CPU time | 168.14 seconds |
| Started | Sep 01 03:03:05 PM UTC 24 |
| Finished | Sep 01 03:05:56 PM UTC 24 |
| Peak memory | 278088 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1995322717 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/s pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_all.1995322717 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/40.spi_device_flash_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/40.spi_device_flash_and_tpm.1800856288 |
| Short name | T1001 |
| Test name | |
| Test status | |
| Simulation time | 38139905760 ps |
| CPU time | 402.58 seconds |
| Started | Sep 01 03:03:06 PM UTC 24 |
| Finished | Sep 01 03:09:54 PM UTC 24 |
| Peak memory | 265872 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1800856288 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_ 31/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_and_tpm.1800856288 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/40.spi_device_flash_and_tpm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/40.spi_device_flash_and_tpm_min_idle.559709264 |
| Short name | T995 |
| Test name | |
| Test status | |
| Simulation time | 29038278415 ps |
| CPU time | 350.91 seconds |
| Started | Sep 01 03:03:07 PM UTC 24 |
| Finished | Sep 01 03:09:03 PM UTC 24 |
| Peak memory | 265872 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=559709264 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_31/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_and_tpm_min_idle.559709264 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/40.spi_device_flash_and_tpm_min_idle/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/40.spi_device_flash_mode.837222036 |
| Short name | T380 |
| Test name | |
| Test status | |
| Simulation time | 10285353365 ps |
| CPU time | 24.89 seconds |
| Started | Sep 01 03:03:00 PM UTC 24 |
| Finished | Sep 01 03:03:26 PM UTC 24 |
| Peak memory | 251468 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=837222036 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/s pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_mode.837222036 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/40.spi_device_flash_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/40.spi_device_flash_mode_ignore_cmds.2701563031 |
| Short name | T988 |
| Test name | |
| Test status | |
| Simulation time | 23985110509 ps |
| CPU time | 276.97 seconds |
| Started | Sep 01 03:03:03 PM UTC 24 |
| Finished | Sep 01 03:07:45 PM UTC 24 |
| Peak memory | 263760 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2701563031 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_31/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_mode_ignore_cmds.2701563031 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/40.spi_device_flash_mode_ignore_cmds/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/40.spi_device_intercept.2893701352 |
| Short name | T818 |
| Test name | |
| Test status | |
| Simulation time | 141071510 ps |
| CPU time | 6.96 seconds |
| Started | Sep 01 03:02:56 PM UTC 24 |
| Finished | Sep 01 03:03:04 PM UTC 24 |
| Peak memory | 244936 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2893701352 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/s pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_intercept.2893701352 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/40.spi_device_intercept/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/40.spi_device_mailbox.1689164690 |
| Short name | T840 |
| Test name | |
| Test status | |
| Simulation time | 2014942205 ps |
| CPU time | 26.36 seconds |
| Started | Sep 01 03:02:56 PM UTC 24 |
| Finished | Sep 01 03:03:23 PM UTC 24 |
| Peak memory | 244884 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1689164690 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_mailbox.1689164690 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/40.spi_device_mailbox/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/40.spi_device_pass_addr_payload_swap.1091010286 |
| Short name | T816 |
| Test name | |
| Test status | |
| Simulation time | 98150948 ps |
| CPU time | 3.33 seconds |
| Started | Sep 01 03:02:54 PM UTC 24 |
| Finished | Sep 01 03:02:58 PM UTC 24 |
| Peak memory | 245196 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1091010286 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_31/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_pass_addr_payload_swap.1091010286 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/40.spi_device_pass_addr_payload_swap/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/40.spi_device_pass_cmd_filtering.3464124684 |
| Short name | T821 |
| Test name | |
| Test status | |
| Simulation time | 2235123777 ps |
| CPU time | 11.27 seconds |
| Started | Sep 01 03:02:54 PM UTC 24 |
| Finished | Sep 01 03:03:07 PM UTC 24 |
| Peak memory | 245336 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3464124684 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_08_31/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_pass_cmd_filtering.3464124684 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/40.spi_device_pass_cmd_filtering/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/40.spi_device_read_buffer_direct.3940924544 |
| Short name | T829 |
| Test name | |
| Test status | |
| Simulation time | 1441622681 ps |
| CPU time | 8.57 seconds |
| Started | Sep 01 03:03:05 PM UTC 24 |
| Finished | Sep 01 03:03:15 PM UTC 24 |
| Peak memory | 233380 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3940924544 -assert nopostproc +UVM_TESTNAME=spi_device _base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_read_buffer_direct.3940924544 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/40.spi_device_read_buffer_direct/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/40.spi_device_tpm_all.3859372884 |
| Short name | T853 |
| Test name | |
| Test status | |
| Simulation time | 26396450737 ps |
| CPU time | 44.96 seconds |
| Started | Sep 01 03:02:51 PM UTC 24 |
| Finished | Sep 01 03:03:37 PM UTC 24 |
| Peak memory | 227596 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3859372884 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_all.3859372884 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/40.spi_device_tpm_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/40.spi_device_tpm_read_hw_reg.2220432634 |
| Short name | T824 |
| Test name | |
| Test status | |
| Simulation time | 3256905490 ps |
| CPU time | 16.98 seconds |
| Started | Sep 01 03:02:50 PM UTC 24 |
| Finished | Sep 01 03:03:09 PM UTC 24 |
| Peak memory | 227676 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2220432634 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_31/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_read_hw_reg.2220432634 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/40.spi_device_tpm_read_hw_reg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/40.spi_device_tpm_rw.841759082 |
| Short name | T814 |
| Test name | |
| Test status | |
| Simulation time | 46742725 ps |
| CPU time | 1.82 seconds |
| Started | Sep 01 03:02:52 PM UTC 24 |
| Finished | Sep 01 03:02:55 PM UTC 24 |
| Peak memory | 216352 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=841759082 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/spi_d evice_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_rw.841759082 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/40.spi_device_tpm_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/40.spi_device_tpm_sts_read.51424650 |
| Short name | T813 |
| Test name | |
| Test status | |
| Simulation time | 73313180 ps |
| CPU time | 1.11 seconds |
| Started | Sep 01 03:02:51 PM UTC 24 |
| Finished | Sep 01 03:02:53 PM UTC 24 |
| Peak memory | 215868 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=51424650 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/ spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_sts_read.51424650 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/40.spi_device_tpm_sts_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/40.spi_device_upload.1807450836 |
| Short name | T819 |
| Test name | |
| Test status | |
| Simulation time | 323948944 ps |
| CPU time | 5.41 seconds |
| Started | Sep 01 03:02:58 PM UTC 24 |
| Finished | Sep 01 03:03:05 PM UTC 24 |
| Peak memory | 245216 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1807450836 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_upload.1807450836 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/40.spi_device_upload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/41.spi_device_alert_test.1462317399 |
| Short name | T841 |
| Test name | |
| Test status | |
| Simulation time | 32750563 ps |
| CPU time | 1.09 seconds |
| Started | Sep 01 03:03:23 PM UTC 24 |
| Finished | Sep 01 03:03:25 PM UTC 24 |
| Peak memory | 215744 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1462317399 -assert nopostproc +UVM_TES TNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_alert_test.1462317399 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/41.spi_device_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/41.spi_device_cfg_cmd.1547537694 |
| Short name | T838 |
| Test name | |
| Test status | |
| Simulation time | 86248533 ps |
| CPU time | 4.09 seconds |
| Started | Sep 01 03:03:18 PM UTC 24 |
| Finished | Sep 01 03:03:23 PM UTC 24 |
| Peak memory | 245216 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1547537694 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_cfg_cmd.1547537694 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/41.spi_device_cfg_cmd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/41.spi_device_csb_read.1464560225 |
| Short name | T827 |
| Test name | |
| Test status | |
| Simulation time | 33142896 ps |
| CPU time | 1.01 seconds |
| Started | Sep 01 03:03:09 PM UTC 24 |
| Finished | Sep 01 03:03:11 PM UTC 24 |
| Peak memory | 215808 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1464560225 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/sp i_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_csb_read.1464560225 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/41.spi_device_csb_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/41.spi_device_flash_all.3952293241 |
| Short name | T859 |
| Test name | |
| Test status | |
| Simulation time | 4490023813 ps |
| CPU time | 19.69 seconds |
| Started | Sep 01 03:03:21 PM UTC 24 |
| Finished | Sep 01 03:03:42 PM UTC 24 |
| Peak memory | 267916 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3952293241 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/s pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_all.3952293241 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/41.spi_device_flash_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/41.spi_device_flash_and_tpm.24266252 |
| Short name | T939 |
| Test name | |
| Test status | |
| Simulation time | 66844609197 ps |
| CPU time | 132.35 seconds |
| Started | Sep 01 03:03:23 PM UTC 24 |
| Finished | Sep 01 03:05:38 PM UTC 24 |
| Peak memory | 249528 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=24266252 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31 /spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_and_tpm.24266252 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/41.spi_device_flash_and_tpm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/41.spi_device_flash_and_tpm_min_idle.422607459 |
| Short name | T1009 |
| Test name | |
| Test status | |
| Simulation time | 734194799241 ps |
| CPU time | 595.6 seconds |
| Started | Sep 01 03:03:23 PM UTC 24 |
| Finished | Sep 01 03:13:27 PM UTC 24 |
| Peak memory | 267928 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=422607459 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_31/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_and_tpm_min_idle.422607459 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/41.spi_device_flash_and_tpm_min_idle/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/41.spi_device_flash_mode.2057359304 |
| Short name | T849 |
| Test name | |
| Test status | |
| Simulation time | 592682142 ps |
| CPU time | 10.39 seconds |
| Started | Sep 01 03:03:18 PM UTC 24 |
| Finished | Sep 01 03:03:29 PM UTC 24 |
| Peak memory | 245208 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2057359304 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/ spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_mode.2057359304 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/41.spi_device_flash_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/41.spi_device_flash_mode_ignore_cmds.2790226101 |
| Short name | T836 |
| Test name | |
| Test status | |
| Simulation time | 21972127 ps |
| CPU time | 1.29 seconds |
| Started | Sep 01 03:03:19 PM UTC 24 |
| Finished | Sep 01 03:03:21 PM UTC 24 |
| Peak memory | 225736 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2790226101 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_31/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_mode_ignore_cmds.2790226101 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/41.spi_device_flash_mode_ignore_cmds/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/41.spi_device_intercept.982304252 |
| Short name | T837 |
| Test name | |
| Test status | |
| Simulation time | 375902033 ps |
| CPU time | 4.48 seconds |
| Started | Sep 01 03:03:16 PM UTC 24 |
| Finished | Sep 01 03:03:22 PM UTC 24 |
| Peak memory | 234896 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=982304252 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/sp i_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_intercept.982304252 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/41.spi_device_intercept/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/41.spi_device_mailbox.51439608 |
| Short name | T890 |
| Test name | |
| Test status | |
| Simulation time | 6890316904 ps |
| CPU time | 55.99 seconds |
| Started | Sep 01 03:03:16 PM UTC 24 |
| Finished | Sep 01 03:04:14 PM UTC 24 |
| Peak memory | 251428 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=51439608 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/spi_d evice_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_mailbox.51439608 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/41.spi_device_mailbox/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/41.spi_device_pass_addr_payload_swap.2298879325 |
| Short name | T845 |
| Test name | |
| Test status | |
| Simulation time | 1123190914 ps |
| CPU time | 12.98 seconds |
| Started | Sep 01 03:03:13 PM UTC 24 |
| Finished | Sep 01 03:03:27 PM UTC 24 |
| Peak memory | 245204 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2298879325 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_31/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_pass_addr_payload_swap.2298879325 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/41.spi_device_pass_addr_payload_swap/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/41.spi_device_pass_cmd_filtering.3968630064 |
| Short name | T844 |
| Test name | |
| Test status | |
| Simulation time | 3076932197 ps |
| CPU time | 12.96 seconds |
| Started | Sep 01 03:03:13 PM UTC 24 |
| Finished | Sep 01 03:03:27 PM UTC 24 |
| Peak memory | 235028 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3968630064 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_08_31/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_pass_cmd_filtering.3968630064 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/41.spi_device_pass_cmd_filtering/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/41.spi_device_read_buffer_direct.2315831942 |
| Short name | T865 |
| Test name | |
| Test status | |
| Simulation time | 1309688027 ps |
| CPU time | 22.47 seconds |
| Started | Sep 01 03:03:21 PM UTC 24 |
| Finished | Sep 01 03:03:45 PM UTC 24 |
| Peak memory | 231256 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2315831942 -assert nopostproc +UVM_TESTNAME=spi_device _base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_read_buffer_direct.2315831942 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/41.spi_device_read_buffer_direct/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/41.spi_device_stress_all.594909236 |
| Short name | T914 |
| Test name | |
| Test status | |
| Simulation time | 3796409645 ps |
| CPU time | 73.41 seconds |
| Started | Sep 01 03:03:23 PM UTC 24 |
| Finished | Sep 01 03:04:38 PM UTC 24 |
| Peak memory | 267920 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=594909236 -assert nopostproc +UVM_T ESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_stress_all.594909236 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/41.spi_device_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/41.spi_device_tpm_all.1804810646 |
| Short name | T842 |
| Test name | |
| Test status | |
| Simulation time | 4070887303 ps |
| CPU time | 13.2 seconds |
| Started | Sep 01 03:03:11 PM UTC 24 |
| Finished | Sep 01 03:03:26 PM UTC 24 |
| Peak memory | 227608 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1804810646 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_all.1804810646 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/41.spi_device_tpm_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/41.spi_device_tpm_read_hw_reg.2526856754 |
| Short name | T828 |
| Test name | |
| Test status | |
| Simulation time | 10732871 ps |
| CPU time | 1.1 seconds |
| Started | Sep 01 03:03:10 PM UTC 24 |
| Finished | Sep 01 03:03:12 PM UTC 24 |
| Peak memory | 215800 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2526856754 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_31/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_read_hw_reg.2526856754 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/41.spi_device_tpm_read_hw_reg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/41.spi_device_tpm_rw.1040686647 |
| Short name | T833 |
| Test name | |
| Test status | |
| Simulation time | 1481738206 ps |
| CPU time | 5.82 seconds |
| Started | Sep 01 03:03:13 PM UTC 24 |
| Finished | Sep 01 03:03:20 PM UTC 24 |
| Peak memory | 227496 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1040686647 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_rw.1040686647 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/41.spi_device_tpm_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/41.spi_device_tpm_sts_read.1657304072 |
| Short name | T830 |
| Test name | |
| Test status | |
| Simulation time | 428634808 ps |
| CPU time | 1.43 seconds |
| Started | Sep 01 03:03:13 PM UTC 24 |
| Finished | Sep 01 03:03:15 PM UTC 24 |
| Peak memory | 215508 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1657304072 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_3 1/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_sts_read.1657304072 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/41.spi_device_tpm_sts_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/41.spi_device_upload.304165008 |
| Short name | T874 |
| Test name | |
| Test status | |
| Simulation time | 49505476418 ps |
| CPU time | 41.6 seconds |
| Started | Sep 01 03:03:18 PM UTC 24 |
| Finished | Sep 01 03:04:01 PM UTC 24 |
| Peak memory | 251368 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=304165008 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/spi_d evice_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_upload.304165008 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/41.spi_device_upload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/42.spi_device_alert_test.923631772 |
| Short name | T856 |
| Test name | |
| Test status | |
| Simulation time | 49146160 ps |
| CPU time | 1.12 seconds |
| Started | Sep 01 03:03:38 PM UTC 24 |
| Finished | Sep 01 03:03:40 PM UTC 24 |
| Peak memory | 215680 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=923631772 -assert nopostproc +UVM_TEST NAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_alert_test.923631772 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/42.spi_device_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/42.spi_device_cfg_cmd.3914755900 |
| Short name | T854 |
| Test name | |
| Test status | |
| Simulation time | 1797934556 ps |
| CPU time | 9.28 seconds |
| Started | Sep 01 03:03:29 PM UTC 24 |
| Finished | Sep 01 03:03:39 PM UTC 24 |
| Peak memory | 245212 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3914755900 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_cfg_cmd.3914755900 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/42.spi_device_cfg_cmd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/42.spi_device_csb_read.319261923 |
| Short name | T843 |
| Test name | |
| Test status | |
| Simulation time | 49974387 ps |
| CPU time | 1.14 seconds |
| Started | Sep 01 03:03:24 PM UTC 24 |
| Finished | Sep 01 03:03:27 PM UTC 24 |
| Peak memory | 215744 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=319261923 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_csb_read.319261923 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/42.spi_device_csb_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/42.spi_device_flash_all.4185389472 |
| Short name | T977 |
| Test name | |
| Test status | |
| Simulation time | 17481173909 ps |
| CPU time | 170 seconds |
| Started | Sep 01 03:03:34 PM UTC 24 |
| Finished | Sep 01 03:06:27 PM UTC 24 |
| Peak memory | 261704 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4185389472 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/s pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_all.4185389472 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/42.spi_device_flash_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/42.spi_device_flash_and_tpm.2029041080 |
| Short name | T1008 |
| Test name | |
| Test status | |
| Simulation time | 382602905542 ps |
| CPU time | 574.97 seconds |
| Started | Sep 01 03:03:34 PM UTC 24 |
| Finished | Sep 01 03:13:17 PM UTC 24 |
| Peak memory | 267904 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2029041080 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_ 31/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_and_tpm.2029041080 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/42.spi_device_flash_and_tpm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/42.spi_device_flash_and_tpm_min_idle.2904669320 |
| Short name | T348 |
| Test name | |
| Test status | |
| Simulation time | 58154999612 ps |
| CPU time | 192.73 seconds |
| Started | Sep 01 03:03:36 PM UTC 24 |
| Finished | Sep 01 03:06:52 PM UTC 24 |
| Peak memory | 265872 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2904669320 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_31/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_and_tpm_min_idle.2904669320 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/42.spi_device_flash_and_tpm_min_idle/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/42.spi_device_flash_mode_ignore_cmds.701030987 |
| Short name | T896 |
| Test name | |
| Test status | |
| Simulation time | 19008821092 ps |
| CPU time | 48.1 seconds |
| Started | Sep 01 03:03:30 PM UTC 24 |
| Finished | Sep 01 03:04:20 PM UTC 24 |
| Peak memory | 251472 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=701030987 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_31/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_mode_ignore_cmds.701030987 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/42.spi_device_flash_mode_ignore_cmds/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/42.spi_device_intercept.41560234 |
| Short name | T832 |
| Test name | |
| Test status | |
| Simulation time | 513335306 ps |
| CPU time | 5.83 seconds |
| Started | Sep 01 03:03:29 PM UTC 24 |
| Finished | Sep 01 03:03:36 PM UTC 24 |
| Peak memory | 244940 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=41560234 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_intercept.41560234 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/42.spi_device_intercept/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/42.spi_device_mailbox.2439906967 |
| Short name | T858 |
| Test name | |
| Test status | |
| Simulation time | 1462740377 ps |
| CPU time | 10.71 seconds |
| Started | Sep 01 03:03:29 PM UTC 24 |
| Finished | Sep 01 03:03:41 PM UTC 24 |
| Peak memory | 234896 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2439906967 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_mailbox.2439906967 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/42.spi_device_mailbox/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/42.spi_device_pass_addr_payload_swap.1952871076 |
| Short name | T850 |
| Test name | |
| Test status | |
| Simulation time | 231374915 ps |
| CPU time | 3.66 seconds |
| Started | Sep 01 03:03:27 PM UTC 24 |
| Finished | Sep 01 03:03:32 PM UTC 24 |
| Peak memory | 234924 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1952871076 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_31/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_pass_addr_payload_swap.1952871076 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/42.spi_device_pass_addr_payload_swap/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/42.spi_device_pass_cmd_filtering.3459938523 |
| Short name | T862 |
| Test name | |
| Test status | |
| Simulation time | 16188016577 ps |
| CPU time | 15.47 seconds |
| Started | Sep 01 03:03:27 PM UTC 24 |
| Finished | Sep 01 03:03:44 PM UTC 24 |
| Peak memory | 245268 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3459938523 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_08_31/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_pass_cmd_filtering.3459938523 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/42.spi_device_pass_cmd_filtering/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/42.spi_device_read_buffer_direct.894121042 |
| Short name | T872 |
| Test name | |
| Test status | |
| Simulation time | 1490931409 ps |
| CPU time | 25.28 seconds |
| Started | Sep 01 03:03:33 PM UTC 24 |
| Finished | Sep 01 03:03:59 PM UTC 24 |
| Peak memory | 233452 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=894121042 -assert nopostproc +UVM_TESTNAME=spi_device_ base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_read_buffer_direct.894121042 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/42.spi_device_read_buffer_direct/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/42.spi_device_stress_all.562377159 |
| Short name | T361 |
| Test name | |
| Test status | |
| Simulation time | 13275160334 ps |
| CPU time | 196.12 seconds |
| Started | Sep 01 03:03:36 PM UTC 24 |
| Finished | Sep 01 03:06:56 PM UTC 24 |
| Peak memory | 282240 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=562377159 -assert nopostproc +UVM_T ESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_stress_all.562377159 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/42.spi_device_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/42.spi_device_tpm_all.3587571011 |
| Short name | T847 |
| Test name | |
| Test status | |
| Simulation time | 883291091 ps |
| CPU time | 2.6 seconds |
| Started | Sep 01 03:03:25 PM UTC 24 |
| Finished | Sep 01 03:03:28 PM UTC 24 |
| Peak memory | 227496 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3587571011 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_all.3587571011 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/42.spi_device_tpm_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/42.spi_device_tpm_read_hw_reg.3331318911 |
| Short name | T848 |
| Test name | |
| Test status | |
| Simulation time | 3133086177 ps |
| CPU time | 3.47 seconds |
| Started | Sep 01 03:03:25 PM UTC 24 |
| Finished | Sep 01 03:03:29 PM UTC 24 |
| Peak memory | 227548 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3331318911 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_31/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_read_hw_reg.3331318911 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/42.spi_device_tpm_read_hw_reg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/42.spi_device_tpm_rw.1417183546 |
| Short name | T851 |
| Test name | |
| Test status | |
| Simulation time | 362740576 ps |
| CPU time | 4.7 seconds |
| Started | Sep 01 03:03:27 PM UTC 24 |
| Finished | Sep 01 03:03:33 PM UTC 24 |
| Peak memory | 227436 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1417183546 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_rw.1417183546 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/42.spi_device_tpm_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/42.spi_device_tpm_sts_read.1105600477 |
| Short name | T846 |
| Test name | |
| Test status | |
| Simulation time | 117963843 ps |
| CPU time | 1.3 seconds |
| Started | Sep 01 03:03:26 PM UTC 24 |
| Finished | Sep 01 03:03:28 PM UTC 24 |
| Peak memory | 215868 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1105600477 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_3 1/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_sts_read.1105600477 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/42.spi_device_tpm_sts_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/43.spi_device_alert_test.3451517552 |
| Short name | T875 |
| Test name | |
| Test status | |
| Simulation time | 39861310 ps |
| CPU time | 1.03 seconds |
| Started | Sep 01 03:03:59 PM UTC 24 |
| Finished | Sep 01 03:04:01 PM UTC 24 |
| Peak memory | 215640 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3451517552 -assert nopostproc +UVM_TES TNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_alert_test.3451517552 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/43.spi_device_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/43.spi_device_cfg_cmd.4160424571 |
| Short name | T867 |
| Test name | |
| Test status | |
| Simulation time | 1477152434 ps |
| CPU time | 6.05 seconds |
| Started | Sep 01 03:03:46 PM UTC 24 |
| Finished | Sep 01 03:03:53 PM UTC 24 |
| Peak memory | 234960 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4160424571 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_cfg_cmd.4160424571 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/43.spi_device_cfg_cmd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/43.spi_device_csb_read.2203329117 |
| Short name | T861 |
| Test name | |
| Test status | |
| Simulation time | 28364487 ps |
| CPU time | 0.99 seconds |
| Started | Sep 01 03:03:41 PM UTC 24 |
| Finished | Sep 01 03:03:43 PM UTC 24 |
| Peak memory | 215616 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2203329117 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/sp i_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_csb_read.2203329117 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/43.spi_device_csb_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/43.spi_device_flash_all.1845372178 |
| Short name | T352 |
| Test name | |
| Test status | |
| Simulation time | 31892626792 ps |
| CPU time | 157.72 seconds |
| Started | Sep 01 03:03:54 PM UTC 24 |
| Finished | Sep 01 03:06:34 PM UTC 24 |
| Peak memory | 263816 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1845372178 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/s pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_all.1845372178 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/43.spi_device_flash_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/43.spi_device_flash_and_tpm.1735551154 |
| Short name | T363 |
| Test name | |
| Test status | |
| Simulation time | 180563854226 ps |
| CPU time | 118.45 seconds |
| Started | Sep 01 03:03:54 PM UTC 24 |
| Finished | Sep 01 03:05:55 PM UTC 24 |
| Peak memory | 261776 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1735551154 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_ 31/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_and_tpm.1735551154 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/43.spi_device_flash_and_tpm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/43.spi_device_flash_and_tpm_min_idle.1229628888 |
| Short name | T881 |
| Test name | |
| Test status | |
| Simulation time | 728004112 ps |
| CPU time | 6.86 seconds |
| Started | Sep 01 03:03:55 PM UTC 24 |
| Finished | Sep 01 03:04:03 PM UTC 24 |
| Peak memory | 229532 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1229628888 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_31/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_and_tpm_min_idle.1229628888 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/43.spi_device_flash_and_tpm_min_idle/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/43.spi_device_flash_mode.2857874718 |
| Short name | T869 |
| Test name | |
| Test status | |
| Simulation time | 212448544 ps |
| CPU time | 5.46 seconds |
| Started | Sep 01 03:03:47 PM UTC 24 |
| Finished | Sep 01 03:03:53 PM UTC 24 |
| Peak memory | 235020 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2857874718 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/ spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_mode.2857874718 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/43.spi_device_flash_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/43.spi_device_flash_mode_ignore_cmds.1084057007 |
| Short name | T1007 |
| Test name | |
| Test status | |
| Simulation time | 98137677594 ps |
| CPU time | 516.31 seconds |
| Started | Sep 01 03:03:49 PM UTC 24 |
| Finished | Sep 01 03:12:33 PM UTC 24 |
| Peak memory | 267856 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1084057007 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_31/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_mode_ignore_cmds.1084057007 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/43.spi_device_flash_mode_ignore_cmds/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/43.spi_device_intercept.888664302 |
| Short name | T866 |
| Test name | |
| Test status | |
| Simulation time | 94033785 ps |
| CPU time | 2.88 seconds |
| Started | Sep 01 03:03:44 PM UTC 24 |
| Finished | Sep 01 03:03:48 PM UTC 24 |
| Peak memory | 233968 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=888664302 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/sp i_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_intercept.888664302 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/43.spi_device_intercept/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/43.spi_device_mailbox.3095266419 |
| Short name | T958 |
| Test name | |
| Test status | |
| Simulation time | 57416967898 ps |
| CPU time | 134.5 seconds |
| Started | Sep 01 03:03:46 PM UTC 24 |
| Finished | Sep 01 03:06:03 PM UTC 24 |
| Peak memory | 251468 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3095266419 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_mailbox.3095266419 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/43.spi_device_mailbox/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/43.spi_device_pass_addr_payload_swap.2661968835 |
| Short name | T320 |
| Test name | |
| Test status | |
| Simulation time | 294642826 ps |
| CPU time | 5.03 seconds |
| Started | Sep 01 03:03:44 PM UTC 24 |
| Finished | Sep 01 03:03:50 PM UTC 24 |
| Peak memory | 234900 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2661968835 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_31/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_pass_addr_payload_swap.2661968835 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/43.spi_device_pass_addr_payload_swap/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/43.spi_device_pass_cmd_filtering.1987659666 |
| Short name | T889 |
| Test name | |
| Test status | |
| Simulation time | 15997598067 ps |
| CPU time | 27.79 seconds |
| Started | Sep 01 03:03:44 PM UTC 24 |
| Finished | Sep 01 03:04:13 PM UTC 24 |
| Peak memory | 245276 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1987659666 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_08_31/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_pass_cmd_filtering.1987659666 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/43.spi_device_pass_cmd_filtering/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/43.spi_device_read_buffer_direct.4084414646 |
| Short name | T879 |
| Test name | |
| Test status | |
| Simulation time | 11875912523 ps |
| CPU time | 10.22 seconds |
| Started | Sep 01 03:03:51 PM UTC 24 |
| Finished | Sep 01 03:04:03 PM UTC 24 |
| Peak memory | 231444 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4084414646 -assert nopostproc +UVM_TESTNAME=spi_device _base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_read_buffer_direct.4084414646 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/43.spi_device_read_buffer_direct/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/43.spi_device_stress_all.514723569 |
| Short name | T877 |
| Test name | |
| Test status | |
| Simulation time | 45191116 ps |
| CPU time | 1.51 seconds |
| Started | Sep 01 03:03:59 PM UTC 24 |
| Finished | Sep 01 03:04:02 PM UTC 24 |
| Peak memory | 215544 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=514723569 -assert nopostproc +UVM_T ESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_stress_all.514723569 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/43.spi_device_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/43.spi_device_tpm_all.736814132 |
| Short name | T878 |
| Test name | |
| Test status | |
| Simulation time | 3738996086 ps |
| CPU time | 19.76 seconds |
| Started | Sep 01 03:03:41 PM UTC 24 |
| Finished | Sep 01 03:04:02 PM UTC 24 |
| Peak memory | 227612 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=736814132 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_all.736814132 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/43.spi_device_tpm_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/43.spi_device_tpm_read_hw_reg.3984150735 |
| Short name | T873 |
| Test name | |
| Test status | |
| Simulation time | 2312912088 ps |
| CPU time | 17.52 seconds |
| Started | Sep 01 03:03:41 PM UTC 24 |
| Finished | Sep 01 03:04:00 PM UTC 24 |
| Peak memory | 227576 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3984150735 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_31/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_read_hw_reg.3984150735 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/43.spi_device_tpm_read_hw_reg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/43.spi_device_tpm_rw.3168752931 |
| Short name | T863 |
| Test name | |
| Test status | |
| Simulation time | 12745939 ps |
| CPU time | 1.12 seconds |
| Started | Sep 01 03:03:43 PM UTC 24 |
| Finished | Sep 01 03:03:45 PM UTC 24 |
| Peak memory | 215864 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3168752931 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_rw.3168752931 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/43.spi_device_tpm_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/43.spi_device_tpm_sts_read.2467730500 |
| Short name | T864 |
| Test name | |
| Test status | |
| Simulation time | 42231005 ps |
| CPU time | 1.18 seconds |
| Started | Sep 01 03:03:43 PM UTC 24 |
| Finished | Sep 01 03:03:45 PM UTC 24 |
| Peak memory | 215868 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2467730500 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_3 1/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_sts_read.2467730500 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/43.spi_device_tpm_sts_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/43.spi_device_upload.3255933095 |
| Short name | T868 |
| Test name | |
| Test status | |
| Simulation time | 329664480 ps |
| CPU time | 6.29 seconds |
| Started | Sep 01 03:03:46 PM UTC 24 |
| Finished | Sep 01 03:03:53 PM UTC 24 |
| Peak memory | 251360 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3255933095 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_upload.3255933095 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/43.spi_device_upload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/44.spi_device_alert_test.3718534428 |
| Short name | T892 |
| Test name | |
| Test status | |
| Simulation time | 14094193 ps |
| CPU time | 1.08 seconds |
| Started | Sep 01 03:04:14 PM UTC 24 |
| Finished | Sep 01 03:04:16 PM UTC 24 |
| Peak memory | 215740 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3718534428 -assert nopostproc +UVM_TES TNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_alert_test.3718534428 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/44.spi_device_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/44.spi_device_cfg_cmd.3725812132 |
| Short name | T886 |
| Test name | |
| Test status | |
| Simulation time | 62764891 ps |
| CPU time | 3.18 seconds |
| Started | Sep 01 03:04:05 PM UTC 24 |
| Finished | Sep 01 03:04:09 PM UTC 24 |
| Peak memory | 234908 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3725812132 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_cfg_cmd.3725812132 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/44.spi_device_cfg_cmd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/44.spi_device_csb_read.1842656205 |
| Short name | T880 |
| Test name | |
| Test status | |
| Simulation time | 42693957 ps |
| CPU time | 1 seconds |
| Started | Sep 01 03:04:01 PM UTC 24 |
| Finished | Sep 01 03:04:03 PM UTC 24 |
| Peak memory | 215808 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1842656205 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/sp i_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_csb_read.1842656205 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/44.spi_device_csb_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/44.spi_device_flash_all.2689396056 |
| Short name | T970 |
| Test name | |
| Test status | |
| Simulation time | 21485576657 ps |
| CPU time | 121.18 seconds |
| Started | Sep 01 03:04:10 PM UTC 24 |
| Finished | Sep 01 03:06:13 PM UTC 24 |
| Peak memory | 267852 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2689396056 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/s pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_all.2689396056 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/44.spi_device_flash_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/44.spi_device_flash_and_tpm.331965835 |
| Short name | T936 |
| Test name | |
| Test status | |
| Simulation time | 8616945818 ps |
| CPU time | 77.35 seconds |
| Started | Sep 01 03:04:10 PM UTC 24 |
| Finished | Sep 01 03:05:29 PM UTC 24 |
| Peak memory | 265796 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=331965835 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_3 1/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_and_tpm.331965835 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/44.spi_device_flash_and_tpm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/44.spi_device_flash_and_tpm_min_idle.4019010419 |
| Short name | T1003 |
| Test name | |
| Test status | |
| Simulation time | 140504750533 ps |
| CPU time | 376.57 seconds |
| Started | Sep 01 03:04:12 PM UTC 24 |
| Finished | Sep 01 03:10:34 PM UTC 24 |
| Peak memory | 261776 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4019010419 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_31/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_and_tpm_min_idle.4019010419 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/44.spi_device_flash_and_tpm_min_idle/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/44.spi_device_flash_mode.4079518428 |
| Short name | T887 |
| Test name | |
| Test status | |
| Simulation time | 84243300 ps |
| CPU time | 3.77 seconds |
| Started | Sep 01 03:04:06 PM UTC 24 |
| Finished | Sep 01 03:04:11 PM UTC 24 |
| Peak memory | 234956 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4079518428 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/ spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_mode.4079518428 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/44.spi_device_flash_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/44.spi_device_flash_mode_ignore_cmds.1748043804 |
| Short name | T885 |
| Test name | |
| Test status | |
| Simulation time | 20470766 ps |
| CPU time | 1.18 seconds |
| Started | Sep 01 03:04:06 PM UTC 24 |
| Finished | Sep 01 03:04:08 PM UTC 24 |
| Peak memory | 215736 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1748043804 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_31/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_mode_ignore_cmds.1748043804 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/44.spi_device_flash_mode_ignore_cmds/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/44.spi_device_intercept.515076352 |
| Short name | T888 |
| Test name | |
| Test status | |
| Simulation time | 548603063 ps |
| CPU time | 7.66 seconds |
| Started | Sep 01 03:04:04 PM UTC 24 |
| Finished | Sep 01 03:04:13 PM UTC 24 |
| Peak memory | 245196 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=515076352 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/sp i_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_intercept.515076352 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/44.spi_device_intercept/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/44.spi_device_mailbox.2787825158 |
| Short name | T907 |
| Test name | |
| Test status | |
| Simulation time | 9259584982 ps |
| CPU time | 25.29 seconds |
| Started | Sep 01 03:04:04 PM UTC 24 |
| Finished | Sep 01 03:04:31 PM UTC 24 |
| Peak memory | 245344 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2787825158 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_mailbox.2787825158 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/44.spi_device_mailbox/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/44.spi_device_pass_addr_payload_swap.2510458943 |
| Short name | T897 |
| Test name | |
| Test status | |
| Simulation time | 10600814081 ps |
| CPU time | 16.39 seconds |
| Started | Sep 01 03:04:03 PM UTC 24 |
| Finished | Sep 01 03:04:20 PM UTC 24 |
| Peak memory | 235156 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2510458943 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_31/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_pass_addr_payload_swap.2510458943 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/44.spi_device_pass_addr_payload_swap/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/44.spi_device_pass_cmd_filtering.993806768 |
| Short name | T917 |
| Test name | |
| Test status | |
| Simulation time | 17144443088 ps |
| CPU time | 42.83 seconds |
| Started | Sep 01 03:04:03 PM UTC 24 |
| Finished | Sep 01 03:04:47 PM UTC 24 |
| Peak memory | 251472 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=993806768 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _08_31/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_pass_cmd_filtering.993806768 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/44.spi_device_pass_cmd_filtering/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/44.spi_device_read_buffer_direct.806965395 |
| Short name | T891 |
| Test name | |
| Test status | |
| Simulation time | 181337500 ps |
| CPU time | 5.92 seconds |
| Started | Sep 01 03:04:08 PM UTC 24 |
| Finished | Sep 01 03:04:15 PM UTC 24 |
| Peak memory | 231328 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=806965395 -assert nopostproc +UVM_TESTNAME=spi_device_ base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_read_buffer_direct.806965395 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/44.spi_device_read_buffer_direct/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/44.spi_device_stress_all.1028937945 |
| Short name | T185 |
| Test name | |
| Test status | |
| Simulation time | 12061286313 ps |
| CPU time | 95.4 seconds |
| Started | Sep 01 03:04:14 PM UTC 24 |
| Finished | Sep 01 03:05:52 PM UTC 24 |
| Peak memory | 267976 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1028937945 -assert nopostproc +UVM_ TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_stress_all.1028937945 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/44.spi_device_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/44.spi_device_tpm_all.108619323 |
| Short name | T882 |
| Test name | |
| Test status | |
| Simulation time | 53441018 ps |
| CPU time | 1.1 seconds |
| Started | Sep 01 03:04:03 PM UTC 24 |
| Finished | Sep 01 03:04:05 PM UTC 24 |
| Peak memory | 215744 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=108619323 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_all.108619323 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/44.spi_device_tpm_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/44.spi_device_tpm_read_hw_reg.2609742967 |
| Short name | T900 |
| Test name | |
| Test status | |
| Simulation time | 5320917424 ps |
| CPU time | 21.1 seconds |
| Started | Sep 01 03:04:01 PM UTC 24 |
| Finished | Sep 01 03:04:23 PM UTC 24 |
| Peak memory | 227676 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2609742967 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_31/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_read_hw_reg.2609742967 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/44.spi_device_tpm_read_hw_reg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/44.spi_device_tpm_rw.2080129154 |
| Short name | T884 |
| Test name | |
| Test status | |
| Simulation time | 58314222 ps |
| CPU time | 3.9 seconds |
| Started | Sep 01 03:04:03 PM UTC 24 |
| Finished | Sep 01 03:04:08 PM UTC 24 |
| Peak memory | 227492 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2080129154 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_rw.2080129154 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/44.spi_device_tpm_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/44.spi_device_tpm_sts_read.1869368300 |
| Short name | T883 |
| Test name | |
| Test status | |
| Simulation time | 179344512 ps |
| CPU time | 1.2 seconds |
| Started | Sep 01 03:04:03 PM UTC 24 |
| Finished | Sep 01 03:04:05 PM UTC 24 |
| Peak memory | 215868 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1869368300 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_3 1/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_sts_read.1869368300 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/44.spi_device_tpm_sts_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/44.spi_device_upload.3372986694 |
| Short name | T903 |
| Test name | |
| Test status | |
| Simulation time | 1091354807 ps |
| CPU time | 22.97 seconds |
| Started | Sep 01 03:04:05 PM UTC 24 |
| Finished | Sep 01 03:04:29 PM UTC 24 |
| Peak memory | 261732 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3372986694 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_upload.3372986694 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/44.spi_device_upload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/45.spi_device_alert_test.2735805809 |
| Short name | T910 |
| Test name | |
| Test status | |
| Simulation time | 40866136 ps |
| CPU time | 1.12 seconds |
| Started | Sep 01 03:04:32 PM UTC 24 |
| Finished | Sep 01 03:04:35 PM UTC 24 |
| Peak memory | 215680 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2735805809 -assert nopostproc +UVM_TES TNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_alert_test.2735805809 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/45.spi_device_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/45.spi_device_cfg_cmd.3248839152 |
| Short name | T908 |
| Test name | |
| Test status | |
| Simulation time | 3100477086 ps |
| CPU time | 10.58 seconds |
| Started | Sep 01 03:04:22 PM UTC 24 |
| Finished | Sep 01 03:04:34 PM UTC 24 |
| Peak memory | 245264 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3248839152 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_cfg_cmd.3248839152 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/45.spi_device_cfg_cmd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/45.spi_device_csb_read.540387417 |
| Short name | T893 |
| Test name | |
| Test status | |
| Simulation time | 14826043 ps |
| CPU time | 1.15 seconds |
| Started | Sep 01 03:04:16 PM UTC 24 |
| Finished | Sep 01 03:04:18 PM UTC 24 |
| Peak memory | 215804 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=540387417 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_csb_read.540387417 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/45.spi_device_csb_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/45.spi_device_flash_all.2311236008 |
| Short name | T949 |
| Test name | |
| Test status | |
| Simulation time | 7784688392 ps |
| CPU time | 81.45 seconds |
| Started | Sep 01 03:04:29 PM UTC 24 |
| Finished | Sep 01 03:05:53 PM UTC 24 |
| Peak memory | 267912 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2311236008 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/s pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_all.2311236008 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/45.spi_device_flash_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/45.spi_device_flash_and_tpm.3375535803 |
| Short name | T994 |
| Test name | |
| Test status | |
| Simulation time | 93145228752 ps |
| CPU time | 252.21 seconds |
| Started | Sep 01 03:04:31 PM UTC 24 |
| Finished | Sep 01 03:08:47 PM UTC 24 |
| Peak memory | 261364 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3375535803 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_ 31/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_and_tpm.3375535803 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/45.spi_device_flash_and_tpm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/45.spi_device_flash_and_tpm_min_idle.4096184602 |
| Short name | T219 |
| Test name | |
| Test status | |
| Simulation time | 17530892335 ps |
| CPU time | 265.09 seconds |
| Started | Sep 01 03:04:31 PM UTC 24 |
| Finished | Sep 01 03:09:01 PM UTC 24 |
| Peak memory | 277784 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4096184602 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_31/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_and_tpm_min_idle.4096184602 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/45.spi_device_flash_and_tpm_min_idle/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/45.spi_device_flash_mode.1365284502 |
| Short name | T905 |
| Test name | |
| Test status | |
| Simulation time | 111167565 ps |
| CPU time | 3.05 seconds |
| Started | Sep 01 03:04:25 PM UTC 24 |
| Finished | Sep 01 03:04:29 PM UTC 24 |
| Peak memory | 234896 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1365284502 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/ spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_mode.1365284502 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/45.spi_device_flash_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/45.spi_device_flash_mode_ignore_cmds.1886294980 |
| Short name | T1002 |
| Test name | |
| Test status | |
| Simulation time | 124657925988 ps |
| CPU time | 333.13 seconds |
| Started | Sep 01 03:04:25 PM UTC 24 |
| Finished | Sep 01 03:10:03 PM UTC 24 |
| Peak memory | 267848 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1886294980 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_31/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_mode_ignore_cmds.1886294980 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/45.spi_device_flash_mode_ignore_cmds/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/45.spi_device_intercept.3408659331 |
| Short name | T906 |
| Test name | |
| Test status | |
| Simulation time | 2364114152 ps |
| CPU time | 8.7 seconds |
| Started | Sep 01 03:04:21 PM UTC 24 |
| Finished | Sep 01 03:04:31 PM UTC 24 |
| Peak memory | 235020 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3408659331 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/s pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_intercept.3408659331 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/45.spi_device_intercept/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/45.spi_device_mailbox.2705138854 |
| Short name | T966 |
| Test name | |
| Test status | |
| Simulation time | 12411831463 ps |
| CPU time | 108.3 seconds |
| Started | Sep 01 03:04:21 PM UTC 24 |
| Finished | Sep 01 03:06:12 PM UTC 24 |
| Peak memory | 245324 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2705138854 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_mailbox.2705138854 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/45.spi_device_mailbox/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/45.spi_device_pass_addr_payload_swap.3874597690 |
| Short name | T901 |
| Test name | |
| Test status | |
| Simulation time | 873147834 ps |
| CPU time | 3.39 seconds |
| Started | Sep 01 03:04:20 PM UTC 24 |
| Finished | Sep 01 03:04:24 PM UTC 24 |
| Peak memory | 245196 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3874597690 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_31/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_pass_addr_payload_swap.3874597690 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/45.spi_device_pass_addr_payload_swap/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/45.spi_device_pass_cmd_filtering.2350546360 |
| Short name | T902 |
| Test name | |
| Test status | |
| Simulation time | 224922285 ps |
| CPU time | 5.85 seconds |
| Started | Sep 01 03:04:20 PM UTC 24 |
| Finished | Sep 01 03:04:26 PM UTC 24 |
| Peak memory | 251360 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2350546360 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_08_31/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_pass_cmd_filtering.2350546360 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/45.spi_device_pass_cmd_filtering/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/45.spi_device_read_buffer_direct.1818003441 |
| Short name | T909 |
| Test name | |
| Test status | |
| Simulation time | 177332537 ps |
| CPU time | 6.54 seconds |
| Started | Sep 01 03:04:27 PM UTC 24 |
| Finished | Sep 01 03:04:35 PM UTC 24 |
| Peak memory | 233524 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1818003441 -assert nopostproc +UVM_TESTNAME=spi_device _base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_read_buffer_direct.1818003441 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/45.spi_device_read_buffer_direct/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/45.spi_device_stress_all.1459719588 |
| Short name | T911 |
| Test name | |
| Test status | |
| Simulation time | 61118483 ps |
| CPU time | 1.72 seconds |
| Started | Sep 01 03:04:32 PM UTC 24 |
| Finished | Sep 01 03:04:35 PM UTC 24 |
| Peak memory | 215736 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1459719588 -assert nopostproc +UVM_ TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_stress_all.1459719588 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/45.spi_device_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/45.spi_device_tpm_all.3325377793 |
| Short name | T895 |
| Test name | |
| Test status | |
| Simulation time | 34193850 ps |
| CPU time | 1.09 seconds |
| Started | Sep 01 03:04:17 PM UTC 24 |
| Finished | Sep 01 03:04:19 PM UTC 24 |
| Peak memory | 215684 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3325377793 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_all.3325377793 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/45.spi_device_tpm_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/45.spi_device_tpm_read_hw_reg.1385443938 |
| Short name | T894 |
| Test name | |
| Test status | |
| Simulation time | 45442563 ps |
| CPU time | 1.1 seconds |
| Started | Sep 01 03:04:16 PM UTC 24 |
| Finished | Sep 01 03:04:18 PM UTC 24 |
| Peak memory | 215800 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1385443938 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_31/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_read_hw_reg.1385443938 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/45.spi_device_tpm_read_hw_reg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/45.spi_device_tpm_rw.3721462410 |
| Short name | T899 |
| Test name | |
| Test status | |
| Simulation time | 17986849 ps |
| CPU time | 1.08 seconds |
| Started | Sep 01 03:04:19 PM UTC 24 |
| Finished | Sep 01 03:04:22 PM UTC 24 |
| Peak memory | 215740 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3721462410 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_rw.3721462410 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/45.spi_device_tpm_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/45.spi_device_tpm_sts_read.2848600456 |
| Short name | T898 |
| Test name | |
| Test status | |
| Simulation time | 29749187 ps |
| CPU time | 1.1 seconds |
| Started | Sep 01 03:04:19 PM UTC 24 |
| Finished | Sep 01 03:04:21 PM UTC 24 |
| Peak memory | 215868 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2848600456 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_3 1/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_sts_read.2848600456 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/45.spi_device_tpm_sts_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/45.spi_device_upload.1644450938 |
| Short name | T921 |
| Test name | |
| Test status | |
| Simulation time | 4532402888 ps |
| CPU time | 28.32 seconds |
| Started | Sep 01 03:04:22 PM UTC 24 |
| Finished | Sep 01 03:04:52 PM UTC 24 |
| Peak memory | 235024 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1644450938 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_upload.1644450938 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/45.spi_device_upload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/46.spi_device_alert_test.2876338347 |
| Short name | T925 |
| Test name | |
| Test status | |
| Simulation time | 51314187 ps |
| CPU time | 1.15 seconds |
| Started | Sep 01 03:05:02 PM UTC 24 |
| Finished | Sep 01 03:05:04 PM UTC 24 |
| Peak memory | 215680 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2876338347 -assert nopostproc +UVM_TES TNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_alert_test.2876338347 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/46.spi_device_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/46.spi_device_cfg_cmd.3609456661 |
| Short name | T922 |
| Test name | |
| Test status | |
| Simulation time | 3392133555 ps |
| CPU time | 9.42 seconds |
| Started | Sep 01 03:04:48 PM UTC 24 |
| Finished | Sep 01 03:04:59 PM UTC 24 |
| Peak memory | 245240 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3609456661 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_cfg_cmd.3609456661 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/46.spi_device_cfg_cmd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/46.spi_device_csb_read.731861420 |
| Short name | T912 |
| Test name | |
| Test status | |
| Simulation time | 60715344 ps |
| CPU time | 1.14 seconds |
| Started | Sep 01 03:04:35 PM UTC 24 |
| Finished | Sep 01 03:04:38 PM UTC 24 |
| Peak memory | 215808 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=731861420 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_csb_read.731861420 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/46.spi_device_csb_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/46.spi_device_flash_all.4224672195 |
| Short name | T354 |
| Test name | |
| Test status | |
| Simulation time | 46945083170 ps |
| CPU time | 276.03 seconds |
| Started | Sep 01 03:04:53 PM UTC 24 |
| Finished | Sep 01 03:09:33 PM UTC 24 |
| Peak memory | 261708 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4224672195 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/s pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_all.4224672195 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/46.spi_device_flash_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/46.spi_device_flash_and_tpm.1902212518 |
| Short name | T972 |
| Test name | |
| Test status | |
| Simulation time | 4118326076 ps |
| CPU time | 82.56 seconds |
| Started | Sep 01 03:04:56 PM UTC 24 |
| Finished | Sep 01 03:06:21 PM UTC 24 |
| Peak memory | 265856 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1902212518 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_ 31/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_and_tpm.1902212518 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/46.spi_device_flash_and_tpm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/46.spi_device_flash_and_tpm_min_idle.3137035596 |
| Short name | T981 |
| Test name | |
| Test status | |
| Simulation time | 17336573086 ps |
| CPU time | 94.7 seconds |
| Started | Sep 01 03:04:56 PM UTC 24 |
| Finished | Sep 01 03:06:33 PM UTC 24 |
| Peak memory | 251528 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3137035596 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_31/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_and_tpm_min_idle.3137035596 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/46.spi_device_flash_and_tpm_min_idle/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/46.spi_device_flash_mode.1270340659 |
| Short name | T947 |
| Test name | |
| Test status | |
| Simulation time | 3022651031 ps |
| CPU time | 60.32 seconds |
| Started | Sep 01 03:04:49 PM UTC 24 |
| Finished | Sep 01 03:05:52 PM UTC 24 |
| Peak memory | 261712 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1270340659 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/ spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_mode.1270340659 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/46.spi_device_flash_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/46.spi_device_flash_mode_ignore_cmds.3706735117 |
| Short name | T940 |
| Test name | |
| Test status | |
| Simulation time | 3042217656 ps |
| CPU time | 48.47 seconds |
| Started | Sep 01 03:04:51 PM UTC 24 |
| Finished | Sep 01 03:05:41 PM UTC 24 |
| Peak memory | 235212 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3706735117 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_31/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_mode_ignore_cmds.3706735117 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/46.spi_device_flash_mode_ignore_cmds/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/46.spi_device_intercept.1815149411 |
| Short name | T920 |
| Test name | |
| Test status | |
| Simulation time | 290548431 ps |
| CPU time | 9.54 seconds |
| Started | Sep 01 03:04:41 PM UTC 24 |
| Finished | Sep 01 03:04:51 PM UTC 24 |
| Peak memory | 245188 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1815149411 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/s pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_intercept.1815149411 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/46.spi_device_intercept/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/46.spi_device_mailbox.2625758155 |
| Short name | T923 |
| Test name | |
| Test status | |
| Simulation time | 1564753220 ps |
| CPU time | 16.68 seconds |
| Started | Sep 01 03:04:43 PM UTC 24 |
| Finished | Sep 01 03:05:01 PM UTC 24 |
| Peak memory | 245156 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2625758155 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_mailbox.2625758155 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/46.spi_device_mailbox/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/46.spi_device_pass_addr_payload_swap.2421992892 |
| Short name | T918 |
| Test name | |
| Test status | |
| Simulation time | 3393174595 ps |
| CPU time | 6.64 seconds |
| Started | Sep 01 03:04:39 PM UTC 24 |
| Finished | Sep 01 03:04:47 PM UTC 24 |
| Peak memory | 234956 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2421992892 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_31/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_pass_addr_payload_swap.2421992892 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/46.spi_device_pass_addr_payload_swap/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/46.spi_device_pass_cmd_filtering.18676032 |
| Short name | T926 |
| Test name | |
| Test status | |
| Simulation time | 3557346811 ps |
| CPU time | 26.09 seconds |
| Started | Sep 01 03:04:39 PM UTC 24 |
| Finished | Sep 01 03:05:07 PM UTC 24 |
| Peak memory | 261716 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=18676032 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_31/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_pass_cmd_filtering.18676032 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/46.spi_device_pass_cmd_filtering/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/46.spi_device_read_buffer_direct.1062394651 |
| Short name | T930 |
| Test name | |
| Test status | |
| Simulation time | 1131542091 ps |
| CPU time | 20.09 seconds |
| Started | Sep 01 03:04:52 PM UTC 24 |
| Finished | Sep 01 03:05:13 PM UTC 24 |
| Peak memory | 233356 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1062394651 -assert nopostproc +UVM_TESTNAME=spi_device _base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_read_buffer_direct.1062394651 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/46.spi_device_read_buffer_direct/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/46.spi_device_stress_all.554010953 |
| Short name | T997 |
| Test name | |
| Test status | |
| Simulation time | 21888800510 ps |
| CPU time | 246.47 seconds |
| Started | Sep 01 03:05:00 PM UTC 24 |
| Finished | Sep 01 03:09:10 PM UTC 24 |
| Peak memory | 261788 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=554010953 -assert nopostproc +UVM_T ESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_stress_all.554010953 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/46.spi_device_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/46.spi_device_tpm_all.4266787908 |
| Short name | T941 |
| Test name | |
| Test status | |
| Simulation time | 18406834787 ps |
| CPU time | 64.24 seconds |
| Started | Sep 01 03:04:36 PM UTC 24 |
| Finished | Sep 01 03:05:42 PM UTC 24 |
| Peak memory | 227608 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4266787908 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_all.4266787908 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/46.spi_device_tpm_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/46.spi_device_tpm_read_hw_reg.4194339598 |
| Short name | T913 |
| Test name | |
| Test status | |
| Simulation time | 37925516 ps |
| CPU time | 1.07 seconds |
| Started | Sep 01 03:04:35 PM UTC 24 |
| Finished | Sep 01 03:04:38 PM UTC 24 |
| Peak memory | 215800 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4194339598 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_31/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_read_hw_reg.4194339598 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/46.spi_device_tpm_read_hw_reg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/46.spi_device_tpm_rw.1838236035 |
| Short name | T916 |
| Test name | |
| Test status | |
| Simulation time | 95671507 ps |
| CPU time | 1.83 seconds |
| Started | Sep 01 03:04:39 PM UTC 24 |
| Finished | Sep 01 03:04:42 PM UTC 24 |
| Peak memory | 216508 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1838236035 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_rw.1838236035 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/46.spi_device_tpm_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/46.spi_device_tpm_sts_read.2562932203 |
| Short name | T915 |
| Test name | |
| Test status | |
| Simulation time | 45169853 ps |
| CPU time | 1.32 seconds |
| Started | Sep 01 03:04:37 PM UTC 24 |
| Finished | Sep 01 03:04:39 PM UTC 24 |
| Peak memory | 215868 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2562932203 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_3 1/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_sts_read.2562932203 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/46.spi_device_tpm_sts_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/46.spi_device_upload.1843833558 |
| Short name | T933 |
| Test name | |
| Test status | |
| Simulation time | 6015598582 ps |
| CPU time | 29.41 seconds |
| Started | Sep 01 03:04:48 PM UTC 24 |
| Finished | Sep 01 03:05:19 PM UTC 24 |
| Peak memory | 261748 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1843833558 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_upload.1843833558 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/46.spi_device_upload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/47.spi_device_alert_test.2698530030 |
| Short name | T942 |
| Test name | |
| Test status | |
| Simulation time | 38023981 ps |
| CPU time | 1.07 seconds |
| Started | Sep 01 03:05:40 PM UTC 24 |
| Finished | Sep 01 03:05:42 PM UTC 24 |
| Peak memory | 215680 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2698530030 -assert nopostproc +UVM_TES TNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_alert_test.2698530030 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/47.spi_device_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/47.spi_device_cfg_cmd.3776792791 |
| Short name | T218 |
| Test name | |
| Test status | |
| Simulation time | 650629654 ps |
| CPU time | 11.87 seconds |
| Started | Sep 01 03:05:20 PM UTC 24 |
| Finished | Sep 01 03:05:33 PM UTC 24 |
| Peak memory | 245212 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3776792791 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_cfg_cmd.3776792791 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/47.spi_device_cfg_cmd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/47.spi_device_csb_read.3993969976 |
| Short name | T927 |
| Test name | |
| Test status | |
| Simulation time | 38641966 ps |
| CPU time | 1.2 seconds |
| Started | Sep 01 03:05:05 PM UTC 24 |
| Finished | Sep 01 03:05:07 PM UTC 24 |
| Peak memory | 215804 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3993969976 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/sp i_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_csb_read.3993969976 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/47.spi_device_csb_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/47.spi_device_flash_all.210789387 |
| Short name | T229 |
| Test name | |
| Test status | |
| Simulation time | 70360202935 ps |
| CPU time | 57.96 seconds |
| Started | Sep 01 03:05:31 PM UTC 24 |
| Finished | Sep 01 03:06:31 PM UTC 24 |
| Peak memory | 261704 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=210789387 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/sp i_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_all.210789387 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/47.spi_device_flash_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/47.spi_device_flash_and_tpm.142989008 |
| Short name | T993 |
| Test name | |
| Test status | |
| Simulation time | 13130823395 ps |
| CPU time | 188.1 seconds |
| Started | Sep 01 03:05:35 PM UTC 24 |
| Finished | Sep 01 03:08:46 PM UTC 24 |
| Peak memory | 261764 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=142989008 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_3 1/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_and_tpm.142989008 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/47.spi_device_flash_and_tpm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/47.spi_device_flash_and_tpm_min_idle.1143063257 |
| Short name | T967 |
| Test name | |
| Test status | |
| Simulation time | 6646084815 ps |
| CPU time | 32.43 seconds |
| Started | Sep 01 03:05:38 PM UTC 24 |
| Finished | Sep 01 03:06:12 PM UTC 24 |
| Peak memory | 235144 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1143063257 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_31/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_and_tpm_min_idle.1143063257 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/47.spi_device_flash_and_tpm_min_idle/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/47.spi_device_flash_mode.4127294251 |
| Short name | T946 |
| Test name | |
| Test status | |
| Simulation time | 1084362434 ps |
| CPU time | 27.5 seconds |
| Started | Sep 01 03:05:22 PM UTC 24 |
| Finished | Sep 01 03:05:50 PM UTC 24 |
| Peak memory | 234896 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4127294251 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/ spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_mode.4127294251 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/47.spi_device_flash_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/47.spi_device_flash_mode_ignore_cmds.3266579145 |
| Short name | T952 |
| Test name | |
| Test status | |
| Simulation time | 2937481886 ps |
| CPU time | 30.99 seconds |
| Started | Sep 01 03:05:25 PM UTC 24 |
| Finished | Sep 01 03:05:57 PM UTC 24 |
| Peak memory | 261720 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3266579145 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_31/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_mode_ignore_cmds.3266579145 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/47.spi_device_flash_mode_ignore_cmds/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/47.spi_device_intercept.872216649 |
| Short name | T935 |
| Test name | |
| Test status | |
| Simulation time | 523181309 ps |
| CPU time | 7.15 seconds |
| Started | Sep 01 03:05:16 PM UTC 24 |
| Finished | Sep 01 03:05:24 PM UTC 24 |
| Peak memory | 241820 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=872216649 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/sp i_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_intercept.872216649 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/47.spi_device_intercept/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/47.spi_device_mailbox.423383983 |
| Short name | T989 |
| Test name | |
| Test status | |
| Simulation time | 112507936473 ps |
| CPU time | 147.71 seconds |
| Started | Sep 01 03:05:16 PM UTC 24 |
| Finished | Sep 01 03:07:46 PM UTC 24 |
| Peak memory | 245324 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=423383983 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_mailbox.423383983 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/47.spi_device_mailbox/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/47.spi_device_pass_addr_payload_swap.934907282 |
| Short name | T934 |
| Test name | |
| Test status | |
| Simulation time | 1470525221 ps |
| CPU time | 5.57 seconds |
| Started | Sep 01 03:05:14 PM UTC 24 |
| Finished | Sep 01 03:05:21 PM UTC 24 |
| Peak memory | 235032 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=934907282 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_31/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_pass_addr_payload_swap.934907282 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/47.spi_device_pass_addr_payload_swap/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/47.spi_device_pass_cmd_filtering.3535203816 |
| Short name | T932 |
| Test name | |
| Test status | |
| Simulation time | 112086935 ps |
| CPU time | 3.49 seconds |
| Started | Sep 01 03:05:13 PM UTC 24 |
| Finished | Sep 01 03:05:18 PM UTC 24 |
| Peak memory | 245200 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3535203816 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_08_31/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_pass_cmd_filtering.3535203816 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/47.spi_device_pass_cmd_filtering/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/47.spi_device_read_buffer_direct.1998760929 |
| Short name | T938 |
| Test name | |
| Test status | |
| Simulation time | 680318657 ps |
| CPU time | 5.26 seconds |
| Started | Sep 01 03:05:30 PM UTC 24 |
| Finished | Sep 01 03:05:36 PM UTC 24 |
| Peak memory | 233492 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1998760929 -assert nopostproc +UVM_TESTNAME=spi_device _base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_read_buffer_direct.1998760929 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/47.spi_device_read_buffer_direct/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/47.spi_device_stress_all.69777338 |
| Short name | T1011 |
| Test name | |
| Test status | |
| Simulation time | 224091255392 ps |
| CPU time | 877.7 seconds |
| Started | Sep 01 03:05:39 PM UTC 24 |
| Finished | Sep 01 03:20:28 PM UTC 24 |
| Peak memory | 298640 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=69777338 -assert nopostproc +UVM_TE STNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_stress_all.69777338 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/47.spi_device_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/47.spi_device_tpm_all.2324421296 |
| Short name | T965 |
| Test name | |
| Test status | |
| Simulation time | 113060893820 ps |
| CPU time | 62.37 seconds |
| Started | Sep 01 03:05:07 PM UTC 24 |
| Finished | Sep 01 03:06:11 PM UTC 24 |
| Peak memory | 227580 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2324421296 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_all.2324421296 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/47.spi_device_tpm_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/47.spi_device_tpm_read_hw_reg.615086384 |
| Short name | T929 |
| Test name | |
| Test status | |
| Simulation time | 818705849 ps |
| CPU time | 5.39 seconds |
| Started | Sep 01 03:05:05 PM UTC 24 |
| Finished | Sep 01 03:05:12 PM UTC 24 |
| Peak memory | 227424 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=615086384 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08 _31/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_read_hw_reg.615086384 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/47.spi_device_tpm_read_hw_reg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/47.spi_device_tpm_rw.362153974 |
| Short name | T931 |
| Test name | |
| Test status | |
| Simulation time | 83661245 ps |
| CPU time | 2.12 seconds |
| Started | Sep 01 03:05:12 PM UTC 24 |
| Finished | Sep 01 03:05:15 PM UTC 24 |
| Peak memory | 227480 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=362153974 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/spi_d evice_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_rw.362153974 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/47.spi_device_tpm_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/47.spi_device_tpm_sts_read.3604647938 |
| Short name | T928 |
| Test name | |
| Test status | |
| Simulation time | 48980987 ps |
| CPU time | 1.32 seconds |
| Started | Sep 01 03:05:09 PM UTC 24 |
| Finished | Sep 01 03:05:11 PM UTC 24 |
| Peak memory | 215868 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3604647938 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_3 1/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_sts_read.3604647938 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/47.spi_device_tpm_sts_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/47.spi_device_upload.2191935474 |
| Short name | T937 |
| Test name | |
| Test status | |
| Simulation time | 435351369 ps |
| CPU time | 9.85 seconds |
| Started | Sep 01 03:05:19 PM UTC 24 |
| Finished | Sep 01 03:05:30 PM UTC 24 |
| Peak memory | 234976 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2191935474 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_upload.2191935474 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/47.spi_device_upload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/48.spi_device_alert_test.1669841157 |
| Short name | T957 |
| Test name | |
| Test status | |
| Simulation time | 172788544 ps |
| CPU time | 1.08 seconds |
| Started | Sep 01 03:06:00 PM UTC 24 |
| Finished | Sep 01 03:06:02 PM UTC 24 |
| Peak memory | 215740 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1669841157 -assert nopostproc +UVM_TES TNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_alert_test.1669841157 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/48.spi_device_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/48.spi_device_cfg_cmd.3081801829 |
| Short name | T956 |
| Test name | |
| Test status | |
| Simulation time | 198980755 ps |
| CPU time | 5.9 seconds |
| Started | Sep 01 03:05:54 PM UTC 24 |
| Finished | Sep 01 03:06:01 PM UTC 24 |
| Peak memory | 245196 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3081801829 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_cfg_cmd.3081801829 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/48.spi_device_cfg_cmd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/48.spi_device_csb_read.3042793928 |
| Short name | T943 |
| Test name | |
| Test status | |
| Simulation time | 92028521 ps |
| CPU time | 1.14 seconds |
| Started | Sep 01 03:05:42 PM UTC 24 |
| Finished | Sep 01 03:05:44 PM UTC 24 |
| Peak memory | 215808 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3042793928 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/sp i_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_csb_read.3042793928 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/48.spi_device_csb_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/48.spi_device_flash_and_tpm.2046168925 |
| Short name | T984 |
| Test name | |
| Test status | |
| Simulation time | 8318064941 ps |
| CPU time | 92.95 seconds |
| Started | Sep 01 03:05:58 PM UTC 24 |
| Finished | Sep 01 03:07:34 PM UTC 24 |
| Peak memory | 261704 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2046168925 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_ 31/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_and_tpm.2046168925 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/48.spi_device_flash_and_tpm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/48.spi_device_flash_and_tpm_min_idle.343421601 |
| Short name | T990 |
| Test name | |
| Test status | |
| Simulation time | 95818103404 ps |
| CPU time | 127.81 seconds |
| Started | Sep 01 03:05:58 PM UTC 24 |
| Finished | Sep 01 03:08:09 PM UTC 24 |
| Peak memory | 263880 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=343421601 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_31/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_and_tpm_min_idle.343421601 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/48.spi_device_flash_and_tpm_min_idle/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/48.spi_device_flash_mode.2694568163 |
| Short name | T955 |
| Test name | |
| Test status | |
| Simulation time | 79644943 ps |
| CPU time | 4.81 seconds |
| Started | Sep 01 03:05:54 PM UTC 24 |
| Finished | Sep 01 03:06:00 PM UTC 24 |
| Peak memory | 245344 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2694568163 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/ spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_mode.2694568163 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/48.spi_device_flash_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/48.spi_device_flash_mode_ignore_cmds.2398435824 |
| Short name | T992 |
| Test name | |
| Test status | |
| Simulation time | 50155328219 ps |
| CPU time | 136.17 seconds |
| Started | Sep 01 03:05:55 PM UTC 24 |
| Finished | Sep 01 03:08:14 PM UTC 24 |
| Peak memory | 263756 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2398435824 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_31/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_mode_ignore_cmds.2398435824 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/48.spi_device_flash_mode_ignore_cmds/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/48.spi_device_intercept.2328596738 |
| Short name | T950 |
| Test name | |
| Test status | |
| Simulation time | 43871953 ps |
| CPU time | 3.71 seconds |
| Started | Sep 01 03:05:51 PM UTC 24 |
| Finished | Sep 01 03:05:56 PM UTC 24 |
| Peak memory | 245188 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2328596738 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/s pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_intercept.2328596738 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/48.spi_device_intercept/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/48.spi_device_mailbox.1796585154 |
| Short name | T951 |
| Test name | |
| Test status | |
| Simulation time | 156601739 ps |
| CPU time | 3.41 seconds |
| Started | Sep 01 03:05:53 PM UTC 24 |
| Finished | Sep 01 03:05:57 PM UTC 24 |
| Peak memory | 245196 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1796585154 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_mailbox.1796585154 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/48.spi_device_mailbox/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/48.spi_device_pass_addr_payload_swap.110293355 |
| Short name | T948 |
| Test name | |
| Test status | |
| Simulation time | 106387035 ps |
| CPU time | 3.22 seconds |
| Started | Sep 01 03:05:48 PM UTC 24 |
| Finished | Sep 01 03:05:52 PM UTC 24 |
| Peak memory | 234860 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=110293355 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_31/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_pass_addr_payload_swap.110293355 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/48.spi_device_pass_addr_payload_swap/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/48.spi_device_pass_cmd_filtering.2957422778 |
| Short name | T222 |
| Test name | |
| Test status | |
| Simulation time | 29240366796 ps |
| CPU time | 40.15 seconds |
| Started | Sep 01 03:05:47 PM UTC 24 |
| Finished | Sep 01 03:06:28 PM UTC 24 |
| Peak memory | 245380 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2957422778 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_08_31/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_pass_cmd_filtering.2957422778 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/48.spi_device_pass_cmd_filtering/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/48.spi_device_read_buffer_direct.3373419412 |
| Short name | T964 |
| Test name | |
| Test status | |
| Simulation time | 2580639042 ps |
| CPU time | 12.23 seconds |
| Started | Sep 01 03:05:57 PM UTC 24 |
| Finished | Sep 01 03:06:10 PM UTC 24 |
| Peak memory | 232844 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3373419412 -assert nopostproc +UVM_TESTNAME=spi_device _base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_read_buffer_direct.3373419412 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/48.spi_device_read_buffer_direct/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/48.spi_device_stress_all.2956608925 |
| Short name | T1006 |
| Test name | |
| Test status | |
| Simulation time | 175871370551 ps |
| CPU time | 324.5 seconds |
| Started | Sep 01 03:06:00 PM UTC 24 |
| Finished | Sep 01 03:11:29 PM UTC 24 |
| Peak memory | 261764 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2956608925 -assert nopostproc +UVM_ TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_stress_all.2956608925 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/48.spi_device_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/48.spi_device_tpm_all.1941120042 |
| Short name | T961 |
| Test name | |
| Test status | |
| Simulation time | 2824152112 ps |
| CPU time | 20.73 seconds |
| Started | Sep 01 03:05:43 PM UTC 24 |
| Finished | Sep 01 03:06:05 PM UTC 24 |
| Peak memory | 227284 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1941120042 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_all.1941120042 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/48.spi_device_tpm_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/48.spi_device_tpm_read_hw_reg.4262098094 |
| Short name | T953 |
| Test name | |
| Test status | |
| Simulation time | 4902822550 ps |
| CPU time | 15.17 seconds |
| Started | Sep 01 03:05:42 PM UTC 24 |
| Finished | Sep 01 03:05:58 PM UTC 24 |
| Peak memory | 227536 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4262098094 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_31/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_read_hw_reg.4262098094 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/48.spi_device_tpm_read_hw_reg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/48.spi_device_tpm_rw.1791493607 |
| Short name | T945 |
| Test name | |
| Test status | |
| Simulation time | 20356015 ps |
| CPU time | 1.47 seconds |
| Started | Sep 01 03:05:44 PM UTC 24 |
| Finished | Sep 01 03:05:47 PM UTC 24 |
| Peak memory | 216476 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1791493607 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_rw.1791493607 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/48.spi_device_tpm_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/48.spi_device_tpm_sts_read.1531665108 |
| Short name | T944 |
| Test name | |
| Test status | |
| Simulation time | 127017027 ps |
| CPU time | 1.23 seconds |
| Started | Sep 01 03:05:43 PM UTC 24 |
| Finished | Sep 01 03:05:45 PM UTC 24 |
| Peak memory | 215588 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1531665108 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_3 1/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_sts_read.1531665108 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/48.spi_device_tpm_sts_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/48.spi_device_upload.3371604493 |
| Short name | T954 |
| Test name | |
| Test status | |
| Simulation time | 1472638514 ps |
| CPU time | 5.16 seconds |
| Started | Sep 01 03:05:53 PM UTC 24 |
| Finished | Sep 01 03:05:59 PM UTC 24 |
| Peak memory | 245216 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3371604493 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_upload.3371604493 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/48.spi_device_upload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/49.spi_device_alert_test.989592988 |
| Short name | T974 |
| Test name | |
| Test status | |
| Simulation time | 12254593 ps |
| CPU time | 1.06 seconds |
| Started | Sep 01 03:06:22 PM UTC 24 |
| Finished | Sep 01 03:06:25 PM UTC 24 |
| Peak memory | 215680 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=989592988 -assert nopostproc +UVM_TEST NAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_alert_test.989592988 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/49.spi_device_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/49.spi_device_cfg_cmd.625858392 |
| Short name | T980 |
| Test name | |
| Test status | |
| Simulation time | 6964938294 ps |
| CPU time | 18.68 seconds |
| Started | Sep 01 03:06:13 PM UTC 24 |
| Finished | Sep 01 03:06:33 PM UTC 24 |
| Peak memory | 245284 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=625858392 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_cfg_cmd.625858392 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/49.spi_device_cfg_cmd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/49.spi_device_csb_read.4155083136 |
| Short name | T959 |
| Test name | |
| Test status | |
| Simulation time | 18213741 ps |
| CPU time | 1.18 seconds |
| Started | Sep 01 03:06:01 PM UTC 24 |
| Finished | Sep 01 03:06:04 PM UTC 24 |
| Peak memory | 215808 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4155083136 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/sp i_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_csb_read.4155083136 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/49.spi_device_csb_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/49.spi_device_flash_all.2329297213 |
| Short name | T991 |
| Test name | |
| Test status | |
| Simulation time | 14718323998 ps |
| CPU time | 113.6 seconds |
| Started | Sep 01 03:06:15 PM UTC 24 |
| Finished | Sep 01 03:08:11 PM UTC 24 |
| Peak memory | 278104 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2329297213 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/s pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_all.2329297213 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/49.spi_device_flash_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/49.spi_device_flash_and_tpm.3105671426 |
| Short name | T982 |
| Test name | |
| Test status | |
| Simulation time | 2017523531 ps |
| CPU time | 34.75 seconds |
| Started | Sep 01 03:06:15 PM UTC 24 |
| Finished | Sep 01 03:06:51 PM UTC 24 |
| Peak memory | 229600 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3105671426 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_ 31/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_and_tpm.3105671426 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/49.spi_device_flash_and_tpm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/49.spi_device_flash_and_tpm_min_idle.1867290587 |
| Short name | T985 |
| Test name | |
| Test status | |
| Simulation time | 6125161044 ps |
| CPU time | 71.74 seconds |
| Started | Sep 01 03:06:21 PM UTC 24 |
| Finished | Sep 01 03:07:34 PM UTC 24 |
| Peak memory | 278172 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1867290587 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_31/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_and_tpm_min_idle.1867290587 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/49.spi_device_flash_and_tpm_min_idle/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/49.spi_device_flash_mode.1972336057 |
| Short name | T971 |
| Test name | |
| Test status | |
| Simulation time | 89895820 ps |
| CPU time | 5.28 seconds |
| Started | Sep 01 03:06:13 PM UTC 24 |
| Finished | Sep 01 03:06:19 PM UTC 24 |
| Peak memory | 234908 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1972336057 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/ spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_mode.1972336057 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/49.spi_device_flash_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/49.spi_device_flash_mode_ignore_cmds.1611798717 |
| Short name | T996 |
| Test name | |
| Test status | |
| Simulation time | 17496937885 ps |
| CPU time | 167.6 seconds |
| Started | Sep 01 03:06:13 PM UTC 24 |
| Finished | Sep 01 03:09:04 PM UTC 24 |
| Peak memory | 263748 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1611798717 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_31/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_mode_ignore_cmds.1611798717 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/49.spi_device_flash_mode_ignore_cmds/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/49.spi_device_intercept.2543089670 |
| Short name | T968 |
| Test name | |
| Test status | |
| Simulation time | 72042485 ps |
| CPU time | 3.23 seconds |
| Started | Sep 01 03:06:08 PM UTC 24 |
| Finished | Sep 01 03:06:12 PM UTC 24 |
| Peak memory | 245208 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2543089670 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/s pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_intercept.2543089670 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/49.spi_device_intercept/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/49.spi_device_mailbox.2899526777 |
| Short name | T978 |
| Test name | |
| Test status | |
| Simulation time | 1443309871 ps |
| CPU time | 18.48 seconds |
| Started | Sep 01 03:06:10 PM UTC 24 |
| Finished | Sep 01 03:06:30 PM UTC 24 |
| Peak memory | 251488 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2899526777 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_mailbox.2899526777 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/49.spi_device_mailbox/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/49.spi_device_pass_addr_payload_swap.3056209269 |
| Short name | T969 |
| Test name | |
| Test status | |
| Simulation time | 414694622 ps |
| CPU time | 4.97 seconds |
| Started | Sep 01 03:06:06 PM UTC 24 |
| Finished | Sep 01 03:06:13 PM UTC 24 |
| Peak memory | 245264 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3056209269 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_31/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_pass_addr_payload_swap.3056209269 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/49.spi_device_pass_addr_payload_swap/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/49.spi_device_pass_cmd_filtering.2887842739 |
| Short name | T979 |
| Test name | |
| Test status | |
| Simulation time | 14734076774 ps |
| CPU time | 23.54 seconds |
| Started | Sep 01 03:06:06 PM UTC 24 |
| Finished | Sep 01 03:06:31 PM UTC 24 |
| Peak memory | 251480 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2887842739 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_08_31/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_pass_cmd_filtering.2887842739 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/49.spi_device_pass_cmd_filtering/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/49.spi_device_read_buffer_direct.1908021975 |
| Short name | T973 |
| Test name | |
| Test status | |
| Simulation time | 586066651 ps |
| CPU time | 6.36 seconds |
| Started | Sep 01 03:06:13 PM UTC 24 |
| Finished | Sep 01 03:06:21 PM UTC 24 |
| Peak memory | 233636 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1908021975 -assert nopostproc +UVM_TESTNAME=spi_device _base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_read_buffer_direct.1908021975 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/49.spi_device_read_buffer_direct/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/49.spi_device_stress_all.3197310959 |
| Short name | T1004 |
| Test name | |
| Test status | |
| Simulation time | 18037875555 ps |
| CPU time | 261.27 seconds |
| Started | Sep 01 03:06:22 PM UTC 24 |
| Finished | Sep 01 03:10:48 PM UTC 24 |
| Peak memory | 276252 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3197310959 -assert nopostproc +UVM_ TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_stress_all.3197310959 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/49.spi_device_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/49.spi_device_tpm_all.4066618371 |
| Short name | T983 |
| Test name | |
| Test status | |
| Simulation time | 24511206371 ps |
| CPU time | 46.24 seconds |
| Started | Sep 01 03:06:04 PM UTC 24 |
| Finished | Sep 01 03:06:52 PM UTC 24 |
| Peak memory | 227620 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4066618371 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_all.4066618371 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/49.spi_device_tpm_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/49.spi_device_tpm_read_hw_reg.1823521577 |
| Short name | T960 |
| Test name | |
| Test status | |
| Simulation time | 43890470 ps |
| CPU time | 1.05 seconds |
| Started | Sep 01 03:06:02 PM UTC 24 |
| Finished | Sep 01 03:06:05 PM UTC 24 |
| Peak memory | 215800 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1823521577 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_31/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_read_hw_reg.1823521577 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/49.spi_device_tpm_read_hw_reg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/49.spi_device_tpm_rw.446032883 |
| Short name | T963 |
| Test name | |
| Test status | |
| Simulation time | 100263276 ps |
| CPU time | 1.95 seconds |
| Started | Sep 01 03:06:05 PM UTC 24 |
| Finished | Sep 01 03:06:08 PM UTC 24 |
| Peak memory | 226636 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=446032883 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/spi_d evice_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_rw.446032883 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/49.spi_device_tpm_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/49.spi_device_tpm_sts_read.59769410 |
| Short name | T962 |
| Test name | |
| Test status | |
| Simulation time | 106812943 ps |
| CPU time | 1.38 seconds |
| Started | Sep 01 03:06:04 PM UTC 24 |
| Finished | Sep 01 03:06:06 PM UTC 24 |
| Peak memory | 215868 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=59769410 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/ spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_sts_read.59769410 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/49.spi_device_tpm_sts_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/49.spi_device_upload.1120843973 |
| Short name | T975 |
| Test name | |
| Test status | |
| Simulation time | 6372601448 ps |
| CPU time | 12.49 seconds |
| Started | Sep 01 03:06:11 PM UTC 24 |
| Finished | Sep 01 03:06:25 PM UTC 24 |
| Peak memory | 263772 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1120843973 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_upload.1120843973 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/49.spi_device_upload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/5.spi_device_alert_test.1965654398 |
| Short name | T406 |
| Test name | |
| Test status | |
| Simulation time | 31262413 ps |
| CPU time | 1.04 seconds |
| Started | Sep 01 02:47:59 PM UTC 24 |
| Finished | Sep 01 02:48:01 PM UTC 24 |
| Peak memory | 215804 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1965654398 -assert nopostproc +UVM_TES TNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_alert_test.1965654398 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/5.spi_device_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/5.spi_device_cfg_cmd.3296293442 |
| Short name | T110 |
| Test name | |
| Test status | |
| Simulation time | 384682586 ps |
| CPU time | 10.64 seconds |
| Started | Sep 01 02:47:47 PM UTC 24 |
| Finished | Sep 01 02:47:59 PM UTC 24 |
| Peak memory | 245212 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3296293442 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_cfg_cmd.3296293442 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/5.spi_device_cfg_cmd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/5.spi_device_csb_read.1810163189 |
| Short name | T400 |
| Test name | |
| Test status | |
| Simulation time | 23040408 ps |
| CPU time | 1.15 seconds |
| Started | Sep 01 02:47:38 PM UTC 24 |
| Finished | Sep 01 02:47:41 PM UTC 24 |
| Peak memory | 215632 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1810163189 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/sp i_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_csb_read.1810163189 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/5.spi_device_csb_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/5.spi_device_flash_all.2701574685 |
| Short name | T46 |
| Test name | |
| Test status | |
| Simulation time | 294256095 ps |
| CPU time | 10.02 seconds |
| Started | Sep 01 02:47:54 PM UTC 24 |
| Finished | Sep 01 02:48:05 PM UTC 24 |
| Peak memory | 245200 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2701574685 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/s pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_all.2701574685 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/5.spi_device_flash_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/5.spi_device_flash_and_tpm_min_idle.3585254292 |
| Short name | T202 |
| Test name | |
| Test status | |
| Simulation time | 29621724976 ps |
| CPU time | 255.82 seconds |
| Started | Sep 01 02:47:54 PM UTC 24 |
| Finished | Sep 01 02:52:13 PM UTC 24 |
| Peak memory | 261924 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3585254292 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_31/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_and_tpm_min_idle.3585254292 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/5.spi_device_flash_and_tpm_min_idle/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/5.spi_device_flash_mode.3555674800 |
| Short name | T405 |
| Test name | |
| Test status | |
| Simulation time | 123893713 ps |
| CPU time | 3.5 seconds |
| Started | Sep 01 02:47:48 PM UTC 24 |
| Finished | Sep 01 02:47:53 PM UTC 24 |
| Peak memory | 245192 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3555674800 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/ spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_mode.3555674800 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/5.spi_device_flash_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/5.spi_device_flash_mode_ignore_cmds.496442120 |
| Short name | T404 |
| Test name | |
| Test status | |
| Simulation time | 33430951 ps |
| CPU time | 1.19 seconds |
| Started | Sep 01 02:47:48 PM UTC 24 |
| Finished | Sep 01 02:47:51 PM UTC 24 |
| Peak memory | 225740 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=496442120 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_31/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_mode_ignore_cmds.496442120 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/5.spi_device_flash_mode_ignore_cmds/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/5.spi_device_intercept.3652412778 |
| Short name | T255 |
| Test name | |
| Test status | |
| Simulation time | 5267036483 ps |
| CPU time | 37.55 seconds |
| Started | Sep 01 02:47:45 PM UTC 24 |
| Finished | Sep 01 02:48:24 PM UTC 24 |
| Peak memory | 235108 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3652412778 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/s pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_intercept.3652412778 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/5.spi_device_intercept/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/5.spi_device_mailbox.2648386200 |
| Short name | T249 |
| Test name | |
| Test status | |
| Simulation time | 3185889308 ps |
| CPU time | 35.28 seconds |
| Started | Sep 01 02:47:46 PM UTC 24 |
| Finished | Sep 01 02:48:23 PM UTC 24 |
| Peak memory | 261664 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2648386200 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_mailbox.2648386200 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/5.spi_device_mailbox/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/5.spi_device_pass_addr_payload_swap.96738184 |
| Short name | T279 |
| Test name | |
| Test status | |
| Simulation time | 6726492728 ps |
| CPU time | 6.79 seconds |
| Started | Sep 01 02:47:45 PM UTC 24 |
| Finished | Sep 01 02:47:53 PM UTC 24 |
| Peak memory | 245324 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=96738184 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_31/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_pass_addr_payload_swap.96738184 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/5.spi_device_pass_addr_payload_swap/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/5.spi_device_pass_cmd_filtering.1329451181 |
| Short name | T67 |
| Test name | |
| Test status | |
| Simulation time | 662674665 ps |
| CPU time | 16.77 seconds |
| Started | Sep 01 02:47:44 PM UTC 24 |
| Finished | Sep 01 02:48:02 PM UTC 24 |
| Peak memory | 245136 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1329451181 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_08_31/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_pass_cmd_filtering.1329451181 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/5.spi_device_pass_cmd_filtering/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/5.spi_device_read_buffer_direct.3815170452 |
| Short name | T167 |
| Test name | |
| Test status | |
| Simulation time | 269342648 ps |
| CPU time | 7.47 seconds |
| Started | Sep 01 02:47:52 PM UTC 24 |
| Finished | Sep 01 02:48:00 PM UTC 24 |
| Peak memory | 233652 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3815170452 -assert nopostproc +UVM_TESTNAME=spi_device _base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_read_buffer_direct.3815170452 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/5.spi_device_read_buffer_direct/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/5.spi_device_tpm_all.1528767162 |
| Short name | T382 |
| Test name | |
| Test status | |
| Simulation time | 4411385795 ps |
| CPU time | 39.06 seconds |
| Started | Sep 01 02:47:42 PM UTC 24 |
| Finished | Sep 01 02:48:22 PM UTC 24 |
| Peak memory | 227668 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1528767162 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_all.1528767162 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/5.spi_device_tpm_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/5.spi_device_tpm_read_hw_reg.3246598459 |
| Short name | T403 |
| Test name | |
| Test status | |
| Simulation time | 341045321 ps |
| CPU time | 5.35 seconds |
| Started | Sep 01 02:47:41 PM UTC 24 |
| Finished | Sep 01 02:47:47 PM UTC 24 |
| Peak memory | 227536 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3246598459 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_31/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_read_hw_reg.3246598459 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/5.spi_device_tpm_read_hw_reg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/5.spi_device_tpm_rw.3414460558 |
| Short name | T389 |
| Test name | |
| Test status | |
| Simulation time | 19542987 ps |
| CPU time | 1.44 seconds |
| Started | Sep 01 02:47:43 PM UTC 24 |
| Finished | Sep 01 02:47:45 PM UTC 24 |
| Peak memory | 215864 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3414460558 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_rw.3414460558 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/5.spi_device_tpm_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/5.spi_device_tpm_sts_read.4066971323 |
| Short name | T401 |
| Test name | |
| Test status | |
| Simulation time | 36683649 ps |
| CPU time | 1.11 seconds |
| Started | Sep 01 02:47:42 PM UTC 24 |
| Finished | Sep 01 02:47:44 PM UTC 24 |
| Peak memory | 215864 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4066971323 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_3 1/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_sts_read.4066971323 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/5.spi_device_tpm_sts_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/5.spi_device_upload.2127173565 |
| Short name | T258 |
| Test name | |
| Test status | |
| Simulation time | 158357776 ps |
| CPU time | 5.65 seconds |
| Started | Sep 01 02:47:46 PM UTC 24 |
| Finished | Sep 01 02:47:53 PM UTC 24 |
| Peak memory | 234900 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2127173565 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_upload.2127173565 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/5.spi_device_upload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/6.spi_device_alert_test.2388434099 |
| Short name | T411 |
| Test name | |
| Test status | |
| Simulation time | 12511744 ps |
| CPU time | 1.14 seconds |
| Started | Sep 01 02:48:27 PM UTC 24 |
| Finished | Sep 01 02:48:29 PM UTC 24 |
| Peak memory | 215740 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2388434099 -assert nopostproc +UVM_TES TNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_alert_test.2388434099 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/6.spi_device_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/6.spi_device_cfg_cmd.730367421 |
| Short name | T284 |
| Test name | |
| Test status | |
| Simulation time | 946974188 ps |
| CPU time | 5.09 seconds |
| Started | Sep 01 02:48:17 PM UTC 24 |
| Finished | Sep 01 02:48:23 PM UTC 24 |
| Peak memory | 234956 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=730367421 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_cfg_cmd.730367421 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/6.spi_device_cfg_cmd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/6.spi_device_csb_read.3331829872 |
| Short name | T407 |
| Test name | |
| Test status | |
| Simulation time | 17040364 ps |
| CPU time | 1.18 seconds |
| Started | Sep 01 02:48:00 PM UTC 24 |
| Finished | Sep 01 02:48:02 PM UTC 24 |
| Peak memory | 215804 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3331829872 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/sp i_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_csb_read.3331829872 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/6.spi_device_csb_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/6.spi_device_flash_all.3750111019 |
| Short name | T410 |
| Test name | |
| Test status | |
| Simulation time | 17036575 ps |
| CPU time | 1.15 seconds |
| Started | Sep 01 02:48:23 PM UTC 24 |
| Finished | Sep 01 02:48:25 PM UTC 24 |
| Peak memory | 225740 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3750111019 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/s pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_all.3750111019 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/6.spi_device_flash_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/6.spi_device_flash_and_tpm.2965458465 |
| Short name | T231 |
| Test name | |
| Test status | |
| Simulation time | 373819907884 ps |
| CPU time | 473.11 seconds |
| Started | Sep 01 02:48:24 PM UTC 24 |
| Finished | Sep 01 02:56:24 PM UTC 24 |
| Peak memory | 263816 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2965458465 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_ 31/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_and_tpm.2965458465 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/6.spi_device_flash_and_tpm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/6.spi_device_flash_and_tpm_min_idle.1406580232 |
| Short name | T90 |
| Test name | |
| Test status | |
| Simulation time | 109322523211 ps |
| CPU time | 362.74 seconds |
| Started | Sep 01 02:48:24 PM UTC 24 |
| Finished | Sep 01 02:54:32 PM UTC 24 |
| Peak memory | 263812 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1406580232 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_31/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_and_tpm_min_idle.1406580232 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/6.spi_device_flash_and_tpm_min_idle/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/6.spi_device_flash_mode.1875053748 |
| Short name | T276 |
| Test name | |
| Test status | |
| Simulation time | 463197561 ps |
| CPU time | 13.68 seconds |
| Started | Sep 01 02:48:18 PM UTC 24 |
| Finished | Sep 01 02:48:33 PM UTC 24 |
| Peak memory | 234960 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1875053748 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/ spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_mode.1875053748 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/6.spi_device_flash_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/6.spi_device_flash_mode_ignore_cmds.195659110 |
| Short name | T199 |
| Test name | |
| Test status | |
| Simulation time | 63547766386 ps |
| CPU time | 165.07 seconds |
| Started | Sep 01 02:48:20 PM UTC 24 |
| Finished | Sep 01 02:51:08 PM UTC 24 |
| Peak memory | 263840 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=195659110 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_31/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_mode_ignore_cmds.195659110 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/6.spi_device_flash_mode_ignore_cmds/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/6.spi_device_intercept.3670106227 |
| Short name | T234 |
| Test name | |
| Test status | |
| Simulation time | 1060414078 ps |
| CPU time | 14.04 seconds |
| Started | Sep 01 02:48:12 PM UTC 24 |
| Finished | Sep 01 02:48:27 PM UTC 24 |
| Peak memory | 245220 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3670106227 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/s pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_intercept.3670106227 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/6.spi_device_intercept/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/6.spi_device_mailbox.687918888 |
| Short name | T313 |
| Test name | |
| Test status | |
| Simulation time | 45327008359 ps |
| CPU time | 82.83 seconds |
| Started | Sep 01 02:48:15 PM UTC 24 |
| Finished | Sep 01 02:49:39 PM UTC 24 |
| Peak memory | 245332 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=687918888 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_mailbox.687918888 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/6.spi_device_mailbox/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/6.spi_device_pass_addr_payload_swap.779004859 |
| Short name | T267 |
| Test name | |
| Test status | |
| Simulation time | 417457287 ps |
| CPU time | 9.41 seconds |
| Started | Sep 01 02:48:07 PM UTC 24 |
| Finished | Sep 01 02:48:17 PM UTC 24 |
| Peak memory | 245144 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=779004859 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_31/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_pass_addr_payload_swap.779004859 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/6.spi_device_pass_addr_payload_swap/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/6.spi_device_pass_cmd_filtering.1587966062 |
| Short name | T68 |
| Test name | |
| Test status | |
| Simulation time | 16196350178 ps |
| CPU time | 26.82 seconds |
| Started | Sep 01 02:48:06 PM UTC 24 |
| Finished | Sep 01 02:48:34 PM UTC 24 |
| Peak memory | 245340 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1587966062 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_08_31/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_pass_cmd_filtering.1587966062 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/6.spi_device_pass_cmd_filtering/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/6.spi_device_read_buffer_direct.3877790670 |
| Short name | T168 |
| Test name | |
| Test status | |
| Simulation time | 1900349663 ps |
| CPU time | 7.49 seconds |
| Started | Sep 01 02:48:22 PM UTC 24 |
| Finished | Sep 01 02:48:31 PM UTC 24 |
| Peak memory | 231264 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3877790670 -assert nopostproc +UVM_TESTNAME=spi_device _base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_read_buffer_direct.3877790670 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/6.spi_device_read_buffer_direct/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/6.spi_device_tpm_all.786949884 |
| Short name | T383 |
| Test name | |
| Test status | |
| Simulation time | 4941498260 ps |
| CPU time | 15.72 seconds |
| Started | Sep 01 02:48:02 PM UTC 24 |
| Finished | Sep 01 02:48:19 PM UTC 24 |
| Peak memory | 227564 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=786949884 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_all.786949884 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/6.spi_device_tpm_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/6.spi_device_tpm_read_hw_reg.1789655780 |
| Short name | T409 |
| Test name | |
| Test status | |
| Simulation time | 6832592522 ps |
| CPU time | 11.28 seconds |
| Started | Sep 01 02:48:02 PM UTC 24 |
| Finished | Sep 01 02:48:15 PM UTC 24 |
| Peak memory | 227548 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1789655780 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_31/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_read_hw_reg.1789655780 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/6.spi_device_tpm_read_hw_reg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/6.spi_device_tpm_rw.1150625744 |
| Short name | T386 |
| Test name | |
| Test status | |
| Simulation time | 1139969429 ps |
| CPU time | 5.41 seconds |
| Started | Sep 01 02:48:04 PM UTC 24 |
| Finished | Sep 01 02:48:11 PM UTC 24 |
| Peak memory | 227500 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1150625744 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_rw.1150625744 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/6.spi_device_tpm_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/6.spi_device_tpm_sts_read.47005427 |
| Short name | T408 |
| Test name | |
| Test status | |
| Simulation time | 157355146 ps |
| CPU time | 1.32 seconds |
| Started | Sep 01 02:48:03 PM UTC 24 |
| Finished | Sep 01 02:48:06 PM UTC 24 |
| Peak memory | 215868 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=47005427 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/ spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_sts_read.47005427 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/6.spi_device_tpm_sts_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/6.spi_device_upload.1671684052 |
| Short name | T66 |
| Test name | |
| Test status | |
| Simulation time | 118877555 ps |
| CPU time | 4.04 seconds |
| Started | Sep 01 02:48:16 PM UTC 24 |
| Finished | Sep 01 02:48:21 PM UTC 24 |
| Peak memory | 251296 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1671684052 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_upload.1671684052 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/6.spi_device_upload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/7.spi_device_alert_test.2638939702 |
| Short name | T417 |
| Test name | |
| Test status | |
| Simulation time | 11961398 ps |
| CPU time | 1.06 seconds |
| Started | Sep 01 02:49:01 PM UTC 24 |
| Finished | Sep 01 02:49:03 PM UTC 24 |
| Peak memory | 215740 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2638939702 -assert nopostproc +UVM_TES TNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_alert_test.2638939702 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/7.spi_device_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/7.spi_device_cfg_cmd.1306967559 |
| Short name | T416 |
| Test name | |
| Test status | |
| Simulation time | 1390264896 ps |
| CPU time | 12.43 seconds |
| Started | Sep 01 02:48:47 PM UTC 24 |
| Finished | Sep 01 02:49:00 PM UTC 24 |
| Peak memory | 234968 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1306967559 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_cfg_cmd.1306967559 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/7.spi_device_cfg_cmd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/7.spi_device_csb_read.2154408290 |
| Short name | T412 |
| Test name | |
| Test status | |
| Simulation time | 12195438 ps |
| CPU time | 1.14 seconds |
| Started | Sep 01 02:48:27 PM UTC 24 |
| Finished | Sep 01 02:48:29 PM UTC 24 |
| Peak memory | 215808 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2154408290 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/sp i_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_csb_read.2154408290 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/7.spi_device_csb_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/7.spi_device_flash_all.4090093092 |
| Short name | T74 |
| Test name | |
| Test status | |
| Simulation time | 23809536662 ps |
| CPU time | 103.28 seconds |
| Started | Sep 01 02:48:52 PM UTC 24 |
| Finished | Sep 01 02:50:37 PM UTC 24 |
| Peak memory | 276068 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4090093092 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/s pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_all.4090093092 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/7.spi_device_flash_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/7.spi_device_flash_and_tpm.1583165511 |
| Short name | T50 |
| Test name | |
| Test status | |
| Simulation time | 4974269135 ps |
| CPU time | 85.59 seconds |
| Started | Sep 01 02:48:53 PM UTC 24 |
| Finished | Sep 01 02:50:21 PM UTC 24 |
| Peak memory | 261828 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1583165511 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_ 31/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_and_tpm.1583165511 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/7.spi_device_flash_and_tpm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/7.spi_device_flash_and_tpm_min_idle.750005926 |
| Short name | T309 |
| Test name | |
| Test status | |
| Simulation time | 49831383856 ps |
| CPU time | 123 seconds |
| Started | Sep 01 02:48:54 PM UTC 24 |
| Finished | Sep 01 02:51:00 PM UTC 24 |
| Peak memory | 251444 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=750005926 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_31/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_and_tpm_min_idle.750005926 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/7.spi_device_flash_and_tpm_min_idle/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/7.spi_device_flash_mode.3339501308 |
| Short name | T415 |
| Test name | |
| Test status | |
| Simulation time | 98042204 ps |
| CPU time | 4.88 seconds |
| Started | Sep 01 02:48:47 PM UTC 24 |
| Finished | Sep 01 02:48:52 PM UTC 24 |
| Peak memory | 245216 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3339501308 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/ spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_mode.3339501308 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/7.spi_device_flash_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/7.spi_device_flash_mode_ignore_cmds.2882854580 |
| Short name | T115 |
| Test name | |
| Test status | |
| Simulation time | 4025636607 ps |
| CPU time | 67.5 seconds |
| Started | Sep 01 02:48:48 PM UTC 24 |
| Finished | Sep 01 02:49:57 PM UTC 24 |
| Peak memory | 267876 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2882854580 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_31/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_mode_ignore_cmds.2882854580 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/7.spi_device_flash_mode_ignore_cmds/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/7.spi_device_intercept.858392736 |
| Short name | T261 |
| Test name | |
| Test status | |
| Simulation time | 9191865382 ps |
| CPU time | 17.41 seconds |
| Started | Sep 01 02:48:34 PM UTC 24 |
| Finished | Sep 01 02:48:53 PM UTC 24 |
| Peak memory | 235156 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=858392736 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/sp i_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_intercept.858392736 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/7.spi_device_intercept/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/7.spi_device_mailbox.1811114761 |
| Short name | T111 |
| Test name | |
| Test status | |
| Simulation time | 3617916300 ps |
| CPU time | 27.4 seconds |
| Started | Sep 01 02:48:34 PM UTC 24 |
| Finished | Sep 01 02:49:03 PM UTC 24 |
| Peak memory | 245324 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1811114761 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_mailbox.1811114761 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/7.spi_device_mailbox/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/7.spi_device_pass_addr_payload_swap.3288257222 |
| Short name | T246 |
| Test name | |
| Test status | |
| Simulation time | 998124615 ps |
| CPU time | 11.6 seconds |
| Started | Sep 01 02:48:33 PM UTC 24 |
| Finished | Sep 01 02:48:46 PM UTC 24 |
| Peak memory | 251352 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3288257222 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_31/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_pass_addr_payload_swap.3288257222 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/7.spi_device_pass_addr_payload_swap/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/7.spi_device_pass_cmd_filtering.1283529847 |
| Short name | T250 |
| Test name | |
| Test status | |
| Simulation time | 1060596805 ps |
| CPU time | 12.41 seconds |
| Started | Sep 01 02:48:32 PM UTC 24 |
| Finished | Sep 01 02:48:46 PM UTC 24 |
| Peak memory | 251300 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1283529847 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_08_31/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_pass_cmd_filtering.1283529847 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/7.spi_device_pass_cmd_filtering/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/7.spi_device_read_buffer_direct.574756775 |
| Short name | T169 |
| Test name | |
| Test status | |
| Simulation time | 355602114 ps |
| CPU time | 6.19 seconds |
| Started | Sep 01 02:48:50 PM UTC 24 |
| Finished | Sep 01 02:48:58 PM UTC 24 |
| Peak memory | 233656 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=574756775 -assert nopostproc +UVM_TESTNAME=spi_device_ base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_read_buffer_direct.574756775 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/7.spi_device_read_buffer_direct/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/7.spi_device_stress_all.2348335628 |
| Short name | T197 |
| Test name | |
| Test status | |
| Simulation time | 97787899493 ps |
| CPU time | 270.48 seconds |
| Started | Sep 01 02:48:58 PM UTC 24 |
| Finished | Sep 01 02:53:33 PM UTC 24 |
| Peak memory | 249484 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2348335628 -assert nopostproc +UVM_ TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_stress_all.2348335628 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/7.spi_device_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/7.spi_device_tpm_all.2005021052 |
| Short name | T385 |
| Test name | |
| Test status | |
| Simulation time | 15995739007 ps |
| CPU time | 72.21 seconds |
| Started | Sep 01 02:48:30 PM UTC 24 |
| Finished | Sep 01 02:49:44 PM UTC 24 |
| Peak memory | 227560 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2005021052 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_all.2005021052 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/7.spi_device_tpm_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/7.spi_device_tpm_read_hw_reg.1241837078 |
| Short name | T414 |
| Test name | |
| Test status | |
| Simulation time | 2405515823 ps |
| CPU time | 15.18 seconds |
| Started | Sep 01 02:48:30 PM UTC 24 |
| Finished | Sep 01 02:48:46 PM UTC 24 |
| Peak memory | 227556 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1241837078 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_31/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_read_hw_reg.1241837078 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/7.spi_device_tpm_read_hw_reg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/7.spi_device_tpm_rw.2838262804 |
| Short name | T392 |
| Test name | |
| Test status | |
| Simulation time | 99233540 ps |
| CPU time | 1.54 seconds |
| Started | Sep 01 02:48:31 PM UTC 24 |
| Finished | Sep 01 02:48:34 PM UTC 24 |
| Peak memory | 216392 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2838262804 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_rw.2838262804 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/7.spi_device_tpm_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/7.spi_device_tpm_sts_read.2164864946 |
| Short name | T413 |
| Test name | |
| Test status | |
| Simulation time | 87587136 ps |
| CPU time | 1.47 seconds |
| Started | Sep 01 02:48:30 PM UTC 24 |
| Finished | Sep 01 02:48:33 PM UTC 24 |
| Peak memory | 215860 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2164864946 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_3 1/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_sts_read.2164864946 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/7.spi_device_tpm_sts_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/7.spi_device_upload.578048722 |
| Short name | T230 |
| Test name | |
| Test status | |
| Simulation time | 10819920312 ps |
| CPU time | 25.09 seconds |
| Started | Sep 01 02:48:34 PM UTC 24 |
| Finished | Sep 01 02:49:01 PM UTC 24 |
| Peak memory | 244068 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=578048722 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/spi_d evice_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_upload.578048722 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/7.spi_device_upload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/8.spi_device_alert_test.3944846122 |
| Short name | T423 |
| Test name | |
| Test status | |
| Simulation time | 21886154 ps |
| CPU time | 1.07 seconds |
| Started | Sep 01 02:49:40 PM UTC 24 |
| Finished | Sep 01 02:49:42 PM UTC 24 |
| Peak memory | 215680 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3944846122 -assert nopostproc +UVM_TES TNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_alert_test.3944846122 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/8.spi_device_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/8.spi_device_cfg_cmd.2291287304 |
| Short name | T285 |
| Test name | |
| Test status | |
| Simulation time | 518184398 ps |
| CPU time | 9.49 seconds |
| Started | Sep 01 02:49:25 PM UTC 24 |
| Finished | Sep 01 02:49:36 PM UTC 24 |
| Peak memory | 245208 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2291287304 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_cfg_cmd.2291287304 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/8.spi_device_cfg_cmd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/8.spi_device_csb_read.4036422934 |
| Short name | T418 |
| Test name | |
| Test status | |
| Simulation time | 16767599 ps |
| CPU time | 1.2 seconds |
| Started | Sep 01 02:49:01 PM UTC 24 |
| Finished | Sep 01 02:49:04 PM UTC 24 |
| Peak memory | 215804 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4036422934 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/sp i_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_csb_read.4036422934 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/8.spi_device_csb_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/8.spi_device_flash_all.162055317 |
| Short name | T422 |
| Test name | |
| Test status | |
| Simulation time | 12782269 ps |
| CPU time | 1.14 seconds |
| Started | Sep 01 02:49:33 PM UTC 24 |
| Finished | Sep 01 02:49:35 PM UTC 24 |
| Peak memory | 225740 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=162055317 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/sp i_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_all.162055317 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/8.spi_device_flash_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/8.spi_device_flash_and_tpm.3491612236 |
| Short name | T291 |
| Test name | |
| Test status | |
| Simulation time | 18261811860 ps |
| CPU time | 76.98 seconds |
| Started | Sep 01 02:49:33 PM UTC 24 |
| Finished | Sep 01 02:50:52 PM UTC 24 |
| Peak memory | 235148 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3491612236 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_ 31/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_and_tpm.3491612236 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/8.spi_device_flash_and_tpm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/8.spi_device_flash_and_tpm_min_idle.408539842 |
| Short name | T104 |
| Test name | |
| Test status | |
| Simulation time | 29850077624 ps |
| CPU time | 109.14 seconds |
| Started | Sep 01 02:49:36 PM UTC 24 |
| Finished | Sep 01 02:51:27 PM UTC 24 |
| Peak memory | 278288 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=408539842 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_31/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_and_tpm_min_idle.408539842 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/8.spi_device_flash_and_tpm_min_idle/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/8.spi_device_flash_mode.3571846522 |
| Short name | T275 |
| Test name | |
| Test status | |
| Simulation time | 2686178548 ps |
| CPU time | 46.93 seconds |
| Started | Sep 01 02:49:27 PM UTC 24 |
| Finished | Sep 01 02:50:16 PM UTC 24 |
| Peak memory | 235088 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3571846522 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/ spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_mode.3571846522 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/8.spi_device_flash_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/8.spi_device_flash_mode_ignore_cmds.10326557 |
| Short name | T206 |
| Test name | |
| Test status | |
| Simulation time | 1786639742 ps |
| CPU time | 26.15 seconds |
| Started | Sep 01 02:49:30 PM UTC 24 |
| Finished | Sep 01 02:49:57 PM UTC 24 |
| Peak memory | 251360 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=10326557 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_31/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_mode_ignore_cmds.10326557 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/8.spi_device_flash_mode_ignore_cmds/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/8.spi_device_intercept.251912572 |
| Short name | T302 |
| Test name | |
| Test status | |
| Simulation time | 1195278436 ps |
| CPU time | 18.35 seconds |
| Started | Sep 01 02:49:12 PM UTC 24 |
| Finished | Sep 01 02:49:32 PM UTC 24 |
| Peak memory | 245220 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=251912572 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/sp i_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_intercept.251912572 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/8.spi_device_intercept/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/8.spi_device_mailbox.2260016798 |
| Short name | T297 |
| Test name | |
| Test status | |
| Simulation time | 163906065 ps |
| CPU time | 3.42 seconds |
| Started | Sep 01 02:49:16 PM UTC 24 |
| Finished | Sep 01 02:49:21 PM UTC 24 |
| Peak memory | 245148 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2260016798 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_mailbox.2260016798 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/8.spi_device_mailbox/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/8.spi_device_pass_addr_payload_swap.1538809704 |
| Short name | T71 |
| Test name | |
| Test status | |
| Simulation time | 8259376695 ps |
| CPU time | 17.37 seconds |
| Started | Sep 01 02:49:10 PM UTC 24 |
| Finished | Sep 01 02:49:29 PM UTC 24 |
| Peak memory | 249424 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1538809704 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_31/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_pass_addr_payload_swap.1538809704 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/8.spi_device_pass_addr_payload_swap/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/8.spi_device_pass_cmd_filtering.2965180537 |
| Short name | T315 |
| Test name | |
| Test status | |
| Simulation time | 1520241555 ps |
| CPU time | 6.51 seconds |
| Started | Sep 01 02:49:08 PM UTC 24 |
| Finished | Sep 01 02:49:15 PM UTC 24 |
| Peak memory | 234732 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2965180537 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_08_31/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_pass_cmd_filtering.2965180537 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/8.spi_device_pass_cmd_filtering/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/8.spi_device_read_buffer_direct.301330 |
| Short name | T424 |
| Test name | |
| Test status | |
| Simulation time | 444459308 ps |
| CPU time | 11.6 seconds |
| Started | Sep 01 02:49:31 PM UTC 24 |
| Finished | Sep 01 02:49:43 PM UTC 24 |
| Peak memory | 231260 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=301330 -assert nopostproc +UVM_TESTNAME=spi_device_bas e_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_read_buffer_direct.301330 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/8.spi_device_read_buffer_direct/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/8.spi_device_stress_all.4128506389 |
| Short name | T35 |
| Test name | |
| Test status | |
| Simulation time | 3107293383 ps |
| CPU time | 18.99 seconds |
| Started | Sep 01 02:49:37 PM UTC 24 |
| Finished | Sep 01 02:49:57 PM UTC 24 |
| Peak memory | 235152 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4128506389 -assert nopostproc +UVM_ TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_stress_all.4128506389 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/8.spi_device_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/8.spi_device_tpm_all.421842005 |
| Short name | T390 |
| Test name | |
| Test status | |
| Simulation time | 2976604064 ps |
| CPU time | 20.55 seconds |
| Started | Sep 01 02:49:05 PM UTC 24 |
| Finished | Sep 01 02:49:26 PM UTC 24 |
| Peak memory | 227548 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=421842005 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_all.421842005 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/8.spi_device_tpm_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/8.spi_device_tpm_read_hw_reg.1420886100 |
| Short name | T421 |
| Test name | |
| Test status | |
| Simulation time | 1119632302 ps |
| CPU time | 5.71 seconds |
| Started | Sep 01 02:49:04 PM UTC 24 |
| Finished | Sep 01 02:49:11 PM UTC 24 |
| Peak memory | 227408 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1420886100 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_31/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_read_hw_reg.1420886100 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/8.spi_device_tpm_read_hw_reg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/8.spi_device_tpm_rw.2892930337 |
| Short name | T420 |
| Test name | |
| Test status | |
| Simulation time | 166084919 ps |
| CPU time | 1.51 seconds |
| Started | Sep 01 02:49:07 PM UTC 24 |
| Finished | Sep 01 02:49:09 PM UTC 24 |
| Peak memory | 215864 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2892930337 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_rw.2892930337 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/8.spi_device_tpm_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/8.spi_device_tpm_sts_read.2265758492 |
| Short name | T419 |
| Test name | |
| Test status | |
| Simulation time | 93384351 ps |
| CPU time | 1.31 seconds |
| Started | Sep 01 02:49:05 PM UTC 24 |
| Finished | Sep 01 02:49:07 PM UTC 24 |
| Peak memory | 215864 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2265758492 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_3 1/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_sts_read.2265758492 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/8.spi_device_tpm_sts_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/8.spi_device_upload.1349209981 |
| Short name | T298 |
| Test name | |
| Test status | |
| Simulation time | 4428737104 ps |
| CPU time | 28.97 seconds |
| Started | Sep 01 02:49:21 PM UTC 24 |
| Finished | Sep 01 02:49:52 PM UTC 24 |
| Peak memory | 245396 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1349209981 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_upload.1349209981 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/8.spi_device_upload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/9.spi_device_alert_test.3621975031 |
| Short name | T429 |
| Test name | |
| Test status | |
| Simulation time | 51143298 ps |
| CPU time | 1.05 seconds |
| Started | Sep 01 02:50:13 PM UTC 24 |
| Finished | Sep 01 02:50:15 PM UTC 24 |
| Peak memory | 215680 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3621975031 -assert nopostproc +UVM_TES TNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_alert_test.3621975031 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/9.spi_device_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/9.spi_device_cfg_cmd.1237856135 |
| Short name | T300 |
| Test name | |
| Test status | |
| Simulation time | 169848986 ps |
| CPU time | 5.76 seconds |
| Started | Sep 01 02:49:58 PM UTC 24 |
| Finished | Sep 01 02:50:05 PM UTC 24 |
| Peak memory | 234968 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1237856135 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_cfg_cmd.1237856135 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/9.spi_device_cfg_cmd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/9.spi_device_csb_read.144339490 |
| Short name | T425 |
| Test name | |
| Test status | |
| Simulation time | 37972503 ps |
| CPU time | 1.2 seconds |
| Started | Sep 01 02:49:43 PM UTC 24 |
| Finished | Sep 01 02:49:45 PM UTC 24 |
| Peak memory | 215632 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=144339490 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_csb_read.144339490 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/9.spi_device_csb_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/9.spi_device_flash_all.2290748625 |
| Short name | T204 |
| Test name | |
| Test status | |
| Simulation time | 5113611697 ps |
| CPU time | 19.2 seconds |
| Started | Sep 01 02:50:03 PM UTC 24 |
| Finished | Sep 01 02:50:24 PM UTC 24 |
| Peak memory | 249488 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2290748625 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/s pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_all.2290748625 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/9.spi_device_flash_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/9.spi_device_flash_and_tpm.891893860 |
| Short name | T105 |
| Test name | |
| Test status | |
| Simulation time | 5821196628 ps |
| CPU time | 97.49 seconds |
| Started | Sep 01 02:50:04 PM UTC 24 |
| Finished | Sep 01 02:51:44 PM UTC 24 |
| Peak memory | 267996 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=891893860 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_3 1/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_and_tpm.891893860 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/9.spi_device_flash_and_tpm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/9.spi_device_flash_and_tpm_min_idle.125226379 |
| Short name | T251 |
| Test name | |
| Test status | |
| Simulation time | 15693624564 ps |
| CPU time | 181.51 seconds |
| Started | Sep 01 02:50:06 PM UTC 24 |
| Finished | Sep 01 02:53:10 PM UTC 24 |
| Peak memory | 280288 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=125226379 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_31/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_and_tpm_min_idle.125226379 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/9.spi_device_flash_and_tpm_min_idle/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/9.spi_device_flash_mode.796343 |
| Short name | T280 |
| Test name | |
| Test status | |
| Simulation time | 1245663652 ps |
| CPU time | 16.07 seconds |
| Started | Sep 01 02:49:58 PM UTC 24 |
| Finished | Sep 01 02:50:15 PM UTC 24 |
| Peak memory | 251344 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=796343 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UV M_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_mode.796343 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/9.spi_device_flash_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/9.spi_device_flash_mode_ignore_cmds.530683795 |
| Short name | T205 |
| Test name | |
| Test status | |
| Simulation time | 2606604459 ps |
| CPU time | 55.53 seconds |
| Started | Sep 01 02:49:59 PM UTC 24 |
| Finished | Sep 01 02:50:56 PM UTC 24 |
| Peak memory | 263824 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=530683795 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_31/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_mode_ignore_cmds.530683795 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/9.spi_device_flash_mode_ignore_cmds/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/9.spi_device_intercept.292202324 |
| Short name | T237 |
| Test name | |
| Test status | |
| Simulation time | 1986618164 ps |
| CPU time | 12.7 seconds |
| Started | Sep 01 02:49:55 PM UTC 24 |
| Finished | Sep 01 02:50:09 PM UTC 24 |
| Peak memory | 244724 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=292202324 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/sp i_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_intercept.292202324 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/9.spi_device_intercept/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/9.spi_device_mailbox.3119090320 |
| Short name | T273 |
| Test name | |
| Test status | |
| Simulation time | 439741031 ps |
| CPU time | 6.14 seconds |
| Started | Sep 01 02:49:55 PM UTC 24 |
| Finished | Sep 01 02:50:02 PM UTC 24 |
| Peak memory | 246924 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3119090320 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_mailbox.3119090320 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/9.spi_device_mailbox/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/9.spi_device_pass_addr_payload_swap.1548302027 |
| Short name | T73 |
| Test name | |
| Test status | |
| Simulation time | 4000758958 ps |
| CPU time | 18.4 seconds |
| Started | Sep 01 02:49:53 PM UTC 24 |
| Finished | Sep 01 02:50:12 PM UTC 24 |
| Peak memory | 251412 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1548302027 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_31/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_pass_addr_payload_swap.1548302027 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/9.spi_device_pass_addr_payload_swap/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/9.spi_device_pass_cmd_filtering.971814378 |
| Short name | T293 |
| Test name | |
| Test status | |
| Simulation time | 215779049 ps |
| CPU time | 6.91 seconds |
| Started | Sep 01 02:49:51 PM UTC 24 |
| Finished | Sep 01 02:49:59 PM UTC 24 |
| Peak memory | 245332 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=971814378 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _08_31/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_pass_cmd_filtering.971814378 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/9.spi_device_pass_cmd_filtering/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/9.spi_device_read_buffer_direct.388643257 |
| Short name | T428 |
| Test name | |
| Test status | |
| Simulation time | 1615311929 ps |
| CPU time | 9.46 seconds |
| Started | Sep 01 02:50:01 PM UTC 24 |
| Finished | Sep 01 02:50:12 PM UTC 24 |
| Peak memory | 233368 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=388643257 -assert nopostproc +UVM_TESTNAME=spi_device_ base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_read_buffer_direct.388643257 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/9.spi_device_read_buffer_direct/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/9.spi_device_stress_all.1111446854 |
| Short name | T263 |
| Test name | |
| Test status | |
| Simulation time | 437456949336 ps |
| CPU time | 331 seconds |
| Started | Sep 01 02:50:10 PM UTC 24 |
| Finished | Sep 01 02:55:45 PM UTC 24 |
| Peak memory | 251528 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1111446854 -assert nopostproc +UVM_ TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_stress_all.1111446854 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/9.spi_device_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/9.spi_device_tpm_all.1084146595 |
| Short name | T387 |
| Test name | |
| Test status | |
| Simulation time | 34159978017 ps |
| CPU time | 70.97 seconds |
| Started | Sep 01 02:49:46 PM UTC 24 |
| Finished | Sep 01 02:50:59 PM UTC 24 |
| Peak memory | 227552 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1084146595 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_all.1084146595 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/9.spi_device_tpm_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/9.spi_device_tpm_read_hw_reg.2737855394 |
| Short name | T427 |
| Test name | |
| Test status | |
| Simulation time | 455696964 ps |
| CPU time | 3.77 seconds |
| Started | Sep 01 02:49:45 PM UTC 24 |
| Finished | Sep 01 02:49:50 PM UTC 24 |
| Peak memory | 227392 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2737855394 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_31/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_read_hw_reg.2737855394 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/9.spi_device_tpm_read_hw_reg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/9.spi_device_tpm_rw.665777169 |
| Short name | T393 |
| Test name | |
| Test status | |
| Simulation time | 97718304 ps |
| CPU time | 1.93 seconds |
| Started | Sep 01 02:49:51 PM UTC 24 |
| Finished | Sep 01 02:49:54 PM UTC 24 |
| Peak memory | 216388 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=665777169 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/spi_d evice_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_rw.665777169 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/9.spi_device_tpm_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/9.spi_device_tpm_sts_read.264758 |
| Short name | T426 |
| Test name | |
| Test status | |
| Simulation time | 39547493 ps |
| CPU time | 1.4 seconds |
| Started | Sep 01 02:49:47 PM UTC 24 |
| Finished | Sep 01 02:49:50 PM UTC 24 |
| Peak memory | 215860 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=264758 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UV M_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/sp i_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_sts_read.264758 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/9.spi_device_tpm_sts_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/9.spi_device_upload.2765345397 |
| Short name | T316 |
| Test name | |
| Test status | |
| Simulation time | 630225813 ps |
| CPU time | 4.65 seconds |
| Started | Sep 01 02:49:58 PM UTC 24 |
| Finished | Sep 01 02:50:04 PM UTC 24 |
| Peak memory | 234904 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2765345397 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_upload.2765345397 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/9.spi_device_upload/latest |
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