| T838 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/41.spi_device_cfg_cmd.1547537694 |
|
|
Sep 01 03:03:18 PM UTC 24 |
Sep 01 03:03:23 PM UTC 24 |
86248533 ps |
| T839 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/39.spi_device_pass_cmd_filtering.4256781384 |
|
|
Sep 01 03:02:35 PM UTC 24 |
Sep 01 03:03:23 PM UTC 24 |
31463784831 ps |
| T840 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/40.spi_device_mailbox.1689164690 |
|
|
Sep 01 03:02:56 PM UTC 24 |
Sep 01 03:03:23 PM UTC 24 |
2014942205 ps |
| T841 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/41.spi_device_alert_test.1462317399 |
|
|
Sep 01 03:03:23 PM UTC 24 |
Sep 01 03:03:25 PM UTC 24 |
32750563 ps |
| T842 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/41.spi_device_tpm_all.1804810646 |
|
|
Sep 01 03:03:11 PM UTC 24 |
Sep 01 03:03:26 PM UTC 24 |
4070887303 ps |
| T380 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/40.spi_device_flash_mode.837222036 |
|
|
Sep 01 03:03:00 PM UTC 24 |
Sep 01 03:03:26 PM UTC 24 |
10285353365 ps |
| T843 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/42.spi_device_csb_read.319261923 |
|
|
Sep 01 03:03:24 PM UTC 24 |
Sep 01 03:03:27 PM UTC 24 |
49974387 ps |
| T844 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/41.spi_device_pass_cmd_filtering.3968630064 |
|
|
Sep 01 03:03:13 PM UTC 24 |
Sep 01 03:03:27 PM UTC 24 |
3076932197 ps |
| T845 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/41.spi_device_pass_addr_payload_swap.2298879325 |
|
|
Sep 01 03:03:13 PM UTC 24 |
Sep 01 03:03:27 PM UTC 24 |
1123190914 ps |
| T846 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/42.spi_device_tpm_sts_read.1105600477 |
|
|
Sep 01 03:03:26 PM UTC 24 |
Sep 01 03:03:28 PM UTC 24 |
117963843 ps |
| T847 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/42.spi_device_tpm_all.3587571011 |
|
|
Sep 01 03:03:25 PM UTC 24 |
Sep 01 03:03:28 PM UTC 24 |
883291091 ps |
| T848 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/42.spi_device_tpm_read_hw_reg.3331318911 |
|
|
Sep 01 03:03:25 PM UTC 24 |
Sep 01 03:03:29 PM UTC 24 |
3133086177 ps |
| T849 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/41.spi_device_flash_mode.2057359304 |
|
|
Sep 01 03:03:18 PM UTC 24 |
Sep 01 03:03:29 PM UTC 24 |
592682142 ps |
| T850 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/42.spi_device_pass_addr_payload_swap.1952871076 |
|
|
Sep 01 03:03:27 PM UTC 24 |
Sep 01 03:03:32 PM UTC 24 |
231374915 ps |
| T851 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/42.spi_device_tpm_rw.1417183546 |
|
|
Sep 01 03:03:27 PM UTC 24 |
Sep 01 03:03:33 PM UTC 24 |
362740576 ps |
| T217 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/42.spi_device_upload.2907528168 |
|
|
Sep 01 03:03:29 PM UTC 24 |
Sep 01 03:03:33 PM UTC 24 |
1661534721 ps |
| T852 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/36.spi_device_flash_and_tpm.2314931836 |
|
|
Sep 01 03:01:48 PM UTC 24 |
Sep 01 03:03:35 PM UTC 24 |
6808741381 ps |
| T853 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/40.spi_device_tpm_all.3859372884 |
|
|
Sep 01 03:02:51 PM UTC 24 |
Sep 01 03:03:37 PM UTC 24 |
26396450737 ps |
| T854 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/42.spi_device_cfg_cmd.3914755900 |
|
|
Sep 01 03:03:29 PM UTC 24 |
Sep 01 03:03:39 PM UTC 24 |
1797934556 ps |
| T855 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/31.spi_device_stress_all.1850766737 |
|
|
Sep 01 03:00:00 PM UTC 24 |
Sep 01 03:03:40 PM UTC 24 |
19411918139 ps |
| T856 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/42.spi_device_alert_test.923631772 |
|
|
Sep 01 03:03:38 PM UTC 24 |
Sep 01 03:03:40 PM UTC 24 |
49146160 ps |
| T857 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/34.spi_device_flash_all.1221470572 |
|
|
Sep 01 03:01:07 PM UTC 24 |
Sep 01 03:03:41 PM UTC 24 |
19741266138 ps |
| T858 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/42.spi_device_mailbox.2439906967 |
|
|
Sep 01 03:03:29 PM UTC 24 |
Sep 01 03:03:41 PM UTC 24 |
1462740377 ps |
| T859 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/41.spi_device_flash_all.3952293241 |
|
|
Sep 01 03:03:21 PM UTC 24 |
Sep 01 03:03:42 PM UTC 24 |
4490023813 ps |
| T860 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/38.spi_device_flash_all.3620427551 |
|
|
Sep 01 03:02:21 PM UTC 24 |
Sep 01 03:03:43 PM UTC 24 |
6652168722 ps |
| T861 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/43.spi_device_csb_read.2203329117 |
|
|
Sep 01 03:03:41 PM UTC 24 |
Sep 01 03:03:43 PM UTC 24 |
28364487 ps |
| T862 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/42.spi_device_pass_cmd_filtering.3459938523 |
|
|
Sep 01 03:03:27 PM UTC 24 |
Sep 01 03:03:44 PM UTC 24 |
16188016577 ps |
| T863 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/43.spi_device_tpm_rw.3168752931 |
|
|
Sep 01 03:03:43 PM UTC 24 |
Sep 01 03:03:45 PM UTC 24 |
12745939 ps |
| T864 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/43.spi_device_tpm_sts_read.2467730500 |
|
|
Sep 01 03:03:43 PM UTC 24 |
Sep 01 03:03:45 PM UTC 24 |
42231005 ps |
| T865 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/41.spi_device_read_buffer_direct.2315831942 |
|
|
Sep 01 03:03:21 PM UTC 24 |
Sep 01 03:03:45 PM UTC 24 |
1309688027 ps |
| T866 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/43.spi_device_intercept.888664302 |
|
|
Sep 01 03:03:44 PM UTC 24 |
Sep 01 03:03:48 PM UTC 24 |
94033785 ps |
| T320 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/43.spi_device_pass_addr_payload_swap.2661968835 |
|
|
Sep 01 03:03:44 PM UTC 24 |
Sep 01 03:03:50 PM UTC 24 |
294642826 ps |
| T867 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/43.spi_device_cfg_cmd.4160424571 |
|
|
Sep 01 03:03:46 PM UTC 24 |
Sep 01 03:03:53 PM UTC 24 |
1477152434 ps |
| T868 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/43.spi_device_upload.3255933095 |
|
|
Sep 01 03:03:46 PM UTC 24 |
Sep 01 03:03:53 PM UTC 24 |
329664480 ps |
| T869 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/43.spi_device_flash_mode.2857874718 |
|
|
Sep 01 03:03:47 PM UTC 24 |
Sep 01 03:03:53 PM UTC 24 |
212448544 ps |
| T870 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/39.spi_device_stress_all.2366587710 |
|
|
Sep 01 03:02:47 PM UTC 24 |
Sep 01 03:03:58 PM UTC 24 |
17486659113 ps |
| T871 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/36.spi_device_flash_all.3723762550 |
|
|
Sep 01 03:01:46 PM UTC 24 |
Sep 01 03:03:58 PM UTC 24 |
9336142461 ps |
| T872 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/42.spi_device_read_buffer_direct.894121042 |
|
|
Sep 01 03:03:33 PM UTC 24 |
Sep 01 03:03:59 PM UTC 24 |
1490931409 ps |
| T873 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/43.spi_device_tpm_read_hw_reg.3984150735 |
|
|
Sep 01 03:03:41 PM UTC 24 |
Sep 01 03:04:00 PM UTC 24 |
2312912088 ps |
| T378 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/42.spi_device_flash_mode.1887116534 |
|
|
Sep 01 03:03:30 PM UTC 24 |
Sep 01 03:04:01 PM UTC 24 |
2553341340 ps |
| T874 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/41.spi_device_upload.304165008 |
|
|
Sep 01 03:03:18 PM UTC 24 |
Sep 01 03:04:01 PM UTC 24 |
49505476418 ps |
| T875 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/43.spi_device_alert_test.3451517552 |
|
|
Sep 01 03:03:59 PM UTC 24 |
Sep 01 03:04:01 PM UTC 24 |
39861310 ps |
| T876 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/37.spi_device_flash_and_tpm.3030873733 |
|
|
Sep 01 03:02:08 PM UTC 24 |
Sep 01 03:04:01 PM UTC 24 |
7020650795 ps |
| T877 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/43.spi_device_stress_all.514723569 |
|
|
Sep 01 03:03:59 PM UTC 24 |
Sep 01 03:04:02 PM UTC 24 |
45191116 ps |
| T878 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/43.spi_device_tpm_all.736814132 |
|
|
Sep 01 03:03:41 PM UTC 24 |
Sep 01 03:04:02 PM UTC 24 |
3738996086 ps |
| T879 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/43.spi_device_read_buffer_direct.4084414646 |
|
|
Sep 01 03:03:51 PM UTC 24 |
Sep 01 03:04:03 PM UTC 24 |
11875912523 ps |
| T880 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/44.spi_device_csb_read.1842656205 |
|
|
Sep 01 03:04:01 PM UTC 24 |
Sep 01 03:04:03 PM UTC 24 |
42693957 ps |
| T881 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/43.spi_device_flash_and_tpm_min_idle.1229628888 |
|
|
Sep 01 03:03:55 PM UTC 24 |
Sep 01 03:04:03 PM UTC 24 |
728004112 ps |
| T882 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/44.spi_device_tpm_all.108619323 |
|
|
Sep 01 03:04:03 PM UTC 24 |
Sep 01 03:04:05 PM UTC 24 |
53441018 ps |
| T883 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/44.spi_device_tpm_sts_read.1869368300 |
|
|
Sep 01 03:04:03 PM UTC 24 |
Sep 01 03:04:05 PM UTC 24 |
179344512 ps |
| T884 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/44.spi_device_tpm_rw.2080129154 |
|
|
Sep 01 03:04:03 PM UTC 24 |
Sep 01 03:04:08 PM UTC 24 |
58314222 ps |
| T885 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/44.spi_device_flash_mode_ignore_cmds.1748043804 |
|
|
Sep 01 03:04:06 PM UTC 24 |
Sep 01 03:04:08 PM UTC 24 |
20470766 ps |
| T886 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/44.spi_device_cfg_cmd.3725812132 |
|
|
Sep 01 03:04:05 PM UTC 24 |
Sep 01 03:04:09 PM UTC 24 |
62764891 ps |
| T887 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/44.spi_device_flash_mode.4079518428 |
|
|
Sep 01 03:04:06 PM UTC 24 |
Sep 01 03:04:11 PM UTC 24 |
84243300 ps |
| T888 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/44.spi_device_intercept.515076352 |
|
|
Sep 01 03:04:04 PM UTC 24 |
Sep 01 03:04:13 PM UTC 24 |
548603063 ps |
| T889 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/43.spi_device_pass_cmd_filtering.1987659666 |
|
|
Sep 01 03:03:44 PM UTC 24 |
Sep 01 03:04:13 PM UTC 24 |
15997598067 ps |
| T890 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/41.spi_device_mailbox.51439608 |
|
|
Sep 01 03:03:16 PM UTC 24 |
Sep 01 03:04:14 PM UTC 24 |
6890316904 ps |
| T891 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/44.spi_device_read_buffer_direct.806965395 |
|
|
Sep 01 03:04:08 PM UTC 24 |
Sep 01 03:04:15 PM UTC 24 |
181337500 ps |
| T892 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/44.spi_device_alert_test.3718534428 |
|
|
Sep 01 03:04:14 PM UTC 24 |
Sep 01 03:04:16 PM UTC 24 |
14094193 ps |
| T893 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/45.spi_device_csb_read.540387417 |
|
|
Sep 01 03:04:16 PM UTC 24 |
Sep 01 03:04:18 PM UTC 24 |
14826043 ps |
| T894 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/45.spi_device_tpm_read_hw_reg.1385443938 |
|
|
Sep 01 03:04:16 PM UTC 24 |
Sep 01 03:04:18 PM UTC 24 |
45442563 ps |
| T160 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/39.spi_device_flash_and_tpm_min_idle.3667142481 |
|
|
Sep 01 03:02:44 PM UTC 24 |
Sep 01 03:04:18 PM UTC 24 |
10340014501 ps |
| T895 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/45.spi_device_tpm_all.3325377793 |
|
|
Sep 01 03:04:17 PM UTC 24 |
Sep 01 03:04:19 PM UTC 24 |
34193850 ps |
| T896 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/42.spi_device_flash_mode_ignore_cmds.701030987 |
|
|
Sep 01 03:03:30 PM UTC 24 |
Sep 01 03:04:20 PM UTC 24 |
19008821092 ps |
| T897 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/44.spi_device_pass_addr_payload_swap.2510458943 |
|
|
Sep 01 03:04:03 PM UTC 24 |
Sep 01 03:04:20 PM UTC 24 |
10600814081 ps |
| T898 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/45.spi_device_tpm_sts_read.2848600456 |
|
|
Sep 01 03:04:19 PM UTC 24 |
Sep 01 03:04:21 PM UTC 24 |
29749187 ps |
| T899 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/45.spi_device_tpm_rw.3721462410 |
|
|
Sep 01 03:04:19 PM UTC 24 |
Sep 01 03:04:22 PM UTC 24 |
17986849 ps |
| T900 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/44.spi_device_tpm_read_hw_reg.2609742967 |
|
|
Sep 01 03:04:01 PM UTC 24 |
Sep 01 03:04:23 PM UTC 24 |
5320917424 ps |
| T901 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/45.spi_device_pass_addr_payload_swap.3874597690 |
|
|
Sep 01 03:04:20 PM UTC 24 |
Sep 01 03:04:24 PM UTC 24 |
873147834 ps |
| T902 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/45.spi_device_pass_cmd_filtering.2350546360 |
|
|
Sep 01 03:04:20 PM UTC 24 |
Sep 01 03:04:26 PM UTC 24 |
224922285 ps |
| T903 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/44.spi_device_upload.3372986694 |
|
|
Sep 01 03:04:05 PM UTC 24 |
Sep 01 03:04:29 PM UTC 24 |
1091354807 ps |
| T904 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/16.spi_device_flash_and_tpm_min_idle.1517160826 |
|
|
Sep 01 02:53:43 PM UTC 24 |
Sep 01 03:04:29 PM UTC 24 |
222175899967 ps |
| T905 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/45.spi_device_flash_mode.1365284502 |
|
|
Sep 01 03:04:25 PM UTC 24 |
Sep 01 03:04:29 PM UTC 24 |
111167565 ps |
| T906 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/45.spi_device_intercept.3408659331 |
|
|
Sep 01 03:04:21 PM UTC 24 |
Sep 01 03:04:31 PM UTC 24 |
2364114152 ps |
| T907 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/44.spi_device_mailbox.2787825158 |
|
|
Sep 01 03:04:04 PM UTC 24 |
Sep 01 03:04:31 PM UTC 24 |
9259584982 ps |
| T908 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/45.spi_device_cfg_cmd.3248839152 |
|
|
Sep 01 03:04:22 PM UTC 24 |
Sep 01 03:04:34 PM UTC 24 |
3100477086 ps |
| T909 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/45.spi_device_read_buffer_direct.1818003441 |
|
|
Sep 01 03:04:27 PM UTC 24 |
Sep 01 03:04:35 PM UTC 24 |
177332537 ps |
| T910 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/45.spi_device_alert_test.2735805809 |
|
|
Sep 01 03:04:32 PM UTC 24 |
Sep 01 03:04:35 PM UTC 24 |
40866136 ps |
| T911 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/45.spi_device_stress_all.1459719588 |
|
|
Sep 01 03:04:32 PM UTC 24 |
Sep 01 03:04:35 PM UTC 24 |
61118483 ps |
| T912 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/46.spi_device_csb_read.731861420 |
|
|
Sep 01 03:04:35 PM UTC 24 |
Sep 01 03:04:38 PM UTC 24 |
60715344 ps |
| T913 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/46.spi_device_tpm_read_hw_reg.4194339598 |
|
|
Sep 01 03:04:35 PM UTC 24 |
Sep 01 03:04:38 PM UTC 24 |
37925516 ps |
| T914 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/41.spi_device_stress_all.594909236 |
|
|
Sep 01 03:03:23 PM UTC 24 |
Sep 01 03:04:38 PM UTC 24 |
3796409645 ps |
| T915 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/46.spi_device_tpm_sts_read.2562932203 |
|
|
Sep 01 03:04:37 PM UTC 24 |
Sep 01 03:04:39 PM UTC 24 |
45169853 ps |
| T916 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/46.spi_device_tpm_rw.1838236035 |
|
|
Sep 01 03:04:39 PM UTC 24 |
Sep 01 03:04:42 PM UTC 24 |
95671507 ps |
| T917 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/44.spi_device_pass_cmd_filtering.993806768 |
|
|
Sep 01 03:04:03 PM UTC 24 |
Sep 01 03:04:47 PM UTC 24 |
17144443088 ps |
| T918 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/46.spi_device_pass_addr_payload_swap.2421992892 |
|
|
Sep 01 03:04:39 PM UTC 24 |
Sep 01 03:04:47 PM UTC 24 |
3393174595 ps |
| T358 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/36.spi_device_stress_all.1746595453 |
|
|
Sep 01 03:01:50 PM UTC 24 |
Sep 01 03:04:48 PM UTC 24 |
68459291607 ps |
| T919 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/38.spi_device_stress_all.3789416008 |
|
|
Sep 01 03:02:26 PM UTC 24 |
Sep 01 03:04:49 PM UTC 24 |
8388298579 ps |
| T920 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/46.spi_device_intercept.1815149411 |
|
|
Sep 01 03:04:41 PM UTC 24 |
Sep 01 03:04:51 PM UTC 24 |
290548431 ps |
| T921 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/45.spi_device_upload.1644450938 |
|
|
Sep 01 03:04:22 PM UTC 24 |
Sep 01 03:04:52 PM UTC 24 |
4532402888 ps |
| T351 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/14.spi_device_stress_all.861575515 |
|
|
Sep 01 02:52:35 PM UTC 24 |
Sep 01 03:04:55 PM UTC 24 |
351339092964 ps |
| T922 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/46.spi_device_cfg_cmd.3609456661 |
|
|
Sep 01 03:04:48 PM UTC 24 |
Sep 01 03:04:59 PM UTC 24 |
3392133555 ps |
| T923 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/46.spi_device_mailbox.2625758155 |
|
|
Sep 01 03:04:43 PM UTC 24 |
Sep 01 03:05:01 PM UTC 24 |
1564753220 ps |
| T924 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/23.spi_device_flash_mode_ignore_cmds.1771044391 |
|
|
Sep 01 02:57:04 PM UTC 24 |
Sep 01 03:05:04 PM UTC 24 |
583685217066 ps |
| T925 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/46.spi_device_alert_test.2876338347 |
|
|
Sep 01 03:05:02 PM UTC 24 |
Sep 01 03:05:04 PM UTC 24 |
51314187 ps |
| T926 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/46.spi_device_pass_cmd_filtering.18676032 |
|
|
Sep 01 03:04:39 PM UTC 24 |
Sep 01 03:05:07 PM UTC 24 |
3557346811 ps |
| T927 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/47.spi_device_csb_read.3993969976 |
|
|
Sep 01 03:05:05 PM UTC 24 |
Sep 01 03:05:07 PM UTC 24 |
38641966 ps |
| T928 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/47.spi_device_tpm_sts_read.3604647938 |
|
|
Sep 01 03:05:09 PM UTC 24 |
Sep 01 03:05:11 PM UTC 24 |
48980987 ps |
| T929 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/47.spi_device_tpm_read_hw_reg.615086384 |
|
|
Sep 01 03:05:05 PM UTC 24 |
Sep 01 03:05:12 PM UTC 24 |
818705849 ps |
| T930 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/46.spi_device_read_buffer_direct.1062394651 |
|
|
Sep 01 03:04:52 PM UTC 24 |
Sep 01 03:05:13 PM UTC 24 |
1131542091 ps |
| T241 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/10.spi_device_flash_and_tpm.3927801901 |
|
|
Sep 01 02:50:34 PM UTC 24 |
Sep 01 03:05:14 PM UTC 24 |
66628108211 ps |
| T931 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/47.spi_device_tpm_rw.362153974 |
|
|
Sep 01 03:05:12 PM UTC 24 |
Sep 01 03:05:15 PM UTC 24 |
83661245 ps |
| T932 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/47.spi_device_pass_cmd_filtering.3535203816 |
|
|
Sep 01 03:05:13 PM UTC 24 |
Sep 01 03:05:18 PM UTC 24 |
112086935 ps |
| T933 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/46.spi_device_upload.1843833558 |
|
|
Sep 01 03:04:48 PM UTC 24 |
Sep 01 03:05:19 PM UTC 24 |
6015598582 ps |
| T934 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/47.spi_device_pass_addr_payload_swap.934907282 |
|
|
Sep 01 03:05:14 PM UTC 24 |
Sep 01 03:05:21 PM UTC 24 |
1470525221 ps |
| T935 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/47.spi_device_intercept.872216649 |
|
|
Sep 01 03:05:16 PM UTC 24 |
Sep 01 03:05:24 PM UTC 24 |
523181309 ps |
| T936 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/44.spi_device_flash_and_tpm.331965835 |
|
|
Sep 01 03:04:10 PM UTC 24 |
Sep 01 03:05:29 PM UTC 24 |
8616945818 ps |
| T937 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/47.spi_device_upload.2191935474 |
|
|
Sep 01 03:05:19 PM UTC 24 |
Sep 01 03:05:30 PM UTC 24 |
435351369 ps |
| T218 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/47.spi_device_cfg_cmd.3776792791 |
|
|
Sep 01 03:05:20 PM UTC 24 |
Sep 01 03:05:33 PM UTC 24 |
650629654 ps |
| T938 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/47.spi_device_read_buffer_direct.1998760929 |
|
|
Sep 01 03:05:30 PM UTC 24 |
Sep 01 03:05:36 PM UTC 24 |
680318657 ps |
| T939 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/41.spi_device_flash_and_tpm.24266252 |
|
|
Sep 01 03:03:23 PM UTC 24 |
Sep 01 03:05:38 PM UTC 24 |
66844609197 ps |
| T369 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/34.spi_device_stress_all.642415043 |
|
|
Sep 01 03:01:09 PM UTC 24 |
Sep 01 03:05:39 PM UTC 24 |
21626152624 ps |
| T242 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/33.spi_device_flash_and_tpm_min_idle.2648792039 |
|
|
Sep 01 03:00:46 PM UTC 24 |
Sep 01 03:05:41 PM UTC 24 |
19882640061 ps |
| T940 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/46.spi_device_flash_mode_ignore_cmds.3706735117 |
|
|
Sep 01 03:04:51 PM UTC 24 |
Sep 01 03:05:41 PM UTC 24 |
3042217656 ps |
| T941 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/46.spi_device_tpm_all.4266787908 |
|
|
Sep 01 03:04:36 PM UTC 24 |
Sep 01 03:05:42 PM UTC 24 |
18406834787 ps |
| T942 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/47.spi_device_alert_test.2698530030 |
|
|
Sep 01 03:05:40 PM UTC 24 |
Sep 01 03:05:42 PM UTC 24 |
38023981 ps |
| T943 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/48.spi_device_csb_read.3042793928 |
|
|
Sep 01 03:05:42 PM UTC 24 |
Sep 01 03:05:44 PM UTC 24 |
92028521 ps |
| T944 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/48.spi_device_tpm_sts_read.1531665108 |
|
|
Sep 01 03:05:43 PM UTC 24 |
Sep 01 03:05:45 PM UTC 24 |
127017027 ps |
| T945 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/48.spi_device_tpm_rw.1791493607 |
|
|
Sep 01 03:05:44 PM UTC 24 |
Sep 01 03:05:47 PM UTC 24 |
20356015 ps |
| T946 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/47.spi_device_flash_mode.4127294251 |
|
|
Sep 01 03:05:22 PM UTC 24 |
Sep 01 03:05:50 PM UTC 24 |
1084362434 ps |
| T185 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/44.spi_device_stress_all.1028937945 |
|
|
Sep 01 03:04:14 PM UTC 24 |
Sep 01 03:05:52 PM UTC 24 |
12061286313 ps |
| T947 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/46.spi_device_flash_mode.1270340659 |
|
|
Sep 01 03:04:49 PM UTC 24 |
Sep 01 03:05:52 PM UTC 24 |
3022651031 ps |
| T948 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/48.spi_device_pass_addr_payload_swap.110293355 |
|
|
Sep 01 03:05:48 PM UTC 24 |
Sep 01 03:05:52 PM UTC 24 |
106387035 ps |
| T949 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/45.spi_device_flash_all.2311236008 |
|
|
Sep 01 03:04:29 PM UTC 24 |
Sep 01 03:05:53 PM UTC 24 |
7784688392 ps |
| T363 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/43.spi_device_flash_and_tpm.1735551154 |
|
|
Sep 01 03:03:54 PM UTC 24 |
Sep 01 03:05:55 PM UTC 24 |
180563854226 ps |
| T245 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/40.spi_device_flash_all.1995322717 |
|
|
Sep 01 03:03:05 PM UTC 24 |
Sep 01 03:05:56 PM UTC 24 |
97166856387 ps |
| T950 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/48.spi_device_intercept.2328596738 |
|
|
Sep 01 03:05:51 PM UTC 24 |
Sep 01 03:05:56 PM UTC 24 |
43871953 ps |
| T951 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/48.spi_device_mailbox.1796585154 |
|
|
Sep 01 03:05:53 PM UTC 24 |
Sep 01 03:05:57 PM UTC 24 |
156601739 ps |
| T952 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/47.spi_device_flash_mode_ignore_cmds.3266579145 |
|
|
Sep 01 03:05:25 PM UTC 24 |
Sep 01 03:05:57 PM UTC 24 |
2937481886 ps |
| T953 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/48.spi_device_tpm_read_hw_reg.4262098094 |
|
|
Sep 01 03:05:42 PM UTC 24 |
Sep 01 03:05:58 PM UTC 24 |
4902822550 ps |
| T954 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/48.spi_device_upload.3371604493 |
|
|
Sep 01 03:05:53 PM UTC 24 |
Sep 01 03:05:59 PM UTC 24 |
1472638514 ps |
| T955 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/48.spi_device_flash_mode.2694568163 |
|
|
Sep 01 03:05:54 PM UTC 24 |
Sep 01 03:06:00 PM UTC 24 |
79644943 ps |
| T956 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/48.spi_device_cfg_cmd.3081801829 |
|
|
Sep 01 03:05:54 PM UTC 24 |
Sep 01 03:06:01 PM UTC 24 |
198980755 ps |
| T957 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/48.spi_device_alert_test.1669841157 |
|
|
Sep 01 03:06:00 PM UTC 24 |
Sep 01 03:06:02 PM UTC 24 |
172788544 ps |
| T958 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/43.spi_device_mailbox.3095266419 |
|
|
Sep 01 03:03:46 PM UTC 24 |
Sep 01 03:06:03 PM UTC 24 |
57416967898 ps |
| T959 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/49.spi_device_csb_read.4155083136 |
|
|
Sep 01 03:06:01 PM UTC 24 |
Sep 01 03:06:04 PM UTC 24 |
18213741 ps |
| T960 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/49.spi_device_tpm_read_hw_reg.1823521577 |
|
|
Sep 01 03:06:02 PM UTC 24 |
Sep 01 03:06:05 PM UTC 24 |
43890470 ps |
| T961 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/48.spi_device_tpm_all.1941120042 |
|
|
Sep 01 03:05:43 PM UTC 24 |
Sep 01 03:06:05 PM UTC 24 |
2824152112 ps |
| T962 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/49.spi_device_tpm_sts_read.59769410 |
|
|
Sep 01 03:06:04 PM UTC 24 |
Sep 01 03:06:06 PM UTC 24 |
106812943 ps |
| T963 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/49.spi_device_tpm_rw.446032883 |
|
|
Sep 01 03:06:05 PM UTC 24 |
Sep 01 03:06:08 PM UTC 24 |
100263276 ps |
| T964 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/48.spi_device_read_buffer_direct.3373419412 |
|
|
Sep 01 03:05:57 PM UTC 24 |
Sep 01 03:06:10 PM UTC 24 |
2580639042 ps |
| T965 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/47.spi_device_tpm_all.2324421296 |
|
|
Sep 01 03:05:07 PM UTC 24 |
Sep 01 03:06:11 PM UTC 24 |
113060893820 ps |
| T966 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/45.spi_device_mailbox.2705138854 |
|
|
Sep 01 03:04:21 PM UTC 24 |
Sep 01 03:06:12 PM UTC 24 |
12411831463 ps |
| T967 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/47.spi_device_flash_and_tpm_min_idle.1143063257 |
|
|
Sep 01 03:05:38 PM UTC 24 |
Sep 01 03:06:12 PM UTC 24 |
6646084815 ps |
| T968 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/49.spi_device_intercept.2543089670 |
|
|
Sep 01 03:06:08 PM UTC 24 |
Sep 01 03:06:12 PM UTC 24 |
72042485 ps |
| T969 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/49.spi_device_pass_addr_payload_swap.3056209269 |
|
|
Sep 01 03:06:06 PM UTC 24 |
Sep 01 03:06:13 PM UTC 24 |
414694622 ps |
| T970 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/44.spi_device_flash_all.2689396056 |
|
|
Sep 01 03:04:10 PM UTC 24 |
Sep 01 03:06:13 PM UTC 24 |
21485576657 ps |
| T971 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/49.spi_device_flash_mode.1972336057 |
|
|
Sep 01 03:06:13 PM UTC 24 |
Sep 01 03:06:19 PM UTC 24 |
89895820 ps |
| T972 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/46.spi_device_flash_and_tpm.1902212518 |
|
|
Sep 01 03:04:56 PM UTC 24 |
Sep 01 03:06:21 PM UTC 24 |
4118326076 ps |
| T973 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/49.spi_device_read_buffer_direct.1908021975 |
|
|
Sep 01 03:06:13 PM UTC 24 |
Sep 01 03:06:21 PM UTC 24 |
586066651 ps |
| T974 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/49.spi_device_alert_test.989592988 |
|
|
Sep 01 03:06:22 PM UTC 24 |
Sep 01 03:06:25 PM UTC 24 |
12254593 ps |
| T975 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/49.spi_device_upload.1120843973 |
|
|
Sep 01 03:06:11 PM UTC 24 |
Sep 01 03:06:25 PM UTC 24 |
6372601448 ps |
| T976 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/29.spi_device_flash_and_tpm.1541946209 |
|
|
Sep 01 02:59:15 PM UTC 24 |
Sep 01 03:06:26 PM UTC 24 |
35177872033 ps |
| T977 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/42.spi_device_flash_all.4185389472 |
|
|
Sep 01 03:03:34 PM UTC 24 |
Sep 01 03:06:27 PM UTC 24 |
17481173909 ps |
| T222 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/48.spi_device_pass_cmd_filtering.2957422778 |
|
|
Sep 01 03:05:47 PM UTC 24 |
Sep 01 03:06:28 PM UTC 24 |
29240366796 ps |
| T978 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/49.spi_device_mailbox.2899526777 |
|
|
Sep 01 03:06:10 PM UTC 24 |
Sep 01 03:06:30 PM UTC 24 |
1443309871 ps |
| T161 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/38.spi_device_flash_and_tpm.2639667440 |
|
|
Sep 01 03:02:22 PM UTC 24 |
Sep 01 03:06:30 PM UTC 24 |
91084988243 ps |
| T229 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/47.spi_device_flash_all.210789387 |
|
|
Sep 01 03:05:31 PM UTC 24 |
Sep 01 03:06:31 PM UTC 24 |
70360202935 ps |
| T979 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/49.spi_device_pass_cmd_filtering.2887842739 |
|
|
Sep 01 03:06:06 PM UTC 24 |
Sep 01 03:06:31 PM UTC 24 |
14734076774 ps |
| T980 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/49.spi_device_cfg_cmd.625858392 |
|
|
Sep 01 03:06:13 PM UTC 24 |
Sep 01 03:06:33 PM UTC 24 |
6964938294 ps |
| T981 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/46.spi_device_flash_and_tpm_min_idle.3137035596 |
|
|
Sep 01 03:04:56 PM UTC 24 |
Sep 01 03:06:33 PM UTC 24 |
17336573086 ps |
| T352 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/43.spi_device_flash_all.1845372178 |
|
|
Sep 01 03:03:54 PM UTC 24 |
Sep 01 03:06:34 PM UTC 24 |
31892626792 ps |
| T365 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/32.spi_device_stress_all.18033698 |
|
|
Sep 01 03:00:22 PM UTC 24 |
Sep 01 03:06:38 PM UTC 24 |
35517507139 ps |
| T355 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/28.spi_device_flash_and_tpm_min_idle.4229527234 |
|
|
Sep 01 02:58:51 PM UTC 24 |
Sep 01 03:06:45 PM UTC 24 |
165985324882 ps |
| T982 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/49.spi_device_flash_and_tpm.3105671426 |
|
|
Sep 01 03:06:15 PM UTC 24 |
Sep 01 03:06:51 PM UTC 24 |
2017523531 ps |
| T983 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/49.spi_device_tpm_all.4066618371 |
|
|
Sep 01 03:06:04 PM UTC 24 |
Sep 01 03:06:52 PM UTC 24 |
24511206371 ps |
| T348 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/42.spi_device_flash_and_tpm_min_idle.2904669320 |
|
|
Sep 01 03:03:36 PM UTC 24 |
Sep 01 03:06:52 PM UTC 24 |
58154999612 ps |
| T361 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/42.spi_device_stress_all.562377159 |
|
|
Sep 01 03:03:36 PM UTC 24 |
Sep 01 03:06:56 PM UTC 24 |
13275160334 ps |
| T984 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/48.spi_device_flash_and_tpm.2046168925 |
|
|
Sep 01 03:05:58 PM UTC 24 |
Sep 01 03:07:34 PM UTC 24 |
8318064941 ps |
| T985 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/49.spi_device_flash_and_tpm_min_idle.1867290587 |
|
|
Sep 01 03:06:21 PM UTC 24 |
Sep 01 03:07:34 PM UTC 24 |
6125161044 ps |
| T986 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/24.spi_device_flash_mode_ignore_cmds.2152470944 |
|
|
Sep 01 02:57:19 PM UTC 24 |
Sep 01 03:07:35 PM UTC 24 |
147137622935 ps |
| T186 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/16.spi_device_stress_all.1031570402 |
|
|
Sep 01 02:53:45 PM UTC 24 |
Sep 01 03:07:39 PM UTC 24 |
133409850595 ps |
| T987 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/39.spi_device_flash_and_tpm.1515168292 |
|
|
Sep 01 03:02:44 PM UTC 24 |
Sep 01 03:07:40 PM UTC 24 |
28993041191 ps |
| T356 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/48.spi_device_flash_all.2007583938 |
|
|
Sep 01 03:05:57 PM UTC 24 |
Sep 01 03:07:42 PM UTC 24 |
4455084351 ps |
| T988 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/40.spi_device_flash_mode_ignore_cmds.2701563031 |
|
|
Sep 01 03:03:03 PM UTC 24 |
Sep 01 03:07:45 PM UTC 24 |
23985110509 ps |
| T989 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/47.spi_device_mailbox.423383983 |
|
|
Sep 01 03:05:16 PM UTC 24 |
Sep 01 03:07:46 PM UTC 24 |
112507936473 ps |
| T990 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/48.spi_device_flash_and_tpm_min_idle.343421601 |
|
|
Sep 01 03:05:58 PM UTC 24 |
Sep 01 03:08:09 PM UTC 24 |
95818103404 ps |
| T991 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/49.spi_device_flash_all.2329297213 |
|
|
Sep 01 03:06:15 PM UTC 24 |
Sep 01 03:08:11 PM UTC 24 |
14718323998 ps |
| T992 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/48.spi_device_flash_mode_ignore_cmds.2398435824 |
|
|
Sep 01 03:05:55 PM UTC 24 |
Sep 01 03:08:14 PM UTC 24 |
50155328219 ps |
| T349 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/25.spi_device_flash_and_tpm.1216603501 |
|
|
Sep 01 02:57:47 PM UTC 24 |
Sep 01 03:08:17 PM UTC 24 |
260220245147 ps |
| T993 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/47.spi_device_flash_and_tpm.142989008 |
|
|
Sep 01 03:05:35 PM UTC 24 |
Sep 01 03:08:46 PM UTC 24 |
13130823395 ps |
| T994 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/45.spi_device_flash_and_tpm.3375535803 |
|
|
Sep 01 03:04:31 PM UTC 24 |
Sep 01 03:08:47 PM UTC 24 |
93145228752 ps |
| T219 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/45.spi_device_flash_and_tpm_min_idle.4096184602 |
|
|
Sep 01 03:04:31 PM UTC 24 |
Sep 01 03:09:01 PM UTC 24 |
17530892335 ps |
| T995 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/40.spi_device_flash_and_tpm_min_idle.559709264 |
|
|
Sep 01 03:03:07 PM UTC 24 |
Sep 01 03:09:03 PM UTC 24 |
29038278415 ps |
| T996 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/49.spi_device_flash_mode_ignore_cmds.1611798717 |
|
|
Sep 01 03:06:13 PM UTC 24 |
Sep 01 03:09:04 PM UTC 24 |
17496937885 ps |
| T997 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/46.spi_device_stress_all.554010953 |
|
|
Sep 01 03:05:00 PM UTC 24 |
Sep 01 03:09:10 PM UTC 24 |
21888800510 ps |
| T998 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/35.spi_device_stress_all.1394838606 |
|
|
Sep 01 03:01:24 PM UTC 24 |
Sep 01 03:09:16 PM UTC 24 |
89579094179 ps |
| T999 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/36.spi_device_flash_mode_ignore_cmds.75048445 |
|
|
Sep 01 03:01:42 PM UTC 24 |
Sep 01 03:09:23 PM UTC 24 |
210503988841 ps |
| T354 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/46.spi_device_flash_all.4224672195 |
|
|
Sep 01 03:04:53 PM UTC 24 |
Sep 01 03:09:33 PM UTC 24 |
46945083170 ps |
| T162 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/40.spi_device_stress_all.3400909077 |
|
|
Sep 01 03:03:07 PM UTC 24 |
Sep 01 03:09:42 PM UTC 24 |
11270397870 ps |
| T1000 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/37.spi_device_flash_and_tpm_min_idle.3696236796 |
|
|
Sep 01 03:02:10 PM UTC 24 |
Sep 01 03:09:43 PM UTC 24 |
86447175371 ps |
| T1001 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/40.spi_device_flash_and_tpm.1800856288 |
|
|
Sep 01 03:03:06 PM UTC 24 |
Sep 01 03:09:54 PM UTC 24 |
38139905760 ps |
| T1002 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/45.spi_device_flash_mode_ignore_cmds.1886294980 |
|
|
Sep 01 03:04:25 PM UTC 24 |
Sep 01 03:10:03 PM UTC 24 |
124657925988 ps |
| T1003 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/44.spi_device_flash_and_tpm_min_idle.4019010419 |
|
|
Sep 01 03:04:12 PM UTC 24 |
Sep 01 03:10:34 PM UTC 24 |
140504750533 ps |
| T362 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/32.spi_device_flash_and_tpm_min_idle.1061415877 |
|
|
Sep 01 03:00:22 PM UTC 24 |
Sep 01 03:10:41 PM UTC 24 |
107704574372 ps |
| T1004 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/49.spi_device_stress_all.3197310959 |
|
|
Sep 01 03:06:22 PM UTC 24 |
Sep 01 03:10:48 PM UTC 24 |
18037875555 ps |
| T1005 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/32.spi_device_flash_all.114004989 |
|
|
Sep 01 03:00:20 PM UTC 24 |
Sep 01 03:11:22 PM UTC 24 |
243244118662 ps |
| T1006 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/48.spi_device_stress_all.2956608925 |
|
|
Sep 01 03:06:00 PM UTC 24 |
Sep 01 03:11:29 PM UTC 24 |
175871370551 ps |
| T81 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/18.spi_device_stress_all.556485308 |
|
|
Sep 01 02:54:40 PM UTC 24 |
Sep 01 03:12:09 PM UTC 24 |
89638623619 ps |
| T1007 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/43.spi_device_flash_mode_ignore_cmds.1084057007 |
|
|
Sep 01 03:03:49 PM UTC 24 |
Sep 01 03:12:33 PM UTC 24 |
98137677594 ps |
| T1008 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/42.spi_device_flash_and_tpm.2029041080 |
|
|
Sep 01 03:03:34 PM UTC 24 |
Sep 01 03:13:17 PM UTC 24 |
382602905542 ps |
| T1009 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/41.spi_device_flash_and_tpm_min_idle.422607459 |
|
|
Sep 01 03:03:23 PM UTC 24 |
Sep 01 03:13:27 PM UTC 24 |
734194799241 ps |
| T1010 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/38.spi_device_flash_and_tpm_min_idle.2057954157 |
|
|
Sep 01 03:02:26 PM UTC 24 |
Sep 01 03:14:57 PM UTC 24 |
606650799715 ps |
| T82 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/13.spi_device_stress_all.812268968 |
|
|
Sep 01 02:52:03 PM UTC 24 |
Sep 01 03:17:44 PM UTC 24 |
579730389770 ps |
| T1011 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/47.spi_device_stress_all.69777338 |
|
|
Sep 01 03:05:39 PM UTC 24 |
Sep 01 03:20:28 PM UTC 24 |
224091255392 ps |
| T163 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/default/30.spi_device_stress_all.702945709 |
|
|
Sep 01 02:59:37 PM UTC 24 |
Sep 01 03:25:32 PM UTC 24 |
112743118812 ps |
| T1012 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/0.spi_device_intr_test.2969132724 |
|
|
Sep 01 02:44:49 PM UTC 24 |
Sep 01 02:44:51 PM UTC 24 |
12219646 ps |
| T1013 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/0.spi_device_mem_walk.634722969 |
|
|
Sep 01 02:44:49 PM UTC 24 |
Sep 01 02:44:51 PM UTC 24 |
13052801 ps |
| T106 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/0.spi_device_csr_hw_reset.4261873489 |
|
|
Sep 01 02:44:49 PM UTC 24 |
Sep 01 02:44:52 PM UTC 24 |
321930464 ps |
| T164 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/0.spi_device_csr_rw.4292893942 |
|
|
Sep 01 02:44:49 PM UTC 24 |
Sep 01 02:44:52 PM UTC 24 |
42957486 ps |
| T1014 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/1.spi_device_mem_walk.2648165938 |
|
|
Sep 01 02:44:51 PM UTC 24 |
Sep 01 02:44:53 PM UTC 24 |
15058476 ps |
| T1015 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/1.spi_device_intr_test.1737261951 |
|
|
Sep 01 02:44:51 PM UTC 24 |
Sep 01 02:44:53 PM UTC 24 |
85339568 ps |
| T138 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/0.spi_device_mem_partial_access.3201051664 |
|
|
Sep 01 02:44:49 PM UTC 24 |
Sep 01 02:44:53 PM UTC 24 |
27021220 ps |
| T1016 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/1.spi_device_csr_hw_reset.3333055544 |
|
|
Sep 01 02:44:52 PM UTC 24 |
Sep 01 02:44:55 PM UTC 24 |
114913096 ps |
| T139 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/1.spi_device_csr_rw.2665079458 |
|
|
Sep 01 02:44:52 PM UTC 24 |
Sep 01 02:44:55 PM UTC 24 |
39705806 ps |
| T140 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/7.spi_device_csr_rw.4287194450 |
|
|
Sep 01 02:45:22 PM UTC 24 |
Sep 01 02:45:27 PM UTC 24 |
72490227 ps |
| T100 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/9.spi_device_tl_errors.2369278177 |
|
|
Sep 01 02:45:27 PM UTC 24 |
Sep 01 02:45:31 PM UTC 24 |
50474058 ps |
| T141 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/1.spi_device_mem_partial_access.4279409767 |
|
|
Sep 01 02:44:52 PM UTC 24 |
Sep 01 02:44:55 PM UTC 24 |
40312200 ps |
| T101 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/0.spi_device_csr_mem_rw_with_rand_reset.4195149766 |
|
|
Sep 01 02:44:51 PM UTC 24 |
Sep 01 02:44:55 PM UTC 24 |
37008953 ps |
| T1017 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/0.spi_device_same_csr_outstanding.990749277 |
|
|
Sep 01 02:44:50 PM UTC 24 |
Sep 01 02:44:56 PM UTC 24 |
113814235 ps |
| T102 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/7.spi_device_tl_intg_err.1447512413 |
|
|
Sep 01 02:45:21 PM UTC 24 |
Sep 01 02:45:32 PM UTC 24 |
1077108814 ps |
| T116 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/0.spi_device_tl_intg_err.3991028059 |
|
|
Sep 01 02:44:49 PM UTC 24 |
Sep 01 02:44:57 PM UTC 24 |
846359141 ps |
| T1018 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/2.spi_device_mem_walk.143793853 |
|
|
Sep 01 02:44:55 PM UTC 24 |
Sep 01 02:44:57 PM UTC 24 |
12201457 ps |
| T117 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/0.spi_device_tl_errors.1422750187 |
|
|
Sep 01 02:44:49 PM UTC 24 |
Sep 01 02:44:57 PM UTC 24 |
406416053 ps |
| T1019 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/2.spi_device_intr_test.581313037 |
|
|
Sep 01 02:44:55 PM UTC 24 |
Sep 01 02:44:58 PM UTC 24 |
22229405 ps |
| T119 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/2.spi_device_tl_errors.3887399172 |
|
|
Sep 01 02:44:54 PM UTC 24 |
Sep 01 02:44:58 PM UTC 24 |
79349239 ps |
| T129 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/1.spi_device_tl_errors.1656722259 |
|
|
Sep 01 02:44:51 PM UTC 24 |
Sep 01 02:44:59 PM UTC 24 |
196509987 ps |
| T130 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/1.spi_device_csr_mem_rw_with_rand_reset.516987058 |
|
|
Sep 01 02:44:54 PM UTC 24 |
Sep 01 02:44:59 PM UTC 24 |
88904630 ps |
| T107 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/2.spi_device_csr_hw_reset.4285140900 |
|
|
Sep 01 02:44:57 PM UTC 24 |
Sep 01 02:44:59 PM UTC 24 |
55738045 ps |
| T142 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/2.spi_device_csr_rw.639235256 |
|
|
Sep 01 02:44:57 PM UTC 24 |
Sep 01 02:44:59 PM UTC 24 |
41477543 ps |
| T143 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/2.spi_device_mem_partial_access.47230495 |
|
|
Sep 01 02:44:55 PM UTC 24 |
Sep 01 02:45:00 PM UTC 24 |
133708063 ps |
| T136 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/7.spi_device_csr_mem_rw_with_rand_reset.1043366823 |
|
|
Sep 01 02:45:22 PM UTC 24 |
Sep 01 02:45:27 PM UTC 24 |
361978387 ps |
| T118 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/3.spi_device_tl_intg_err.1500950877 |
|
|
Sep 01 02:45:00 PM UTC 24 |
Sep 01 02:45:27 PM UTC 24 |
315482119 ps |
| T1020 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/1.spi_device_same_csr_outstanding.1139688222 |
|
|
Sep 01 02:44:53 PM UTC 24 |
Sep 01 02:45:01 PM UTC 24 |
1275562725 ps |
| T1021 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/3.spi_device_mem_walk.1312651578 |
|
|
Sep 01 02:45:00 PM UTC 24 |
Sep 01 02:45:02 PM UTC 24 |
34618803 ps |
| T1022 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/3.spi_device_intr_test.1291881789 |
|
|
Sep 01 02:45:00 PM UTC 24 |
Sep 01 02:45:02 PM UTC 24 |
47035361 ps |
| T170 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/9.spi_device_csr_rw.4036648803 |
|
|
Sep 01 02:45:28 PM UTC 24 |
Sep 01 02:45:32 PM UTC 24 |
89155308 ps |
| T171 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/2.spi_device_same_csr_outstanding.1266326655 |
|
|
Sep 01 02:44:59 PM UTC 24 |
Sep 01 02:45:03 PM UTC 24 |
81997353 ps |
| T144 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/3.spi_device_mem_partial_access.85917456 |
|
|
Sep 01 02:45:00 PM UTC 24 |
Sep 01 02:45:03 PM UTC 24 |
115511142 ps |
| T1023 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/0.spi_device_csr_bit_bash.1634144237 |
|
|
Sep 01 02:44:50 PM UTC 24 |
Sep 01 02:45:03 PM UTC 24 |
194647261 ps |
| T108 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/3.spi_device_csr_hw_reset.2233353687 |
|
|
Sep 01 02:45:01 PM UTC 24 |
Sep 01 02:45:04 PM UTC 24 |
19478887 ps |
| T1024 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/3.spi_device_csr_rw.4214717747 |
|
|
Sep 01 02:45:01 PM UTC 24 |
Sep 01 02:45:04 PM UTC 24 |
32853677 ps |
| T135 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/2.spi_device_csr_mem_rw_with_rand_reset.1377734656 |
|
|
Sep 01 02:44:59 PM UTC 24 |
Sep 01 02:45:05 PM UTC 24 |
95177495 ps |
| T126 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/3.spi_device_tl_errors.674278424 |
|
|
Sep 01 02:44:59 PM UTC 24 |
Sep 01 02:45:06 PM UTC 24 |
3478468554 ps |
| T1025 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/4.spi_device_intr_test.1582670557 |
|
|
Sep 01 02:45:05 PM UTC 24 |
Sep 01 02:45:07 PM UTC 24 |
16212706 ps |
| T1026 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/4.spi_device_mem_walk.4102692577 |
|
|
Sep 01 02:45:06 PM UTC 24 |
Sep 01 02:45:08 PM UTC 24 |
12670964 ps |
| T137 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/3.spi_device_csr_mem_rw_with_rand_reset.1623329688 |
|
|
Sep 01 02:45:05 PM UTC 24 |
Sep 01 02:45:10 PM UTC 24 |
559884772 ps |
| T145 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/4.spi_device_mem_partial_access.583220569 |
|
|
Sep 01 02:45:07 PM UTC 24 |
Sep 01 02:45:10 PM UTC 24 |
25798693 ps |
| T1027 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/3.spi_device_same_csr_outstanding.2414547599 |
|
|
Sep 01 02:45:04 PM UTC 24 |
Sep 01 02:45:10 PM UTC 24 |
310894343 ps |
| T109 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/4.spi_device_csr_hw_reset.368657307 |
|
|
Sep 01 02:45:08 PM UTC 24 |
Sep 01 02:45:10 PM UTC 24 |
41172418 ps |