| T643 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/29.spi_device_pass_cmd_filtering.4197380973 |
|
|
Sep 09 11:34:32 AM UTC 24 |
Sep 09 11:34:38 AM UTC 24 |
369047612 ps |
| T644 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/28.spi_device_pass_cmd_filtering.1103802995 |
|
|
Sep 09 11:34:13 AM UTC 24 |
Sep 09 11:34:38 AM UTC 24 |
14522426014 ps |
| T645 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/29.spi_device_pass_addr_payload_swap.3401929451 |
|
|
Sep 09 11:34:33 AM UTC 24 |
Sep 09 11:34:39 AM UTC 24 |
459606760 ps |
| T646 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/29.spi_device_cfg_cmd.3700954692 |
|
|
Sep 09 11:34:35 AM UTC 24 |
Sep 09 11:34:40 AM UTC 24 |
266795290 ps |
| T647 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/28.spi_device_flash_and_tpm_min_idle.1989829391 |
|
|
Sep 09 11:34:24 AM UTC 24 |
Sep 09 11:34:41 AM UTC 24 |
4416935872 ps |
| T648 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/21.spi_device_flash_and_tpm_min_idle.3998256449 |
|
|
Sep 09 11:32:52 AM UTC 24 |
Sep 09 11:34:42 AM UTC 24 |
10294491259 ps |
| T649 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/29.spi_device_intercept.1069221922 |
|
|
Sep 09 11:34:35 AM UTC 24 |
Sep 09 11:34:42 AM UTC 24 |
384533728 ps |
| T650 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/29.spi_device_read_buffer_direct.1841983229 |
|
|
Sep 09 11:34:39 AM UTC 24 |
Sep 09 11:34:45 AM UTC 24 |
69700424 ps |
| T651 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/29.spi_device_alert_test.4173428983 |
|
|
Sep 09 11:34:43 AM UTC 24 |
Sep 09 11:34:46 AM UTC 24 |
150059236 ps |
| T652 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/30.spi_device_csb_read.2366659648 |
|
|
Sep 09 11:34:44 AM UTC 24 |
Sep 09 11:34:46 AM UTC 24 |
20722592 ps |
| T653 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/27.spi_device_flash_all.2584608167 |
|
|
Sep 09 11:34:06 AM UTC 24 |
Sep 09 11:34:47 AM UTC 24 |
10480032278 ps |
| T654 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/29.spi_device_tpm_read_hw_reg.3906124120 |
|
|
Sep 09 11:34:29 AM UTC 24 |
Sep 09 11:34:47 AM UTC 24 |
20931866971 ps |
| T655 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/30.spi_device_tpm_sts_read.1067940495 |
|
|
Sep 09 11:34:47 AM UTC 24 |
Sep 09 11:34:49 AM UTC 24 |
65554027 ps |
| T656 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/30.spi_device_tpm_rw.4158336222 |
|
|
Sep 09 11:34:48 AM UTC 24 |
Sep 09 11:34:50 AM UTC 24 |
169695048 ps |
| T657 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/28.spi_device_mailbox.1541740386 |
|
|
Sep 09 11:34:16 AM UTC 24 |
Sep 09 11:34:54 AM UTC 24 |
34467347525 ps |
| T294 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/12.spi_device_flash_and_tpm_min_idle.1476972994 |
|
|
Sep 09 11:30:47 AM UTC 24 |
Sep 09 11:34:55 AM UTC 24 |
72368572958 ps |
| T658 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/29.spi_device_upload.721246008 |
|
|
Sep 09 11:34:35 AM UTC 24 |
Sep 09 11:34:56 AM UTC 24 |
14347865265 ps |
| T108 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/13.spi_device_flash_and_tpm.642460594 |
|
|
Sep 09 11:31:00 AM UTC 24 |
Sep 09 11:34:59 AM UTC 24 |
23272287429 ps |
| T276 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/29.spi_device_mailbox.821586335 |
|
|
Sep 09 11:34:35 AM UTC 24 |
Sep 09 11:35:00 AM UTC 24 |
2578260218 ps |
| T330 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/30.spi_device_pass_addr_payload_swap.1752982000 |
|
|
Sep 09 11:34:50 AM UTC 24 |
Sep 09 11:35:03 AM UTC 24 |
4363959258 ps |
| T659 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/30.spi_device_cfg_cmd.4001862494 |
|
|
Sep 09 11:34:56 AM UTC 24 |
Sep 09 11:35:05 AM UTC 24 |
670617399 ps |
| T660 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/24.spi_device_flash_and_tpm_min_idle.2627027163 |
|
|
Sep 09 11:33:29 AM UTC 24 |
Sep 09 11:35:07 AM UTC 24 |
20209920419 ps |
| T661 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/26.spi_device_flash_and_tpm_min_idle.4082563140 |
|
|
Sep 09 11:33:54 AM UTC 24 |
Sep 09 11:35:07 AM UTC 24 |
10686672978 ps |
| T662 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/26.spi_device_mailbox.2956651392 |
|
|
Sep 09 11:33:51 AM UTC 24 |
Sep 09 11:35:08 AM UTC 24 |
29393389188 ps |
| T663 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/30.spi_device_upload.1669006892 |
|
|
Sep 09 11:34:55 AM UTC 24 |
Sep 09 11:35:08 AM UTC 24 |
2830277414 ps |
| T264 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/30.spi_device_intercept.2958463995 |
|
|
Sep 09 11:34:51 AM UTC 24 |
Sep 09 11:35:10 AM UTC 24 |
5377988552 ps |
| T664 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/30.spi_device_read_buffer_direct.1737600214 |
|
|
Sep 09 11:35:04 AM UTC 24 |
Sep 09 11:35:10 AM UTC 24 |
640821185 ps |
| T665 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/30.spi_device_alert_test.789265094 |
|
|
Sep 09 11:35:09 AM UTC 24 |
Sep 09 11:35:11 AM UTC 24 |
10639644 ps |
| T666 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/24.spi_device_flash_all.3428678161 |
|
|
Sep 09 11:33:28 AM UTC 24 |
Sep 09 11:35:13 AM UTC 24 |
173741427663 ps |
| T667 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/31.spi_device_csb_read.815094695 |
|
|
Sep 09 11:35:11 AM UTC 24 |
Sep 09 11:35:13 AM UTC 24 |
77708532 ps |
| T668 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/30.spi_device_mailbox.961535157 |
|
|
Sep 09 11:34:54 AM UTC 24 |
Sep 09 11:35:13 AM UTC 24 |
20351753807 ps |
| T669 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/30.spi_device_tpm_all.3215130622 |
|
|
Sep 09 11:34:47 AM UTC 24 |
Sep 09 11:35:14 AM UTC 24 |
2818020322 ps |
| T670 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/31.spi_device_tpm_read_hw_reg.500200130 |
|
|
Sep 09 11:35:11 AM UTC 24 |
Sep 09 11:35:14 AM UTC 24 |
387100713 ps |
| T671 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/31.spi_device_tpm_sts_read.3137129487 |
|
|
Sep 09 11:35:14 AM UTC 24 |
Sep 09 11:35:16 AM UTC 24 |
31904555 ps |
| T672 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/30.spi_device_tpm_read_hw_reg.3932720334 |
|
|
Sep 09 11:34:46 AM UTC 24 |
Sep 09 11:35:16 AM UTC 24 |
8015902509 ps |
| T673 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/31.spi_device_tpm_rw.602342914 |
|
|
Sep 09 11:35:15 AM UTC 24 |
Sep 09 11:35:17 AM UTC 24 |
22817246 ps |
| T674 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/31.spi_device_tpm_all.4236330216 |
|
|
Sep 09 11:35:12 AM UTC 24 |
Sep 09 11:35:19 AM UTC 24 |
569588158 ps |
| T325 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/30.spi_device_pass_cmd_filtering.2265896926 |
|
|
Sep 09 11:34:48 AM UTC 24 |
Sep 09 11:35:21 AM UTC 24 |
9887655661 ps |
| T675 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/31.spi_device_pass_addr_payload_swap.981262975 |
|
|
Sep 09 11:35:15 AM UTC 24 |
Sep 09 11:35:22 AM UTC 24 |
288696937 ps |
| T305 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/2.spi_device_flash_all.1612431097 |
|
|
Sep 09 11:29:09 AM UTC 24 |
Sep 09 11:35:23 AM UTC 24 |
95734135343 ps |
| T326 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/31.spi_device_upload.3604359188 |
|
|
Sep 09 11:35:17 AM UTC 24 |
Sep 09 11:35:27 AM UTC 24 |
999741495 ps |
| T676 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/31.spi_device_pass_cmd_filtering.2698482824 |
|
|
Sep 09 11:35:15 AM UTC 24 |
Sep 09 11:35:28 AM UTC 24 |
7033074234 ps |
| T90 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/2.spi_device_stress_all.624858998 |
|
|
Sep 09 11:29:10 AM UTC 24 |
Sep 09 11:35:30 AM UTC 24 |
42869884634 ps |
| T94 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/31.spi_device_intercept.4263487223 |
|
|
Sep 09 11:35:15 AM UTC 24 |
Sep 09 11:35:31 AM UTC 24 |
719061434 ps |
| T95 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/25.spi_device_flash_mode_ignore_cmds.462143290 |
|
|
Sep 09 11:33:41 AM UTC 24 |
Sep 09 11:35:31 AM UTC 24 |
8460734473 ps |
| T96 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/31.spi_device_alert_test.2793134109 |
|
|
Sep 09 11:35:32 AM UTC 24 |
Sep 09 11:35:34 AM UTC 24 |
17257739 ps |
| T97 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/32.spi_device_csb_read.1697454555 |
|
|
Sep 09 11:35:32 AM UTC 24 |
Sep 09 11:35:34 AM UTC 24 |
16196659 ps |
| T98 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/31.spi_device_read_buffer_direct.4280445472 |
|
|
Sep 09 11:35:24 AM UTC 24 |
Sep 09 11:35:37 AM UTC 24 |
1616190781 ps |
| T99 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/31.spi_device_mailbox.2019667621 |
|
|
Sep 09 11:35:17 AM UTC 24 |
Sep 09 11:35:39 AM UTC 24 |
4486124239 ps |
| T100 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/32.spi_device_tpm_sts_read.3571278704 |
|
|
Sep 09 11:35:38 AM UTC 24 |
Sep 09 11:35:40 AM UTC 24 |
74818672 ps |
| T101 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/29.spi_device_flash_all.2687821476 |
|
|
Sep 09 11:34:39 AM UTC 24 |
Sep 09 11:35:43 AM UTC 24 |
30198923573 ps |
| T102 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/32.spi_device_tpm_read_hw_reg.3838660169 |
|
|
Sep 09 11:35:36 AM UTC 24 |
Sep 09 11:35:43 AM UTC 24 |
1127371967 ps |
| T677 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/32.spi_device_tpm_rw.54643694 |
|
|
Sep 09 11:35:40 AM UTC 24 |
Sep 09 11:35:43 AM UTC 24 |
285559107 ps |
| T391 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/29.spi_device_flash_mode.3343254576 |
|
|
Sep 09 11:34:36 AM UTC 24 |
Sep 09 11:35:44 AM UTC 24 |
3719372910 ps |
| T390 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/30.spi_device_flash_mode.929917103 |
|
|
Sep 09 11:35:01 AM UTC 24 |
Sep 09 11:35:48 AM UTC 24 |
7980342345 ps |
| T678 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/15.spi_device_flash_all.1277359933 |
|
|
Sep 09 11:31:26 AM UTC 24 |
Sep 09 11:35:48 AM UTC 24 |
206692897879 ps |
| T679 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/28.spi_device_flash_all.914970102 |
|
|
Sep 09 11:34:21 AM UTC 24 |
Sep 09 11:35:49 AM UTC 24 |
34476059098 ps |
| T680 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/31.spi_device_cfg_cmd.1804462056 |
|
|
Sep 09 11:35:18 AM UTC 24 |
Sep 09 11:35:50 AM UTC 24 |
7946191668 ps |
| T681 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/22.spi_device_flash_and_tpm_min_idle.1538677707 |
|
|
Sep 09 11:33:06 AM UTC 24 |
Sep 09 11:35:50 AM UTC 24 |
18494068402 ps |
| T682 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/32.spi_device_upload.1096001417 |
|
|
Sep 09 11:35:46 AM UTC 24 |
Sep 09 11:35:50 AM UTC 24 |
43234825 ps |
| T683 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/32.spi_device_cfg_cmd.1088792513 |
|
|
Sep 09 11:35:49 AM UTC 24 |
Sep 09 11:35:53 AM UTC 24 |
297653633 ps |
| T684 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/32.spi_device_pass_cmd_filtering.1131948631 |
|
|
Sep 09 11:35:42 AM UTC 24 |
Sep 09 11:35:53 AM UTC 24 |
1164089666 ps |
| T381 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/32.spi_device_pass_addr_payload_swap.238911763 |
|
|
Sep 09 11:35:45 AM UTC 24 |
Sep 09 11:35:53 AM UTC 24 |
2100092875 ps |
| T191 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/19.spi_device_stress_all.3124361096 |
|
|
Sep 09 11:32:17 AM UTC 24 |
Sep 09 11:35:53 AM UTC 24 |
18204441128 ps |
| T685 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/32.spi_device_intercept.1219935423 |
|
|
Sep 09 11:35:45 AM UTC 24 |
Sep 09 11:35:55 AM UTC 24 |
942521897 ps |
| T686 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/24.spi_device_flash_mode_ignore_cmds.2275200439 |
|
|
Sep 09 11:33:28 AM UTC 24 |
Sep 09 11:35:55 AM UTC 24 |
19225498814 ps |
| T687 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/32.spi_device_alert_test.2190255645 |
|
|
Sep 09 11:35:53 AM UTC 24 |
Sep 09 11:35:55 AM UTC 24 |
17596038 ps |
| T688 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/31.spi_device_flash_all.662932650 |
|
|
Sep 09 11:35:25 AM UTC 24 |
Sep 09 11:35:57 AM UTC 24 |
25748285682 ps |
| T689 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/33.spi_device_csb_read.932764885 |
|
|
Sep 09 11:35:55 AM UTC 24 |
Sep 09 11:35:57 AM UTC 24 |
47259869 ps |
| T690 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/33.spi_device_tpm_read_hw_reg.535716052 |
|
|
Sep 09 11:35:55 AM UTC 24 |
Sep 09 11:35:57 AM UTC 24 |
11517843 ps |
| T691 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/6.spi_device_flash_and_tpm.4208567753 |
|
|
Sep 09 11:29:44 AM UTC 24 |
Sep 09 11:35:58 AM UTC 24 |
37571913614 ps |
| T692 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/33.spi_device_tpm_sts_read.1890498553 |
|
|
Sep 09 11:35:56 AM UTC 24 |
Sep 09 11:35:58 AM UTC 24 |
106365706 ps |
| T693 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/33.spi_device_tpm_rw.3757131458 |
|
|
Sep 09 11:35:57 AM UTC 24 |
Sep 09 11:36:00 AM UTC 24 |
104192399 ps |
| T694 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/33.spi_device_pass_addr_payload_swap.2545315070 |
|
|
Sep 09 11:35:58 AM UTC 24 |
Sep 09 11:36:02 AM UTC 24 |
122989421 ps |
| T306 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/31.spi_device_flash_and_tpm_min_idle.4097777633 |
|
|
Sep 09 11:35:30 AM UTC 24 |
Sep 09 11:36:02 AM UTC 24 |
4260797452 ps |
| T695 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/32.spi_device_read_buffer_direct.4130291919 |
|
|
Sep 09 11:35:50 AM UTC 24 |
Sep 09 11:36:03 AM UTC 24 |
5105305408 ps |
| T696 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/33.spi_device_pass_cmd_filtering.2121815665 |
|
|
Sep 09 11:35:58 AM UTC 24 |
Sep 09 11:36:03 AM UTC 24 |
141910995 ps |
| T697 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/33.spi_device_mailbox.2565325688 |
|
|
Sep 09 11:35:59 AM UTC 24 |
Sep 09 11:36:03 AM UTC 24 |
111208170 ps |
| T258 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/26.spi_device_stress_all.2705537181 |
|
|
Sep 09 11:33:55 AM UTC 24 |
Sep 09 11:36:04 AM UTC 24 |
5272448163 ps |
| T698 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/33.spi_device_cfg_cmd.3504991102 |
|
|
Sep 09 11:36:00 AM UTC 24 |
Sep 09 11:36:04 AM UTC 24 |
96874320 ps |
| T699 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/33.spi_device_intercept.1249662032 |
|
|
Sep 09 11:35:58 AM UTC 24 |
Sep 09 11:36:05 AM UTC 24 |
653781096 ps |
| T393 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/31.spi_device_flash_mode.3972905733 |
|
|
Sep 09 11:35:20 AM UTC 24 |
Sep 09 11:36:06 AM UTC 24 |
4099742362 ps |
| T700 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/33.spi_device_flash_mode.2607593291 |
|
|
Sep 09 11:36:02 AM UTC 24 |
Sep 09 11:36:07 AM UTC 24 |
113829979 ps |
| T701 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/33.spi_device_alert_test.1666484119 |
|
|
Sep 09 11:36:06 AM UTC 24 |
Sep 09 11:36:08 AM UTC 24 |
32776239 ps |
| T702 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/34.spi_device_csb_read.681231262 |
|
|
Sep 09 11:36:07 AM UTC 24 |
Sep 09 11:36:09 AM UTC 24 |
14966122 ps |
| T703 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/33.spi_device_read_buffer_direct.3681880527 |
|
|
Sep 09 11:36:04 AM UTC 24 |
Sep 09 11:36:10 AM UTC 24 |
80978861 ps |
| T704 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/32.spi_device_flash_mode.3150367478 |
|
|
Sep 09 11:35:49 AM UTC 24 |
Sep 09 11:36:10 AM UTC 24 |
767863101 ps |
| T174 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/15.spi_device_stress_all.1507745164 |
|
|
Sep 09 11:31:29 AM UTC 24 |
Sep 09 11:36:10 AM UTC 24 |
33222651373 ps |
| T705 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/32.spi_device_tpm_all.874650879 |
|
|
Sep 09 11:35:36 AM UTC 24 |
Sep 09 11:36:11 AM UTC 24 |
11738239536 ps |
| T706 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/33.spi_device_upload.1262509009 |
|
|
Sep 09 11:35:59 AM UTC 24 |
Sep 09 11:36:12 AM UTC 24 |
10060345111 ps |
| T707 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/34.spi_device_tpm_sts_read.759973344 |
|
|
Sep 09 11:36:10 AM UTC 24 |
Sep 09 11:36:13 AM UTC 24 |
18104855 ps |
| T708 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/34.spi_device_tpm_rw.1322370554 |
|
|
Sep 09 11:36:10 AM UTC 24 |
Sep 09 11:36:14 AM UTC 24 |
44144041 ps |
| T709 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/34.spi_device_pass_cmd_filtering.208825260 |
|
|
Sep 09 11:36:12 AM UTC 24 |
Sep 09 11:36:15 AM UTC 24 |
76214617 ps |
| T710 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/34.spi_device_pass_addr_payload_swap.3306461653 |
|
|
Sep 09 11:36:12 AM UTC 24 |
Sep 09 11:36:16 AM UTC 24 |
37609545 ps |
| T259 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/34.spi_device_intercept.3795060752 |
|
|
Sep 09 11:36:12 AM UTC 24 |
Sep 09 11:36:17 AM UTC 24 |
207435727 ps |
| T711 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/34.spi_device_tpm_read_hw_reg.4278425713 |
|
|
Sep 09 11:36:07 AM UTC 24 |
Sep 09 11:36:19 AM UTC 24 |
2636892245 ps |
| T712 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/33.spi_device_tpm_all.774984321 |
|
|
Sep 09 11:35:56 AM UTC 24 |
Sep 09 11:36:20 AM UTC 24 |
5057306243 ps |
| T713 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/27.spi_device_flash_and_tpm.4205068701 |
|
|
Sep 09 11:34:07 AM UTC 24 |
Sep 09 11:36:21 AM UTC 24 |
11436914924 ps |
| T714 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/34.spi_device_upload.2424086353 |
|
|
Sep 09 11:36:14 AM UTC 24 |
Sep 09 11:36:21 AM UTC 24 |
3928212811 ps |
| T715 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/30.spi_device_flash_and_tpm.2863837353 |
|
|
Sep 09 11:35:08 AM UTC 24 |
Sep 09 11:36:22 AM UTC 24 |
8019630200 ps |
| T716 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/33.spi_device_flash_mode_ignore_cmds.712782190 |
|
|
Sep 09 11:36:04 AM UTC 24 |
Sep 09 11:36:23 AM UTC 24 |
1588560632 ps |
| T717 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/34.spi_device_alert_test.2254971775 |
|
|
Sep 09 11:36:23 AM UTC 24 |
Sep 09 11:36:25 AM UTC 24 |
11550835 ps |
| T718 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/34.spi_device_flash_mode.419701088 |
|
|
Sep 09 11:36:16 AM UTC 24 |
Sep 09 11:36:25 AM UTC 24 |
1121257711 ps |
| T719 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/35.spi_device_csb_read.943538555 |
|
|
Sep 09 11:36:24 AM UTC 24 |
Sep 09 11:36:26 AM UTC 24 |
88867551 ps |
| T720 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/35.spi_device_tpm_sts_read.3865592439 |
|
|
Sep 09 11:36:27 AM UTC 24 |
Sep 09 11:36:30 AM UTC 24 |
428935737 ps |
| T721 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/34.spi_device_read_buffer_direct.2436360276 |
|
|
Sep 09 11:36:18 AM UTC 24 |
Sep 09 11:36:30 AM UTC 24 |
678951943 ps |
| T722 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/34.spi_device_cfg_cmd.3403474742 |
|
|
Sep 09 11:36:14 AM UTC 24 |
Sep 09 11:36:30 AM UTC 24 |
745710720 ps |
| T337 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/16.spi_device_flash_and_tpm.2179781674 |
|
|
Sep 09 11:31:43 AM UTC 24 |
Sep 09 11:36:32 AM UTC 24 |
344562106073 ps |
| T723 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/35.spi_device_tpm_rw.369886290 |
|
|
Sep 09 11:36:31 AM UTC 24 |
Sep 09 11:36:36 AM UTC 24 |
55598010 ps |
| T91 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/23.spi_device_flash_and_tpm_min_idle.4222327775 |
|
|
Sep 09 11:33:20 AM UTC 24 |
Sep 09 11:36:36 AM UTC 24 |
103623184300 ps |
| T724 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/35.spi_device_intercept.3838133531 |
|
|
Sep 09 11:36:32 AM UTC 24 |
Sep 09 11:36:37 AM UTC 24 |
114448429 ps |
| T725 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/34.spi_device_tpm_all.1491537261 |
|
|
Sep 09 11:36:09 AM UTC 24 |
Sep 09 11:36:41 AM UTC 24 |
3903320272 ps |
| T726 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/35.spi_device_tpm_read_hw_reg.631987136 |
|
|
Sep 09 11:36:26 AM UTC 24 |
Sep 09 11:36:41 AM UTC 24 |
1202833605 ps |
| T727 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/5.spi_device_flash_and_tpm_min_idle.3356269393 |
|
|
Sep 09 11:29:36 AM UTC 24 |
Sep 09 11:36:41 AM UTC 24 |
43881696622 ps |
| T728 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/35.spi_device_upload.3827085409 |
|
|
Sep 09 11:36:38 AM UTC 24 |
Sep 09 11:36:42 AM UTC 24 |
234945798 ps |
| T729 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/35.spi_device_cfg_cmd.2798952558 |
|
|
Sep 09 11:36:38 AM UTC 24 |
Sep 09 11:36:43 AM UTC 24 |
116190247 ps |
| T730 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/35.spi_device_mailbox.4164474947 |
|
|
Sep 09 11:36:36 AM UTC 24 |
Sep 09 11:36:44 AM UTC 24 |
148818208 ps |
| T731 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/35.spi_device_pass_cmd_filtering.713783540 |
|
|
Sep 09 11:36:31 AM UTC 24 |
Sep 09 11:36:46 AM UTC 24 |
1813495424 ps |
| T732 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/33.spi_device_flash_all.78603598 |
|
|
Sep 09 11:36:05 AM UTC 24 |
Sep 09 11:36:48 AM UTC 24 |
7868299647 ps |
| T733 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/35.spi_device_read_buffer_direct.3499621410 |
|
|
Sep 09 11:36:42 AM UTC 24 |
Sep 09 11:36:48 AM UTC 24 |
300860955 ps |
| T734 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/35.spi_device_stress_all.4092820727 |
|
|
Sep 09 11:36:47 AM UTC 24 |
Sep 09 11:36:50 AM UTC 24 |
59485368 ps |
| T735 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/35.spi_device_alert_test.3898078636 |
|
|
Sep 09 11:36:48 AM UTC 24 |
Sep 09 11:36:50 AM UTC 24 |
19124029 ps |
| T736 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/36.spi_device_csb_read.4237590650 |
|
|
Sep 09 11:36:49 AM UTC 24 |
Sep 09 11:36:52 AM UTC 24 |
57237718 ps |
| T737 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/36.spi_device_tpm_read_hw_reg.4125746851 |
|
|
Sep 09 11:36:51 AM UTC 24 |
Sep 09 11:36:54 AM UTC 24 |
241969151 ps |
| T373 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/13.spi_device_flash_all.3664207833 |
|
|
Sep 09 11:30:59 AM UTC 24 |
Sep 09 11:36:54 AM UTC 24 |
47828370760 ps |
| T738 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/36.spi_device_tpm_sts_read.4213786795 |
|
|
Sep 09 11:36:53 AM UTC 24 |
Sep 09 11:36:55 AM UTC 24 |
25207448 ps |
| T739 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/34.spi_device_mailbox.2830689982 |
|
|
Sep 09 11:36:13 AM UTC 24 |
Sep 09 11:36:56 AM UTC 24 |
19789937906 ps |
| T740 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/35.spi_device_flash_all.3956710747 |
|
|
Sep 09 11:36:43 AM UTC 24 |
Sep 09 11:36:57 AM UTC 24 |
2391776216 ps |
| T741 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/36.spi_device_tpm_rw.1066623230 |
|
|
Sep 09 11:36:55 AM UTC 24 |
Sep 09 11:36:58 AM UTC 24 |
109029722 ps |
| T383 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/35.spi_device_pass_addr_payload_swap.1719579051 |
|
|
Sep 09 11:36:31 AM UTC 24 |
Sep 09 11:37:00 AM UTC 24 |
12348142644 ps |
| T742 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/36.spi_device_pass_cmd_filtering.3643886586 |
|
|
Sep 09 11:36:55 AM UTC 24 |
Sep 09 11:37:00 AM UTC 24 |
1469845166 ps |
| T743 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/35.spi_device_tpm_all.2812932386 |
|
|
Sep 09 11:36:26 AM UTC 24 |
Sep 09 11:37:02 AM UTC 24 |
16139421948 ps |
| T744 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/36.spi_device_intercept.426113802 |
|
|
Sep 09 11:36:57 AM UTC 24 |
Sep 09 11:37:02 AM UTC 24 |
56131830 ps |
| T745 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/36.spi_device_upload.15212021 |
|
|
Sep 09 11:36:59 AM UTC 24 |
Sep 09 11:37:04 AM UTC 24 |
163881412 ps |
| T746 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/29.spi_device_stress_all.2215425658 |
|
|
Sep 09 11:34:41 AM UTC 24 |
Sep 09 11:37:04 AM UTC 24 |
111069908760 ps |
| T747 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/36.spi_device_flash_mode.2595668387 |
|
|
Sep 09 11:37:01 AM UTC 24 |
Sep 09 11:37:06 AM UTC 24 |
123818988 ps |
| T192 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/23.spi_device_stress_all.3586975981 |
|
|
Sep 09 11:33:22 AM UTC 24 |
Sep 09 11:37:08 AM UTC 24 |
105276111626 ps |
| T748 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/36.spi_device_mailbox.1807250781 |
|
|
Sep 09 11:36:58 AM UTC 24 |
Sep 09 11:37:08 AM UTC 24 |
585750957 ps |
| T39 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/30.spi_device_stress_all.2801305401 |
|
|
Sep 09 11:35:09 AM UTC 24 |
Sep 09 11:37:11 AM UTC 24 |
35416095017 ps |
| T749 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/32.spi_device_flash_and_tpm_min_idle.2524886358 |
|
|
Sep 09 11:35:51 AM UTC 24 |
Sep 09 11:37:11 AM UTC 24 |
89168569113 ps |
| T750 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/32.spi_device_mailbox.40820673 |
|
|
Sep 09 11:35:45 AM UTC 24 |
Sep 09 11:37:11 AM UTC 24 |
21946530760 ps |
| T751 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/36.spi_device_cfg_cmd.3175094394 |
|
|
Sep 09 11:37:01 AM UTC 24 |
Sep 09 11:37:11 AM UTC 24 |
458023683 ps |
| T752 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/36.spi_device_alert_test.4024483652 |
|
|
Sep 09 11:37:09 AM UTC 24 |
Sep 09 11:37:11 AM UTC 24 |
16079363 ps |
| T753 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/31.spi_device_flash_and_tpm.3802389907 |
|
|
Sep 09 11:35:28 AM UTC 24 |
Sep 09 11:37:13 AM UTC 24 |
3633029512 ps |
| T754 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/37.spi_device_csb_read.31319227 |
|
|
Sep 09 11:37:11 AM UTC 24 |
Sep 09 11:37:14 AM UTC 24 |
95185001 ps |
| T755 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/37.spi_device_tpm_sts_read.179440047 |
|
|
Sep 09 11:37:12 AM UTC 24 |
Sep 09 11:37:15 AM UTC 24 |
71787976 ps |
| T756 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/37.spi_device_tpm_rw.3172967025 |
|
|
Sep 09 11:37:13 AM UTC 24 |
Sep 09 11:37:16 AM UTC 24 |
139668848 ps |
| T757 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/30.spi_device_flash_all.112099810 |
|
|
Sep 09 11:35:06 AM UTC 24 |
Sep 09 11:37:16 AM UTC 24 |
7071353753 ps |
| T758 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/35.spi_device_flash_and_tpm.2124781049 |
|
|
Sep 09 11:36:44 AM UTC 24 |
Sep 09 11:37:18 AM UTC 24 |
7002014379 ps |
| T759 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/28.spi_device_stress_all.2083673364 |
|
|
Sep 09 11:34:24 AM UTC 24 |
Sep 09 11:37:19 AM UTC 24 |
8505982970 ps |
| T760 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/36.spi_device_read_buffer_direct.806310587 |
|
|
Sep 09 11:37:03 AM UTC 24 |
Sep 09 11:37:21 AM UTC 24 |
18191650337 ps |
| T761 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/35.spi_device_flash_mode.3732844755 |
|
|
Sep 09 11:36:42 AM UTC 24 |
Sep 09 11:37:21 AM UTC 24 |
6448874274 ps |
| T762 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/36.spi_device_tpm_all.2452506437 |
|
|
Sep 09 11:36:52 AM UTC 24 |
Sep 09 11:37:26 AM UTC 24 |
4253473675 ps |
| T368 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/37.spi_device_pass_addr_payload_swap.1352878251 |
|
|
Sep 09 11:37:15 AM UTC 24 |
Sep 09 11:37:27 AM UTC 24 |
1006039740 ps |
| T763 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/37.spi_device_cfg_cmd.3133100132 |
|
|
Sep 09 11:37:19 AM UTC 24 |
Sep 09 11:37:27 AM UTC 24 |
441302389 ps |
| T764 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/37.spi_device_intercept.2574226539 |
|
|
Sep 09 11:37:16 AM UTC 24 |
Sep 09 11:37:28 AM UTC 24 |
1335675613 ps |
| T765 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/37.spi_device_tpm_read_hw_reg.1277955548 |
|
|
Sep 09 11:37:11 AM UTC 24 |
Sep 09 11:37:34 AM UTC 24 |
27170204496 ps |
| T766 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/37.spi_device_read_buffer_direct.1013542749 |
|
|
Sep 09 11:37:22 AM UTC 24 |
Sep 09 11:37:35 AM UTC 24 |
1279129092 ps |
| T767 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/37.spi_device_pass_cmd_filtering.1710549198 |
|
|
Sep 09 11:37:14 AM UTC 24 |
Sep 09 11:37:36 AM UTC 24 |
5731664859 ps |
| T768 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/37.spi_device_alert_test.3766230336 |
|
|
Sep 09 11:37:35 AM UTC 24 |
Sep 09 11:37:37 AM UTC 24 |
34319549 ps |
| T769 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/20.spi_device_flash_and_tpm.3835549853 |
|
|
Sep 09 11:32:35 AM UTC 24 |
Sep 09 11:37:38 AM UTC 24 |
26146103691 ps |
| T770 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/38.spi_device_csb_read.3989920959 |
|
|
Sep 09 11:37:36 AM UTC 24 |
Sep 09 11:37:38 AM UTC 24 |
23091072 ps |
| T367 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/36.spi_device_pass_addr_payload_swap.293899098 |
|
|
Sep 09 11:36:56 AM UTC 24 |
Sep 09 11:37:39 AM UTC 24 |
23005209252 ps |
| T771 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/38.spi_device_tpm_read_hw_reg.3749678664 |
|
|
Sep 09 11:37:37 AM UTC 24 |
Sep 09 11:37:39 AM UTC 24 |
123937944 ps |
| T272 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/17.spi_device_stress_all.4187322512 |
|
|
Sep 09 11:31:55 AM UTC 24 |
Sep 09 11:37:39 AM UTC 24 |
30284847962 ps |
| T772 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/37.spi_device_tpm_all.1966425816 |
|
|
Sep 09 11:37:12 AM UTC 24 |
Sep 09 11:37:40 AM UTC 24 |
2860902408 ps |
| T773 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/38.spi_device_tpm_all.1269547352 |
|
|
Sep 09 11:37:38 AM UTC 24 |
Sep 09 11:37:40 AM UTC 24 |
34129206 ps |
| T265 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/24.spi_device_stress_all.1686879872 |
|
|
Sep 09 11:33:33 AM UTC 24 |
Sep 09 11:37:40 AM UTC 24 |
25844517485 ps |
| T774 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/38.spi_device_tpm_sts_read.851218433 |
|
|
Sep 09 11:37:39 AM UTC 24 |
Sep 09 11:37:41 AM UTC 24 |
35678275 ps |
| T775 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/38.spi_device_tpm_rw.1732794230 |
|
|
Sep 09 11:37:39 AM UTC 24 |
Sep 09 11:37:43 AM UTC 24 |
80430930 ps |
| T776 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/36.spi_device_flash_all.2426728001 |
|
|
Sep 09 11:37:05 AM UTC 24 |
Sep 09 11:37:45 AM UTC 24 |
5722296092 ps |
| T777 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/38.spi_device_upload.1660499423 |
|
|
Sep 09 11:37:41 AM UTC 24 |
Sep 09 11:37:47 AM UTC 24 |
228388304 ps |
| T778 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/38.spi_device_cfg_cmd.2306098906 |
|
|
Sep 09 11:37:42 AM UTC 24 |
Sep 09 11:37:48 AM UTC 24 |
820061566 ps |
| T252 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/37.spi_device_upload.1220916788 |
|
|
Sep 09 11:37:17 AM UTC 24 |
Sep 09 11:37:48 AM UTC 24 |
6770049865 ps |
| T779 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/38.spi_device_intercept.227571832 |
|
|
Sep 09 11:37:41 AM UTC 24 |
Sep 09 11:37:49 AM UTC 24 |
632273443 ps |
| T780 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/38.spi_device_mailbox.3790409634 |
|
|
Sep 09 11:37:41 AM UTC 24 |
Sep 09 11:37:51 AM UTC 24 |
439801848 ps |
| T781 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/23.spi_device_flash_all.2149930408 |
|
|
Sep 09 11:33:18 AM UTC 24 |
Sep 09 11:37:52 AM UTC 24 |
328955264527 ps |
| T782 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/36.spi_device_flash_and_tpm.2902282409 |
|
|
Sep 09 11:37:05 AM UTC 24 |
Sep 09 11:37:52 AM UTC 24 |
15843202850 ps |
| T783 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/38.spi_device_read_buffer_direct.2406181099 |
|
|
Sep 09 11:37:46 AM UTC 24 |
Sep 09 11:37:53 AM UTC 24 |
2046410771 ps |
| T784 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/38.spi_device_alert_test.2500397523 |
|
|
Sep 09 11:37:51 AM UTC 24 |
Sep 09 11:37:54 AM UTC 24 |
14086657 ps |
| T785 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/39.spi_device_csb_read.427627892 |
|
|
Sep 09 11:37:53 AM UTC 24 |
Sep 09 11:37:55 AM UTC 24 |
30977961 ps |
| T786 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/39.spi_device_tpm_sts_read.3739427302 |
|
|
Sep 09 11:37:55 AM UTC 24 |
Sep 09 11:37:57 AM UTC 24 |
47428570 ps |
| T387 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/15.spi_device_flash_and_tpm.1191391248 |
|
|
Sep 09 11:31:26 AM UTC 24 |
Sep 09 11:37:57 AM UTC 24 |
191554314200 ps |
| T358 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/34.spi_device_flash_and_tpm.3493456939 |
|
|
Sep 09 11:36:20 AM UTC 24 |
Sep 09 11:37:57 AM UTC 24 |
2935701869 ps |
| T787 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/39.spi_device_tpm_rw.618793831 |
|
|
Sep 09 11:37:56 AM UTC 24 |
Sep 09 11:37:58 AM UTC 24 |
91494002 ps |
| T788 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/37.spi_device_flash_mode.1886251518 |
|
|
Sep 09 11:37:20 AM UTC 24 |
Sep 09 11:37:59 AM UTC 24 |
10183745670 ps |
| T392 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/38.spi_device_flash_mode.2142701413 |
|
|
Sep 09 11:37:42 AM UTC 24 |
Sep 09 11:38:00 AM UTC 24 |
589491420 ps |
| T789 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/38.spi_device_pass_cmd_filtering.3601848403 |
|
|
Sep 09 11:37:40 AM UTC 24 |
Sep 09 11:38:02 AM UTC 24 |
7520838877 ps |
| T790 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/38.spi_device_pass_addr_payload_swap.3666459365 |
|
|
Sep 09 11:37:40 AM UTC 24 |
Sep 09 11:38:02 AM UTC 24 |
11779981984 ps |
| T791 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/39.spi_device_intercept.898455248 |
|
|
Sep 09 11:37:58 AM UTC 24 |
Sep 09 11:38:03 AM UTC 24 |
461347238 ps |
| T792 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/39.spi_device_tpm_read_hw_reg.554677996 |
|
|
Sep 09 11:37:54 AM UTC 24 |
Sep 09 11:38:03 AM UTC 24 |
741901197 ps |
| T793 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/26.spi_device_flash_and_tpm.2149499049 |
|
|
Sep 09 11:33:54 AM UTC 24 |
Sep 09 11:38:04 AM UTC 24 |
109398833591 ps |
| T336 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/39.spi_device_pass_addr_payload_swap.1267210194 |
|
|
Sep 09 11:37:58 AM UTC 24 |
Sep 09 11:38:04 AM UTC 24 |
5739676667 ps |
| T175 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/14.spi_device_flash_and_tpm.258652858 |
|
|
Sep 09 11:31:16 AM UTC 24 |
Sep 09 11:38:05 AM UTC 24 |
92584886558 ps |
| T341 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/31.spi_device_flash_mode_ignore_cmds.2453251337 |
|
|
Sep 09 11:35:21 AM UTC 24 |
Sep 09 11:38:06 AM UTC 24 |
87343583044 ps |
| T794 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/39.spi_device_cfg_cmd.3946396372 |
|
|
Sep 09 11:38:01 AM UTC 24 |
Sep 09 11:38:07 AM UTC 24 |
649129544 ps |
| T795 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/39.spi_device_alert_test.13652481 |
|
|
Sep 09 11:38:07 AM UTC 24 |
Sep 09 11:38:09 AM UTC 24 |
44107756 ps |
| T342 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/34.spi_device_flash_all.65784237 |
|
|
Sep 09 11:36:19 AM UTC 24 |
Sep 09 11:38:10 AM UTC 24 |
21942836942 ps |
| T796 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/40.spi_device_csb_read.2392847009 |
|
|
Sep 09 11:38:08 AM UTC 24 |
Sep 09 11:38:10 AM UTC 24 |
52777139 ps |
| T797 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/39.spi_device_pass_cmd_filtering.2437020094 |
|
|
Sep 09 11:37:58 AM UTC 24 |
Sep 09 11:38:13 AM UTC 24 |
2863259645 ps |
| T798 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/39.spi_device_mailbox.2960540334 |
|
|
Sep 09 11:37:59 AM UTC 24 |
Sep 09 11:38:14 AM UTC 24 |
2997601765 ps |
| T799 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/40.spi_device_tpm_sts_read.2329685876 |
|
|
Sep 09 11:38:11 AM UTC 24 |
Sep 09 11:38:14 AM UTC 24 |
51697146 ps |
| T800 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/40.spi_device_tpm_all.1189198329 |
|
|
Sep 09 11:38:10 AM UTC 24 |
Sep 09 11:38:16 AM UTC 24 |
1693532487 ps |
| T801 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/39.spi_device_read_buffer_direct.492113613 |
|
|
Sep 09 11:38:04 AM UTC 24 |
Sep 09 11:38:16 AM UTC 24 |
1879830416 ps |
| T802 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/39.spi_device_tpm_all.848862265 |
|
|
Sep 09 11:37:54 AM UTC 24 |
Sep 09 11:38:17 AM UTC 24 |
11146886254 ps |
| T343 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/18.spi_device_flash_and_tpm_min_idle.3619218134 |
|
|
Sep 09 11:32:05 AM UTC 24 |
Sep 09 11:38:17 AM UTC 24 |
33216066344 ps |
| T803 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/40.spi_device_pass_addr_payload_swap.1393512068 |
|
|
Sep 09 11:38:15 AM UTC 24 |
Sep 09 11:38:18 AM UTC 24 |
284985208 ps |
| T332 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/35.spi_device_flash_mode_ignore_cmds.2030888916 |
|
|
Sep 09 11:36:42 AM UTC 24 |
Sep 09 11:38:20 AM UTC 24 |
57363584668 ps |
| T804 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/39.spi_device_upload.2681927106 |
|
|
Sep 09 11:38:00 AM UTC 24 |
Sep 09 11:38:20 AM UTC 24 |
6123128262 ps |
| T805 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/40.spi_device_cfg_cmd.2432233014 |
|
|
Sep 09 11:38:18 AM UTC 24 |
Sep 09 11:38:22 AM UTC 24 |
461891234 ps |
| T806 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/40.spi_device_mailbox.1542574494 |
|
|
Sep 09 11:38:17 AM UTC 24 |
Sep 09 11:38:22 AM UTC 24 |
108346541 ps |
| T807 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/40.spi_device_tpm_read_hw_reg.1074279121 |
|
|
Sep 09 11:38:10 AM UTC 24 |
Sep 09 11:38:23 AM UTC 24 |
34279420550 ps |
| T808 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/40.spi_device_tpm_rw.3728700524 |
|
|
Sep 09 11:38:15 AM UTC 24 |
Sep 09 11:38:23 AM UTC 24 |
385663674 ps |
| T809 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/39.spi_device_flash_mode.734804876 |
|
|
Sep 09 11:38:02 AM UTC 24 |
Sep 09 11:38:23 AM UTC 24 |
1061005259 ps |
| T810 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/30.spi_device_flash_mode_ignore_cmds.2235798226 |
|
|
Sep 09 11:35:02 AM UTC 24 |
Sep 09 11:38:24 AM UTC 24 |
98612356519 ps |
| T811 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/40.spi_device_read_buffer_direct.1147665046 |
|
|
Sep 09 11:38:20 AM UTC 24 |
Sep 09 11:38:25 AM UTC 24 |
581798599 ps |
| T360 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/9.spi_device_flash_all.2767936188 |
|
|
Sep 09 11:30:09 AM UTC 24 |
Sep 09 11:38:25 AM UTC 24 |
144019425354 ps |
| T812 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/40.spi_device_alert_test.1646927845 |
|
|
Sep 09 11:38:25 AM UTC 24 |
Sep 09 11:38:27 AM UTC 24 |
45748121 ps |
| T813 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/41.spi_device_csb_read.1923740205 |
|
|
Sep 09 11:38:26 AM UTC 24 |
Sep 09 11:38:28 AM UTC 24 |
54665368 ps |
| T814 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/40.spi_device_upload.1939065309 |
|
|
Sep 09 11:38:18 AM UTC 24 |
Sep 09 11:38:29 AM UTC 24 |
497148827 ps |
| T815 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/41.spi_device_tpm_sts_read.3171077754 |
|
|
Sep 09 11:38:27 AM UTC 24 |
Sep 09 11:38:29 AM UTC 24 |
123123826 ps |
| T816 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/40.spi_device_flash_mode_ignore_cmds.4061367153 |
|
|
Sep 09 11:38:20 AM UTC 24 |
Sep 09 11:38:30 AM UTC 24 |
1202434450 ps |
| T817 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/40.spi_device_flash_mode.4084710010 |
|
|
Sep 09 11:38:19 AM UTC 24 |
Sep 09 11:38:32 AM UTC 24 |
2705325620 ps |
| T818 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/41.spi_device_tpm_rw.513716357 |
|
|
Sep 09 11:38:29 AM UTC 24 |
Sep 09 11:38:32 AM UTC 24 |
140518954 ps |
| T819 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/40.spi_device_intercept.1494841807 |
|
|
Sep 09 11:38:17 AM UTC 24 |
Sep 09 11:38:32 AM UTC 24 |
2715477601 ps |
| T820 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/41.spi_device_pass_addr_payload_swap.1863112112 |
|
|
Sep 09 11:38:30 AM UTC 24 |
Sep 09 11:38:34 AM UTC 24 |
88174561 ps |
| T821 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/40.spi_device_pass_cmd_filtering.4013092394 |
|
|
Sep 09 11:38:15 AM UTC 24 |
Sep 09 11:38:34 AM UTC 24 |
40090932654 ps |
| T822 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/41.spi_device_pass_cmd_filtering.2690657145 |
|
|
Sep 09 11:38:30 AM UTC 24 |
Sep 09 11:38:35 AM UTC 24 |
425040179 ps |
| T823 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/41.spi_device_intercept.4183999141 |
|
|
Sep 09 11:38:31 AM UTC 24 |
Sep 09 11:38:37 AM UTC 24 |
590957000 ps |
| T366 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/25.spi_device_flash_all.2376853093 |
|
|
Sep 09 11:33:41 AM UTC 24 |
Sep 09 11:38:39 AM UTC 24 |
208720668685 ps |
| T824 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/39.spi_device_flash_all.2640608161 |
|
|
Sep 09 11:38:05 AM UTC 24 |
Sep 09 11:38:39 AM UTC 24 |
4105002210 ps |
| T825 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/33.spi_device_flash_and_tpm.3227118492 |
|
|
Sep 09 11:36:05 AM UTC 24 |
Sep 09 11:38:41 AM UTC 24 |
55680265527 ps |
| T826 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/39.spi_device_flash_mode_ignore_cmds.142443761 |
|
|
Sep 09 11:38:04 AM UTC 24 |
Sep 09 11:38:41 AM UTC 24 |
2880972019 ps |
| T827 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/41.spi_device_tpm_read_hw_reg.2144767586 |
|
|
Sep 09 11:38:26 AM UTC 24 |
Sep 09 11:38:41 AM UTC 24 |
1804877459 ps |
| T828 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/41.spi_device_flash_mode.3429927487 |
|
|
Sep 09 11:38:35 AM UTC 24 |
Sep 09 11:38:41 AM UTC 24 |
1050694843 ps |
| T829 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/41.spi_device_read_buffer_direct.3276899899 |
|
|
Sep 09 11:38:36 AM UTC 24 |
Sep 09 11:38:43 AM UTC 24 |
176572208 ps |
| T830 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/41.spi_device_tpm_all.3421380157 |
|
|
Sep 09 11:38:26 AM UTC 24 |
Sep 09 11:38:43 AM UTC 24 |
7903747019 ps |
| T831 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/41.spi_device_cfg_cmd.4051129472 |
|
|
Sep 09 11:38:34 AM UTC 24 |
Sep 09 11:38:45 AM UTC 24 |
936046318 ps |
| T832 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/41.spi_device_alert_test.2423353914 |
|
|
Sep 09 11:38:42 AM UTC 24 |
Sep 09 11:38:45 AM UTC 24 |
26076976 ps |
| T833 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/42.spi_device_csb_read.2731434228 |
|
|
Sep 09 11:38:42 AM UTC 24 |
Sep 09 11:38:45 AM UTC 24 |
24279012 ps |
| T834 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/42.spi_device_tpm_sts_read.4267638058 |
|
|
Sep 09 11:38:45 AM UTC 24 |
Sep 09 11:38:47 AM UTC 24 |
51333085 ps |
| T835 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/41.spi_device_upload.2732572601 |
|
|
Sep 09 11:38:34 AM UTC 24 |
Sep 09 11:38:48 AM UTC 24 |
4007933478 ps |
| T836 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/42.spi_device_tpm_rw.548433688 |
|
|
Sep 09 11:38:46 AM UTC 24 |
Sep 09 11:38:48 AM UTC 24 |
24772817 ps |
| T837 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/37.spi_device_flash_all.94817583 |
|
|
Sep 09 11:37:27 AM UTC 24 |
Sep 09 11:38:49 AM UTC 24 |
9530971559 ps |
| T176 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/21.spi_device_flash_and_tpm.2027806139 |
|
|
Sep 09 11:32:48 AM UTC 24 |
Sep 09 11:38:49 AM UTC 24 |
39139221889 ps |
| T359 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/38.spi_device_flash_mode_ignore_cmds.3271384860 |
|
|
Sep 09 11:37:43 AM UTC 24 |
Sep 09 11:38:51 AM UTC 24 |
4000212316 ps |
| T838 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/43.spi_device_upload.1880909639 |
|
|
Sep 09 11:39:02 AM UTC 24 |
Sep 09 11:39:06 AM UTC 24 |
102875007 ps |
| T369 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/27.spi_device_flash_mode_ignore_cmds.2995732240 |
|
|
Sep 09 11:34:03 AM UTC 24 |
Sep 09 11:38:52 AM UTC 24 |
122055114074 ps |
| T839 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/42.spi_device_tpm_all.3287234693 |
|
|
Sep 09 11:38:45 AM UTC 24 |
Sep 09 11:38:52 AM UTC 24 |
599141563 ps |
| T840 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_1r1w-sim-vcs/coverage/default/41.spi_device_stress_all.230034269 |
|
|
Sep 09 11:38:41 AM UTC 24 |
Sep 09 11:38:53 AM UTC 24 |
1329597989 ps |